CH388459A - Verfahren zur Herstellung eines Transistors - Google Patents
Verfahren zur Herstellung eines TransistorsInfo
- Publication number
- CH388459A CH388459A CH1385060A CH1385060A CH388459A CH 388459 A CH388459 A CH 388459A CH 1385060 A CH1385060 A CH 1385060A CH 1385060 A CH1385060 A CH 1385060A CH 388459 A CH388459 A CH 388459A
- Authority
- CH
- Switzerland
- Prior art keywords
- transistor
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3063—Electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB42433/59A GB940443A (en) | 1959-12-14 | 1959-12-14 | Improvements in and relating to semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
CH388459A true CH388459A (de) | 1965-02-28 |
Family
ID=10424389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH1385060A CH388459A (de) | 1959-12-14 | 1960-12-12 | Verfahren zur Herstellung eines Transistors |
Country Status (6)
Country | Link |
---|---|
US (1) | US3160799A (de) |
CH (1) | CH388459A (de) |
DE (1) | DE1121224B (de) |
ES (1) | ES263136A1 (de) |
GB (1) | GB940443A (de) |
NL (2) | NL121714C (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1282190B (de) * | 1964-03-12 | 1968-11-07 | Kabusihiki Kaisha Hitachi Seis | Verfahren zum Herstellen von Transistoren |
US5896486A (en) * | 1997-05-01 | 1999-04-20 | Lucent Technologies Inc. | Mass splice tray for optical fibers |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2829422A (en) * | 1952-05-21 | 1958-04-08 | Bell Telephone Labor Inc | Methods of fabricating semiconductor signal translating devices |
US2821493A (en) * | 1954-03-18 | 1958-01-28 | Hughes Aircraft Co | Fused junction transistors with regrown base regions |
GB807995A (en) * | 1955-09-02 | 1959-01-28 | Gen Electric Co Ltd | Improvements in or relating to the production of semiconductor bodies |
NL101253C (de) * | 1955-09-12 | |||
NL215949A (de) * | 1956-04-03 | |||
NL106110C (de) * | 1956-08-24 | |||
US2842831A (en) * | 1956-08-30 | 1958-07-15 | Bell Telephone Labor Inc | Manufacture of semiconductor devices |
GB849477A (en) * | 1957-09-23 | 1960-09-28 | Nat Res Dev | Improvements in or relating to semiconductor control devices |
BE574814A (de) * | 1958-01-16 | |||
NL134168C (de) * | 1958-07-29 | |||
NL245567A (de) * | 1958-11-20 |
-
0
- NL NL258921D patent/NL258921A/xx unknown
- NL NL121714D patent/NL121714C/xx active
-
1959
- 1959-12-14 GB GB42433/59A patent/GB940443A/en not_active Expired
-
1960
- 1960-12-08 US US74544A patent/US3160799A/en not_active Expired - Lifetime
- 1960-12-10 ES ES0263136A patent/ES263136A1/es not_active Expired
- 1960-12-12 DE DEN19306A patent/DE1121224B/de active Pending
- 1960-12-12 CH CH1385060A patent/CH388459A/de unknown
Also Published As
Publication number | Publication date |
---|---|
GB940443A (en) | 1963-10-30 |
US3160799A (en) | 1964-12-08 |
DE1121224B (de) | 1962-01-04 |
NL121714C (de) | |
ES263136A1 (es) | 1961-05-01 |
NL258921A (de) |
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