KR20150103697A - Processes and apparatus for preparing heterostructures with reduced strain by radial distention - Google Patents

Abstract

Apparatus and processes for making heterogeneous structures with reduced strain are disclosed. Heterogeneous structures may include semiconductor structures that are tailored to a surface layer having a crystal lattice constant that is different from the structure to form a relatively low defect heterostructure.

Description

FIELD OF THE INVENTION [0001] The present invention relates to processes and apparatus for producing heterogeneous structures with reduced strain by radial expansion. ≪ Desc / Clms Page number 1 >

[Cross reference to related application]

This application is related to U.S. Provisional Application No. 61 / 747,613, filed December 31, 2012; U.S. Provisional Application No. 61 / 793,999, filed March 15, 2013; U.S. Provisional Application No. 61 / 790,445, filed March 15, 2013; And U. S. Provisional Application No. 61 / 788,744, filed March 15, 2013, each of which is incorporated herein by reference.

This disclosure relates generally to the fabrication of semiconductor heterostructures with reduced strain, in particular to a surface layer having a crystal lattice constant different from that of itself, thereby forming a heterostructure of relatively low defect Lt; RTI ID = 0.0 > a < / RTI > semiconductor substrate.

Device Properties Multi-layered structures comprising a substrate having a crystal lattice structure that is different from the material of the device layer and the device layer with the surface are useful for a number of different purposes. These multilayer structures typically include multiple layers of material with varying lattice constants. Lattice mismatch between the layers allows the layers to deform. Misfit dislocations can be spontaneously formed in the device layer to relax deformation between the layers. Such potentials degrade the quality and usability of multilayer semiconductor structures.

There is a continuing need for methods for relaxing deformation between lattice mismatched semiconductor layers and for methods in which substrates and device layers with substantially no dislocations are achieved.

One aspect of the present disclosure is directed to a process for relaxing deformation in a heterogeneous structure comprising a substrate, a surface layer disposed on the substrate, and an interface between the substrate and the surface layer. The substrate includes a central axis, a rear surface generally perpendicular to the central axis, and a diameter extending across the substrate through the central axis. A dislocation source layer is formed on the substrate. The substrate is radially distended to generate dislocations and to glide dislocations from the dislocation source layer toward the surface layer.

Another aspect of the disclosure is directed to a process for making a relaxed heterologous structure. The surface layer is deposited on the front surface of the semiconductor substrate, thereby creating deformation between the surface layer and the substrate. A dislocation source layer is formed on the substrate. Deformation in the surface layer and the substrate is relaxed by radially expanding the substrate to generate dislocations and to slip the potentials from the dislocation source layer toward the surface layer.

Another aspect of the present disclosure is directed to an apparatus for radially expanding semiconductor structures having front, back, and circumferential edges. The apparatus includes a structure holder including a top plate and a back plate for contacting a structure adjacent a circumference of the structure. The top plate is adapted to contact the front surface of the structure and the back plate is adapted to contact the back surface of the structure. The top and rear plates are further adapted to form a peripheral chamber around the circumference of the top plate, rear plate and structure.

Another aspect of the present disclosure is directed to an apparatus for radially expanding semiconductor structures having front, back, circumferential peripheries and a central axis. The device includes triangular shaped segments pointing inwardly to the central side. The segments are configured to move outwardly from the central axis to cause the structure to expand. Fluid passages are formed in each segment to form a vacuum between the segment and the structure.

Figure 1 is a schematic cross-sectional view of a silicon hetero structure;
Figure 2 is a flow diagram depicting a process for manufacturing a heterogeneous structure;
3-4 are cross-sectional views of a structure holder for inflating a semiconductor structure and a semiconductor structure;
5 is a cross-sectional view of another embodiment of a structure holder for inflating a semiconductor structure and a semiconductor structure;
Figures 6-7 are cross-sectional views of the semiconductor structure with the coating thereon and the structure holder of Figure 3;
8 is a schematic cross-sectional view of a semiconductor structure and an apparatus for expanding the structure by the structure holder of FIG. 3 mounted therebetween;
9 is a cross-sectional view of another embodiment of a structure holder for inflating a semiconductor structure and a semiconductor structure;
10 is a cross-sectional view of a structure holder having a semiconductor structure and a compression plate for expanding the semiconductor structure;
11 is a cross-sectional view of another embodiment of a structure holder for inflating a semiconductor structure and a semiconductor structure;
12 is a cross-sectional view of another embodiment of a structure holder for inflating a semiconductor structure and a semiconductor structure;
13 is a cross-sectional view of a structure holder having a semiconductor structure and a compression plate for expanding the semiconductor structure;
14 is a cross-sectional view of a structure holder for inflating a plurality of semiconductor structures and semiconductor structures;
15 is a cross-sectional view of another embodiment of a structure holder for inflating a plurality of semiconductor structures and semiconductor structures;
16 is a plan view of another embodiment of a structure holder for inflating a semiconductor structure;
17 is a cross-sectional view of another embodiment of a structure holder for inflating a semiconductor structure and semiconductor structures;
18 is a cross-sectional view of another embodiment of a structure holder with a groove and a semiconductor structure for expanding the semiconductor structure;
19 is a cross-sectional view of the structure holder of Fig. 18 with a semiconductor structure and a top plate.
20 is a cross-sectional view of another embodiment of a semiconductor structure having two grooves and a structure holder for inflating a semiconductor structure;
21 is a cross-sectional view of another embodiment of a structure holder having a semiconductor structure and a flange.
Corresponding reference numerals designate corresponding parts throughout the drawings.

According to one or more aspects of the present disclosure, heterogeneous structures having reduced deformation between surface layers having different lattice constants between the substrate and the substrate may be fabricated as such by the process of FIG. The surface layer can also be referred to herein as an "epitaxial layer", "heteroepitaxial layer", "deposited film", "film", "heterolayer" or " . A heterostructure having a substantially relaxed surface layer and also achieving a reduced concentration of misfit dislocations, also referred to as threading dislocations, can be formed.

Generally, the processes of the present disclosure include forming a dislocation source layer on a semiconductor substrate, depositing a hetero layer on the substrate before and after formation of the dislocation source layer, and generating (i.e., " And radially expanding the heterostructure to slip the potentials from the source layer toward the surface layer. The activation of the source layer and the slippage of dislocations from the source layer toward the interface with the deposited layer occur in parallel by applying strain (e.g., tension) to the substrate. This strain may be applied in one or more steps and various combinations to activate and slip the dislocations, thereby plastically stretching the heterogeneous structure.

The hetero layer may have a crystal lattice constant a _SI different from the original crystal lattice constant a _S of the substrate to form a film on the surface of the substrate. In general, the crystal lattice constant a _SI of the hetero layer is larger than the original crystal lattice constant a _s of the substrate, and by controlling the generation and slippage of dislocation loops in the substrate by expansion, the substrate is subjected to a plastic stress deformation And is more appropriately aligned with the crystal lattice of the film thereby allowing the film to be completely relaxed and also to have reduced density of threading dislocations on the substrate.

The methods of the present disclosure have several advantages over conventional methods in relaxing the hetero layers. Conventional methods produce a large asymmetry in stresses between the membrane and the substrate, leading to the generation of dislocations in the membrane where the stresses are at a maximum. By limiting the dislocation loops to the membrane, the potentials leave behind segments that serve as the degradation threading potentials. Much effort has been devoted to attempting to minimize the density of such threaded dislocations.

In contrast, the methods of the present disclosure may be used to reduce stress (e.g., by weakening the substrate and by using a relatively thin film to avoid dislocations therein during the weakening of the substrate) Asymmetry. This allows the dislocations to be confined to the substrate during formation of the mismatch dislocation layer at the interface between the substrate and the film. By weakening the substrate by introducing dislocations in a variety of controlled manners, eternal stresses can be applied to the system to activate dislocations. This is different from conventional methods that result in self relaxation due to relatively large intrinsic internal stresses (i.e., relaxation without the application of external stresses). The methods of the present disclosure prevent relative self-relaxation from occurring due to relaxation and dissipation at appropriate temperatures with the addition of external strain, which is a relatively thin film, accompanied by relaxation other than by self-relaxation.

I. Semiconductor substrate

Referring to Figure 1, the semiconductor substrate 1 may be any single crystalline semiconductor material suitable for use as a substrate for supporting a surface layer, such as by deposition of an epitaxial layer by chemical vapor deposition (CVD) . In general, the semiconductor substrate may be comprised of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide or any combination thereof. Typically, the semiconductor substrate is comprised of silicon.

The semiconductor substrate 1 may have any form suitable for both as a substrate for depositing a surface layer and as applying strain to the substrate material as will be described in more detail below. Typically, the semiconductor substrate comprises a central axis 2; The interface 3 and the rear face 4 with the deposition layer 7 wherein the substrate-surface layer interface 3 and the rear face 4 are generally perpendicular to the central axis 2; A thickness t corresponding to the distance from the interface to the back surface of the substrate; Circumference 5; And a diameter D extending across the substrate passing through the central axis. For purposes of illustration, the backside 4 will be described as the opposing face at or near where the dislocation source layer is formed, and thus will be referred to herein as the "opposing surface" and / ≪ / RTI > In this regard, the heterogeneous structure itself and the deposition layer 7 described below are concentric with the substrate 1 as a whole, and also have a central axis 2; Circumference 5; And a diameter D extending across the heterogeneous structure (and also the surface layer) and through the central axis.

The substrate 1 may have any suitable diameter for use as a substrate on which the semiconductor layer is to be deposited. Generally, the substrate 1 has a diameter of about 150 mm or more. Typically, the substrate 1 has a diameter of at least about 200 mm, at least about 300 mm, or even at least about 450 mm. It should be noted that the substrate diameter may be diametrically before the heterogeneous structure is deformed and in such a case the diameter may increase from the values expressed after the firing stress deformation as discussed in more detail below. Alternatively, the substrate prior to the plastic stress relief may have a smaller diameter than the stated values so that the diameter after the plastic stress deformation is approximately equal to the stated values.

Similarly, the substrate 1 may have any thickness, t, suitable for use as a substrate on which a semiconductor layer may be deposited. For example, the substrate may have a thickness of from about 500 microns to about 1000 microns, typically from about 600 microns to about 1000 microns, from about 700 microns to about 1000 microns, from about 700 microns to about 900 microns, or even about And may have a thickness, t, from 700 microns to about 800 microns.

In some embodiments, for example, the substrate 1 may have a diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or even at least about 450 mm, and a length of from about 675 microns to about 1000 microns, or even about 725 Crystal silicon wafer that has been sliced from a single crystal silicon ingot grown by Czochralski crystal growth methods with a thickness of from about 1 micron to about 925 microns.

The substrate surface on which the epitaxial layer is deposited may be polished to conform to the deposition of the epitaxial layer or may be further controlled prior to CVD. The facing surfaces may also be polished or alternatively may be non-polished without departing from the scope of the present disclosure, i.e., as-ground, as-lapped, or lapped and etched ≪ / RTI > In various embodiments, the opposing surface may be left in a non-polished state, wherein a surface that is ground, ground, or wrapped and etched may be utilized as a dislocation source layer. Alternatively or additionally, the opposing face may be damaged to form a dislocation source layer as described in more detail below.

That a Czochralski grown silicon typically has an oxygen concentration within the range of about 5x10 ¹⁷ to about 9x10 ¹⁷ atoms / cm ³ (ASTM standard F-121-83) should be noted. In general, a monocrystalline silicon wafer used in a substrate in the present disclosure is a single crystal silicon wafer typically used within a range obtainable by the Czochralski process or even outside of that range, unless the oxygen concentration is so excessive as to prevent activation and slip of the dislocations. Will have a value of oxygen concentration.

II. Deposited Surface layer

The surface layer 7 can be positioned on the front surface of the substrate 1. The deposition layer 7 may be any single crystal semiconductor material suitable for deposition as an epitaxial layer by CVD. Generally, the hetero layer comprises a crystal lattice constant a _SI that is greater than the original crystal lattice constant a _S of the substrate. The deposited layer may be comprised of any suitable material, including but not limited to silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, or any combination thereof ≪ / RTI > In embodiments where the substrate is comprised of silicon, the hetero layers having a larger lattice constant include, for example, germanium, silicon germanium, polytypes of silicon carbide, gallium arsenide and indium gallium arsenide.

In one preferred embodiment, the deposited layer is silicon germanium, also referred to herein as SiGe. The specific composition of the deposited SiGe layer may vary without departing from the scope of the present disclosure. Typically, the SiGe layer comprises at least about 10% Ge and in some instances about 15%, about 20%, about 25%, about 35%, about 50% Ge or more (e.g., 60% , 80%, 90%, or more) Ge. However, in one preferred embodiment, the SiGe layer has a Ge concentration ranging from at least about 10% to less than about 50%, or at least about 15% to less than about 35%, wherein a concentration of about 20% Ge Is preferred.

Any technique that is generally known in the art may be used to form a deposition layer (e.g., a SiGe layer), such as one of the known epitaxial deposition techniques. Generally speaking, the thickness of the deposited layer can vary widely without departing from the scope of the present disclosure. This thickness may, for example, have a substantially uniform thickness, with an average thickness of at least about 0.1 microns, at least about 0.5 microns, at least about 1.0 microns, and even at least about 2.0 microns. Alternatively, it may be desirable to express the thickness in terms of range. For example, the average thickness is typically in the range of from about 0.1 micron to about 2.0 microns, for example from about 0.5 microns to about 1.0 microns.

It should be noted that since the deposited layer is grown on a substrate having a varying lattice constant, the same but opposite stresses are formed on both the deposited layer and the substrate. The relative amount of stress at the deposition layer and substrate directly above and below the substrate is proportional to the relative thicknesses of the deposition layer and the substrate. As a result, the stress in the deposited layer just above the interface can be larger by some orders of magnitude than the stress in the substrate just below the interface. For example, when a 500 nm SiGe layer containing about 22% Ge is grown on a 700-micron thick silicon semiconductor substrate, SiGe just above the interface will undergo a roughly 1.7 GPa squeeze, MPa tensile strength. The stress in the deposited layer can increase during growth until the layer self-relaxes by forming mismatches or threading dislocations in the deposited layer. Thus, in order to avoid self-relays of the deposited layer, it is desirable to at least initially grow a thin deposited layer on the substrate. Typically, the deposited layer will have a thickness of from about 1 nm to about 100 nm, more typically from about 1 nm to about 50 nm, more typically from about 10 nm to about 50 nm, more typically from about 1 nm to about 50 nm, when the SiGe layer is deposited on a monocrystalline silicon substrate 20 nm. ≪ / RTI > The thin layer can then be relaxed or partially relaxed at or near its original lattice constant by activating and extending dislocations in the substrate, as discussed in more detail below. If a thicker deposition layer is desired, additional material may be deposited after the layer is sufficiently relaxed.

Any technique that is generally inherently known in the art can be used to form a deposited layer on a substrate. For example, epitaxial deposition techniques (e.g., atmospheric-pressure chemical vapor phase deposition (APCVD)); Low-or reduced-pressure CVD (LPCVD); Ultra-high-vacuum CVD (UHVCVD); MBE (molecular beam epitaxy); Or atomic layer deposition (ALD)) may be used, where a SiGe material is deposited, for example. The epitaxial growth system may comprise a single wafer or multiple wafer batch reactors.

The surface layer (7) comprises a surface forming the front surface (8) of the hetero structure. The surface layer 7 may extend continuously across the entire diameter of the substrate 1, as shown in Fig. In some embodiments, the surface layer 7 does not extend continuously over the substrate 1 but rather is formed of discrete segments or "islands " of a number of semiconductor materials disposed on the substrate as further described below. ) &Quot;. For example, the surface layer may be disposed on a portion that is less than about 95% of the substrate, or on a portion less than about 80% of the substrate, such as in other embodiments, less than about 40% On a smaller portion, or on a portion less than about 20%.

III. Preparation of Dislocation Source Layer

 The dislocation source layer 6 may be located within the substrate 1 and may also be spaced from the substrate surface on which the epitaxial layer is to be deposited. Typically, the dislocation source layer 6 is at or near a surface on which the epitaxial layer is deposited or is opposed to the surface to be deposited. For example, if the epitaxial layer is to be deposited on the front side of the substrate, the potential source layer 6 will be at or near the backside 4 of the substrate. In such an example, the front side of the substrate will be the interface between the substrate and the deposition layer 7.

The source layer 6 is present above or above the substantially radial width of the substrate 1. [ In the embodiment illustrated in FIG. 1, the source layer 6 extends across the entire diameter of the substrate 1. Although this embodiment is preferred, in other embodiments the source layer may not extend across the entire diameter. Thus, generally, the source layer 6 has a radial width of typically at least about 75%, more typically at least about 85%, and even more typically at least about 95%, or even at least about 99% of the radius of the wafer . In some embodiments, the source layer 6 extends within a few millimeters around the circumference, for example, within about 1 millimeter around the circumference.

In general, the source layer 6 may comprise any portion of the substrate, as long as the source layer does not include a surface to be deposited thereon the epitaxial layer. Generally, the source layer 6 has a thickness of about 100 microns or less, about 50 microns or less, about 25 microns or less or about 10 microns or less (e.g., about 1 micron to about 100 microns, about 1 micron to about 50 microns, Microns to about 25 microns, or from about 5 microns to about 25 microns). The source layer 6 comprises the backside of the substrate and can extend therefrom. It should be noted that the source layer 6 need not include the backside of the wafer, but may extend from the backside to a predetermined depth toward the front side of the substrate.

The dislocation source layer 6 may be any layer capable of producing measurable concentrations of potentials when it is subjected to sufficiently high stresses at sufficiently high temperatures. In general, the dislocation source layer 6 is formed at a temperature of between about 5 MPa and about 100 MPa (typically at temperatures between about 500 DEG C and about 1000 DEG C, as discussed in more detail below with respect to activation of dislocations in the substrate Lt; RTI ID = 0.0 > 15 MPa). ≪ / RTI >

The dislocation source layer 6 may be formed on the substrate 1 before or after deposition of the surface layer 7. In embodiments where the substrate is a sliced wafer from a single crystal ingot, the potential source layer 6 may be a mechanical damage caused by a slicing process, a grinding process, or a lapping process included as part of the overall wafer ring process. have.

Alternatively or additionally, the dislocation source layer 6 may be partially or wholly formed by mechanically damaging the backside of the substrate by one or more processes selected from the group consisting of: back grinding, backside Forming soft indentations by lapping, sandblasting back, forming indentations on the backside, implanting ions on the backside, and / or combinations thereof.

In some embodiments, the dislocation source layer 6 may be formed by pressing an array of pointed pins onto the backside of the wafer to form indentations on the backside. The indentations may be formed non-uniformly across the surface or may be formed in a predetermined pattern. Such a pattern can be arranged in a specific relationship to the wafer crystal directions. For example, the square matrix pattern may be arranged at a shallow angle with respect to the 110 direction. This allows the potentials generated at these sites to slip along the parallel Glide planes and not interact with each other. In addition, such processing can have precise control of the dislocation loop density.

In some embodiments, the source layer 6 may be formed by implanting ions through the backside of the substrate. The implanted ions may be electronically neutral, neutral, or inert to minimize any effect on the electronic properties of the substrate. For example, implanted ions may be selected from the group consisting of silicon, germanium, hydrogen, helium, neon, argon, xenon, and combinations thereof.

The ions are implanted at the target depth, D _i , relatively to the backside. However, as a practical matter, some of the implanted ions will not travel this distance, and others will travel even larger distances (i. E., Reaching a relatively larger depth at the rear). The actual depth of ion implantation can vary from D _i by about 5%, 10%, 15%, 20%, 25% or more. This produces an amorphous material zone or layer containing a relatively high concentration of implanted ions at or near D _i , while the concentration of implanted ions decreases from D _{i in the} front and back direction (3) . The target depth, D _i, may also be referred to as the projected range of implanted ions.

Since lighter ions tend to penetrate deeper into the substrate for a given implant energy, the implant depth can be at least partially influenced by implanted ion species. Thus, for example, at an implant energy of 50 keV, the silicon ions will have an average implantation depth of about 750 A, while the germanium ions will have an average implantation depth of 400 A. In general, the ions are preferably implanted with an energy of at least about 30 keV, for example at least about 40 keV or even at least about 50 keV. In one application, the ions are implanted with an energy of at least about 45 keV and less than about 55 KeV. The selected ions and implantation energy should be sufficient to form an amorphous layer in the substrate that serves as the dislocation source layer.

Generally, dislocation loops are formed at the end of the range of implanted ions during subsequent annealing, provided that sufficient energy is used to implant ions of sufficient concentration to form the amorphous silicon layer. Typically, dislocation loops can be formed below the implanted ions at a depth of about 100 A to about 300 A, although the exact depth may be somewhat different. In general, it is more difficult to form amorphous materials with smaller masses of elements. Thus, a much higher concentration of elements of a lower mass should be used to cause sufficient damage, while a lower concentration of elements of a higher mass is sufficient to form amorphous silicon. For example, when the implanted ions are silicon ions, the implanted dose is preferably at least about 2 x 10 ¹⁴ atoms / cm ² , such as at least about 5 x 10 ¹⁴ atoms / cm ^2, or even at least about About 1 x 10 < ^{15 &} gt ;. In one preferred embodiment, the dose of ion dose implanted is at least about 2 x 10 ¹⁵ atoms / cm ² . In comparison, when the implanted ions are germanium ions of larger mass, the injected dose is preferably at least about 6 x 10 ¹³ atoms / cm ² , at least about 1 x 10 ¹⁴ atoms / cm ^2, or even at least about 5 x 10 ¹⁴ atoms / cm ² . In one preferred embodiment, the dose of ion dose implanted is at least about 1 x 10 ¹⁵ atoms / cm ² .

In some preferred embodiments, the source layer 6 is formed by grinding the back surface of the substrate. The surface can be ground using any grinding processes typically used in the semiconductor silicon industry to create the shape of the surface of the silicon wafer after being sliced from the Czochralski grown single crystal silicon ingot. In a particularly preferred embodiment, the backside can be ground using a grinding process utilizing a grit size of about 600.

 IV. Activation and Slipping of Dislocations

The dislocation source layer may be activated to form dislocations at or near the source layer, which may slide toward the substrate-surface layer interface. According to embodiments of the present disclosure, activation and slippage of dislocations are performed after the surface layer is deposited on the substrate such that the substrate and / or surface layer undergo deformation.

The dislocation source layer may be formed by exposing the substrate at elevated temperatures (which may also be referred to herein as "stretching", "tension" or "tensile strain") to cause formation of dislocations, (And typically the substrate) is subjected to a deformation force. The expansion is applied to the entire substrate in a direction perpendicular to the axis, i.e. in a radial direction, using one or more suitable devices. That is, the wafer is stretched radially outward from the perimeter circumference. In this way, the dislocations will be formed at or near the source layer and the dislocations will slip toward the opposite surface.

In general, less severely damaged dislocation source layers will be activated at lower stress levels and lower temperatures while less severely damaged dislocation source layers will be activated at higher stress levels and temperatures. Generally, a strain force applied by a tensile force of at least about 5 MPa, typically from about 5 MPa to about 100 MPa, or from about 10 MPa to about 100 MPa, is applied to the dislocation source layer at a temperature between about 550 DEG C and about 1000 DEG C All. More typically, the tensile force is from about 10 MPa to about 50 MPa or from about 10 MPa to about 25 MPa. Typically, activation and / or slippage of dislocations is performed at temperatures of from about 650 ° C to about 1000 ° C, or even from about 700 ° C to about 1000 ° C. Typical stresses that may be applied to activate the dislocation source layer formed by, for example, lapping and / or grinding, are those at temperatures higher than about 600 ° C and even more typically at temperatures higher than about 700 ° C 15 MPa. In addition, the more severely damaged layers can be activated even at lower stress levels.

The substrate is maintained to undergo tensile forces at elevated temperatures for a duration sufficient to activate and slip the dislocations. In general, the substrate may be held under elevated temperature under tension and maintained for at least about 5 hours, at least about 10 hours, or even longer, under such conditions for a period of at least about 10 seconds, as described above. Typically, the substrate is subjected to a tensile force at an elevated temperature for a period of at least about 1 minute, for a period of from about 5 minutes to about 60 minutes, more typically from about 10 minutes to about 45 minutes, and in some embodiments, 10 minutes to about 20 minutes. It should be noted that the higher tensile force levels and higher temperatures each tend to reduce the duration required to activate and slip the dislocations.

The expansion may be applied to the substrate alone, or it may be applied to the entire heterogeneous structure (i. E., Both the substrate and the hetero layer) as in other embodiments. It is also preferred that the strain forces exerted by the expansion are relatively uniform (in direction and / or size) across the heterogeneous structure (e.g. both radially and circumferentially). It should be noted that the uniformity of the deformation force can be limited by the apparatus used to inflate the substrate and some variations (radial or circumferential variations) can result from uneven stress distribution. In some embodiments, a strain of at least about 5 MPa is applied along the entire circumference of the substrate, or a strain of at least about 10 MPa, as in other embodiments, is applied along the entire circumference of the substrate.

When sufficient strain is applied, dislocations are continuously formed in the dislocation source layer and slid toward the substrate-surface layer interface. At a given point in time during which strain is applied, the dislocations can generally be evenly distributed throughout the thickness of the substrate. Upon reaching the substrate-surface layer interface, dislocations form misfit interfacial dislocations at the interface. The mismatch dislocations increase in density at the interface during substrate expansion and continue to relax deformation between the surface layer and the substrate. Deformation eventually balances when enough density of misfits accumulates.

The dislocations generated in the dislocation source layer and also sliding towards the substrate-surface layer interface are substantially parallel (i.e., transversely aligned) to the back and front of the heterogeneous structure. It is believed that a relatively small amount of threading dislocations are generated in the dislocation source layer or even no threading dislocations are generated in the dislocation source layer.

It is preferred that the substrate expansion be stopped at or near the point at which the deformation is balanced as further generation and slippage of the dislocations can cause the dislocations to penetrate the surface layer. Once the substrate expansion ceases, the potentials in transit on the substrate cease to slip at the interface and no additional potentials are generated (i.e., the potentials are frozen).

The number of potentials that may be present in the substrate at any given point in time at which strain and heat are applied may be at least about 1 x 10 ⁵ dislocations / cm ² or even at least about ⁵ x 10 ⁵ dislocations / cm ² (e.g., ⁵ dislocations / cm ² to 5 x 10 ⁷ dislocations / cm ² , or about ⁵ × 10 ⁵ dislocations / cm ² to about ¹ × 10 ⁷ dislocations / cm ² ). The number density of dislocations is determined using any potential loop detection method, including, for example, sampling a substrate and placing the sample in a delineating etchant before observing and counting dislocation loops through a microscope .

In some embodiments, the deformation force exerted on the substrate by substrate expansion is a value that is of sufficient magnitude to allow existing potentials to slip further toward the interface . In this way, a heterostructure having a substrate substantially free of dislocations can be calculated. In such embodiments, the initial strain S ₁ may be applied to the substrate by substrate expansion to generate and slip dislocations from the source layer to the substrate-surface layer interface. The applied strain is then lowered to S ₂ (i.e., S ₂ is less than S ₁ ). The strain S ₂ is a stress that is below a threshold that allows the potentials to be generated in the potential source layer and also to slip further upward toward the interface to produce a substrate in which the existing potentials are substantially free of potentials. S ₁ may be at least about 5 MPa, at least about 10 MPa, or at least about 25 MPa (e.g., from about 5 MPa to about 100 MPa, or from about 10 MPa to about 100 MPa). S ₂ may be less than about 10 MPa, less than about 5 MPa, or even less than about 1 MPa. Typically, the displacements will also slip at a rate of about 1 micron per second at a temperature of about 850 占 폚 or at a rate of about 2.5 microns per second at a temperature of about 900 占 폚, even at a strain of about 1 MPa.

The magnitude of the deformation force, the time to apply the deformation force, and / or the temperature at which the deformation force is applied to the substrate may vary depending on the difference between the lattice constant a _S of the substrate and the lattice constant a _SL of the semiconductor material of the surface layer. Depending on the selected substrate material and the semiconductor material deposited thereon, a _SL and a _S may vary. In general, when a _SL is greater than a _S , that is, when the ratio a _SL / a _S is greater than 1, the expansion is effective to relax the hetero layer. a _SL / a _S ratio of from about 1.01 to about 1.16, in other embodiments from about 1.01 to about 1.10, from about 1.01 to about 1.08, from about 1.01 to about 1.05, from about 1.02 to about 1.16, 1.05 to about 1.16.

By slipping dislocations to the interface, the surface layer is at least about 85% relaxed, at least about 90% relaxed, at least about 95% relaxed, or even completely relaxed, i.e., 100% relaxed. The surface layer may be substantially free of threading dislocations or may have a concentration of threading dislocations less than about 10 ⁴ threaded dislocations / cm ² .

In embodiments involving discontinuous segments (i.e., islands) in which the surface layer is not continuous but is disposed on the surface of the substrate, the discrete segments are arranged in an island- Lt; RTI ID = 0.0 > a < / RTI > dislocation source layer to the interface. Dislocations reaching the surface of the substrate between the islands are dissipated at the surface, which allows regions between the islands to have substantially no dislocations upon completion of the expansion. After the relaxation of the islands, semiconductor material may be further deposited to yield a continuously extending surface layer over the entire diameter of the substrate. In such embodiments, dislocations under the islands propagate laterally at the interface between the newly deposited material and the substrate, thereby totally relaxing the newly deposited material and the continuous surface layer.

A relaxed heterogeneous structure fabricated by any of the methods described above may be used to fabricate silicon-on-insulator (SOI) structures for integrated circuits using wafer bonding and layer transfer methods or to fabricate subsequently modified SOI structures ≪ / RTI >

Additional layers can be deposited on the relaxed surface layer thereby forming heteroepitaxial structures with a strained layer on the relax layer above the substrate. Such a structure may also be used to transfer both the relaxed layer and the strained layer to another substrate, thereby forming a heteroepitaxial structure with a buried strained layer or alternatively a buried strained layer on the insulator. That is, the heteroepitaxial structure may have a relaxed layer of semiconductor material on a strained layer of semiconductor material over either the substrate or the insulating layer on the substrate.

In addition, structures fabricated by the methods of the present disclosure can be used to fabricate semiconductor devices such as field effect transistors (FETs) or modulation-doped field effect transistor (MODFET) layer structures. Relaxed SiGe layers can also be used for a variety of other applications, such as thermoelectric cooling devices.

V. Expansion device

In this regard, processes described herein in connection with substrate expansion may be performed using any of the devices described below.

Referring now to Figures 3-15, substrate swell can be achieved using a substrate holder comprising chambers and / or fluid passageways for applying differential pressure across the substrate.

Referring now to Figs. 3-4, the inflation of the structure 9 is achieved using the structure holder 11. The structure holder (11) includes a top plate (13). 3-4, the top plate 13 is a ring. The top plate 13 may have other shapes and may extend entirely across the substrate 9 without limitation. The top plate 13 is adapted to contact the front surface of the structure 9 at the circumferential periphery 5 of the structure.

The structure holder 11 includes a rear plate 15 for contacting the rear surface of the structure 9 adjacent the circumferential periphery 5. The rear plate (15) includes a peripheral ring (20) extending upwardly toward the top plate (13). In other embodiments, however, the peripheral ring 20 may be part of the top plate 13, or it may be separate from both the top plate 13 and the back plate 15. Both the back plate 15, the top plate 13 and the peripheral ring 20 are located between the top plate 13, the back plate 15 (including the peripheral ring) and the circumferential periphery 5 of the structure 9 Is adapted to form the peripheral chamber (18). Generally, the rear plate 15 and the top plate 13 form a seal with the structure 9, which ensures that the pressure in the peripheral chamber 18 is relatively high relative to the external pressure to the holder 11, . The circumferential chamber 18 is configured to position the semiconductor structure 9 on the back plate 15 until the seal is formed between the top plate 13, the back plate 15 and the circumferential periphery 5 of the structure 9 And lowering the uppermost plate 13 onto the rear plate 15. [0035]

The holder 11 includes a vent 22 in the rear plate 15 for regulating the pressure in the peripheral chamber 18. Alternatively, the outlet may extend through the front plate 13 and / or the peripheral ring 20. The outlet 22 may be in fluid communication with a pump (not shown) for reducing the pressure in the peripheral chamber 18.

Referring now to Fig. 8, the holder 11 may be part of the device 36 for inflating the structure 9. The device 36 may also include a housing 35 defining a main chamber 27 on which the holder 11 is mounted. The device 36 may include an outlet 32 in fluid communication with a pump (not shown) for adjusting the pressure P ₁ in the main chamber. The outlet (22) in the structure holder (11) extends through the housing (35). In this way, the pressure P ₁ can be held in the main chamber 27 and a different pressure P ₂ can be held in the peripheral chamber 18 of the structure holder 11. By maintaining the pressure P ₁ in the main chamber 27 greater than the pressure P ₂ in the peripheral chamber 18, the structure 9 can be inflated (i.e., the radius of the substrate can be increased).

In this regard, the arrows associated with pressures P ₁ and / or P ₂ in FIG. 3-15 are provided for illustrative purposes, and the apparatus may be operated with a specific pressure profile (i.e., vacuum or pressure in the ambient chamber or main chamber Use) of the product.

During the expansion of structure 9, P ₁ may be at least about 10 MPa greater than P ₂ , or at least about 20 MPa, at least about 50 MPa, or at least about 75 MPa greater than P ₂ , as in other embodiments (E.g., from about 10 MPa to about 100 MPa, from about 10 MPa to about 50 MPa, or from about 10 MPa to about 25 MPa). In some embodiments, P ₁ is the ambient pressure. In such embodiments, the main chamber 27 and the housing 35 can be removed, and the housing can be exposed to the ambient environment (i.e., atmospheric pressure).

The heating element 30 can be used to heat the structure 9 during expansion to activate the dislocation source layer. As described above, the structure can be heated to a temperature of about 650 ° C to about 1000 ° C or to a temperature of about 700 ° C to about 1000 ° C.

Another embodiment of the structure holder 111 is shown in Fig. The holder components shown in Figure 5, similar to those of Figure 3, are designated by adding "100" to the corresponding reference numbers in Figure 3 (e.g., portion 15 becomes portion 115) Be careful. 5, the top plate 113 includes a projection 117 for contacting the front surface 8 of the structure 9. As shown in FIG. The protrusion 117 may form a seal with the structure 9 to allow the pressure in the peripheral chamber 118 to be increased or decreased.

In some embodiments and as shown in FIGS. 6-7, structure 9 has a coating 39 (FIG. 6) or a coating 40 (FIG. 7) on at least a portion of the structural surfaces. The coating 39 extends over a portion of the front surface 8 and the back surface 4 adjacent the circumference 5 and circumferential periphery 5 of the structure 9. As shown in Fig. As shown in FIG. 7, the coating 40 also extends over the entire rear surface 4 of the structure. Alternatively or additionally, the coating may extend over one or more surfaces of the structure holder. Coating 39 or coating 40 (or coating that can be extended over the structure holder) are graphite, hexagonal boron nitride, MS _2, WS _2, SiCN, AlCr (V) n, TiAl (Y) N, CaF ₂ , BaF ₂ , SrF _2, or BaCrO ₄ . In some embodiments, structure 9 has a coating on the structure front that reduces or even prevents evaporation of volatile film components of the structure. Suitable coatings for reducing evaporation include amorphous silicon.

Another embodiment of the structure holder 211 is shown in Fig. The holder components shown in Fig. 9, similar to those of Fig. 3, are designated by adding "200" to the corresponding reference numbers in Fig. 3 (for example, part 15 becomes part 215) Be careful. The uppermost plate 213 of the structure holder 211 is positioned in the middle of the upper surface 213 of the structure 9, Includes Seth. The central chamber 240 is formed by lowering the top plate 213 onto the semiconductor structure 9. The recess is defined by annular wall 242. The recess has a radius that is less than the deformation radius of the structure. As used herein, "strained radius" refers to the radius of the structure before radial expansion (stress deformation) of structure 9 by using structure holder 211.

The top plate 213 includes an outlet 246 in fluid communication with a pump (not shown) to maintain pressure P ₁ in the central chamber 240. In this way, a differential pressure can be maintained between the central chamber 240 and the surrounding chamber 218 to cause the structure 9 to expand radially. By maintaining the pressure P ₁ in the central chamber 240 to be greater than the pressure P ₂ in the peripheral chamber 218, the structure can be expanded. The pressures P ₁ and / or P ₂ may be within the ranges described above.

An embodiment of a self-limiting structure holder for expanding the structure radially is shown in Fig. The holder components shown in Fig. 11 similar to those of Fig. 3 are designated by adding "300" to the corresponding reference numbers in Fig. The rear plate 315 of the structure holder 311 includes a recess defined by an annular wall 352 adapted to limit the expansion of the structure during expansion of the structure. The radius of the recess of the rear plate 315 is larger than the deformation radius of the structure. During the expansion, the radius of the structure 9 increases until the structure contacts the annular wall 352. Upon contact with the annular wall 352, the expansion of the structure 9 ceases.

Another embodiment of a self-limiting structure holder for inflating the structure 9 radially is shown in Fig. The holder components shown in Fig. 12 similar to those of Fig. 3 are designated by adding "400" to the corresponding reference numerals in Fig. The holder 411 includes a perforated wall 455 in the peripheral chamber 418 adapted to limit the expansion of the structure during the expansion of the structure 9. The holes formed in the wall 455 allow pressure to be equilibrated across the peripheral chamber 418. The peripheral wall 455 limits the expansion of the structure 9 during radial expansion.

Another embodiment of a self-limiting structure holder for radially expanding the structure is shown in Fig. The holder components shown in Fig. 13 similar to those of Fig. 3 are designated by adding "500" to the corresponding reference numerals in Fig. The peripheral ring 520 of the rear plate 515 of the structure holder 511 extends relatively close to the relaxed structure before use. During the expansion, the structure 9 extends radially until the structure 9 contacts the peripheral ring 520 to limit the expansion of the structure.

Structure (9) inflation to (i.e., stretch), as an alternative of using a higher pressure in the main chamber or in addition, compression plates (659) (Fig. 10) to apply a downward pressure P ₁ on the structure Can be used. The holder components shown in Fig. 10 similar to those of Fig. 3 are designated by adding "600" to the corresponding reference numbers in Fig. And the pressure P ₂ is maintained in the peripheral chamber 618. P ₂ Is smaller than P ₁ to maintain the differential pressure for expanding the structure (9). As described above, P ₁ At least about 10 MPa greater than P ₂ , or at least about 20 MPa greater than P ₂ in other embodiments, at least about 50 MPa, or at least about 75 MPa (e.g., from about 10 MPa to about 100 MPa, from about 10 MPa to about 50 MPa or about 10 MPa to about 25 MPa). The force can be applied to the structure 9 via the compression plate 659 by any suitable means such as by the use of hydraulics, pneumatics and electrical actuators. The self-limiting features described above may be used in combination with the compression plate 659. [

A structure holder for inflating the structure radially may be adapted to expand the plurality of structures in parallel as shown in Fig. The holder components shown in Fig. 14, similar to those of Fig. 3, are designated by adding "700" to the corresponding reference numbers in Fig. The holder 711 includes a rear plate 715 adapted to contact structures 9a, 9b, 9c, 9d adjacent to the circumferential peripheries of the structures. The holder 711 includes a top plate 713 in contact with structures 9a, 9b, 9c, 9d adjacent to the circumferential peripheries of the structures. The peripheral chamber 718 is formed between the circumferential peripheries of the rear plate 715, top plate 713 and structures 9a, 9b, 9c, 9d. The top plate 713 includes chambers 760 extending to the front of the structures 9a, 9b, 9c, 9d to allow the structures to be exposed to pressure P ₁ in the main chamber (not shown). Ambient chamber 718 is maintained at pressure P < _{2 &} gt ;.

By increasing maintain than P ₁ P _2, the structures (9a, 9b, 9c, 9d ) can be expanded radially. The difference between P ₁ and P ₂ can be at least about 10 MPa and within any of the ranges described above. P ₁ may be atmospheric pressure, and in such embodiments top plate 713 may be a continuous portion that does not include separate chambers 760. Although the substrate holder shown in Fig. 14 is described and shown as having only one rear plate and one top plate, it is also possible for the holder to have a plurality of separate rear plates or top plates ≪ / RTI > It should also be noted that although the substrate holder 711 shown in Fig. 14 is intended to radially expand the four structures, the holder may be arranged such that more or fewer structures can be inflated in parallel without limitation do.

An embodiment of a self-limiting structure holder for processing a plurality of structures is shown in Fig. The holder components shown in Fig. 15, similar to those of Fig. 3, are designated by adding "800" to the corresponding reference numbers in Fig. The rear plate 815 includes a plurality of recesses adapted to receive the structures 9a, 9b, 9c, 9d. The recesses are defined by annular walls 852a, 852b, 852c, 852d. The annular walls 852a, 852b, 852c, 852d serve to limit the radial expansion of the structures 9a, 9b, 9c, 9d.

As well as the devices described above, there is a device which grasps the structure (as is the case for the periphery, for example by the use of clamps or other gripping elements) and also allows the structure to be inflated (stretched) Can be used to relax the heterogeneous structure as such in a device as described below. Referring now to Figures 16-21, the expansion of the structure can be achieved using a structure holder that is relatively radially movable relative to the structure. In such embodiments, the structure holder may be part of an apparatus for expanding the structure. Such an apparatus may be similar to the apparatus 36 shown in Fig. 8 in that the apparatus includes a housing 35 defining a main chamber 27 on which the holder is mounted. The apparatus may include a heating element 30 for heating the structure 9 during expansion by using any of the structures of Figs. 16-21 to activate the dislocation source layer.

Referring now to FIG. 16, the structure holder 1720 may include a plurality of triangular segments 1785 pointing inwardly at a central axis A of the holder. Each segment has at least one fluid passageway 1787 formed therein to attract vacuum to the substrate. Segments 1785 can be mounted for movement outwardly from the central axis A, causing the substrate to expand.

17, the apparatus 911 may be a clamp comprising a front plate 931 and a rear plate 932 that exerts a holding force on the substrate 9. [ As shown in Fig. 17, the uppermost plate 931 and the rear plate 932 are rings. The top plate 931 may have other shapes and extend entirely across the substrate 9 without limitation. The front plate 931 and the rear plate 932 may be moved radially outwardly from the center of the device by any mechanical means, including the use of pneumatics, hydraulics, motors, and the like. It can be possible. It should be noted that such mechanical methods and the like can be used to move any of the front plate and / or rear plate in the structure holder described below.

Referring now to Figure 18, in another embodiment, the structure holder 1011 includes an annular boss 1147 sized and shaped to be received in the groove 1148 at the rear of the structure 9 And includes an overall flat rear plate 1146, The projection 1147 may be movable in such a way that it expands the structure 9.

In some embodiments and as shown in FIG. 19, the structure holder 1120 also includes a front plate 1250 having an annular ring 1252 extending from the front plate. The ring 1252 exerts a downward force on the structure 9 to prevent the structure from peeling off the protrusion 1247 during the expansion of the structure during heating. Other structures for accomplishing this function are also contemplated within the scope of the present invention.

In other embodiments and as shown in FIG. 20, the structure holder 1320 includes a back plate 1346 and protrusions 1347 similar or identical to those shown in FIGS. 18 and 19. The substrate holder 1320 includes a front plate 1351 and a front projection 1355 that is sized and shaped to be received in a groove 1357 at the front of the structure 9.

Referring to Fig. 21, the structure holder 1620 includes an overall flat back plate 1681 and a flange 1683. Fig. Structure 9 includes a ring 1680 attached to the backside of the structure near the peripheral edge of the structure. The flange 1683 is adapted to engage the ring 1680. Support 1681 and flange 1683 are movable relative to the structure to expand the structure.

In some embodiments, the deformation force exerted by the apparatus described above may be such as by reducing the differential pressure across the structure (e.g., by reducing or increasing pressure in the surrounding or main chambers) Lt; Desc / Clms Page number 7 > Such a cycling can relieve any elastic stresses formed in the structure.

As used herein, the terms "about", "substantially", "essentially", and "roughly" refer to a range of dimensions, concentrations, temperatures, Quot; is intended to include variations that may be present at the upper and / or lower bounds of the ranges of properties or properties, including variations due to rounding, measurement methodology or other statistical variations, for example, when used in connection with the present invention.

 When introducing elements of the present disclosure or the preferred embodiment (s) thereof, the singular expressions and "above" are intended to mean that there are one or more of the elements. It is intended that the terms " comprise ", "comprise" and "comprise" are not exclusive, and that there may be additional elements other than the listed elements.

 As various changes may be made in the device and method without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense do.

Claims (57)

A process for relaxing a deformation in a heterogeneous structure comprising a substrate, a surface layer disposed on the substrate, and an interface between the substrate and the surface layer, the substrate having a central axis, a rear surface generally perpendicular to the central axis, A diameter extending across the central axis through the substrate;
Forming a dislocation source layer on the substrate; And
Radially expanding the substrate to generate dislocations and to glide the potentials from the dislocation source layer toward the surface layer
/ RTI > 2. The strain relax process according to claim 1, wherein the dislocations slip into the substrate-surface layer interface and also form mismatch interface potentials at the interface. 3. The strain relax process according to claim 1 or 2, wherein the structure has a diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or even at least about 450 mm. 4. The method according to any one of claims 1 to 3, wherein the substrate is made of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide or any combination thereof ≪ / RTI > 5. A method according to any one of claims 1 to 4, wherein the surface layer is made of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide or any combination thereof A strain relax process comprising a material selected from the group consisting of: 5. The strain relax process according to any one of claims 1 to 4, wherein the surface layer is comprised of silicon germanium. 7. The strain relax process according to claim 6, wherein the substrate is made of silicon. 4. The strain relax process according to any one of claims 1 to 3, wherein the substrate is made of silicon. 9. The strain relax process according to any one of claims 1 to 8, wherein the dislocation source layer is formed by slicing the substrate from an ingot comprising a semiconductor material. 9. The strain relax process according to any one of claims 1 to 8, wherein the dislocation source layer is formed by lapping the back surface of the substrate. 9. The strain relax process according to any one of claims 1 to 8, wherein the dislocation source layer is formed by sand blasting the back surface of the substrate. 9. The strain relax process according to any one of claims 1 to 8, wherein the dislocation source layer is formed by implanting ions into the substrate through the backside of the substrate. 13. The method of any one of claims 1 to 12, wherein the substrate is heated to at least about 550 DEG C while expanding the heterogeneous structure in a radial direction, or at least about 650 DEG C while radially expanding the heterogeneous structure, At least about 700 캜, from about 550 캜 to about 1000 캜, from about 650 캜 to about 1000 캜, or from about 700 캜 to about 1000 캜. 14. The method of any one of claims 1 to 13, wherein a deformation force is applied to the heterogeneous structure during the radial expansion, the deformation force being at least about 5 MPa, at least about 10 MPa, from about 5 MPa to about 100 MPa, MPa to about 100 MPa, from about 10 MPa to about 50 MPa, or from about 10 MPa to about 25 MPa. 15. The strain relax process according to any one of claims 1 to 14, wherein the substrate is radially expanded for a period of at least about 10 seconds, from about 10 seconds to about 5 hours, or from about 10 minutes to about 20 minutes. 16. The strain relaxation process according to any one of claims 1 to 15, wherein radially expanding the substrate comprises radially expanding the heterogeneous structure. 17. The method of any one of claims 1 to 16, wherein a strain S ₁ is applied to the heterogeneous structure during the radial expansion, the process further comprising reducing the strain S ₁ to a strain S ₂ , wherein S ₂ Is less than S &_lt; _{1 &} gt ;, S < ₂ > is a threshold that allows the potentials to fall below the threshold generated at the potential source and to slip toward the substrate-surface layer interface to yield a substrate where existing potentials are substantially free of potentials Deformation relaxation process, which is the overstretching force. The method according to any one of claims 1 to 17, wherein the surface layer is substantially missing are in threading dislocation or about 10 ⁴ threading dislocations / cm ² A strain relax process with a concentration of smaller threading dislocations. 19. The strain relax process according to any one of claims 1 to 18, wherein the surface layer extends continuously across the diameter of the substrate. 19. The strain relax process according to any one of claims 1 to 18, wherein the surface layer comprises discontinuous segments. A process for making a relaxed heterogeneous structure comprising:
Depositing a surface layer on a front surface of a semiconductor substrate, thereby creating a deformation between the surface layer and the substrate; and
20. A method for manufacturing a semiconductor device, comprising: luracing the deformation in the surface layer and the substrate by the process of any one of claims 1 to 20
≪ / RTI > 22. The method of claim 21, wherein the semiconductor substrate has a lattice constant a _S , The surface layer has a lattice constant a _SL , a _SL / a _S A ratio of greater than about 1 to about 1.01 to about 1.16, from about 1.01 to about 1.10, from about 1.01 to about 1.08, from about 1.01 to about 1.05, from about 1.02 to about 1.16, or from about 1.05 to about 1.16 . 24. The method of claim 21 or 22, wherein the surface layer comprises discrete segments, the process further comprising: after the substrate is radially expanded, depositing a semiconductor material on a front surface of the semiconductor substrate, The deposition produces a continuous surface layer on the surface of the substrate. CLAIMS What is claimed is: 1. An apparatus for radially expanding a semiconductor structure having front, rear and circumferential peripheries, comprising:
A structure holder comprising a top plate and a rear plate adjacent to a circumference of the structure for contacting the structure, the top plate being adapted to contact a front surface of the structure and the rear plate adapted to contact the back surface of the structure Wherein the top plate and the rear plate are further adapted to form a circumferential chamber around the circumference of the top plate, the rear plate and the structure,
/ RTI > 25. The apparatus of claim 24, wherein the front plate and the rear plate are adapted to form a seal with the structure to facilitate causing differential pressure across the structure. 26. The apparatus of claim 24 or 25, wherein the structure holder further comprises a peripheral ring, a top plate, a rear plate, and the peripheral ring adapted to form a chamber about a circumference of the structure. A device according to any one of claims 24 to 26, further comprising a main chamber, wherein said structure holder is mounted in said main chamber. 28. The apparatus of claim 27, further comprising a pump in fluid communication with the main chamber to cause a differential pressure between the main chamber and the peripheral chamber. 29. The apparatus of any one of claims 25 to 28, further comprising a pump in fluid communication with the surrounding chamber to cause a differential pressure over the structure sufficient to exert a strain on the structure. 30. Apparatus according to any one of claims 24 to 29, further comprising a heating element for heating the structure. 31. A device according to any one of claims 24 to 30, wherein the structure holder comprises an outlet in fluid communication with the surrounding chamber to pressurize or create a vacuum in the peripheral chamber. 32. The apparatus of any one of claims 24 to 31, further comprising a compression plate for contacting a front surface of the structure to exert a force on the structure. 33. Apparatus according to any one of claims 24 to 32, wherein the top plate comprises a protrusion for contacting a front surface of the structure. 35. Apparatus according to any one of claims 24 to 34, wherein the apparatus is combined with a structure, the structure having a coating adapted to contact the top plate and / or the rear plate. 35. The apparatus of claim 34, wherein the coating does not extend entirely over the front and / or rear surface of the structure. A device according to any one of claims 24 to 35, wherein the top plate comprises a recess adapted to form a central chamber between the top plate and the front surface of the structure. 37. The apparatus of any one of claims 36 to 35, wherein the device is combined with a structure, the recess has a radius, the structure has a radius of deformation, and the radius of the recess is less than the deformation radius of the structure. 38. The apparatus of claim 36 or 37, wherein the top plate includes an outlet in fluid communication with the pump to cause a differential pressure between the central chamber and the peripheral chamber. 39. Apparatus according to any one of claims 24 to 38, wherein the rear plate comprises a recess adapted to receive the structure, the recess being defined by an annular wall, And adapted to limit expansion of the structure during expansion. 40. The apparatus of claim 39, wherein the device is combined with a structure, the recess has a radius, the structure has a radius of deformation, and the radius of the recess is greater than a radius of deformation of the structure. 41. A structure according to any one of claims 24 to 40, wherein the structure holder further comprises a perforated wall in the peripheral chamber, the perforated wall being adapted to limit the expansion of the structure during expansion of the structure Adaptive device. 42. The apparatus according to any one of claims 24 to 41, wherein the apparatus is adapted to radially expand a plurality of semiconductor structures concurrently. 43. The apparatus of claim 42, wherein the back plate is adapted to contact the structures adjacent to circumferential perimeters of the structures, and wherein the structure holder comprises a plurality of top plates. CLAIMS What is claimed is: 1. A method for radially expanding a semiconductor structure in a device, the structure having front, back and circumferential peripheries, the device comprising a top plate and a back plate adjacent to a circumference of the structure for contacting the structure Wherein the top plate is adapted to contact a front surface of the structure and the rear plate is adapted to contact a rear surface of the structure;
Forming a circumferential chamber around the circumference of the top plate, the rear plate, and the structure; And
Varying the pressure in the surrounding chamber to expand the structure radially
/ RTI > 45. The apparatus of claim 44, wherein the ambient chamber comprises:
Placing the semiconductor structure on the back plate; And
The top plate being formed by lowering the top plate
Expansion method. 46. The method of Claim 44 or 45 wherein said pressure is varied by reducing said pressure in said ambient chamber. 46. A method according to any one of claims 44 to 46, wherein the device comprises a main chamber in which the structure holder is mounted, the method comprising generating a differential pressure between the main chamber and the peripheral chamber . 48. The method of claim 47, wherein the pressure in the main chamber is at least about 10 MPa greater than the pressure in the peripheral chamber, or at least about 20 MPa, at least about 50 MPa, at least about 75 MPa From about 10 MPa to about 100 MPa, from about 10 MPa to about 50 MPa, or from about 10 MPa to about 25 MPa. 49. The method of Claim 47 or 48, comprising varying the pressure in the main chamber by increasing the pressure in the main chamber. 50. A method according to any one of claims 44 to 49, further comprising heating the structure during radial expansion of the structure. 52. A method according to any one of claims 44 to 50, wherein the device comprises a compression plate, the method further comprising the step of contacting the front side of the structure by the compression plate to exert pressure on the structure Lt; / RTI > 52. A method according to any one of claims 44 to 51, wherein said top plate comprises a recess defined by an annular wall, said method comprising:
Forming a central chamber between the top plate and the front surface of the structure; And
Changing the pressure in the central chamber by increasing the pressure in the central chamber
/ RTI > 53. The method of any one of claims 44 to 52, wherein the back plate comprises a recess defined by an annular wall, the method comprising:
Positioning the semiconductor structure on the rear plate in the recess; And
Radially expanding the structure with the annular wall
/ RTI > 55. A method according to any one of claims 44 to 53, wherein the structure holder further comprises a perforated wall in the peripheral chamber, the method comprising the step of radially expanding the structure into the peripheral chamber. 55. A method according to any one of claims 44 to 54, wherein a plurality of semiconductor structures are radially expanded in parallel. 56. The method of claim 55, comprising positioning a plurality of structures on the back plate and lowering one or more top plates over the structures. 55. A method according to any one of claims 44 to 56, wherein the semiconductor structure comprises a substrate and an epitaxial layer, wherein the substrate and the epitaxial layer form a substrate-epitaxial layer interface.

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