JP3347848B2 - Multi-level signal decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit for decoding a multilevel data transmission signal in a packet format.

[0002]

2. Description of the Related Art In a wired or wireless transmission system for transmitting a multi-level signal, a transmission line and a transmission / reception circuit are transmitted to a multi-level signal decoding circuit by the influence of environmental conditions such as ambient temperature and power supply voltage. Of the input baseband signal and the DC center level fluctuate, which directly leads to the reduction of the noise margin. If this fluctuation is large, an error occurs in the determination in the decoding circuit. Therefore, usually, a circuit design and a mechanism design are performed so as not to be affected by external factors such as an ambient temperature and a power supply voltage as much as possible. However, the higher the achievable performance is, the higher the manufacturing cost necessarily becomes. . For this reason, automatic amplitude control circuit,
The application of an automatic correction circuit of the DC center level to the fluctuation of the DC center level can be considered, but each of them generally operates on a specific signal, for example, a bit synchronization signal at the head of a packet. A negative feedback control loop must be formed. Therefore, in order to stabilize the operation of this loop, a certain period of time is required until the operation of the loop converges, and this operation is completed before the start of the multi-value signal as data information. Therefore, if high stability and high accuracy are required for the operation of the automatic control loop, a long training time is required as much as possible, and transmission efficiency is reduced.

[0003] Further, utilizing the fact that a bit synchronization signal is generally transmitted as a sine wave, the DC center level and amplitude are detected from a signal for one or two cycles, and a multi-level signal is used by using both. There is a method of creating a reference voltage for signal decoding. According to this method, a reference voltage that changes in accordance with a change in an input signal is obtained, and the time required to generate the reference voltage is extremely short. Therefore, there is no disadvantage that the transmission efficiency is reduced. However, because the integration circuit and the detection circuit are used without the negative feedback control loop, it is necessary to design and structure these circuits with high accuracy and high stability.
After all, you cannot escape the fate of having to find a compromise between performance and manufacturing cost.

[0004]

As described above, in the transmission of a digital multi-level signal, the DC level and amplitude of the input signal to the decoding circuit are controlled so as not to be affected by various environmental conditions. There is a limit on the transmission efficiency in the method of maintaining, and in the method of creating a decoding reference voltage according to the fluctuation of the DC center level and the amplitude of the input signal using an integration circuit or a detection circuit, high performance (accordingly, high cost) It is necessary to use the circuit of.

An object of the present invention is to create a decoding reference voltage directly from an input signal using an extremely simple circuit, thereby achieving a very simple and high-performance multi-level signal without the disadvantage of a reduction in transmission efficiency. It is to provide a decoding circuit.

[0006]

DISCLOSURE OF THE INVENTION In the transmission of a digital signal, usually, 128 bits are used to detect a code error due to the transmission.
Bytes to 1024 bytes long (10 bytes for 8-bit code)
A signal in the form of a packet (also called a burst or a block) divided into codes of about 24 bits to 8192 bits in length is used. In order to extract and reproduce a clock required for demodulation and decoding on the receiving side from the received signal, the head of the packet signal is usually 2 bits.
A bit synchronization signal having a length of several bits to several tens of bits is transmitted by alternately repeating values (usually transmitted by a sine wave for effective use of the transmission bandwidth). According to the present invention, the bit synchronization signal transmitted by the sine wave is simply sampled and held to obtain the decoding reference voltage, so that the reference voltage corresponding to the fluctuation itself of the input signal is obtained. With an extremely simple circuit, accurate decoding can always be performed.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows a configuration example of the packet signal. At the beginning of the packet, first, a bit synchronization code indicated by A is transmitted in a length of several bits to several tens of bits. This signal is
As described above, the signal is usually a binary repetition signal, but is substantially a sine wave (240 when the synchronization code is 4800 bps).
0 Hz), and even when transmitting multi-valued data, the header portions of A, B, C, and D in FIG. 2 are usually transmitted as binary signals having an amplitude equal to the maximum amplitude of the multi-valued data portion. You. Since the bit synchronization code A is transmitted in a sine wave analog waveform, the analog waveform is hereinafter referred to as a bit synchronization signal. As described above, the bit synchronization signal has a maximum amplitude and a constant amplitude, and this amplitude is equal to the maximum amplitude of the multi-level data signal, and the waveform is a sine wave. Therefore, the sine wave is sampled at an appropriate time. Thus, a sampled output pulse having a voltage equal to the reference voltage required for decoding can be obtained, and if this voltage is held during the packet section and used as the reference voltage, the reference voltage can be directly created from the input signal. Thus, a correct decoding operation can always be maintained.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a transmission path, for example, wireless FSK
In the case of (frequency shift keying), it is the output of the frequency discrimination circuit, and in the case of wired transmission, it is the reception input signal terminal and the input terminal of the multilevel baseband signal. 2 is a decoded signal output terminal decoded into a digital signal, 3 is a bit synchronization signal rising detection circuit, 4 is a sampling and holding circuit, 5 is a control pulse generation circuit, 6 is a reference frequency generator, and 7 is a decoding circuit. .

There are various types of multi-level signals.
4800p clock speed with 4 values for easy explanation
ps, that is, the case of a data transmission speed of 9600 bps will be described. FIG. 3 is a waveform example of a quaternary signal, showing a case where there is no error in the center level and the amplitude. The waveform A in FIG. 3 shows the waveform of the bit synchronization signal portion in FIG. 2, the waveform E shows the waveform of the quaternary data signal portion, and P ₀ shows the sampling pulse for decoding created by the control pulse generation circuit. . Decoding circuit, the voltage of the sampled waveform during E is, if the reference voltages V ₁ or more outputs "1 1", if during the reference voltages V ₁ and V ₂ a "1 0", V ₂ if there is between the V ₃ "0 1"
The, if V ₃ following outputs "0 0". As is apparent from FIG. 3, the reference voltages V ₁ , V ₂ , and V ₃ are set to the respective central voltages of adjacent two values of the four-value input signal in order to maximize the noise margin. Is desirable. Therefore, even when the DC center level or amplitude of the input signal changes, each reference voltage may be changed and moved so as to maintain the above-described voltage relationship in accordance with the change.

Before explaining the circuit configuration and the outline of its operation,
First, the principle of the present invention will be described for easy understanding. FIG. 4 is a waveform diagram showing the time relationship between the bit synchronization signal waveform and the sampling pulse waveform. FIGS. 7A and 7B show two examples in which the DC center level and the amplitude are different, but the decoding reference voltages V ₁ , V ₂ , and V ₃ for each are different from each other as shown. However, A, B, as apparent from comparison of three waveforms C, and pulse P ₁ or if sampling and holding the waveform of the upper at P ₄ V ₂ is obtained, the pulse P ₂ or P ₃ V ₁ if the sampling and holding is, since the pulse P ₅ or V ₃ when sampling and holding at P ₆ is obtained, if created even correct sampling pulse, always correct reference voltage will be obtained. For the sampling pulse, for P ₁ or P ₄ , P ₂ or P ₃ and P ₅ or P ₆ are obtained from the zero-cross (rising or falling) information of the signal obtained by removing the DC offset component from the received bit synchronization signal. Is V ₁
-V ₂ between voltage and V ₃ -V ₂ between voltages of the peak voltage 2 /
3, P ₁ or P _{4 is} converted to sin ⁻¹ (2 /
Since the time is 3) apart (shown as a phase angle in FIG. D), they can be easily created as described later.

Hereinafter, a circuit configuration and an operation outline thereof will be described. When the signal having the waveform shown in FIG. 3 is applied to the input signal terminal 1 in FIG. 1, the entire operation starts with the operation of the bit synchronization signal rising detection circuit 3 first. FIG.
Is a circuit configuration diagram of the bit synchronization signal rising detection circuit 3. In FIG. 5, 8 is an AC coupling circuit, 9 is a shaping circuit, 10 is a shift register, 11 is a coincidence detecting circuit, 12
Is a flip-flop, 13 is a gate circuit, and 14 is a rise detection circuit. The AC coupling circuit 8 is configured such that the phase difference between the input and output of the bit synchronization signal at 2400 Hz is zero by using a combination of a high-pass filter and a phase shift circuit or a band-pass filter.
Therefore, even if the DC center level of the input signal is not zero, the DC offset is eliminated by the AC coupling circuit 8 and is applied to the shaping circuit 9 with the DC center level being zero as shown in the waveform A of FIG. Here, it is shaped into a rectangular wave. This rectangular wave is transmitted from the control pulse generation circuit 5 to 4800
pps clock pulse, the shift register 10
Are sequentially read. The content of each stage of the shift register is examined by the coincidence detection circuit 11, and if "1" and "0" are alternately arranged in the required number of bits, a coincidence output is obtained. The coincidence output sets the flip-flop circuit 12 and sets the gate. The circuit 13 opens. As a result, a 2400 Hz sine wave having no DC offset is applied to the rise detection circuit 14, where a zero-cross time from the negative to the positive of the sine wave is detected, and a pulse is output at this time. This detection output pulse resets the flip-flop circuit 12 and is sent to the control pulse generation circuit 5 as a rising detection pulse. Although the rising time of the sine wave is detected here, the falling time may be detected as described later.

FIG. 6 shows an example of the internal circuit configuration of the control pulse generation circuit 5. 6, 15, 16, 17 are gate circuits, 18, 19, 20, 21 are shaping circuits, 27 is a flip-flop circuit, 22, 23, 24, 25 are selection circuits, and 26 is a frequency dividing circuit. When a rising edge detection pulse is applied from 3, the flip-flop circuit 27 is set and the gate circuits 15, 16, 17 open, and at the same time, the frequency dividing circuit 26 is reset. A reference signal with higher accuracy (frequency error of about 1 × 10 ⁻⁶ ) than the reference frequency oscillator 6 is added to this frequency divider circuit. Every time the synchronization signal comes), the content of the frequency dividing circuit (content as a binary counter) instantaneously becomes zero, and the operation of restarting counting from there is repeated. Now, if the reference frequency is 307.2
Assuming that the frequency is 1 kHz, the frequency dividing circuit 26 has just 128 counts (0 to 0) during one cycle of the bit synchronization signal 2400 Hz.
127 counts). Assuming that the sampling pulses generated by the control pulse generation circuit are P ₃ , P ₄ , and P ₅ in FIG.
The times t ₃ , t ₄ , and t ₅ from P ₁ are t ₃ = {π-sin ⁻¹ (2/3)} / π · ・ 800 = 159.942 μs t ₄ = 1/4800 = 208.333 μs t ₅ = {π + sin ⁻¹ (2/3)} / π · 1/4800 = 256.725 μs. Since the frequency dividing circuit 26 counts on the basis of the rising time P ₁ of the bit synchronization signal, the above-mentioned t ₃ ,
The counts performed at times closest to t ₄ and t ₅ are, respectively,
49th, 64th, a 79th, if their time and _{t c49, t c64, t c79} , they _{t c49 = 1/2400 · 49} /128 = 159.505μs t c64 = 1/2400 Since 64/128 = 208.333 μs t _c79 = 1/2400 and 79/128 = 257.161 μs, each can be used with an error of 0.5 μs or less. The selection circuit 23 selects the input reference frequency signal at the 49th count, the selection circuit 24 selects the input reference frequency signal at the 64th count, and the selection circuit 25 selects the 79th count. It can be configured by taking the AND of the output of each stage and the input reference frequency signal. Selection circuit 2
The output pulses of 3, 24 and 25 are 1,628 μm, respectively.
s (1 / 2.1 / 307.2 ksec), these pulses are shaped into pulses of the time width required by the sampling circuit in the shaping circuits 19, 20, and 21 and then gated. The signals are sent to the sampling / holding circuit 4 as sampling pulses P ₃ , P ₄ , and P ₅ through the circuits 15, 16, and 17. The flip-flop circuit 27 outputs the sampling pulse P
₅ , the gate circuits 15, 1
6 and 17 are closed until the next packet signal is generated.
In the above description, the reference frequency was selected to be 307.2 kHz. However, if this frequency is selected to be a higher frequency and the number of frequency dividing stages is increased accordingly,
The time error of the sampling pulse can be reduced.
In this way, control pulses P ₃ , P ₄ , P ₅ (sampling pulses) and decoding pulse P ₀ are obtained in a time relationship with the bit synchronization signal as shown in FIG. The decoding pulse P ₀ is a pulse generated by the selection circuit 22 and the shaping circuit 18 in FIG. 6 so that pulses are generated at the 32nd and 96th counts in the same manner as described above. This occurs at the time when the peak becomes positive and negative, and at the time when the data signal correctly takes any one of four values.

The sampling pulse P thus obtained is
₃ , P ₄ and P ₅ sample the input bit synchronization signal in the sampling / holding circuit 4 and hold the voltage. The sampling and holding circuit, as shown in FIG. 7, the reference voltages V ₁ through P ₃ is, V ₂ by P ₄ is, V ₃ is configured so as to obtain respectively by P _5, the holding output is It is applied to the decoding circuit 7 as a reference voltage.

FIG. 8 is a diagram showing the internal circuit configuration of the decoding circuit 7. In FIG. 8, reference numeral 28 denotes a sampling / holding circuit;
0 and 31 are comparators, and 32 is a selector. Sampling and holding circuit 28, the decoded pulse P ₀ applied from the control pulse generating circuit 5, and sample the input signal (Fig. 7E), and holds the voltage until the next sampling value is obtained. This operation will be described with reference to FIG. A dotted line 28 shown in FIG. 9 is an output waveform of the sampling / holding circuit 28.
Since V ₁ , V ₂ , and V ₃ are added to the comparators 29, 30, and 31 from the sampling and holding circuit 4 as reference voltages, the outputs thereof are 29, 30, and 3 in FIG.
A signal having the waveform shown in FIG. 29 and 31 are added to a selector 32. Here, when 30 is "1", 29 is added.
At the time of "0", 31 is selected, so that the output of the selector 32 becomes a signal as shown at 32 in FIG. The outputs of the comparator 30 and the selector 32 are correctly decoded outputs, and are supplied to the decoded signal output terminal 2.

In the above, the case where P ₃ , P ₄ , and P ₅ are used as the sampling pulses for obtaining the decoding reference voltage has been described as an example.
Of course, P ₁ , P ₂ , and P ₅ may be used, and it is also possible to detect the fall of the bit synchronization signal and generate a sampling pulse based on this time. Of course, it may be possible.

Although the above description has been made with reference to the decoding of a quaternary data signal as an example, as will be apparent from the description of the operation, the present invention can be similarly applied to the decoding of other multi-valued data signals. For example, in the case of an 8-level data signal, if the amplitude (peak value) of the bit synchronization signal is 1.0, the decoding reference voltages are V ₁ = 6/7, V ₂ = 4/7, and V ₃ = 2
_{/ 7, V 4 = 0,} V 5 = -2 / 7, V 6 = -4 / 7, V 7 =
V ₁ may be set to −6/7, but at the time when sin ⁻¹ (6/7) = 59.0 ° of the sine wave of the bit synchronization signal, V _1
4 can be obtained by sampling and holding each at the rise time of the sine wave. If V ₁ and V ₄ are obtained, all the reference voltages can be easily created by a circuit as shown in FIG. 10, 33 are operational amplifiers, as all resistors R same resistance value, if Kuwaware is V ₁ and V ₄ obtained by the above method in this circuit, 2V ₄ -V to the output of the operational amplifier 33 ₁ is obtained. If this voltage and V _x, is a 2V ₄ -V ₁ = V _x, is subtracted the V ₄ from both sides, because the _{V 4 -V 1 = V x -V} 4, V x, i.e. operation This means that V ₇ is obtained from the output of the amplifier 33. Therefore, as shown in FIG. 10, if V ₁ , V ₄ , and V ₇ are divided by resistors, all necessary voltages can be obtained.

In the above description, the reference frequency should be increased in order to reduce the time error of the sampling pulse. However, a correct reference voltage can be created by the following method. . That is, in the quaternary description example, when the reference frequency is 307.2 _kHz , t ₃ -t _c49 is 0.437 _μs. However, when there is a time error, the sampling output voltage is sin · ｛(t _{c64 -t c49) / t c64} ·} π = a 0.67156, is the output of 1.00734 times the correct voltage (2/3 = 0.66666). Therefore, the sampled output voltage difference due t _C49 and t _c64 1 / 1.0
By multiplying by 0734, a reference voltage without error can be obtained. If this method is used, the frequency dividing circuit can be simplified by lowering the reference frequency. When this method is advanced to the extreme, the following method is obtained. That is, in FIG. 4, instead of P ₂ and P ₃ , the center of the two,
That is, if the center of the two peaks, ie, the negative peak values, is sampled instead of the positive peak values P ₅ and P ₆ , these V
Since the voltage from the ₂ is the peak amplitude value itself, the positive peak value V _{P +,} if the negative peak value V _{P- and, V 1 = 2/3 (} V P + -V 2) + V 2 V 3 _{= 2/3 (V P- -V} 2) as + V _2, it is possible to obtain a correct reference voltage V _1, V _3.
These calculations can be easily realized by an operational amplifier. In this last method, since a positive peak value and a negative peak value may be obtained, a positive peak hold circuit and a negative peak hold circuit can be used instead of the sampling circuit.

[0018]

As described above in detail, according to the present invention, in decoding a multilevel data transmission signal in packet format, the decoding reference voltage simply samples and holds the bit synchronization signal in the header of the packet. Since it is created only with the reference signal, it can be decoded with a very simple circuit. Even if the DC center level and amplitude of the received signal fluctuate, the decoding reference voltage is created directly from the received signal. On the other hand, a relatively correct decoding reference voltage is always obtained, and the noise margin can always be maintained at the maximum.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an example of a packet structure for explaining the contents of a packet of a transmission signal applied to the present invention.

FIG. 3 is a waveform diagram showing a relationship between a waveform of a quaternary signal and a decoding reference voltage.

FIG. 4 is a waveform diagram for explaining a process of generating a decoding reference voltage directly from a bit synchronization signal.

FIG. 5 is a circuit configuration diagram of a rising edge detection circuit of a bit synchronization signal which is one of the components of the embodiment of FIG. 1;

FIG. 6 is a circuit configuration diagram of a control pulse generation circuit which is one of the components of the embodiment of FIG.

FIG. 7 is a waveform diagram for explaining a time relationship between an input signal and an output pulse of a control pulse generation circuit.

FIG. 8 is a circuit configuration diagram of a decoding circuit which is one of the components of the embodiment of FIG. 1;

FIG. 9 is a waveform chart for explaining the operation of the decoding circuit of FIG. 8;

FIG. 10 is a circuit diagram showing an example of generating a reference voltage for decoding an 8-level signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multi-level data signal input terminal 2 Decoding signal output terminal 3 Bit synchronization signal rising detection circuit 4 Sampling / holding circuit 5 Control pulse generation circuit 6 Reference frequency generator 7 Decoding circuit 8 AC coupling circuit 9 Shaping circuit 10 Shift register 11 Match Detection circuit 12 Flip-flop circuit 13 Gate circuit 14 Rise detection circuit 15 Gate circuit 16 Gate circuit 17 Gate circuit 18 Shaping circuit 19 Shaping circuit 20 Shaping circuit 21 Shaping circuit 22 Selection circuit 23 Selection circuit 24 Selection circuit 25 Selection circuit 26 Frequency division circuit 27 Flip-flop circuit 28 Sampling / holding circuit 29 Comparator 30 Comparator 31 Comparator 32 Selector 33 Operational amplifier

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-55943 (JP, A) JP-A-52-6452 (JP, A) JP-A-4-175039 (JP, A) JP-A-4- 22239 (JP, A) JP-A-56-154858 (JP, A) JP-A-52-39305 (JP, A) JP-A-62-193335 (JP, A) Japanese Utility Model Laid-open No. 62-112237 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 25/00-27/38

Claims (6)

(57) [Claims] A multi-level signal decoding circuit for decoding a multi-level data signal in a packet format detects repetition of "1, 0" of a bit synchronization signal included in the transmitted multi-level data signal in a packet format. A bit synchronization signal rise or fall detection circuit for detecting a rise or fall time of the bit synchronization signal based on the detected output, a control pulse generation circuit for generating a sampling pulse based on the detection time, A sampling and holding circuit for sampling and holding the bit synchronization signal by using the sampling pulse, and a decoding circuit for decoding the multi-level data signal using the sampling and holding output as a decoding reference voltage. Multi-level signal decoding circuit. 2. The method according to claim 1, wherein the detecting circuit detects a time when the bit synchronization signal matches a predetermined repetition sequence of “1, 0” as a time of a zero crossing point of the bit synchronization signal. Item 2. The multilevel signal decoding circuit according to Item 1. 3. The multi-level signal decoding circuit according to claim 2, wherein said detection circuit includes means for removing a DC offset of said bit synchronization signal before detecting said coincidence. 4. The control pulse generation circuit according to claim 1, wherein the control pulse generation circuit starts counting when receiving the timing signal at the detection time, and a predetermined waveform position from a detected rising or falling position of the waveform of the bit synchronization signal. 4. A multi-level signal decoding circuit according to claim 1, further comprising means for forming said sampling pulse in response to occurrence of a predetermined count value of said counter means representing the timing of the multi-level signal decoding. . 5. The multi-level signal decoding circuit according to claim 4, further comprising means for detecting occurrence of a predetermined count value of said counter and forming a decoding pulse in response thereto. 6. An arithmetic means for receiving the sampling / holding output and forming a decoding reference voltage exceeding the number of sampling / holding outputs in accordance with the DC level difference based on the sampling / holding output. The multi-level signal decoding circuit according to any one of claims 1 to 5, wherein: