JPH0687286B2 - Digital data generator - Google Patents

Description

The present invention relates to a digital recording / reproducing system using a magnetic recording medium such as a digital audio tape recorder, and more particularly to the magnetic recording medium. The present invention relates to an improvement of a digital data generation device for converting a reproduction signal obtained from the original digital data.

(Prior art) As is well known, in the field of audio equipment, information signals such as audio signals are digitalized by PCM (Pulse Code Modulation) technology in order to achieve high-density and high-fidelity recording and reproduction. A digital recording / reproducing system in which data is converted and recorded in a recording medium such as a magnetic tape or a disk and reproduced is widely used.

Among them, the one using a magnetic tape as a recording medium is called a digital audio tape recorder. For example, a fixed head type in which a plurality of heads are arranged in the width direction of the tape and a head having a circumferential side There is a rotary head type in which a tape is wound around a cylindrical drum provided so as to rotate along with a helical scan.

Here, FIG. 11 shows a portion related to the recording / reproducing operation of such a digital audio tape recorder.
First, the recording operation will be described. The analog information signal supplied to the input terminal 11 is converted into digital data by the A / D (analog / digital) conversion circuit 12. This digital data is subjected to predetermined digital processing such as parity generation and formatting in the signal processing circuit 13, and is subjected to specific modulation so that the polarity reversal interval falls within a predetermined width. It is converted into modulated data as shown in (a).

Then, this modulated data is guided to the 1/2 divider circuit 14,
As shown in FIG. 12 (b), after the modulation data is converted into the recording data whose polarity is inverted by "1", the recording amplifying circuit
The data is supplied to the recording head 16 and the recording head 16, and the data is recorded on the tape 17 there.

On the other hand, during reproduction, the data recorded on the tape 17 is read by the reproduction head 18 as an electric reproduction signal. This reproduction signal has a characteristic that it has a positive peak level at the rising edge of the recorded data and a negative peak level at the falling edge. Then, the reproduction signal is supplied to the post-equalization circuit 20 via the reproduction amplification circuit 19, and the twelfth
As shown in FIG. 6C, a data conversion circuit is used as equalized data in which a deviation (so-called peak shift) between the polarity inversion point of the recorded data and the peak level position of the reproduction signal is corrected.
It is output to 21.

The data conversion circuit 21 converts the input equalized data into binary digital data. First, the equalized data is converted by the level comparison circuits 22 and 23 into a pair of positive and negative reference levels + V1,-. Compare the levels with V1 respectively. Therefore, the level comparison circuits 22 and 23 output the comparison data as shown in FIGS. 12 (d) and 12 (e), respectively. These comparison data are output by the OR circuit 24
As shown in FIG. 12 (f), the logical sum is obtained and the peak position detection data is supplied to the input terminal D of the D type flip-flop circuit (hereinafter referred to as the D-FF circuit) 25.

On the other hand, the equalized data is supplied to the differentiating circuit 26 and converted into differential data that crosses the zero level at the peak level position of the equalized data, and then the level comparing circuit 27 compares it with the ground level (that is, zero level). By performing the level comparison, data whose polarity is inverted at the peak level position of the equalized data is generated. This data is supplied to the detection circuit 28 together with the comparison data of the level comparison circuits 22 and 23, after removing unnecessary noise components, and then supplied to the PLL (phase locked loop) circuit 29, as shown in FIG. A bit synchronous clock as shown in g) is generated.

Then, the D-FF circuit 25 extracts the peak position detection data supplied to the input terminal D in synchronization with the rising edge of the bit synchronization clock, and as shown in FIG. Digital data corresponding to the modulated data is generated.

In this way, the digital data generated by the data conversion circuit 21 is supplied to the signal processing circuit 13 together with the bit synchronization clock and subjected to predetermined digital processing such as demodulation and error correction, and then D / A ( It is converted to the original analog information signal by the digital / analog) conversion circuit 30 and output terminal 31
The data recorded on the tape 17 is output to an analog reproducing system (not shown) via the tape.

By the way, the conventional means for generating digital data using the data conversion circuit 21 as described above does not cause any problem as long as the recording / reproducing characteristics with respect to the tape 17 and the adjustment of each part are extremely ideal. is there. However, in an actual recording / reproducing system, it is often the case that accurate recording of digital data occurs because the recording / reproducing characteristics change due to noise mixing, spacing, etc., and the adjustment of each part is often still insufficient for the ideal state. There are many obstacles.

For example, if adjustment of the equalization circuit 20 is insufficient or high frequency deterioration due to spacing occurs, equalization obtained by reproducing the tape 17 on which the recording data shown in FIG. 13 (a) is recorded. Due to waveform interference, the waveform of the data has a non-uniform peak level or a wider width than the ideal waveform shown by the dotted line, as shown by the solid line in FIG.

Therefore, the peak level of the equalized data is the reference level + V
1, -V1 is not exceeded, and the level comparison circuit 22,2
The comparison data output from 3 and the peak position detection data output from the OR circuit 24 are shown in FIGS. 13 (c) to 13 (e).
, And the digital data extracted from the peak position detection data with the bit synchronization clock shown in (f) of FIG.
An error occurs as compared with that shown in FIG. 12 (a).

In this case, if the reference levels + V1 and -V1 are brought close to zero level, accurate peak position detection data can be obtained even if the peak level of the equalized data is low. However, as shown in FIG. 14 (a), when the reference level + V1, -V1 is brought close to zero level, the level of the noise component mixed in the equalized data may exceed the reference level + V1, -V1. Become.

Therefore, the peak position detection data includes a noise component as shown in FIG. 14 (b), and the peak position detection data is digital data extracted by the bit synchronization clock shown in FIG. 14 (c). However, as shown in FIG. 12D, an error occurs as compared with that shown in FIG. 12A.

(Problems to be Solved by the Invention) As described above, in the conventional digital data generating means, it is not possible to generate accurate digital data due to factors such as noise contamination, spacing, and insufficient adjustment of the equalization circuit. It has the problem of not being.

Therefore, the present invention has been made in consideration of the above circumstances, and even if various factors that hinder the generation of accurate digital data occur, accurate digital data is generated without being affected by those factors. It is an object of the present invention to provide an extremely good digital data generation device to be obtained.

[Configuration of Invention] (Means for Solving Problems) That is, the digital data generating device according to the present invention is
The reproduction signal is compared with a pair of first reference levels of positive and negative (positive or negative with reference to a zero level or an intermediate level of the reproduction signal) and a pair of second reference levels of positive and negative different from the first reference level. The polarity data indicating the positive / negative polarity of the reproduction signal (zero level or the polarity compared with a predetermined reference level) is generated, and each level comparison data and the polarity data are extracted in synchronization with a predetermined clock.

Then, it is detected that, in the extracted data, the comparison data component with the first reference level has a portion that violates a predetermined modulation rule applied to the digital data or the normal characteristic of the reproduction signal. Then, the correction processing is performed on the basis of the remaining extracted data components.

(Operation) Then, according to the above-mentioned configuration, in the extracted data, the comparison data component with the first reference level has the normal modulation rule or reproduction signal of the digital signal applied to the digital data. Since the occurrence of the portion that violates the characteristics is detected and corrected based on each of the remaining extracted data components, even if various factors that prevent the generation of accurate digital data occur, It is possible to accurately generate digital data without being affected by the factor of.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as those in FIG. 11 are designated by the same reference numerals, and only different parts will be described here. That is, the equalized data output from the equalizing circuit 20 is supplied to the reference level + V by the level comparing circuits 22 and 23.
Not only level comparison with 1, -V1 but level comparison circuit
32 and 33 compare the levels with a pair of positive and negative reference levels + V2 and -V2, which are closer to the zero level than the reference levels + V1 and -V1, respectively, and the level comparison circuit 34 compares the levels with the ground level (zero level). .

Therefore, if equalization data as shown in FIG. 2A is output from the equalization circuit 20, the OR circuit 24 outputs peak position detection data as shown in FIG. From the OR circuit 35, which takes the logical sum of the comparison data output from the level comparison circuits 32 and 33, FIG.
The peak position detection data as shown in is output. Further, the level comparison circuit 34 outputs comparison data as shown in FIG. 2 (d).

The peak position detection data output from the OR circuits 24 and 35 and the comparison data output from the level comparison circuit 34 are supplied to the input terminals D1 to D3 of the latch circuit 36, respectively. The latch circuit 36 extracts each data supplied to its input terminals D1 to D3 at the rising edge of the bit synchronizing clock shown in FIG. 2 (e) output from the PLL circuit 29, and outputs each output terminal Q1. ~ Output from Q3.

Therefore, the output terminals Q1 to Q3 of the latch circuit 36 generate digital data as shown in FIGS. 2 (f) to (h), respectively. Here, the latch circuit
The digital data output from the output terminals Q1 and Q2 of 36 are referred to as first candidate data and second candidate data, respectively, and the digital data output from the output terminal Q3 of the latch circuit 36 is
It will be referred to as polarity data indicating the positive and negative polarities of the equalized data.

The first and second candidate data and the polarity data generated as described above are supplied to the control circuit 37 and used for final generation of digital data. This control circuit 37, as shown in FIG. 3, is a read-only memory circuit (hereinafter referred to as ROM) 3
8 to 41, selector circuits 42 to 44, D-FF circuits 45 to 55, and exclusive OR circuits (hereinafter referred to as EX-OR circuits) 56 and 57.

Then, the control circuit 37, the input terminal 58 ~ 60 to the first,
By supplying the second candidate data and the polarity data respectively, the first candidate data is used as a reference to detect a portion or the like of the first candidate data that violates the later-described modulation rule or the normal characteristic of the equalized data. The first candidate data is corrected based on the second candidate data and the polarity data to generate final digital data, which is output from the output terminal 61.

That is, the digital data output from the A / D conversion circuit 12 is converted into modulation data by the signal processing circuit 13, but in this modulation method, when the data bit interval is T, the polarity inversion interval is It modulates digital data so as to enter one of 1T, 2T, and 3T, and for example, a 4/5 modulation method is used. Therefore, if the first candidate data is normally obtained, the polarity reversal interval is 1T to 3T.
The modulation rule is that it falls within the range of.

Further, the equalized data has a positive peak level at the rising edge of the recording data and a negative peak level at the falling edge of the recording data. Therefore, if normal, the positive peak level and the negative peak level alternate. It has the characteristic of being generated.

Therefore, it is possible to obtain accurate digital data by detecting a portion that violates the modulation rule of the first candidate data or the normal characteristic of the equalized data as described above and performing a correction process on the first candidate data. Is something that can be done.

Here, the conversion tables as shown in the following table are stored in the ROMs 38 to 41, respectively. These conversion tables are set in consideration of the modulation rule and the characteristics of equalized data so that the control circuit 37 can perform the above-mentioned correction operation.

The selector circuits 42 to 44 are connected to the output terminals D1 and D0 of the ROM 38.
When "0,0" is output, the data supplied to the input terminal "0" is output. When the output terminals D1 and D0 are "0,1", the data supplied to the input terminal "1" is output and output. When the terminals D1 and D0 are "1,0", the data supplied to the input terminal "2" is output and the output terminals D1 and D0 are "1,"
When it is 1 ", it outputs the data supplied to the input terminal" 3 ".

Further, each of the D-FF circuits 45 to 55 performs a latch operation in synchronization with the bit synchronization clock output from the PLL circuit 29.

When the first candidate data shown in FIG. 2 (f) is supplied to the input terminal 58, assuming that the output terminals D1 and D0 of the ROM 38 are "0,0", the selector circuits 42 to 44 will be described. Outputs the data supplied to the input terminal "0", so the addresses A3 to A of ROM38
0 becomes “1,0,0,1” as shown in FIG. 2 (i).
Then, the control circuit 37 performs a process of determining whether or not the first candidate data "1,0,0,1" is correct based on the second candidate data and the polarity data.

That is, the second candidate data indicates the positive and negative peak level positions of the equalized data during the H level period, the polarity data indicates that the equivalent data is in the positive region at the H level, and the equal data at the L level. The converted data is in the negative region. Therefore, the second candidate data and the polarity data are supplied to the address A3 of the ROM 38. It is determined that "1" corresponds to the positive peak level position of the equalized data, and "1" supplied to the address A0 of the ROM 38 is determined to correspond to the negative peak level position of the equalized data. To be done.

Therefore, it is understood that the above-described condition that the positive and negative peak levels of the equalized data are alternately generated is satisfied.

However, “0,” supplied to addresses A2 and A1 of ROM38
For 0 "data, there is a possibility that it was not detected because the level was too low even though there were negative peak level and positive peak level in the equalized data. There is a suspicion that it is 1 ".

Therefore, based on the second candidate data and the polarity data, it is again determined whether or not the positive and negative peak levels of the equalized data are present in the "0,0" portion. And in this case, since there is no peak level, this “1,0,0,
The first candidate data "1" is output to the output terminal 61 as accurate digital data.

Although the control circuit 37 performs the above operation, when the first candidate data “1,0,0,1” is supplied to the addresses A3 to A0 of the ROM 38, the output terminal D1, D0 becomes "1,0", and the selector circuits 42 to 44 output the data supplied to the input terminal "2".

Then, in the state where the above-mentioned determination results are complete, the ROM 40
Since the data "1,1,1,1,0,0" is supplied to the addresses A5 to A0, the data "0,0" is output from the output terminals D1 and D0. Therefore, the first candidate data is directly output to the output terminal 61 without being corrected.

Next, as shown in FIG. 2 (j), the address A3 of the ROM 38 is
When the first candidate data "1,0,1,0" is supplied to ~ A0,
Similarly to the above, the characteristic of the equalized data is determined from the second candidate data and the polarity data. In this case, it is determined that "1" supplied to the addresses A3 and A1 of the ROM 38 both correspond to the negative peak level of the equalized data. As described above, the continuous occurrence of the negative peak level violates the characteristic of the equalized data, and thus the first candidate data “1,0,1,0” is determined to be erroneous. .

Looking at the second candidate data and the polarity data, the positive peak level of the equalized data is between the “1” and “1” of the first candidate data “1,0,1,0”. The data “0” between the “1” and “1” of the first candidate data “1,0,1,0” that has been detected is determined to be “1” and correction processing is performed. Accurate digital data as shown in FIG. 2 (k) is generated.

That is, on the control circuit 37, the address A3 of the ROM 38 is
When the first candidate data "1,0,1,0" is supplied to ~ A0,
The output terminals D1 and D0 become "0,1", and the selector circuits 42 to 44
Will output the data supplied to the input terminal "1". Then, when the above-mentioned determination results are complete, RO
Since the data “0,0” is supplied to the addresses A1 and A0 of the M39, the data “1” is output from the output terminal D0. Therefore, the first candidate data “1,0,1,0” has “1” and “1”.
The data "0" between and is corrected to "1".

Even if the first candidate data is "1,0,1,1", similar correction processing is performed if the second candidate data and the polarity data have the same conditions as above.

As described above, the first candidate data is “1,0,1, *” and “1,0,0,1”
However, what kind of correction process is performed for each pattern of the first candidate data when the second candidate data and the polarity data are in different states, respectively. This is shown in FIGS. 4 and 5, respectively. The waveforms shown by the dotted lines in Fig. 4 and Fig. 5 show ideal equalization data. * Mark may be either "1" or "0", and ☆ mark may be "1" depending on polarity. It's good.

The polarity inversion interval of the first candidate data is set to fall within the range of 1T to 3T according to the above-mentioned modulation rule. Therefore, there should be no more than three "0" s. Therefore, the control circuit 37 detects that the first candidate data has a pattern of "1,0,0,0" in addition to the above-described two types of patterns, and performs the same correction processing as above. It is made possible to do.

FIG. 6 shows what kind of correction process is performed when the second candidate data and the polarity data are in different states when the first candidate data is a pattern of "1,0,0,0". Is shown.

In the above embodiment, when the reproduced signal includes a DC (direct current) offset component, the DC offset component is removed in advance before level comparison, or the reference level shown in FIGS. 1 and 2 is used. ± V1 and ± V2 are DC
The shift will be performed in consideration of the offset component. Further, in the comparison in the level comparison circuit 34 for generating the polarity data, it is not necessary to set the comparison level to a pure zero level, and for example, the above-mentioned reference level + V2 or − near a zero level (or an intermediate level). It may be compared with V2 (substituting the output of the level comparison circuit 32 or 33). Further, the clock for extracting the first candidate data, the second candidate data, and the polarity data is not limited to the bit synchronization clock generated from the reproduction signal as described above, but a rate much higher than the data rate, for example. The asynchronous clock may be used, and if the recording / reproducing method is such that the clock signal is reproduced together with the reproduced signal, the reproduced clock signal may be used.

Next, FIG. 7 shows a modification of the above embodiment.
That is, this is dealt with when a so-called peak shift PS occurs, in which the peak level position of the equalized data shown in FIG. 8B is deviated from the time when the polarity of the recorded data shown in FIG. It was done like this.

In this case, the respective data output from the OR circuits 24 and 35 and the level comparison circuit 34 shown in FIGS.
The latch circuit 36 is extracted by the rising edge of the bit synchronization clock φ1 shown in FIG.
Outputs the first and second candidate data and the polarity data as shown in FIG.

On the other hand, from the PLL circuit 29, as shown in FIGS. 8 (h) and 8 (i), respectively, a bit synchronization clock φ2 with a phase advance of 1/4 period with respect to the bit synchronization clock φ1 and
A bit synchronous clock φ3 with a delayed periodic phase is generated. Then, in synchronization with the rising edges of these bit synchronization clocks φ2 and φ3, the OR circuit 3 is set by the D-FF circuits 62 and 63.
By extracting the output data of 5 respectively, D-FF
The data shown in FIGS. 8 (j) and 8 (k) are output from the circuits 62 and 63.

Here, the second candidate data output from the latch circuit 36 and the data output from the D-FF circuits 62 and 63 are ORed to the OR circuit 64 and supplied to the input terminal D2 of the latch circuit 65. To do. The latch circuit 65 has the input terminals D1 and D3 supplied with the first candidate data and the polarity data output from the latch circuit 36, and is output from the PLL circuit 29 and has the half cycle of the bit synchronization clock φ1. Each input data is extracted and output from the output terminals Q1 to Q3 at the rising edge of the bit synchronization clock φ4 shown in FIG.

Therefore, from the output terminals Q1 to Q3 of the latch circuit 65,
New first and second candidate data and polarity data as shown in FIG. 7M are obtained and output to the control circuit 37. Then, among the new first candidate data, “1,0,0,
The pattern "0" is shown in FIG. 8 (n) based on FIG.
The data is corrected to "1,0,1,1" as shown in.

After that, the new first candidate data “1,0,1” including the above-mentioned corrected data is shown in FIG. 8 (o) based on FIG.
It is corrected as shown in. Further, the new first candidate data “1,0,0,1” including the corrected data is corrected as shown in FIG. 8 (p) based on FIG. The corrective operation is repeated, and the control circuit 37 outputs digital data as shown in FIG. 8 (q).

According to the configuration shown in FIG. 7, the peak position detection data output from the OR circuit 35 is provided with the reference bit synchronizing clock φ1 and the bit synchronizing clocks φ2 and φ3 whose phases are shifted before and after that. Since the second candidate data extracted only by the bit synchronization clock φ1 can be further supplemented by the extraction by the and, the digital data can be generated more accurately without being affected by the peak shift PS. It is a thing.

Next, FIG. 9 shows still another modification of the embodiment shown in FIG. That is, the equalized data is compared by the level comparison circuits 66 and 67 with a pair of positive and negative reference levels + V3, -V3 closer to the zero level than the reference levels + V2, -V2.
And the comparison data is ORed by the OR circuit 68 and supplied to the latch circuit 69.

The latch circuit 69 extracts the output data from the OR circuits 24 and 35 and the level comparison circuit 34 together with the output data of the OR circuit 68 at the rising edge of the bit synchronization clock. Then, the output data component of the OR circuit 68 extracted by the latch circuit 69 becomes the third candidate data.

In this case, with respect to the equalized data shown in FIG. 10A, the first to third candidate data and the polarity data are as shown in FIG. Then, the control circuit 37 uses the pattern "1,0,0,0" of the first candidate data as shown in FIG. 10 (c) by using the second candidate data based on FIG. Correct the data to "1,0,0,1".

After that, the control circuit 37 tries to correct the new first candidate data “1,0,0,0” including the corrected data by using the second candidate data. The combination that satisfies all the second candidate data and the polarity pattern is the sixth combination.
It cannot be corrected because it is not shown in the figure.

At this time, the control circuit 37 replaces the second candidate data with the third candidate data.
Correction processing is performed using the candidate data. That is, the case where the first candidate data is “1,0,0,0”, the third candidate data is “1,1,1,0”, and the polarity data is “0,1,0,0” The correction process will be performed. In this case, the polarity data is “1,0,1,1” when the equalized data is folded back to the zero-level contrast, so that the control circuit 37 ends up based on FIG. As shown in FIG. 3D, the correction processing can be performed on the data “1,1,1,0”.

The present invention is not limited to the above embodiment. In addition, various modifications can be made without departing from the scope of the invention.

[Effect of the Invention] Therefore, as described in detail above, according to the present invention, even if various factors that hinder the generation of accurate digital data occur, accurate digital data can be obtained without being affected by those factors. It is possible to provide a very good digital data generation device that can perform generation.

[Brief description of drawings]

1 and 2 are a block configuration diagram showing an embodiment of a digital data generating apparatus according to the present invention and a timing diagram for explaining the operation thereof, respectively, and FIG. 3 is a specific diagram of the main part of the embodiment. FIG. 4 is a block diagram showing the configuration, FIGS. 4 to 6 are diagrams showing the relationship of correction processing for various patterns of equalized data, and FIGS. 7 and 8 are block configurations showing modified examples of the same embodiment. FIG. 9 is a timing diagram for explaining the operation thereof, FIGS. 9 and 10 are block configuration diagrams showing another modified example of the same embodiment, and timing charts for explaining the operation thereof, FIG. 11 and FIG. FIG. 12 is a block diagram showing a recording / reproducing operation of a digital audio tape recorder and a timing diagram for explaining the operation. FIGS. 13 and 14 are conventional digital data recording devices. It is a timing chart for explaining a problem of a data generation means. 11 …… input terminal, 12 …… A / D converter circuit, 13 …… signal processing circuit, 14 …… 1/2 divider circuit, 15 …… recording amplifier circuit, 16
...... Recording head, 17 ...... tape, 18 ...... Playback head, 19
...... Reproduction amplifier circuit, 20 …… equalization circuit, 21 …… Data conversion circuit, 22,23 …… Level comparison circuit, 24 …… OR circuit, 2
5 …… D-FF circuit, 26 …… differential circuit, 27 …… level comparison circuit, 28 …… detection circuit, 29 …… PLL circuit, 30 …… D / A conversion circuit, 31 …… output terminal, 32 ～ 34: Level comparison circuit, 35
...... OR circuit, 36 ...... Latch circuit, 37 ...... Control circuit, 38
~ 41 …… ROM, 42 ～ 44 …… Selector circuit, 45 ～ 55 …… D
-FF circuit, 56,57 ... EX-OR circuit, 58-60 input terminal, 61 ... output terminal, 62,63 ... D-FF circuit, 64 ... OR circuit, 65 ... latch circuit, 66,67 …… Level comparison circuit, 68 …… OR circuit, 69 …… Latch circuit.

Claims (1)

[Claims] 1. A digital data generating device for reproducing a recording medium on which digital data modulated according to a predetermined rule is recorded and generating original digital data from the reproduced signal reproduced. Polarity data generating means for generating polarity data indicating the positive and negative polarities of the reproduced signal; first level comparing means for comparing and outputting a level of the first reference level and the reproduced signal; and the first reference level. Second level comparing means for comparing and outputting the level of the reproduction signal and a second reference level different from the above, and output signals output from the first and second level comparing means and the polarity data generating means. In synchronization with a predetermined clock and outputting first, second and third extraction signals respectively, and when the first extraction signal is different from the modulation rule, the first extraction signal is changed to the second extraction signal. A digital data generation device, comprising: a correction unit that corrects the extracted signals of 3 and 3.