JP3171205B2 - Modulation frequency detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a modulation frequency of a digital signal transmitted by being channel-coded (digitally modulated).

[0002]

2. Description of the Related Art An EIAJCP-IC is used as an interface for serial data transmission and self-synchronous transmission for interconnection between digital audio devices.
340 are known.

In this digital audio interface standard, a bi-phase mark system is used as a channel coding system as a modulation system. 4A and 4B are diagrams for explaining the bi-phase mark code. FIG. 4A is a modulation clock (double bit rate), FIG. 4B is NRZ code expression source data, and FIG.
Is the bi-phase mark code.

As can be seen from FIG. 1, the bi-phase mark code is such that when one cycle of the modulation clock is T (１ ／ bit clock cycle), the source data “1”,
This is a modulation method in which “0” is represented by whether the inversion time of the signal “1” or “0” is 1T cycle or 2T cycle. In FIG. 4C, “1” of the source data is represented by 1T in the period of the inversion time of the signal “1” and “0”, and “0” of the source data is “1” and “0” of the signal. Cycle of the reversal time of
It is represented as T.

In this bi-phase mark system, the total of the length of the time interval of "1" and the total of the length of the time interval of "0" of the signal become equal, and the DC of the transmission line becomes equal.
This is a modulation method that can minimize the (DC) component. Further, this is a modulation method in which clock reproduction from a transmission signal is easy.

FIG. 6 shows a standard signal format of the digital audio interface. That is, the example of FIG. 6 is an example in which the digital audio data is 2-channel stereo, and one block is composed of 192 frames from frame 0 to frame 191.

[0007] One frame is composed of two subframes. In the case of this two-channel stereo, the first subframe of one frame has channel 1
(For example, the left channel), and channel 2 (for example, the right channel) is assigned to the latter subframe. The subframe is composed of 32 bits (64 modulation clocks).

Then, a preamble as additional data is inserted as the first 4 bits of each subframe.
The preamble is used for synchronizing and identifying subframes and blocks. As the preamble, a special pattern which does not appear as the bi-phase mark code of the data is used.

In this case, the preambles of the two subframes have different patterns in order to identify the first half subframe and the second half subframe of one frame. Also, 1
The preamble of the subframe at the head of the block also uses a different pattern to distinguish it from other subframes. Therefore, three types of synchronization patterns B, M, and W are prepared as preambles.

FIG. 7 shows preambles B, M, and W of these three types of patterns. As shown in the figure,
Depending on whether the preceding symbol data as the biphase mark code is “0” or “1”, two types of patterns are set for each of the preambles B, M, and W.
Basically, the patterns are the same except that the signal polarities are different.

As shown in FIG. 7, the preamble B is inserted into the head subframe of the block and is used for synchronization and identification of the block. The preamble M is a subframe in the first half of each frame, and is inserted into a subframe other than the head of the block. Further, the preamble W is inserted into the second half subframe of each frame. These preambles M and W are used for subframe synchronization and identification.

As can be seen from FIG. 7, these preambles B, M, and W have a pattern of 3T in which the first polarity inversion interval does not appear as biphase mark code data when viewed at the polarity inversion interval. FIG. 5 shows the pattern of the preamble M among them. In FIG.
A is the modulation clock, FIG. 5B is the pattern of the preamble M when the preceding symbol is “0”, and FIG. 5C is the pattern of the preamble M when the preceding symbol is “1”. This preamble M is a pattern including a pattern in which the polarity inversion interval of 3T is continuous twice.

In the standard of the digital audio interface described above, the modulation clock frequency of the transmission signal is not particularly defined. Usually, when the transmission signal is received, the modulation clock frequency is identified from the received data, and the sampled signal is sampled. The sampling frequency (the modulation clock frequency is 128 times the sampling frequency) is detected.

Conventionally, the identification of the modulation clock frequency is performed using the synchronization patterns of the preambles B, M, and W.

That is, as described above, since the polarity inversion interval period having a length of 3T exists in the pattern of any of the preambles B, M, and W, the modulation is performed by measuring the time of 3T. The clock frequency was detected.

[0016]

When digital audio data is transmitted, for example, recorded on a magnetic tape and reproduced, the reproduced signal (received signal) is shown in FIG.
Since the signal has a sine wave shape as shown in A, the reproduced signal must be shaped into a rectangular shape before the bi-phase mark code is restored from the reproduced signal. This waveform shaping method is performed by using the DC level of the reproduction signal as a threshold value and comparing the threshold value with the reproduction signal.

In this case, since the DC level of the biphase mark code is 0, the threshold value for comparison is 0.
However, if a DC offset occurs in a transmission system (recording / reproducing system) or a receiving element, or a DC offset exists in a threshold voltage, the relative level relationship between the threshold value and digital data is changed. Because of the fluctuation, the period in which the signal becomes “1” and the period in which the signal becomes “0” cannot be correctly restored, and time distortion occurs.

For example, in FIG. 8A, when the threshold value is th1, the interval of signal "1" or "0" (polarity inversion interval) is correctly reproduced as shown in FIG. 8B. Is shifted like th2, time distortion occurs in the interval between "1" and "0" of the signal as shown in FIG. 8C.

As described above, when time distortion occurs, the conventional modulation clock frequency detection method measures only the 3T time of the signal polarity inversion interval, so that the 2T data portion is preambled. That is, erroneous detection of detecting a synchronization pattern may occur.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to enable accurate detection of a modulation frequency at all times even when a transmission signal has a cause of time distortion.

[0021]

In order to solve the above-mentioned problem, the invention according to claim 1 is characterized in that the cycle of the inversion time of the binary data is 1T (T; one cycle of the modulation clock) or 2T cycle. For converting the binarized data represented by the formula (1) into blocks each having a predetermined length, and detecting the frequency of the modulation clock from a data sequence in which a predetermined pattern having an inversion time period of 3T or more is inserted between the block data. A frequency detecting circuit, counting means for counting an interval from a rising edge of the polarity inversion of the data string to the next rising edge; and a counting means for counting the interval from the rising edge of the polarity inversion of the data string counted by the counting means to the next rising edge. Memory means for storing the maximum value of the interval; the maximum value stored in the storage means; and the rising edge of the polarity inversion of the data string newly counted by the counting means. Comparing means for comparing the interval from the first rise to the next rise, and the comparing means, wherein the interval from the rise of the polarity inversion of the data string newly counted by the counting means to the next rise is stored in the memory means. When it is determined that the maximum value is larger than the stored maximum value, the maximum value stored in the memory unit is changed from the rising of the polarity inversion of the data sequence newly counted by the counting unit to the next value. It is characterized by comprising a maximum value updating means for updating at intervals until the rise, and a detecting means for detecting the frequency of the modulation clock based on the maximum value stored in the memory means. Also,
The cycle of the inversion time of the binary data is 1
T (T; one cycle of a modulation clock) or 2T cycle, binarized data is divided into blocks every predetermined length, and a period of an inversion time is 3T between the block data.
A modulation frequency detection circuit that detects the frequency of the modulation clock from the data sequence in which the above-described predetermined pattern is inserted, and a counting unit that counts an interval from a fall of the polarity inversion of the data sequence to the next fall. Memory means for storing the maximum value of the interval from the fall of the polarity inversion of the data sequence counted by the counting means to the next fall; the maximum value stored in the storage means; and the counting means Comparing means for comparing the interval between the fall and the next fall of the polarity inversion of the data string newly counted in the data string; and the comparing means, wherein the polarity of the data string newly counted by the counting means is used. When it is determined that the interval from the falling edge of the inversion to the next falling edge is larger than the maximum value stored in the memory means, the memory means A maximum value updating unit that updates the stored maximum value at an interval from the falling edge of the polarity inversion of the data sequence newly counted by the counting unit to the next falling edge; and the memory unit stores the maximum value. Detecting means for detecting the frequency of the modulation clock based on the local maximum value.

[0022]

By the way, as shown in FIG. 8, when the transmission signal can be a rectangular wave with a duty of 50% (the biphase mark code is so), the DC level and the threshold value of the transmission signal When a DC offset occurs between the data, even if a time distortion occurs in the polarity inversion interval of the signal, the interval from the rise of this data to the next rise or the interval from the fall of the data to the next fall, that is, One period TP of the square wave does not change,
It is an accurate value.

In the present invention having the above-described configuration, instead of measuring the polarity reversal interval of the signal, the interval from the rising edge of the signal causing no time distortion to the next rising edge, or the falling edge of the signal to the next falling edge. Measure the interval up to. Then, as the maximum value of the interval, a predetermined pattern having a length of 3T or more inserted in the signal (having a period of 6
An interval from the rise of the portion (length of T or more) to the next rise or an interval period from the fall of the signal to the next fall is detected.

That is, in the case of the above-described digital audio interface, the length of one period of the pattern of the preamble M is detected. Then, the modulation frequency is identified based on the measurement result of the interval.

[0025]

FIG. 1 is a block diagram showing an embodiment of a modulation frequency detecting circuit according to the present invention. This embodiment is based on the digital audio interface standard EIAJ CP-3.
This is a case where the present invention is applied to the case of No. 40. In the case of this example, the interval 6T (six modulation clocks) from the rising edge of the preamble M to the next rising edge or from the falling edge to the next falling edge is measured. Detect frequency.

In FIG. 1, reference numeral 11 denotes a rising counter which measures an interval from the rising of the input bi-phase mark code to the next rising. Reference numeral 12 denotes a falling counter, which measures the interval from the falling of the bi-phase mark code to the next falling.

Reference numeral 13 denotes a selector, 14, 15, and 1
7 is a latch circuit. The selector 13 is a counter 11
Alternatively, it is for selectively supplying the measurement value of the counter 12 to the latch circuit 14.

Reference numeral 16 denotes a comparator which compares the output data of the latch circuit 14 with the output data of the latch circuit 15 and, when the output value of the latch circuit 14 is larger than the output value of the latch circuit 15, The content of the latch circuit 15 is rewritten to the output value of 14. The latch circuits 14 and 15 and the comparator 16 constitute a maximum value detection circuit for the measured value of the interval between the rise and fall of the signal, and the latch circuit 15 latches the maximum value.

In the case of this example, the preamble M is a pattern in which a 3T “1” (or “0”) period and a 3T “0” (or “1”) period are continuous, and the preamble M has a rising edge and a next rising edge. The period from the rise or fall to the next fall is 6T, which is the longest period in the data of the input bi-phase mark code. Therefore, the latch circuit 15 latches the measured value at the interval of 6T between the rising and falling of the signal of the preamble M pattern portion.

A sampling frequency identification circuit 18 detects a modulation clock frequency of an input bi-phase mark code from the local maximum value latched by the latch circuit 15, and identifies a sampling frequency based on the detected output. The latch circuit 17 transfers the local maximum value of the latch circuit 15 to the sampling frequency identification circuit 18 at an appropriate timing.

As the sampling frequency identification circuit 18, for example, a magnitude comparator or the like can be used. That is, since the correspondence between the measured value of the interval 6T, the modulation clock frequency, and the sampling frequency is determined in advance, the output value of the latch circuit 17 is compared with a plurality of threshold values. The modulation clock frequency and the sampling frequency are identified depending on whether they are between the threshold values.

Note that the sampling frequency can be detected because it is 128 times the modulation clock frequency as described above. The circuit 18 is not limited to the configuration of the magnitude comparator, but may employ various other configurations.

Further, reference numeral 10 denotes a timing generation circuit, from which a latch signal for the latch circuits 14, 15 and 17 and a reset signal for the counters 11 and 12 are generated.

Next, the embodiment of FIG. 1 will be described in more detail with reference to the signals of the respective sections shown in FIG.

That is, bi-phase mark code data IBPD of audio data is supplied to the timing generation circuit 10 through the input terminal 1. Also, the high-speed clock IMCK
Is supplied to the timing generation circuit 10 through the input terminal 2 and the counters 11 and 12 and the selector 1
3. It is supplied to the latch circuits 14 and 15. Further, the data clock signal IBCK is supplied to the timing generation circuit 10 through the input terminal 3 and is also supplied to the latch circuit 17.

Further, a signal MXTK for determining the latch timing of the latch circuit 17 is supplied to the timing generation circuit 10 through the input terminal 4. This signal MKTK
Is a low-period signal including the preamble M, for example, a 2-frame period signal.

[0037] Then, when a trailing on wants input Bi-Phase Mark data IBPD from the input terminal 1, in synchronism with the on the rising and the clock IMCK, rising reset pulse RSRR is generated from the timing generating circuit 10, which counter 11 reset terminal. Therefore, the rising counter 11 counts the clock IMCK from the rising of the bi-phase mark code data IBPD to the next rising. Therefore, the counter 11
Is the measured value of the interval from the rise of the bi-phase mark code data IBPD to the next rise.

When the bi-phase mark data IBPD falls, the fall reset signal RSFF is generated from the timing generation circuit 10, whereby the fall counter 12 is reset. Therefore, the counter 12 sets the interval between the falling edge of the bi-phase mark code data IBPD and the next falling edge by the clock IMCK.
Will be measured.

The timing generation circuit 10 generates a select signal SELQ obtained by shaping the bi-phase mark code data IBPD by the clock IMCK. This select signal SE
The LQ is supplied to the selector 13 as a selection control signal. When the select signal SELQ is “0”, the selector 13 selects the output count value of the counter 12 as an output, and the select signal SELQ is “1”. At times, the output count value of the counter 11 is selected as an output.

In the timing generation circuit 10, a latch load pulse LDT generated in response to the falling or rising of the biphase mark code data IBPD is generated and supplied to the latch circuit 14.

That is, if we follow in time, first,
When the bi-phase mark data IBPD rises, a latch load pulse LDT is obtained, and the count value of the rising counter 11 (measured value of the interval from the rising one immediately before the rising to the rising) is selected by the selector 13.
Is latched by the latch circuit 14 via

Immediately after the latch, a rising reset signal RSRR is generated from the timing generation circuit 10, whereby the counter 11 is reset, and measurement during the next rising is started. That is, before the counter 11 is reset, the measured value of the interval from the rise of the biphase mark code data IBPD to the rise is latched by the latch circuit 14 every time the data IBPD falls.

Similarly, when the bi-phase mark code data IBPD falls, a latch load pulse LDT is obtained, and the count value of the fall counter 12 (from the fall immediately before the fall to the fall) is obtained. The measured value of the interval) is supplied to the latch circuit 14 via the selector 13.
Latched.

Immediately after the latch, a falling reset signal RSFF is generated from the timing generation circuit 10, whereby the counter 12 is reset, and measurement during the next falling is started. That is, before the counter 12 is reset, the measured value of the interval from the fall of the biphase mark code data IBPD to the fall is latched by the latch circuit 14 every time the data IBPD falls.

The latch circuit 14 has a select signal
SELQ is also latched and bi-phase mark code data IBPD
Is used as reference data for the polarity of.

In this way, the data IBPD
The measured value of the interval from rising to rising and the measured value from falling to falling are latched. The latch output DSEL of the latch circuit 14 is supplied to the latch circuit 15.

To the latch circuit 15, a pulse obtained one clock before the clock IMCK from the latch load pulse LDT from the timing generation circuit 10 is supplied as a latch load pulse via the gate circuit 19. However, the output CPMX of the comparator 16 is supplied to the gate circuit 19 as a gate control signal, and only when the gate circuit 19 is ON, the latch load pulse LDMX is supplied to the latch circuit 15 to perform a latch operation.

In this case, the comparator 16 includes the latch circuit 1
4 and the output SEMX of the latch circuit 15 are supplied, and the values of the two are compared. When the output value of the latch circuit 14 becomes larger than the output value of the latch circuit 15, the output CPMX of the comparator 16 turns on the gate circuit 19.

Thus, only when the value of the output DSEL of the latch circuit 14 becomes larger than that of the last time, the latch circuit 15 latches the larger value. Therefore, the latch circuit 15 latches the local maximum value of the measured value of the interval from the rising edge to the rising edge of the biphase mark code data or the local maximum value of the measured value of the interval from the falling edge to the falling edge. Become.

Then, from the timing generation circuit 10,
Further, the latch circuit 1 receives the data clock signal IBCK from the input terminal 3 and the signal MXTK having a two-frame period, for example.
7 is obtained, whereby the maximum value of the measured value of the latch circuit 15 is latched by the latch circuit 17. Latch load pulse LTMX is preamble M
Is included in the latch circuit 17, the interval from the rise to the rise or the interval from the fall to the fall of 6T of the preamble M is latched as the maximum value.

The maximum value PHMX of the measured value transferred to the latch circuit 17 in this manner, that is, the measured value of the preamble M portion at the interval of 6T is supplied to the sampling frequency identification circuit 18. The sampling frequency identification circuit 18 detects the modulation clock frequency as described above, and identifies the sampling frequency as 128 times the modulation clock frequency.

As described above, according to this example, the 6T interval of the preamble M is measured as the maximum value of the interval between rising edges or the maximum value of the interval between falling edges of biphase mark code data. The modulation clock frequency is detected based on the measured value of the interval of 6T. In this case, the time interval between the rising and falling edges of the bi-phase mark code data does not change even if a DC offset occurs in the data or the threshold value for waveform shaping, and is an accurate value. Therefore, the modulation clock frequency can be accurately detected.

The select signal SELQ latched by the latch circuit 14 is also transferred from the latch circuit 14 to the latch circuits 15 and 17 and is supplied to the sampling frequency identification circuit 18 as polarity information of the data IBPD. This makes it possible to perform polarity inversion and polarity conversion of the signal.

Using the output of the sampling frequency identification circuit 18, a clock signal for decoding and the like are formed.
That is, FIG. 3 shows a circuit for generating a clock signal using the output of the sampling frequency identification circuit 18.

In FIG. 3, the bi-phase mark code IBPD data through the input terminal 21 is
And is decoded into source data, for example, NRZ data, based on a data clock formed as described later, and is output to an output terminal 23.

The bi-phase mark code data IBPD through the input terminal 21 is supplied to a synchronization pattern (preamble pattern) detection circuit 24. In this case, the polarity detection signal of the bi-phase mark code data is supplied to the synchronization pattern detection circuit 24 from the sampling frequency identification circuit 18. Further, a synchronous pattern detection circuit 2
4 is supplied with a clock formed as described later, and the circuit 24 sets the polarity inversion interval to 3T based on the clock.
Is detected in the preamble, that is, the synchronization pattern, and the detection output is supplied to the phase comparison circuit 33.

Reference numeral 31 denotes a variable frequency oscillating circuit (hereinafter referred to as VCO) for generating a data clock, and its output signal is supplied to a counter circuit 32 constituting a variable frequency dividing circuit.
Supplied to The sampling frequency identification circuit 18 gives a plurality of preset values necessary for the counter circuit 32 based on the modulation clock frequency and the sampling frequency detected as described above. That is, the frequency division ratio is set in each of the plurality of counter circuits 32 as variable frequency dividing circuits.

Then, signals of various frequencies are obtained from the counter circuit 32. One of the signals is as follows.
A signal of a preamble cycle, that is, a subframe cycle is obtained, and is supplied to the phase comparison circuit 33. In the phase comparison circuit 33, the synchronization pattern detection output of the sub-frame cycle from the synchronization pattern detection circuit 24 and the signal of the sub-frame cycle from the counter circuit 32 are compared.
4, the oscillation output signal of the VCO 31 is controlled so that the output of the synchronous pattern detection circuit 24 and the output of the counter circuit 32 have a fixed phase relationship.

That is, the VCO 31 obtains a clock signal that is phase-synchronized with the synchronization pattern (preamble) of the input bi-phase mark code data IBPD. From the counter circuit 32, signals obtained by dividing the output of the VCO 31 are obtained, and a decoding clock signal is supplied to the data decoder 22.
This is used for decoding.

The above example is a case where the present invention is applied to a detection circuit for detecting the modulation frequency of a digital audio signal. However, it goes without saying that the present invention can be used to detect the modulation frequencies of various data transmission signals.

[0061]

As described above, according to the present invention, the period of the inversion time of the binary data is 1T (T;
One value of lock) or 2T period
Data is divided into blocks at a predetermined length, and
Pattern with an inversion time period of 3T or more between
Frequency of the modulation clock from the data sequence
In the modulation frequency detection circuit that detects
The pole of the interval from the rise of the sex reversal to the next rise
The maximum value is detected, and the modulation clock is detected based on the maximum value.
Since it is a configuration that detects the frequency, a relatively simple configuration
Thus, a more accurate modulation frequency can be detected.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a modulation frequency detection circuit according to the present invention.

FIG. 2 is a timing chart showing waveforms of respective units in the example of FIG.

FIG. 3 is a block diagram of an example of a clock generation circuit using a modulation frequency detection circuit according to the present invention.

FIG. 4 is a diagram for explaining a bi-phase mark code.

FIG. 5 is a diagram for explaining a pattern of a preamble M;

FIG. 6 is a diagram illustrating a signal format of an example of a digital audio interface.

FIG. 7 is a diagram for explaining a preamble pattern.

FIG. 8 is a diagram for explaining an influence of a DC offset on a signal.

[Explanation of symbols]

 11 Rise counter 12 Fall counter 13 Select 14 Latch circuit 15 Latch circuit 16 Comparator 18 Sampling frequency identification circuit

Continuation of the front page (56) References JP-A-58-19054 (JP, A) JP-A-59-80047 (JP, A) JP-A-58-209253 (JP, A) JP-A-59-138155 (JP, A) JP-A-3-76344 (JP, A) JP-A-61-19058 (JP, A) JP-A-63-296425 (JP, A) JP-A-2-13150 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 25/49 H04L 7/00

Claims (2)

(57) [Claims] 1. The cycle of the inversion time of binary data is 1T.
(T: one cycle of modulation clock) or 2T cycle, binarized data is divided into blocks every predetermined length, and a predetermined pattern having an inversion time period of 3T or more is formed between the block data. A modulation frequency detection circuit that detects a frequency of the modulation clock from the inserted data sequence, a counting unit that counts an interval from a rising edge of the polarity inversion of the data train to the next rising edge, Memory means for storing a local maximum value of the interval from the rising edge of the polarity inversion of the data string to the next rising edge; the local maximum value stored in the storage means; and the data string newly counted by the counting means. Comparing means for comparing the interval from the rising edge of the polarity inversion to the next rising edge; and When it is determined that the interval from the rising edge of the polarity inversion of the data string to the next rising edge is larger than the maximum value stored in the memory means, the maximum value stored in the memory means is changed to the maximum value. A maximum value updating unit that updates the data sequence newly counted by the counting unit at an interval from the rising edge of the polarity inversion to the next rising edge; and the modulation based on the maximum value stored in the memory unit. A modulation frequency detection circuit, comprising: detection means for detecting a frequency of a clock. 2. The cycle of the inversion time of the binary data is 1T.
(T: one cycle of modulation clock) or 2T cycle, binarized data is divided into blocks every predetermined length, and a predetermined pattern having an inversion time period of 3T or more is formed between the block data. A modulation frequency detection circuit that detects a frequency of the modulation clock from the inserted data sequence, a counting unit that counts an interval from a falling edge of the polarity inversion of the data sequence to the next falling edge, and counting by the counting unit. Memory means for storing the maximum value of the interval from the fall of the polarity inversion of the data sequence to the next fall, and the maximum value stored in the storage means, and newly counted by the counting means. Comparing means for comparing the interval from the fall of the polarity inversion of the data string to the next fall; and When it is determined that the interval from the fall of the polarity inversion of the data sequence to the next fall is greater than the local maximum value stored in the memory unit, the local maximum stored in the memory unit is determined. A maximum value updating unit that updates a value at an interval from a falling edge of the polarity inversion of the data string newly counted by the counting unit to a next falling edge, and a maximum value stored in the memory unit. And a detecting means for detecting the frequency of the modulated clock.