JPS62168442A - Data error controller - Google Patents

Abstract

PURPOSE:To lower an error rate by bringing a data of every bit to sampling at every prescribed time from the center part to the end part, making the weight of the center part larger, deriving the sum total of these data, and deciding a true data. CONSTITUTION:When an input signal 1 is inputted from a transmission line, it is shifted by a shifting part 3 and outputted. An input gate part 5 inputs a start signal 2, cuts an end part data of the input signal 1 and inputs it to an AND circuit 7. A clock of a clock generating part 6 is also inputted to an AND circuit 7, the input signal 1 is brought to sampling, and a data latching signal is inputted to a latch part 4. An output of the latch part 4 is brought to a signal processing by an arithmetic part 9 by adding a larger weight to the center of each bit by a weighting memory part 8. In such a way, an error rate caused by a signal distortion can be lowered by a simple circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data error control device in data communication.

[Conventional technology]

An example of actual input/output waveforms of main parts of data in conventional data communication is shown in FIG.

In the figure, 25 is data for 1 bit of input data,
'26 and 27 represent input waveforms that fluctuate due to code distortion caused by the influence of the transmission line.

Reference numeral 28 represents a synchronization signal for taking in input data, 29 represents an output waveform A when the input data is the input waveform 27, and 30 represents the output waveform B when the input data is the input waveform 25 or 26.

Next, the operation will be explained. First, the data 25 input from the transmission line is launched by the synchronization signal 28 added to each bit of the input data, and the output data 29 or 30 at that time is operated to be taken into the data receiving circuit.

[Problem that the invention seeks to solve]

Conventional data error control devices are configured as described above, so if code distortion occurs due to the influence of the transmission line or other factors, the reliability of the receiving circuit will be significantly reduced depending on the time difference with the synchronization signal that captures each bit data. There is a risk of transmitting data with a low error rate and a high error rate. There was a problem.

The present invention was made to solve the above-mentioned problems, and allows highly reliable data transmission without being affected by code distortion etc. using a relatively simple circuit compared to conventional data error control devices. The purpose is to obtain a data error control device that can be realized.

[Problem t-Means for solving]

The data error control device according to the present invention samples data for each focus at regular intervals from the center to the ends in order to eliminate the influence of code distortion, which is a factor of variation at the significant moment of each bit.

In addition, a weighting section is provided to weight the data, and the weight is increased in the center of the data.

By determining the true data from the sum of these data, it is possible to avoid the influence of end fluctuations due to code distortion.

[Effect]

The data weighting section in the present invention is provided to prevent each bit of data from being received incorrectly due to the influence of code distortion.The data weighting section of the present invention is provided to prevent erroneous reception of data for each bit due to the influence of code distortion. By aggregating and calculating data (the center part has a larger weight than the end parts), data errors due to code distortion occurring at the end parts are removed and the reliability of received data is improved.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. ! 1
In the figure, 1 is an input signal from a transmission line, 2 is a start signal of input signal 1, and 3 is an input shift unit for delaying input data by one cycle.

Reference numeral 4 denotes a data latch section which periodically takes in sampling data of the data shifted by the input shift section 3 in response to a start signal 2. Then, the input gate section 5 which cuts the end data and sets the timing, and the clock generation section 6 periodically pass the data through the AND gate 7 (the clock generation section 6 and the AND gate 7 are collectively referred to as a sampling circuit). Lunch the data. 8 is a weighting memory section for weighting and storing the output of the data latch section 4; 9 is an arithmetic section for determining the result of the weighting memory section 8; 10
is the output. In addition, 11 in Figure 2 is the ideal input waveform 1, 12 is the start signal 2, 13 is the output of the input shift section 3 in the case of an ideal input signal, and 14 is the actual input signal 1 such as sign distortion. 15 is the output of the input gate unit 5, 16 is the output of the clock generator 6, 17 is the output of the AND gate 7 as a data latch signal, and 18 is the output of the data latch unit 4. The waveform 19 of the control signal 31 is the output signal 10.

Also,! In FIG. 3, 15b is an enlarged waveform 14b of the output signal 15 of the input gate section 5 shown in FIG.

14c shows a case where the output (actual) 14 of the input shift section 3 shown in FIG. 2 fluctuates. 17b is an enlarged waveform of the AND gate 17 shown in FIG.
is a signal with a smaller weight than 21 above, hereinafter 23.24
The weight decreases in this order. 32 is a weight set in the weighting memory unit 8. 33 is the output of the weighting memory unit 8 in the case of the output 14b of the actual input shift unit 3;
34 is the difference in the output of the weighting memory section 8 when the actual output 14c of the input shift section 3 changes. Further, 35 is the output of the calculation section 9.

Next, the operation of this invention will be explained. first.

In FIG. 1, when an input signal 11 is input from the transmission line, it is shifted by the input shift section 3;
An ideal output signal 13 is output.

Ideally, signal 13 would be better, but sign distortion occurs due to the influence of transmission lines, etc., and in reality, signal 14 is better.
appears in the output of the input shift section 3.

Further, the input gate section 5 takes in the start signal 2, and the input signal to the AND gate 7 forms the output 15 of the input gate section 5, which has a window function to cant the end data.

In this operation, a window is set up for taking in data in each bit, and the unstable portion of the edge data is removed to narrow the window. Further, by ANDing with the clock generating section 6, a data latch signal 171 is inputted to the data latch section 4 as an output of the AND gate γ (sampling circuit section), and the input data is latched periodically for each bit data.

The manual data launched for each bit is input to the next stage weighting memory section 8 by the output side # signal 18,
A weight is added to each latched data at the output 1T of the AND gate 7. The wc3 diagram details this: for each bit, the data launched at the center 20 of the data has the highest weight, the data latched at both sides 21 has a lower weight, and the data at 22 has the highest weight. teeth,
A weight indicated by 32 is set, which is one step lower. The output of the weighting memory section 8 based on the ideal input 7 output 14b of the foot section 3 becomes the output 33, and even if the input fluctuates like the actual output 14c, the weighting memory is Compared to the output 33 of the unit 8, the output 34 has a small portion, so there is no risk of the input data being mistaken as @ll or IO@ in the next stage arithmetic unit 9, and the output 35 becomes the output signal 10 as data l11. .

In the above embodiment, the weighting memory section 8 is used to make a decision on data weighted by 1, but for each bit of the output 17 of the data latch section 4, 11M data, '
01 data may be aggregated and the data judgment may be made based on the difference.

Further, in the above embodiments, the case where the present invention is used in relation to a transmission line or the like has been described, but the same effects as in the above embodiments can be obtained even if the present invention is implemented in a data reading section of a magnetic disk device or the like.

〔Effect of the invention〕

As described above, according to the present invention, transmission data is weighted and then input to the transmission data calculation section for signal processing, which reduces the error rate during data acquisition due to code distortion and improves quality. data can be obtained, and a data transmitting/receiving device can be provided at low cost using a simple circuit system.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a data error control device according to an embodiment of the present invention, Figs. 2 and 3 are waveform diagrams of various parts in Fig. 1, and Fig. 4 is input/output waveforms of main parts in a conventional embodiment. Show the diagram. 1 is an input signal from a transmission line, 3 is a shift section, 4 is a data latch section, 5 is an input gate section, 8 is a weighting memory section, and 9 is an arithmetic section. Patent applicant: Mitsubishi F-Kuki Co., Ltd. Patent attorney: 1) Hiroshi Sawa (2 others) Fig. 1 IO output number Fig. 2 Fig. 3 5h 32

Claims (1)

[Claims] A data transmission device that receives an input signal from a data transmission line and makes a logical decision, including a sampling circuit section that samples the input signal for each bit at a fixed cycle, and a window that cuts end data of the output data of the sampling section. a gate section having a function, a data latch section that latches the data that controlled the input gate section, a weighting memory section that weights and stores the latched sampling data for each bit, and each of the weighting memory sections. What is claimed is: 1. A data error control device, comprising: an arithmetic unit that determines whether or not held data for each bit is a regular signal; and is configured to eliminate malfunctions due to code distortion during data communication.