CN108809321A - A kind of matrix keyboard operation identification and coding method - Google Patents
A kind of matrix keyboard operation identification and coding method Download PDFInfo
- Publication number
- CN108809321A CN108809321A CN201810591940.0A CN201810591940A CN108809321A CN 108809321 A CN108809321 A CN 108809321A CN 201810591940 A CN201810591940 A CN 201810591940A CN 108809321 A CN108809321 A CN 108809321A
- Authority
- CN
- China
- Prior art keywords
- pulse
- state
- row
- key
- keyboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000006870 function Effects 0.000 claims abstract description 28
- 239000000872 buffer Substances 0.000 claims description 61
- 238000005070 sampling Methods 0.000 claims description 48
- 230000000630 rising effect Effects 0.000 claims description 15
- 210000001367 artery Anatomy 0.000 claims description 14
- 238000012423 maintenance Methods 0.000 claims description 14
- 210000003462 vein Anatomy 0.000 claims description 14
- 238000004080 punching Methods 0.000 claims description 13
- 238000006073 displacement reaction Methods 0.000 claims description 4
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 claims description 4
- 230000007423 decrease Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 13
- 238000003860 storage Methods 0.000 description 12
- 238000009826 distribution Methods 0.000 description 7
- 230000001960 triggered effect Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 102220201076 rs201475876 Human genes 0.000 description 4
- 102100037697 Uridylate-specific endoribonuclease Human genes 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 2
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000007688 edging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 102220091149 rs145688699 Human genes 0.000 description 2
- 102220295519 rs779762640 Human genes 0.000 description 2
- 102220086336 rs864622288 Human genes 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
Abstract
A kind of matrix keyboard operation identification and coding method include the matrix keyboard output N bit keyboard status signals of X row-Y row key-press matrixs, the N=X+Y；Data are carried out according to scanning pulse to N bit keyboard status signals to latch to obtain existing state key assignments, latch pulse carries out state latch to existing state key assignments and preceding state key assignments and obtains 2 × N conditional codes, N number of shift pulse shifts existing state key assignments the sequence of state key assignments before obtaining, and is operated accordingly in cycles；Encode simultaneously run-out key number to conditional code, is realized by the circuit including matrix keyboard, the first shift register, the second shift register, state Code memory, encoder.Button operation function is either adjusted if necessary to increase and decrease button operation function, circuit structure need not be changed, the encoded content of encoder need to be only changed according to the conditional code after increase and decrease and the correspondence between key number.The method does not have to write and run program, reliable operation.
Description
Present patent application is divisional application, and application No. is 201610003664.2, the applying date is in January, 2016 for original bill
5, entitled matrix keyboard operation identifies and coding circuit.
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of matrix keyboard operation identification and coding method.
Background technology
With the continuous development of embedded technology, current each electronic product generally uses microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by run microcontroller in program come into
Row, encounters interference, program is caused to run fast, and scanner program is by cisco unity malfunction.
Application No. is the patents of invention of CN201010153560.2 " a kind of fast scanning and positioning method of matrix keyboard " to adopt
The Scan orientation process for entering keyboard with the mode that keyboard interrupt triggers is judged using the method that keyboard scan step is repeated several times
Whether button is effective, and the key assignments to being obtained carries out condition adjudgement；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then enters singly-bound tupe；Combination key operation in this way then enters Macintosh tupe.Described in the patent
Method is solved causes the Problem-Errors such as wrong key, continuous touching since keyboard caused by the mechanical property of keyboard itself is shaken,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with key operation is combined；
Not accounting for keyboard state maintains a period of time just to execute the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to change keyboard scan finder structure.
Invention content
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of matrix forms
Keyboard operation identification and coding method include the matrix keyboard output N bit keyboard status signals of X row-Y row key-press matrixs,
The N=X+Y；Data are carried out according to scanning pulse to N bit keyboard status signals to latch to obtain existing state key assignments, latch pulse is to existing
State key assignments carries out state latch with preceding state key assignments and obtains 2 × N conditional codes, and N number of shift pulse shifts existing state key assignments
The sequence of state key assignments, is operated accordingly in cycles before obtaining；Encode simultaneously run-out key number to conditional code.
The sequential of the scanning pulse, shift pulse and latch pulse meets claimed below：In one cycle, arteries and veins is scanned
Punching has 1 pulse, shift pulse to have N number of pulse, latch pulse to have 1 pulse；The scanning pulse, shift pulse and latch arteries and veins
Punching according to 1 scanning pulse, 1 latch pulse, N number of shift pulse sequence in cycles.The scanning pulse and latch arteries and veins
The period of punching is 20~100ms.
The scanning pulse, shift pulse and latch pulse are produced by the circuit that oscillator, counter, pulsqe distributor form
It is raw；The clock pulses of oscillator output, which is sent to counter, to be counted, and the output of counter is sent to the input of pulsqe distributor, arteries and veins
Rush distributor output scanning pulse, shift pulse and latch pulse.
The pulsqe distributor is realized using ROM memory；The address input of ROM memory is connected to the defeated of counter
Go out, 3 data output ends of ROM memory export scanning pulse, shift pulse and latch pulse respectively.
The conditional code is made of effective status code and invalid state code, for identification the current state of matrix keyboard and
Mode of operation；The key number is made of effective key number and invalid key number；The effective status code is by effective keyboard operation or state
It generates, the corresponding effectively key number of corresponding output；The invalid state code is generated by invalid keyboard operation or state, corresponding output nothing
Imitate key number；The key number is M, and the selection of M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
Effective keyboard operation includes singly-bound push, singly-bound release operates, singly-bound presses maintenance operation, Macintosh
Operation；The combination key operation refers to after singly-bound is pressed, then presses the operation of other buttons；The invalid keyboard operation is effective
Operation except keyboard operation.
It is described conditional code to be encoded and run-out key number is realized by encoder.Further, the encoder is read-only
Memory；Storage content by changing read-only memory increases and decreases button operation function and either adjusts button operation function.Institute
It states scanning pulse and latches to obtain existing state key assignments and N number of shift pulse to existing state key assignments to N bit keyboard status signals progress data
State key assignments before obtaining is shifted to be realized by the first shift register, the second shift register.
First shift register has the function of the input of N parallel-by-bits, the output of N parallel-by-bits and Serial output；Described second
Shift register has serial input, N parallel-by-bit output functions.The N parallel-by-bit input terminals of first shift register connect
To N bit keyboard status signal outputs；The serial input terminal of second shift register is connected to the serial of the first shift register
Output end；First shift register, the second shift register shift pulse input terminal be connected to shift pulse, the first displacement
The presetting pulse input terminal of register is connected to scanning pulse.
The latch pulse carries out state latch to existing state key assignments and preceding state key assignments and obtains 2 × N conditional codes by state
Code memory is realized.The state Code memory is 2 × N binary registers；The positions N data input in state Code memory
End is connected to the N parallel-by-bit output ends of the first shift register, and in addition N data input pins are connected to the second shift register
N parallel-by-bit output ends；The reception pulse input end of the state Code memory is connected to latch pulse.
First shift register, the shift pulse edge of the second shift register are effective；The state Code memory
Reception porch it is effective.The presetting pulse edge of first shift register is effective.Either, first displacement is posted
Storage, the shift pulse edge of the second shift register are effective；The reception porch of the state Code memory is effective；It is described
When the presetting pulse high level of first shift register is effective, the scanning pulse is positive pulse；First shift register
Presetting pulse low level it is effective when, the scanning pulse be negative pulse.
The matrix keyboard is by X row-Y row key-press matrix, row three state buffer, row status register, row Status register
Device forms；The line of all key-press matrixs is respectively connected to the output end of row three state buffer, the alignment point of all key-press matrixs
It is not connected to the output end of row three state buffer；All input terminals of row three state buffer and row three state buffer are connected to low electricity
It is flat；The line of all key-press matrixs is respectively connected to the input terminal of row status register, and the alignment of all key-press matrixs connects respectively
It is connected to the input terminal of row status register；The output end of the row status register and common group of the output end of row status register
At keyboard state signal output end.
The matrix keyboard is controlled by sampling pulse and obtains keyboard state signal；The sampling pulse selection scanning arteries and veins
One in punching, shift pulse, latch pulse；The row three state buffer is wanted when the low level of sampling pulse enables effective
Row status register is asked to make in the high level of sampling pulse in the rising edge progress data latch of sampling pulse, row three state buffer
Can effectively, row status register sampling pulse failing edge carry out data latch；Either, row three state buffer is in sampling arteries and veins
When the high level of punching enables effective, it is desirable that row status register is slow in the failing edge progress data latch of sampling pulse, row tri-state
Enabled effective, the row status register of low level that device is rushed in sampling pulse carries out data latch in the rising edge of sampling pulse.
The positions N, 2 × N, M refer both to binary digit data.
The matrix keyboard operation identification and coding method operate identification and coding circuit realization, square by matrix keyboard
Configuration keyboard operation identification and coding circuit include matrix keyboard, the first shift register, the second shift register, conditional code
Register, encoder.
Further, matrix keyboard operation identification and coding circuit further include that keyboard state change pulse generates
Whether unit, the key number for the output of judgment matrix formula keyboard change, when the key number of matrix keyboard output changes
When, export keyboard state change pulse.
The keyboard state change pulse generate unit by or door, M delay buffer and M XOR gate form；M are prolonged
Slow buffer for carrying out signal delay respectively to the positions the M key number that matrix keyboard exports；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
The beneficial effects of the invention are as follows：The positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by
Scanning pulse, shift pulse, the latch pulse control for meeting specific time sequence requirement are converted into the conditional code of same binary length,
It is handled by the way of Unified coding, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in conditional code
Be not same as above；Button operation function is either adjusted if necessary to increase and decrease button operation function, circuit structure need not be changed, only
The encoded content of encoder need to be changed according to the conditional code after increase and decrease and the correspondence between key number, remodify write-in only
Read the storage content of memory.The method does not use the microcontrollers such as microcontroller, ARM, does not have to operation program, work
Reliably.
Description of the drawings
Fig. 1 is matrix keyboard operation identification and coding circuit functional block diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the Scan orientation circuit diagram of the embodiment of the present invention；
Fig. 4 is the first shift-register circuit figure of the embodiment of the present invention；
Fig. 5 is the pulse sequence figure of the embodiment of the present invention；
Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention；
Fig. 7 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 8 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific implementation mode
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is matrix keyboard operation identification and coding circuit functional block diagram, is posted by the displacement of matrix keyboard 400, first
Storage 100, the second shift register 200, state Code memory 500, encoder 300 form.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, 2 rows, 2 row is shared, totally 4 buttons, by button
S1, button S2, button S3, button S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, on
Pull-up resistor R4 and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404
Composition.2 output ends Y1, Y2 of row three state buffer 401 are respectively connected to 2 lines, and 2 of row three state buffer 402 are defeated
Outlet Y3, Y4 is respectively connected to 2 alignments；All input terminal X1~X4 of row three state buffer 401 and row three state buffer 402
It is connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of row status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output ends Q41, Q42 of row status register 403 export row state
Signal I1, I2,2 output end Q43, Q44 output row status signals I3, I4 of row status register 404；Row status register
403 2 output ends collectively constitute 4 bit keyboard status signal outputs with 2 output ends of row status register 404, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low levels of row three state buffer 401 are effective, and row three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the sampling pulse CK output ends of oscillator 500.Row status register 403
The sampling pulse CK that oscillator 500 is connected to reception pulse input end CLK3, CLK4 of row status register 404 is exported
End, failing edge of the row status register 403 in sampling pulse CK carry out data latch, and row status register 404 is in sampling pulse
The rising edge of CK carries out data latch.
When row three state buffer 401 and row three state buffer 402 are using the three state buffer with model, for example, making simultaneously
When with three state buffer 74HC241, the enabled input of 74HC241 is that high level is effective, therefore, sampling pulse CK output ends with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With row status register 404 using the data register with model, for example, row status register 403 and row status register 404
When using double D trigger 74HC74 composition data registers, the triggering input of 74HC74 is that rising edge is effective, therefore, is being taken
Between sample pulse CK output ends and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
The first shift register 100, the second shift register 200, state Code memory 500, encoder 300 in Fig. 1
Scan orientation circuit is formed, embodiment circuit diagram is as shown in Figure 3.The status signal of embodiment matrix keyboard circuit output has
4, therefore, the first shift register 100, the second shift register 200 are all 4 binary shift registers, wherein first
Shift register 100 has the function of that input, parallel output and Serial output parallel, the second shift register 200 have serial defeated
Enter, parallel output function；4 parallel input terminal L0~L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4,
The serial input terminal D2 of second shift register 200 is connected to the serial output terminal Q13 of the first shift register 100.First moves
Bit register 100, the second shift register 200 shift pulse input terminal CLK1, CLK2 be connected to shift pulse CP2,
The presetting pulse input terminal CLK0 of one shift register 100 is connected to scanning pulse CP1.
State Code memory 500 requires 8 bit binary datas of deposit, 4 companies in 8 data input pin D57~D50
Be connected to parallel output terminal Q13~Q10 of the first shift register 100, in addition 4 be connected to the second shift register 200 and
Row output end Q23~Q20；In embodiment, D57~D54 is connected to Q23~Q20, and D53~D50 is connected to Q13~Q10.State
The reception pulse input end CLK5 of Code memory 500 is connected to latch pulse CP3.
8 input terminal A7~A0 of encoder 300 be connected to 8 data output end Q57 of state Code memory 500~
Q50.Encoder 300, which exports, is scanned through 4 determining binary system keys number of positioning.
In Fig. 3 embodiments, the second shift register 200 can select to be made of various medium-scale integration shift registers,
Or it is made of edge triggered flip flop；When forming the second shift register 200 by edge triggered flip flop, preferably touched by the D of edging trigger
Send out device composition.State Code memory 500 is made of edge triggered flip flop, is preferably made of the d type flip flop of edging trigger, for example, by
Double D trigger 74HC74,4D trigger 74HC175,8D trigger 74HC273 compositions.
Fig. 4 is the circuit diagram of the first shift register 100 of the embodiment of the present invention, by the low electricity of 4 set, reset functions
101~104,8 NAND gates 105~112 of effective d type flip flop are equalled to form.In embodiment, the double D of the selection of d type flip flop 101~104
Trigger 74HC74, trigger pulse rising edge are effective.Scanning pulse CP1 controls d type flip flop by 8 NAND gates 105~112
101~104 set, reset function.By taking d type flip flop 101 as an example, scanning pulse CP1 be low level when, NAND gate 105, with it is non-
Door 106 exports high level, and the set of d type flip flop 101, reset function are invalid；When scanning pulse CP1 is high level and L0=0, with
The output of NOT gate 105 isThe output of NAND gate 106 is L0, i.e., the set function of d type flip flop 101 is invalid, reset function has
Effect, makes Q10=0；When scanning pulse CP1 is high level and L0=1, the output of NAND gate 105 isThe output of NAND gate 106
For L0, i.e. the set function of d type flip flop 101 is effective, reset function is invalid, makes Q10=1.The work of d type flip flop 102~104 is former
Reason is as d type flip flop 101, when scanning pulse CP1 is high level, Q10=L0, Q11=L1, Q12=L2, Q13=L3；When
Scanning pulse CP1 be low level when, due to trigger pulse input terminal CLK10, CLK11 of d type flip flop 101~104, CLK12,
CLK13 is connected to CP2, and therefore, in the rising edge of each shift pulse CP2, the first shift register 100 moves primary position, i.e.,
Q13=Q12, Q12=Q11, Q11=Q10, Q10=0.
In Fig. 3 embodiments, encoder 300 is read-only memory.Address input end A7~A0 of read-only memory is coding
The input terminal of device 300, data output end D3~D0 of read-only memory are coding output end C3~C0 of encoder 300.
Matrix keyboard operation identification and coding method principle are as follows：
Scan orientation circuit scanning pulse CP1, shift pulse CP2, latch pulse CP3 control under work, it is relevant
Pulse sequence figure is as shown in Figure 5.
The sequential of CP1, CP2, CP3 meet claimed below in embodiment：In one cycle, CP1 has 1 pulse, CP2 to have
4 pulses, CP3 have 1 pulse；Each pulse according to 1 CP1 pulse, 1 CP3 pulse, 4 CP2 pulses sequence Zhou Erfu
Begin.
Meeting CP1, CP2, CP3 pulse of timing requirements can be generated by various pulsqe distributors, and Fig. 6 is implementation of the present invention
The impulse circuit schematic diagram of example, is made of oscillator 801, counter 802, pulsqe distributor 803.Clock pulse CP in Fig. 5
It is generated by oscillator, CP send to counter 802 and counted, and counter 802 is 12 system Counters, 12 shapes of result P
State (numerical value) is followed successively by P0 → P11, as shown in Figure 5.Pulsqe distributor 803 in embodiment is using ROM memory realization, herein
Referred to as pulse distribution ROM memory.The address input of pulse distribution ROM memory is connected to the counting output of counter 802, arteries and veins
3 data output ends of punching distribution ROM memory are exported respectively as CP1 pulses, CP2 pulses, CP3 pulses.Pulse distribution ROM is deposited
The write-in content of reservoir is shown in Table 1.
1 pulse distribution ROM memory tables of data of table
The output of ROM memory address in table 1, i.e. counter is at least 4 binary codes.Under normal circumstances, counter
If 802 using binary addition rule, corresponding 4 binary codes 0000~1011 of P0~P11 sequences, i.e. ROM memory
Address range is 0000~1011, and the storage content of address 0000~1011 is the corresponding contents of P0~P11 in table 1.
Pulse distribution ROM memory needs 3 data outputs.If the address input of pulse distribution ROM memory has R,
When matrix keyboard has the output of N bit keyboard status signals, the selection of R needs satisfaction 2RMore than or equal to 2 × (N+2).
Oscillator 801 is multivibrator.CP1 scanning pulses, CP3 latch pulses period be 20~100ms.CP1,
CP2, CP3 can also be operated circuit or device offer except identification and coding circuit by matrix keyboard.
In Fig. 2,4 buttons of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by sampling pulse CK, using reversal process obtain keyboard state signal I4,
I3,I2,I1.For example, it is 1010 that the keyboard state signal of key pressing, which is not the keyboard state signal that 1111, S1 is pressed, S1, S2
The keyboard state signal pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key assignments.Sampling pulse CK can be with
Any one of scanning pulse CP1, shift pulse CP2, latch pulse CP3 are selected, preferably by shift pulse CP2 conducts simultaneously
Sampling pulse CK.
Sampling pulse CK controls carry out the method that key assignments is read in sampling to matrix keyboard：In the low electricity of sampling pulse CK
It is flat, all lines are controlled by row three state buffer 401 and export low level, row three state buffer 402 exports high-impedance state and opens row
Line；It is sampled by row status register 404 in the rising edge of sampling pulse CK and reads alignment state as the 2 high of key assignments；It is taking
The high level of sample pulse CK controls all alignments by row three state buffer 402 and exports low level, and row three state buffer 401 is defeated
Go out high-impedance state and opens line；It is sampled by row status register 403 in the failing edge of sampling pulse CK and reads line state as key
Low 2 of value；In cycles, 4 key assignments that row status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from sampling pulse CK controls and reads the method for key assignments it is found that row three state buffer
401 when the low level of sampling pulse CK enables effective, while requiring row status register 404 in the rising edge of sampling pulse CK
Carry out data latch, row three state buffer 402 is taking in enabled effective, the row status register 403 of the high level of sampling pulse CK
The failing edge of sample pulse CK carries out data latch.In turn, if high level of the row three state buffer 401 in sampling pulse CK makes
When can be effective, while row status register 404 being required to carry out data latch, row three state buffer in the failing edge of sampling pulse CK
402 sampling pulse CK low level is enabled effectively, rising edge that row status register 403 is in sampling pulse CK carries out data lock
It deposits.
During above-mentioned sampling pulse CK controls sampling and reads key assignments, row status register 403, row status register
404 at the time of precisely row three state buffer 402 is with the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or row status register 404 can be sampled correctly.If it is required that having in certain sequential
Allowance can then postpone, method to being connected to row three state buffer 402 and the sampling pulse CK of row three state buffer 401
Be enable sampling pulse CK by RC retardation ratio circuit be then connected to row three state buffer 401 and row three state buffer 402 EN1,
EN2, delay time are determined by RC retardation ratio circuit, determine that the principle of the delay time of RC retardation ratio circuit is, the sampling pulse of delay
CK phases are no more than 90 °；Either sampling pulse CK is then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of row three state buffer 402, delay time at this time is the overall delay time of several gate circuits.
First shift register 100 is under the control of scanning pulse CP1, to the status signal of the output of matrix keyboard 400
I1, I2, I3, I4 carry out data latch, and the output of the first shift register 100 at this time is known as now state key assignments；Second shift LD
Upper periodic scanning pulses CP1, via the control of 4 CP2 pulses, was latching to the first shift register by device 200 in a upper period
100 output is displaced to 200 output end of the second shift register, therefore, before the output of the second shift register 200 at this time is known as
State key assignments.
Existing state key assignments that latch pulse CP3 after scanning pulse CP1 exports the first shift register 100, second move
The preceding state key assignments that bit register 200 exports is latched in the output end of state Code memory 500, the output of state Code memory 500
State key assignments and existing state key assignments before being similarly.
First shift register 100, the equal edge of shift pulse of the second shift register 200 are effective, and therefore, CP2 can be with
It is positive pulse, can also be negative pulse；The reception porch of state Code memory 500 is effective, and therefore, CP3 can be positive arteries and veins
Punching, can also be negative pulse.When the presetting pulse of first shift register 100 is that edge is effective, scanning pulse CP1 can be just
Pulse can also be negative pulse.When the presetting pulse of first shift register 100 is that high level is effective, it is desirable that scanning pulse CP1
For positive pulse；When the presetting pulse of first shift register 100 is that low level is effective, it is desirable that scanning pulse CP1 is negative pulse；It is real
It applies in example, the presetting pulse of the first shift register 100 is effective for high level, so, scanning pulse CP1 uses positive pulse.
In embodiment, the 4 existing state key assignments and 4 preceding state key assignments of 500 data output end of state Code memory output are common
Form 8 conditional codes.The current state and mode of operation of 8 conditional codes matrix keyboard for identification.For example, this reality
It applies in example, the conditional code of no key pressing is 11111111；The conditional code of S1 key singly-bound pushes is 11111010；S1 key singly-bounds
It presses and the conditional code maintained is 10101010；The conditional code of S1 key singly-bounds release operation is 10101111；S2 key singly-bounds are pressed
The conditional code of operation is 11110110；The conditional code of S4 key singly-bound pushes is 11110101；The S1 of S2+S1 combination operations is pressed
Lower operation after expression first presses S2, presses the operation of S1, the conditional code of the operation is again in the state that S2 maintenances are pressed
01100010。
Encoder 300 is used to conditional code being converted to key number.In embodiment, it is equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound push of button S1, key number are 0000；
Operation 1：The singly-bound push of button S2, key number are 0001；
Operation 2：The singly-bound push of button S3, key number are 0010；
Operation 3：Button S3 singly-bounds press after maintenance state, key number be 0011；
Operation 4：After button S4 singly-bounds are pressed, then the combination key operation of S2 is pushed button, key number is 0100；
Operation 5：The singly-bound release operation of button S1, key number is 0101.
The conditional code and key number obtained according to above-mentioned regulation is shown in coding schedule 2：
2 coding schedule of table
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bounds are pressed | 11111010 | 0000 |
| S2 singly-bounds are pressed | 11110110 | 0001 |
| S3 singly-bounds are pressed | 11111001 | 0010 |
| S3 singly-bounds press maintenance | 10011001 | 0011 |
| S4+S2 combination operations | 01010100 | 0100 |
| S1 singly-bounds discharge | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 2.
The encoder 300 of embodiment is preferably made of read-only memory.Read-only memory has 8 bit address, and totally 28A 4 two
System storage unit.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state；By state
Address A7~A0 of the code as read-only memory, in storage unit corresponding with 6 effective status codes, by corresponding key number
As storage data write-in.The conditional code generated except 6 effective keyboard operations and state is invalid state code, i.e., in table 2
Other operation or state caused by be invalid state code；In other storage units, invalid key number, invalid key is all written
Number for a value except 6 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When read-only memory has piece selected control system, data output slow
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase as needed, or subtract
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M values is answered
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has the output of N bit keyboard status signals
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to change table 2 as needed, it will
Modified content re-writes the storage content of read-only memory.
The edge of latch pulse CP3 at the time of state Code memory 500 is carried out data latch is known as state latch edge,
It is the rising edge of CP3 in embodiment.In embodiment, when matrix keyboard S1 singly-bounds are pressed, after the latch of CP1, CP3 two-stage,
Since the state latch of CP3 along, until the state latch edge of next CP3, output end C3~C0 run-out keies number are encoded
0000；When matrix keyboard S2 singly-bounds are pressed, after the latch of CP1, CP3 two-stage, since the state latch of CP3 along, until under
Until the state latch edge of one CP3, run-out key number 0001；After matrix keyboard first presses S4, then S2 is pressed, encoder
300 combine key pressing in S2, after the latch of CP1, CP3 two-stage, since the state latch of CP3 along, until the shape of next CP3
Until state latches edge, run-out key number 0100；When the release of matrix keyboard S1 singly-bounds, after the latch of CP1, CP3 two-stage, from CP3
State latch along starting, until the state latch edge of next CP3, run-out key number 0101；It can therefore be seen that when identification
Be effective button operation of matrix keyboard when, the state latch of CP3 of the encoder 300 after effective button operation is along opening
Begin, until the state latch edge of next CP3, output duration is effective key number of a CP3 periodic width.
In embodiment, when matrix keyboard S3 singly-bounds are pressed, encoder 300 is pressed in S3 singly-bounds, by CP1, CP3 two
After grade latches, since the state latch of CP3 along, until the state latch edge of next CP3, run-out key number 0010；It is connecing
The state latch edge of the CP3 to get off starts, and terminates until S3 singly-bounds press maintenance state, the CP3 after the latch of CP1, CP3 two-stage
Until state latch edge, 300 run-out key number 0011 of encoder；It can therefore be seen that work as identification is the maintenance of matrix keyboard
When state, encoder 300 exports the duration of effective key number and the duration of the maintenance state is adapted.
When except the state of keyboard or operation being 6 effective keyboard operations and state described in table 2, encoder
300 output invalid keys number 1111.Effective key number, or output invalid key number are either exported, encoder 300 changes output content
At the time of for CP3 state latch edge；In embodiment, encoder 300 changes the rising edge for CP3 at the time of exporting content.
The period of CP3 is the scan period of matrix keyboard.The keyboard scan period in 20ms or more, can effectively keep away
The influence of key point disk key jitter；The keyboard scan period in 100ms or less, is unlikely to omit keyboard operation；Therefore, CP3
Period should control in 20~100ms.
Fig. 7 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is matrix form
When effective button operation of keyboard, the state latch edge of CP3 of the encoder 300 after effective button operation starts, until next
Until the state latch edge of a CP3, output duration is effective key number of a CP3 periodic width.Receive the matrix form
The device of keyboard output, needs the output for inquiring matrix keyboard constantly, obtains key number.The period distances of inquiry are necessarily less than
The period of CP3.
Whether key number of the circuit shown in Fig. 7 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, export keyboard state change pulse, be used for the reception device receiving matrix formula of auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 7 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.By only being formed with 4 edge triggered flip flops of Trigger Function, 4 edge triggered flip flops touch delay buffer 601
The reception pulse input end that input terminal is delay buffer 601 is sent out, CP3 is connected to；State of the delay buffer 601 in CP3
It latches along progress data latch.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output end of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output end C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is buffered by delay
After the first-level buffer of device 601, signal ratio C3~C0 postpones a CP3 pulse period, and Fig. 8 show the key of the embodiment of the present invention
The waveform correlation schematic diagram that disk effectively operates.The sections T1 of CP3 pulses are located at, matrix keyboard has primary effectively operation, real
Apply example it is effective operation include：S1 singly-bounds are pressed, S2 singly-bounds are pressed, S3 singly-bounds are pressed, the S1 of S4+S1 combination operations is pressed, S4+
The S2 of S2 combination operations is pressed, S1 singly-bounds discharge.On the next state latch edge once effectively operated, i.e. CP3 pulses in Fig. 8
Rising edge after the sections T1, coding C3~C0 that encoder 300 exports change；In the sections T2, the output of encoder 300 one
Efficient coding C3~C0 of a CP3 pulse periods；In T3, T4 and section later, coding C3~C0 that encoder 300 exports is another
Secondary to change and enter maintenance state, which may be that such as S1 singly-bounds press subsequent maintenance state, export invalid key
Number, it is also possible to S3 singly-bounds press subsequent maintenance state, export effective key number, until effectively operation next time.
Coding C3~C0 that D6 pulses in Fig. 8 schematically illustrate the output of encoder 300 is to be in maintenance state, is not become
Change, still change, the D6 pulses are not present in actual circuit.As shown in figure 8, D6 pulses are low level, illustrate table
Show that coding C3~C0 that encoder 300 exports is to be in maintenance state, does not change；D6 pulses are high level, schematically illustrate volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 8 reflected is the situation of change of C31~C01, it is clear that
Q6 ratios D6 postpones a CP3 pulse period.Equally, the Q6 pulses are not present in actual circuit.
In Fig. 8, coding C3~C0 that encoder 300 exports is to be in maintenance state, does not change, still changes,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
At logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output end C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 ratio C0 postpone a CP3 pulse period, and therefore, when C0 changes, XOR gate 602 exports 1 CP3 pulse week
The positive pulse of phase width；When C0 is a CP3 pulse period change width signal, XOR gate 602 exports 2 CP3 pulse weeks
The positive pulse of phase width.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 changes respectively, principle with
It is identical to judge whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 output end connect respectively
It is connected to or whether the input terminal of door 606 or door 606 changes for comprehensive descision C0~C3, as long as C0~C3 changes,
Or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D triggers 74HC273 of rising edge triggering.
Delay buffer 601 can also use other schemes, for example, using RC circuits, using 4 RC circuits respectively to C0
~C3 is postponed；If the delay time of RC circuits is less than a CP3 pulse period, encoder 300 exports a cycle
Efficient coding C3~C0 when, output efficient coding C3~C0 start and export efficient coding C3~C0 terminate all generation one
The width of keyboard state change pulse, keyboard state change pulse is equal to RC circuit delay times；If when the delay of RC circuits
Between be more than or equal to a CP3 pulse period, then encoder 300 export a cycle efficient coding C3~C0 when, have in output
Effect coding C3~C0 generates a keyboard state change pulse when starting, which is more than or equal to 2 CP3 pulse periods.
It is required that the delay time of RC circuits is no more than 2 CP3 pulse periods, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by full
3 Pulse Width Controls that sufficient specific time sequence requires are converted into the conditional code of same binary length, by the way of Unified coding into
Row processing, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If necessary to increase
Subtract button operation function and either adjust button operation function, keyboard scanning circuit structure need not be changed, it only need to be according to increase and decrease
The storage content that state code table afterwards updates encoder 300, re-writes update read-only memory.The invention circuit
The microcontrollers such as microcontroller, ARM are not used, operation program, reliable operation are not had to.
Claims (10)
1. a kind of matrix keyboard operation identification and coding method, it is characterised in that：It include the matrix of X row-Y row key-press matrixs
Formula keyboard exports N bit keyboard status signals, the N=X+Y；Data lock is carried out to N bit keyboard status signals according to scanning pulse
It deposits to obtain existing state key assignments, latch pulse carries out state latch to existing state key assignments and preceding state key assignments and obtains 2 × N conditional codes, N number of
Shift pulse shifts existing state key assignments the sequence of state key assignments before obtaining, in cycles；Conditional code is encoded and is exported
Key number；Institute's rheme is binary digit.
2. matrix keyboard operation identification according to claim 1 and coding method, which is characterized in that the scanning arteries and veins
The sequential of punching, shift pulse and latch pulse meets claimed below：In one cycle, scanning pulse has 1 pulse, shifts arteries and veins
Punching has N number of pulse, latch pulse to have 1 pulse；The scanning pulse, shift pulse and latch pulse according to 1 scanning pulse,
1 latch pulse, N number of shift pulse sequence in cycles.
3. matrix keyboard operation identification according to claim 2 and coding method, which is characterized in that the scanning arteries and veins
Punching, shift pulse and latch pulse are generated by the circuit that oscillator, counter, pulsqe distributor form；Oscillator output when
Clock is sent to counter and is counted, and the output of counter is sent to the input of pulsqe distributor, pulsqe distributor output scanning
Pulse, shift pulse and latch pulse.
4. matrix keyboard operation identification according to claim 1 and coding method, it is characterised in that：The conditional code by
Effective status code and invalid state code form, for identification the current state and mode of operation of matrix keyboard；The key number by
Effective key number and invalid key number form；The effective status code is generated by effective keyboard operation or state, and corresponding output is corresponding
Effective key number；The invalid state code is generated by invalid keyboard operation or state, corresponding output invalid key number；The key number is M
Position, the selection of M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
5. matrix keyboard operation identification according to claim 4 and coding method, it is characterised in that：Effective keyboard
Operation includes singly-bound push, singly-bound release operates, singly-bound presses maintenance operation, combination key operation；The combination key operation
Refer to after singly-bound is pressed, then presses the operation of other buttons；The invalid keyboard operation is the operation except effective keyboard operation.
6. matrix keyboard operation identification according to claim 4 and coding method, it is characterised in that：It is described to conditional code
It is encoded and run-out key number is realized by encoder.
7. matrix keyboard operation identification according to claim 1 and coding method, it is characterised in that：The matrix form key
Disk by X row-Y row key-press matrix, row three state buffer, row status register, column-shaped state register group at；All key-press matrixs
Line is respectively connected to the output end of row three state buffer, and the alignment of all key-press matrixs is respectively connected to row three state buffer
Output end；All input terminals of row three state buffer and row three state buffer are connected to low level；The line of all key-press matrixs
It is respectively connected to the input terminal of row status register, the alignment of all key-press matrixs is respectively connected to the input of row status register
End；The output end of the row status register exports N bit keyboard status signals jointly with the output end of row status register.
8. matrix keyboard operation identification according to claim 7 and coding method, it is characterised in that：The matrix form key
Disk is controlled by sampling pulse and obtains keyboard state signal；In the sampling pulse selection scanning pulse, shift pulse, latch pulse
One；The row three state buffer is when the low level of sampling pulse enables effective, it is desirable that row status register is in sampling arteries and veins
The rising edge of punching carries out data latch, row three state buffer exists in enabled effective, the row status register of the high level of sampling pulse
The failing edge of sampling pulse carries out data latch；Either, row three state buffer is when the high level of sampling pulse enables effective,
It is required that row status register the failing edge of sampling pulse carry out data latches, row three state buffer sampling pulse low level
Enabled effective, row status register carries out data latch in the rising edge of sampling pulse.
9. the matrix keyboard operation identification according to any one of claim 1-8 and coding method, it is characterised in that：Institute
It states scanning pulse and latches to obtain existing state key assignments and N number of shift pulse to existing state key assignments to N bit keyboard status signals progress data
State key assignments before obtaining is shifted to be realized by the first shift register, the second shift register；
First shift register has the function of the input of N parallel-by-bits, the output of N parallel-by-bits and Serial output；Second displacement
Register has serial input, N parallel-by-bit output functions；
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second shift LD
The serial input terminal of device is connected to the serial output terminal of the first shift register；First shift register, the second shift register
Shift pulse input terminal be connected to shift pulse, the presetting pulse input terminal of the first shift register is connected to scanning arteries and veins
Punching.
10. matrix keyboard operation identification according to claim 9 and coding method, it is characterised in that：The latch arteries and veins
The conditional code that punching obtains existing state key assignments with preceding state key assignments progress state latch 2 × N is realized by state Code memory；
The state Code memory is 2 × N binary registers；The positions N data input pin in state Code memory is connected to
The N parallel-by-bit output ends of first shift register, in addition N data input pins be connected to the N parallel-by-bits of the second shift register
Output end；The reception pulse input end of the state Code memory is connected to latch pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810591940.0A CN108809321B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard operation identification and coding method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003664.2A CN105680875B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard operation identification and coding circuit |
| CN201810591940.0A CN108809321B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard operation identification and coding method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610003664.2A Division CN105680875B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard operation identification and coding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108809321A true CN108809321A (en) | 2018-11-13 |
| CN108809321B CN108809321B (en) | 2022-03-18 |
Family
ID=56298806
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610003664.2A Active CN105680875B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard operation identification and coding circuit |
| CN201810591940.0A Expired - Fee Related CN108809321B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard operation identification and coding method |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610003664.2A Active CN105680875B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard operation identification and coding circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN105680875B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3675239A (en) * | 1970-09-14 | 1972-07-04 | Ncr Co | Unlimited roll keyboard circuit |
| EP0375328A2 (en) * | 1988-12-19 | 1990-06-27 | Sharp Kabushiki Kaisha | Tablet integrated with display |
| US5254989A (en) * | 1988-12-20 | 1993-10-19 | Bull S.A. | Garbling the identification of a key of a non-coded keyboard, and circuit for performing the method |
| CN1359052A (en) * | 2001-07-11 | 2002-07-17 | 威盛电子股份有限公司 | Keyboard instruction fetch device for notebook computer |
| CN101789793A (en) * | 2010-01-15 | 2010-07-28 | 电子科技大学中山学院 | Determinant linear array coordinate scanning circuit |
| CN202059394U (en) * | 2011-05-09 | 2011-11-30 | 广州励丰声光科技有限公司 | Matrix keyboard scanning device based on programmable element |
| CN102541267A (en) * | 2010-12-31 | 2012-07-04 | 联芯科技有限公司 | Matrix keyboard circuit, scanning method and device, processor and handheld terminal |
| CN103257716A (en) * | 2013-05-14 | 2013-08-21 | 湖南工业大学 | Low-power dissipation keyboard and scanning positioning method thereof |
| CN103279197A (en) * | 2013-06-08 | 2013-09-04 | 湖南工业大学 | Keyboard scanning positioning method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840268B (en) * | 2010-04-23 | 2012-02-15 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
| CN102156542A (en) * | 2011-01-13 | 2011-08-17 | 北京理工大学 | Matrix keyboard for detector of positioning orientating system |
-
2016
- 2016-01-05 CN CN201610003664.2A patent/CN105680875B/en active Active
- 2016-01-05 CN CN201810591940.0A patent/CN108809321B/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3675239A (en) * | 1970-09-14 | 1972-07-04 | Ncr Co | Unlimited roll keyboard circuit |
| EP0375328A2 (en) * | 1988-12-19 | 1990-06-27 | Sharp Kabushiki Kaisha | Tablet integrated with display |
| US5254989A (en) * | 1988-12-20 | 1993-10-19 | Bull S.A. | Garbling the identification of a key of a non-coded keyboard, and circuit for performing the method |
| CN1359052A (en) * | 2001-07-11 | 2002-07-17 | 威盛电子股份有限公司 | Keyboard instruction fetch device for notebook computer |
| CN101789793A (en) * | 2010-01-15 | 2010-07-28 | 电子科技大学中山学院 | Determinant linear array coordinate scanning circuit |
| CN102541267A (en) * | 2010-12-31 | 2012-07-04 | 联芯科技有限公司 | Matrix keyboard circuit, scanning method and device, processor and handheld terminal |
| CN202059394U (en) * | 2011-05-09 | 2011-11-30 | 广州励丰声光科技有限公司 | Matrix keyboard scanning device based on programmable element |
| CN103257716A (en) * | 2013-05-14 | 2013-08-21 | 湖南工业大学 | Low-power dissipation keyboard and scanning positioning method thereof |
| CN103279197A (en) * | 2013-06-08 | 2013-09-04 | 湖南工业大学 | Keyboard scanning positioning method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108809321B (en) | 2022-03-18 |
| CN105680875A (en) | 2016-06-15 |
| CN105680875B (en) | 2018-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105468164B (en) | Matrix keyboard scanner uni coding circuit | |
| CN105677055B (en) | matrix keyboard scanning circuit and method | |
| CN205490496U (en) | Matrix type keyboard operation discernment and coding circuit | |
| CN105677053B (en) | Independent keyboard operation identification and coding circuit | |
| CN105680873B (en) | Independent keyboard scanning encoding circuit | |
| CN105680875B (en) | Matrix keyboard operation identification and coding circuit | |
| CN105677051B (en) | Independent keyboard scanning circuit and coding circuit | |
| CN105700696B (en) | Matrix keyboard scanning encoding circuit | |
| CN105700695B (en) | Matrix keyboard scanning circuit and coding circuit | |
| CN105680874B (en) | Matrix keyboard scanning circuit and scanning encoding method | |
| CN105700697B (en) | independent keyboard scanning circuit and method | |
| CN105677054B (en) | Independent keyboard Scan orientation circuit | |
| CN105677052B (en) | Independent keyboard state recognition and coding circuit | |
| CN205384582U (en) | Matrix type keyboard scanning circuit and coding circuit | |
| CN105703780B (en) | Matrix keyboard Scan orientation circuit | |
| CN105700698B (en) | Matrix keyboard state recognition and coding circuit | |
| CN105677050B (en) | Independent keyboard scanning circuit and scanning encoding method | |
| CN105471439B (en) | Independent keyboard scanner uni coding circuit | |
| CN205318331U (en) | Matrix type keyboard scanning and coding circuit | |
| CN205485933U (en) | Matrix type keyboard scans positioning circuit | |
| CN205320063U (en) | Matrix type keyboard state recognition and coding circuit | |
| CN205318332U (en) | Discernment of stand alone type key board operation and coding circuit | |
| CN205384581U (en) | Stand alone type keyboard scanning circuit and coding circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20220318 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |