CN205318332U - Discernment of stand alone type key board operation and coding circuit - Google Patents

Abstract

The utility model provides a discernment of stand alone type key board operation and coding circuit comprises free -standing keyboard, a shift register, the 2nd shift register, state code register, encoder. The circuit is via satisfying scanning pulse, the shift pulse that specific chronogenesis required, the control of latching the pulse, and the location of will operate the single bond, the state operation being maintain in key combination operation, keyboard converts active state sign indicating number and the invalid state sign indicating number of same binary system length to, invalid key that effective key of corresponding through the back output of encoder code and each active state sign indicating number number or export corresponds with all invalid state sign indicating numbers number, different single bond operation, key combination operation, keyboards is kept the state operation and is only embodied not the same at the status codes, the keyboard scanning circuit structure need not modifyd to if necessary increase/decrease keys operating function or adjustment button operating function, and it can only to need to change the encoder according to the corresponding relation between the status codes after the increase and decrease and the key number. The reliable operation need not be compile and operating program to the invention circuit.

Description

A kind of independent keyboard operation identifies and coding circuit

Technical field

The present invention relates to the scanning circuit of a kind of keyboard, especially a kind of independent keyboard operation identifies and coding circuit.

Background technology

Along with the development of embedded technology, the current commonly used microcontroller of each electronic product is as control core, and keyboard, as main input equipment, is widely used.

Current keyboard scan is mainly controlled by microcontroller, it is necessary to being undertaken by running the program in microcontroller, run into interference, cause program to run fast, scanning imaging system is by cisco unity malfunction.

Application number is the Scan orientation process that the mode that the patent of invention " fast scanning and positioning method of a kind of matrix keyboard " of CN201010153560.2 adopts keyboard interrupt to trigger enters keyboard, whether button is effective to adopt the method repeatedly repeating keyboard scan step to judge, and the key assignments obtained is carried out condition adjudgement; If multiple repairing weld state is identical, being then in steady statue, key assignments is effective; If multiple repairing weld state is different, key assignments is invalid. Single key stroke or Macintosh operation need individually to judge, single key stroke in this way then enters singly-bound tupe; Macintosh operation in this way, then enter Macintosh tupe. Method described in this patent solves the keyboard shake owing to the mechanical property of keyboard self causes and causes the wrong Problem-Error such as key, continuous touching, and the support issue to Macintosh and repeat key. But described method single key stroke needs to process respectively with Macintosh operation; Do not account for keyboard state and maintain a period of time keyboard operation function to rear just execution effectively operation; When increase and decrease button operation function or adjustment button operation function, it is necessary to amendment keyboard scan finder structure.

Summary of the invention

In order to solve the above-mentioned technical problem that existing keyboard scan localization method exists, the invention provides a kind of independent keyboard operation to identify and coding circuit, it is characterized in that, be made up of independent keyboard, the first shift register, the second shift register, conditional code depositor, encoder.

Described a kind of independent keyboard operation identifies and coding circuit is carried out Synchronization Control by scanning impulse, shift pulse and latch pulse.

Described independent keyboard has N number of button, is provided with N bit keyboard status signal output; Described N bit keyboard status signal is level signal.

Described first shift register has N parallel-by-bit input, N parallel-by-bit outfan and serial output terminal; Described second shift register has serial input terminal, N parallel-by-bit outfan.

The N parallel-by-bit input of described first shift register is connected to N bit keyboard status signal output; The serial input terminal of the second shift register is connected to the serial output terminal of the first shift register; First shift register, the second shift register shift pulse input be connected to shift pulse, the presetting pulse input of the first shift register is connected to scanning impulse. The presetting pulse of described first shift register carries out input and latch for the N parallel-by-bit of the first shift register is inputted data.

Described conditional code depositor is 2 × N position binary register; N bit data input in conditional code depositor is connected to the N parallel-by-bit outfan of the first shift register, and additionally N bit data input is connected to the N parallel-by-bit outfan of the second shift register; The reception pulse input end of described conditional code depositor is connected to latch pulse.

Described encoder has 2 × N position coding input end, and described 2 × N position coding input end is connected to 2 × N bit data outfan of conditional code depositor.

The sequential of described scanning impulse, shift pulse and latch pulse meets claimed below: in one cycle, and scanning impulse has 1 pulse, and shift pulse has N number of pulse, and latch pulse has 1 pulse; Described scanning impulse, shift pulse and latch pulse according to 1 scanning impulse, 1 latch pulse, N number of shift pulse order go round and begin again; The cycle of described scanning impulse and latch pulse is 20～100ms.

Described first shift register, the second shift register shift pulse edge effective; The reception porch of described conditional code depositor is effective.

The presetting pulse edge of described first shift register is effective or level is effective; When the presetting pulse high level of described first shift register is effective, described scanning impulse is positive pulse; During the presetting pulse Low level effective of described first shift register, described scanning impulse is negative pulse.

Described encoder is read only memory.

The conditional code of 2 × N bit data outfan output, 2 × N position of described conditional code depositor; Described conditional code is made up of effective status code and disarmed state code; The key number of described encoder output is made up of effective key number and invalid key number; Described effective status code is produced by effective keyboard operation or state, and encoder inputs the corresponding effectively key number of correspondence output during each effective status code; Described disarmed state code is produced by invalid keyboard operation or state, and encoder inputs all corresponding output invalid key number during all disarmed state codes.

Described encoder has M position key outfan, and the selection of M value should meet 2^MQuantity sum be more than or equal to effective key number with invalid key number.

Described a kind of independent keyboard operation identifies and coding circuit also includes keyboard state change pulse generation unit, for judging whether the key number that independent keyboard exports changes, when the key number of independent keyboard output changes, export keyboard state change pulse.

Described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form; M position delay buffer is for carrying out signal delay respectively to the M position key number of independent keyboard output;The input of the input of M XOR gate respectively M position delay buffer, output signal; The output of M XOR gate is respectively connecting to or the input of door; Or the outfan output keyboard state change pulse of door.

One-to-one relationship is met between described N bit keyboard status signal and N number of button.

The operation identification of described a kind of independent keyboard and coding circuit also include the circuit being made up of agitator, enumerator, pulsqe distributor; The circuit that described scanning impulse, shift pulse, latch pulse are made up of agitator, enumerator, pulsqe distributor produces; Described pulsqe distributor is ROM memory.

Described N position, 2 × N position, M position refer both to binary digit data.

The invention has the beneficial effects as follows: single key stroke, Macintosh operation, keyboard will be maintained the location that state operates, by meeting scanning impulse that specific time sequence requires, shift pulse, latch pulse control to convert to the conditional code of same binary length, adopt Unified coding mode process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code not ibid; If needing increase and decrease button operation function or adjusting button operation function, keyboard scanning circuit structure need not be revised, only need to according to the corresponding relation change encoder between conditional code and the key number after increase and decrease, the storage content namely re-writing read only memory. Described invention circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, reliable operation.

Accompanying drawing explanation

Fig. 1 is that a kind of independent keyboard operation identifies and coding circuit theory diagram;

Fig. 2 is the independent keyboard circuit diagram of the embodiment of the present invention;

Fig. 3 is the Scan orientation circuit diagram of the embodiment of the present invention;

Fig. 4 is the first shift-register circuit figure of the embodiment of the present invention;

Fig. 5 is the pulse sequence figure of the embodiment of the present invention;

Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention;

Fig. 7 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention;

Fig. 8 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.

Detailed description of the invention

Below in conjunction with accompanying drawing, the invention will be further described.

Fig. 1 is that a kind of independent keyboard operation identifies and coding circuit theory diagram, is made up of independent keyboard the 400, first shift register the 100, second shift register 200, conditional code depositor 500, encoder 300.

Fig. 2 is the circuit diagram of the independent keyboard 400 of the embodiment of the present invention, has 4 buttons, by button S1, button S2, button S3, button S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4 form. Status signal I1, I2, I3, I4 of 4 outfans of independent keyboard 400 one_to_one corresponding output key S1, button S2, button S3, button S4 respectively, when button is pressed, the status signal of corresponding output end is low level; When button is not pressed, the status signal of corresponding output end is high level.

First shift register the 100, second shift register 200 in Fig. 1, conditional code depositor 500, encoder 300 form Scan orientation circuit, and embodiment circuit diagram is as shown in Figure 3. The status signal of embodiment independent keyboard circuit output has 4, therefore, first shift register the 100, second shift register 200 is all 4 binary shift registers, wherein, first shift register 100 has parallel input, parallel output and Serial output function, and the second shift register 200 has serial input, parallel output function;4 parallel input terminal L0～L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4, and the serial input terminal D2 of the second shift register 200 is connected to the serial output terminal Q13 of the first shift register 100. Shift pulse input CLK1, CLK2 of first shift register the 100, second shift register 200 are connected to shift pulse CP2, and the presetting pulse input CLK0 of the first shift register 100 is connected to scanning impulse CP1.

Conditional code depositor 500 requires to deposit 8 bit binary data, 4 parallel output terminal Q13～Q10 being connected to the first shift register 100 in its 8 bit data input D57～D50, other 4 parallel output terminal Q23～Q20 being connected to the second shift register 200; In embodiment, D57～D54 is connected to Q23～Q20, D53～D50 and is connected to Q13～Q10. The reception pulse input end CLK5 of conditional code depositor 500 is connected to latch pulse CP3.

8 input A7～A0 of encoder 300 are connected to 8 data output end Q57～Q50 of conditional code depositor 500. Encoder 300 output is scanned through positioning 4 the binary system keys number determined.

In Fig. 3 embodiment, the second shift register 200 can select to be made up of various medium-scale integration shift registers, or is made up of edge triggered flip flop; When being formed the second shift register 200 by edge triggered flip flop, it is preferable that be made up of the d type flip flop of edging trigger. Conditional code depositor 500 is made up of edge triggered flip flop, it is preferable that be made up of the d type flip flop of edging trigger, for instance, it is made up of double D trigger 74HC74,4D trigger 74HC175,8D trigger 74HC273.

Fig. 4 is the circuit diagram of the first shift register 100 of the embodiment of the present invention, is made up of 101～104,8 NAND gate 105～112 of d type flip flop of 4 set, the equal Low level effective of reset function. In embodiment, d type flip flop 101～104 selects double D trigger 74HC74, and it is effective that it triggers rising edge of a pulse. Scanning impulse CP1 controls the set of d type flip flop 101～104, reset function by 8 NAND gate 105～112. For d type flip flop 101, when scanning impulse CP1 is low level, NAND gate 105, NAND gate 106 export high level, and the set of d type flip flop 101, reset function are invalid; When scanning impulse CP1 is high level and L0=0, NAND gate 105 is output asNAND gate 106 is output as L0, and namely the set function of d type flip flop 101 is invalid, reset function effective, makes Q10=0; When scanning impulse CP1 is high level and L0=1, NAND gate 105 is output asNAND gate 106 is output as L0, and namely the set function of d type flip flop 101 is effective, reset function is invalid, makes Q10=1. The operation principle of d type flip flop 102～104 is the same with d type flip flop 101, when scanning impulse CP1 is high level, and Q10=L0, Q11=L1, Q12=L2, Q13=L3; When scanning impulse CP1 is low level, owing to triggering pulse input end CLK10, CLK11, CLK12, CLK13 of d type flip flop 101～104 are connected to CP2, therefore, rising edge at each shift pulse CP2, first shift register 100 moves once position, i.e. Q13=Q12, Q12=Q11, Q11=Q10, Q10=0.

In Fig. 3 embodiment, encoder 300 is read only memory. The input that address input end A7～A0 is encoder 300 of read only memory, the coding outfan C3～C0 that data output end D3～D0 is encoder 300 of read only memory.

The operation of a kind of independent keyboard identifies and the operation principle of coding circuit is as follows:

Scan orientation circuit scanning impulse CP1, shift pulse CP2, latch pulse CP3 control under work, relevant pulse sequence figure is as shown in Figure 5.

In embodiment, the sequential of CP1, CP2, CP3 meets claimed below: in one cycle, and CP1 has 1 pulse, and CP2 has 4 pulses, and CP3 has 1 pulse; Each pulse according to 1 CP1 pulse, 1 CP3 pulse, 4 CP2 pulses order go round and begin again.

CP1, CP2, CP3 pulse meeting timing requirements can be produced by various pulsqe distributors, and Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention, is made up of agitator 801, enumerator 802, pulsqe distributor 803. Clock pulse CP in Fig. 5 is produced by agitator, and CP delivers to enumerator 802 and counts, and enumerator 802 is 12 system Counters, and 12 states (numerical value) of its result P are followed successively by P0 → P11, as shown in Figure 5. Pulsqe distributor 803 in embodiment adopts ROM memory to realize, hereon referred to as pulse distribution ROM memory. The address input of pulse distribution ROM memory is connected to the counting output of enumerator 802, and 3 bit data outfans of pulse distribution ROM memory are output as CP1 pulse, CP2 pulse, CP3 pulse respectively. The write content of pulse distribution ROM memory is in Table 1.

Table 1 pulse distribution ROM memory tables of data

ROM memory address in table 1, namely enumerator output is at least 4 binary codes. Generally, if enumerator 802 adopts binary addition rule, then corresponding 4 binary codes 0000～1011 of P0～P11 order, namely ROM memory address realm is 0000～1011, and the storage content of address 0000～1011 is content corresponding for P0～P11 in table 1.

Pulse distribution ROM memory needs 3 bit data outputs. If the address input of pulse distribution ROM memory has R position, when independent keyboard exports N bit keyboard status signal, R needs to meet 2^RBe more than or equal to 2 × (N+2).

Agitator 801 is multivibrator. CP1 scanning impulse, CP3 latch pulse cycle be 20～100ms. CP1, CP2, CP3 can also be operated the circuit outside identification and coding circuit by a kind of independent keyboard or device provides.

Status signal I1, I2, I3, I4 of independent keyboard 400 output, under the control of scanning impulse CP1, is carried out data latch by the first shift register 100, and the now output of the first shift register 100 is called existing state key assignments; The control via 4 CP2 pulses in a upper cycle of second shift register 200, the output that a upper periodic scanning pulses CP1 is latching to the first shift register 100 is displaced to the second shift register 200 outfan, therefore, now the output of the second shift register 200 is called front state key assignments.

The front state key assignments that existing state key assignments that first shift register 100 is exported by the latch pulse CP3 after scanning impulse CP1, the second shift register 200 export is latched in the outfan of conditional code depositor 500, and the output of conditional code depositor 500 is similarly front state key assignments and existing state key assignments.

The equal edge of shift pulse of first shift register the 100, second shift register 200 is effective, and therefore, CP2 can be positive pulse, it is also possible to be negative pulse; The reception porch of conditional code depositor 500 is effective, and therefore, CP3 can be positive pulse, it is also possible to be negative pulse. The presetting pulse of the first shift register 100 be edge effective time, scanning impulse CP1 can be positive pulse, it is also possible to be negative pulse.The presetting pulse of the first shift register 100 be high level effective time, it is desirable to scanning impulse CP1 is positive pulse; When the presetting pulse of the first shift register 100 is Low level effective, it is desirable to scanning impulse CP1 is negative pulse; In embodiment, the presetting pulse of the first shift register 100 is that high level is effective, so, scanning impulse CP1 adopts positive pulse.

In embodiment, 4 existing state key assignments and 4 front state key assignments of the output of conditional code depositor 500 data output end collectively constitute 8 conditional codes. 8 described conditional codes are for identifying current state and the mode of operation of independent keyboard. Such as, in the present embodiment, the conditional code pressed without key is 11111111; The conditional code of S1 key singly-bound push is 11111110; The conditional code that S1 key singly-bound is pressed and maintained is 11101110; The conditional code of S1 key singly-bound release operation is 11101111; The conditional code of S2 key singly-bound push is 11111101; The conditional code of S4 key singly-bound push is 11110111; The S1 push of S2+S1 combination operation, represents after first pressing S2, maintains, at S2, the state pressed and presses the operation of S1 again, and the conditional code of this operation is 11011100.

Encoder 300 is for being converted to key number by conditional code. In embodiment, it is provided with 7 effective keyboard operations and state, including:

The singly-bound push of operation 0: button S1, key number is 0000;

The singly-bound push of operation 1: button S2, key number is 0001;

The singly-bound push of operation 2: button S3, key number is 0010;

Operation 3: button S3 singly-bound press after maintenance state, key number is 0011;

Operation 4: after button S4 singly-bound is pressed, then the Macintosh operation of the S1 that pushes button, key number is 0100;

Operation 5: after button S4 singly-bound is pressed, then the Macintosh operation of the S2 that pushes button, key number is 0101;

The singly-bound release operation of operation 6: button S1, key number is 0110.

The conditional code obtained according to above-mentioned regulation and key number are shown in coding schedule 2:

Table 2 coding schedule

Keyboard operation	Conditional code (address)	Key number (storage data)
			S1 singly-bound is pressed	11111110	0000
S2 singly-bound is pressed	11111101	0001
			S3 singly-bound is pressed	11111011	0010
Maintenance pressed by S3 singly-bound	10111011	0011
			S4+S1 combination operation	01110110	0100
S4+S2 combination operation	01110101	0101
			S1 singly-bound discharges	11101111	0110
Other operation or states	********	1111

Encoder 300 is combinational logic circuit, and the circuit of design meets the logical relation of table 2.

The encoder 300 of embodiment is preferably made up of read only memory. Selected read only memory has 8 bit address, and totally 2⁸Individual 4 binary storage cells. 7 effective keyboard operations have 7 effective status codes, corresponding 7 effective keys number with state; Using conditional code address A7～A0 as read only memory, in the memory element corresponding with 7 effective status code-phase, using corresponding key number as storage data write. The conditional code produced outside 7 effective keyboard operations and state is disarmed state code, is namely disarmed state code produced by the operation of other in table 2 or state; In other memory element, all write invalid keys number, invalid key number is a value outside 7 effective keys number, and in embodiment, invalid key number is 1111.

Read only memory always works at data output state. When read only memory there is chip select control, data export dash-control function time, its chip select should be made to control, data output dash-control is in effective status.

Key number in embodiment is 4 binary codes. The number of bits of key number can increase as required, or reduces, and now, only need to select the read only memory matched with this.If the selection that the number of bits of key number is M, M value should meet 2^MQuantity sum be more than or equal to effective key number with invalid key number. When independent keyboard has N bit keyboard status signal to export, read only memory 301 needs the input of 2 × N bit address, and M-bit data exports.

If needing increase and decrease button operation function or adjusting button operation function, only need to revise table 2 as required, amended content is re-write the storage content of read only memory.

The edge of the latch pulse CP3 that conditional code depositor 500 carries out the moment of data latch is called state latch edge, is the rising edge of CP3 in embodiment. In embodiment, when independent keyboard S1 singly-bound is pressed, encoder 300 is pressed at S1 singly-bound, after CP1, CP3 two-stage latches, from the state latch of CP3 edge, to the state latch edge of next CP3, encodes outfan C3～C0 run-out key number 0000; When independent keyboard S2 singly-bound is pressed, encoder 300 is pressed at S2 singly-bound, after CP1, CP3 two-stage latches, from the state latch of CP3 edge, to the state latch edge of next CP3, and run-out key number 0001; After independent keyboard first presses S4, then pressing S1, encoder 300 is pressed at S1 Macintosh, after CP1, CP3 two-stage latches, from the state latch of CP3 edge, to the state latch edge of next CP3, and run-out key number 0100; After independent keyboard first presses S4, then pressing S2, encoder 300 is pressed at S2 Macintosh, after CP1, CP3 two-stage latches, from the state latch of CP3 edge, to the state latch edge of next CP3, and run-out key number 0101; When independent keyboard S1 singly-bound discharges, encoder 300 discharges at S1 singly-bound, after CP1, CP3 two-stage latches, from the state latch of CP3 edge, to the state latch edge of next CP3, and run-out key number 0110; It can be seen that, when identify be effective button operation of independent keyboard time, the state latch of the encoder 300 CP3 after this effective button operation is along starting, and to the state latch edge of next CP3, output duration is effective key number of a CP3 periodic width.

In embodiment, when independent keyboard S3 singly-bound is pressed, encoder 300 is pressed at S3 singly-bound, after CP1, CP3 two-stage latches, from the state latch of CP3 edge, to the state latch edge of next CP3, and run-out key number 0010; Start on the state latch edge of ensuing CP3, press maintenance state to S3 singly-bound and terminate, till the CP3 state latch edge after CP1, CP3 two-stage latches, encoder 300 run-out key number 0011; It can therefore be seen that when identify be the maintenance state of independent keyboard time, the persistent period of persistent period and this maintenance state that encoder 300 exports effective key number adapts.

When the state of keyboard or operation are for time outside 7 effective keyboard operations described in table 2 and state, encoder 300 exports invalid key number 1111. No matter it is export effective key number, or output invalid key number, encoder 300 changes the state latch edge that the moment is CP3 of output content; In embodiment, encoder 300 changes the rising edge that the moment is CP3 of output content.

The cycle of CP3 is the scan period of independent keyboard. The keyboard scan cycle is when more than 20ms, it is possible to be effectively shielded from the impact of keyboard shake; The keyboard scan cycle, when below 100ms, is unlikely to omit keyboard operation;Therefore, the cycle of CP3 should control at 20～100ms.

Fig. 7 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention. When identify be effective button operation of independent keyboard time, the state latch of the encoder 300 CP3 after this effective button operation is along starting, and to the state latch edge of next one CP3, output duration is effective key number of a CP3 periodic width. Receive the device of described independent keyboard output, it is necessary to the output of moment inquiry independent keyboard, obtain key number. The period distances of inquiry is necessarily less than the cycle of CP3.

Circuit shown in Fig. 7 is for judging whether the key number that independent keyboard exports changes, when the key number of independent keyboard output changes, output keyboard state change pulse, for assisting the device that receives of independent keyboard to receive the key number of independent keyboard output, such as, using keyboard state change pulse as receive device interrupt request singal.

Circuit shown in Fig. 7 is made up of delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606. Delay buffer 601 is made up of 4 edge triggered flip flops only with Trigger Function, and the trigger input of 4 edge triggered flip flops is the reception pulse input end of delay buffer 601, is connected to CP3; Delay buffer 601 carries out data latch on the state latch edge of CP3.

Delay buffer 601 is for carrying out delay disposal respectively to the 4 bit data C3～C0 of the coding outfan of encoder 300. 4 data input pin D63～D60 of delay buffer 601 are connected to the coding outfan C3～C0 of encoder 300, and the data that 4 data output end Q63～Q60 of delay buffer 601 export accordingly are C31～C01; C31～C01 is after the first-level buffer of delay buffer 601, and its signal postpones a CP3 pulse period than C3～C0, and Fig. 8 show the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates. The T1 being located at CP3 pulse is interval, independent keyboard existence once effectively operates, and the effectively operation of embodiment includes: S1 singly-bound is pressed, S2 singly-bound is pressed, S3 singly-bound is pressed, the S1 of S4+S1 combination operation presses, the S2 of S4+S2 combination operation presses, the release of S1 singly-bound. On the next state latch edge of once effectively operation, i.e. rising edge after CP3 pulse T1 interval in Fig. 8, the coding C3～C0 of encoder 300 output changes; Interval at T2, encoder 300 exports the efficient coding C3～C0 of a CP3 pulse period; At T3, T4 and interval afterwards, coding C3～the C0 of encoder 300 output changes again and enters maintenance state, this maintenance state is probably such as S1 singly-bound and presses maintenance state below, output invalid key number, it is also likely to be S3 singly-bound and presses maintenance state below, export effective key number, until effectively operate next time.

D6 pulse in Fig. 8 schematically illustrates the coding C3～C0 of encoder 300 output and is in maintenance state, it does not have change, still changes, is absent from described D6 pulse in side circuit. As shown in Figure 8, D6 pulse is low level, and the coding C3～C0 schematically illustrating encoder 300 output is in maintenance state, it does not have change; D6 pulse is high level, schematically illustrates encoder 300 and exports the efficient coding C3～C0 in a cycle. What the Q6 in Fig. 8 reflected is the situation of change of C31～C01, it is clear that Q6 postpones a CP3 pulse period than D6.Equally, side circuit is absent from described Q6 pulse.

In Fig. 8, coding C3～the C0 of encoder 300 output is in maintenance state, it is not changed in, still changes, be really the logic circuit being made up of 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606 and complete. Encode in outfan C3～C0 with encoder 300 respectively 1 of 4 XOR gates is corresponding, the input of input respectively 4 delay buffers 601, output signal. Such as, two inputs signal respectively C0 and C01, C01 of XOR gate 602 postpone a CP3 pulse period than C0, and therefore, when C0 changes, XOR gate 602 exports the positive pulse of 1 CP3 pulse period width; When C0 is a CP3 pulse period change width signal, XOR gate 602 exports the positive pulse of 2 CP3 pulse period width. XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1～C3 changes respectively, and principle is with to judge whether C0 changes identical. XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 outfan be respectively connecting to or the input of door 606, or whether door 606 changes for comprehensive descision C0～C3, as long as C0～C3 changes, or namely door 606 exports keyboard state change pulse F, this pulse is positive pulse.

In embodiment, delay buffer 601 selects the 8D trigger 74HC273 that rising edge triggers.

Delay buffer 601 can also adopt other schemes, for instance, adopt RC circuit, utilize 4 RC circuit respectively C0～C3 to be postponed; If the time delay of RC circuit is less than a CP3 pulse period, when then encoder 300 exports the efficient coding C3～C0 in a cycle, starting and export efficient coding C3～C0 to terminate all to produce a keyboard state change pulse at output efficient coding C3～C0, the width of keyboard state change pulse is equal to RC circuit delay time; If the time delay of RC circuit is be more than or equal to a CP3 pulse period, when then encoder 300 exports the efficient coding C3～C0 in a cycle, producing a keyboard state change pulse when exporting efficient coding C3～C0 and starting, this pulse width is be more than or equal to 2 CP3 pulse periods. Require that the time delay of RC circuit is less than 2 CP3 pulse periods, in order to avoid producing to fail to report.

In described invention circuit, single key stroke, Macintosh operation, keyboard will be maintained the location that state operates, the conditional code of same binary length is converted to by 3 Pulse Width Control meeting specific time sequence requirement, adopt Unified coding mode process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code not ibid; If needing increase and decrease button operation function or adjusting button operation function, it is not necessary to amendment keyboard scanning circuit structure, only need to update encoder 300 according to the state code table after increase and decrease, namely re-write the storage content updating read only memory. Described invention circuit does not use the microcontroller such as single-chip microcomputer, ARM, need not run program, reliable operation.

Claims (6)

1. an independent keyboard operation identifies and coding circuit, it is characterised in that be made up of independent keyboard, the first shift register, the second shift register, conditional code depositor, encoder;

Described independent keyboard has N number of button, is provided with N bit keyboard status signal output;

Described first shift register has N parallel-by-bit input, N parallel-by-bit outfan and serial output terminal;Described second shift register has serial input terminal, N parallel-by-bit outfan;

The N parallel-by-bit input of described first shift register is connected to N bit keyboard status signal output; The serial input terminal of the second shift register is connected to the serial output terminal of the first shift register; First shift register, the second shift register shift pulse input be connected to shift pulse, the presetting pulse input of the first shift register is connected to scanning impulse;

Described conditional code depositor is 2 × N position binary register; N bit data input in conditional code depositor is connected to the N parallel-by-bit outfan of the first shift register, and additionally N bit data input is connected to the N parallel-by-bit outfan of the second shift register; The reception pulse input end of described conditional code depositor is connected to latch pulse;

Described encoder has 2 × N position coding input end, and described 2 × N position coding input end is connected to 2 × N bit data outfan of conditional code depositor; Described encoder has M position key outfan.

2. a kind of independent keyboard operation according to claim 1 identifies and coding circuit, it is characterised in that: described encoder is read only memory.

3. a kind of independent keyboard operation according to claim 1 identifies and coding circuit, it is characterised in that: also include the circuit being made up of agitator, enumerator, pulsqe distributor; The circuit that described scanning impulse, shift pulse, latch pulse are made up of agitator, enumerator, pulsqe distributor produces.

4. a kind of independent keyboard operation according to claim 3 identifies and coding circuit, it is characterised in that: described pulsqe distributor is ROM memory.

5. a kind of independent keyboard operation according to claim 1 identifies and coding circuit, it is characterised in that: also include keyboard state change pulse generation unit.

6. a kind of independent keyboard operation according to claim 5 identifies and coding circuit, it is characterised in that: described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form; M position delay buffer is for carrying out signal delay respectively to the M position key number of independent keyboard output; The input of the input of M XOR gate respectively M position delay buffer, output signal; The output of M XOR gate is respectively connecting to or the input of door; Or the outfan output keyboard state change pulse of door.