CN105703780B - Matrix keyboard Scan orientation circuit - Google Patents
Matrix keyboard Scan orientation circuit Download PDFInfo
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- CN105703780B CN105703780B CN201610003614.4A CN201610003614A CN105703780B CN 105703780 B CN105703780 B CN 105703780B CN 201610003614 A CN201610003614 A CN 201610003614A CN 105703780 B CN105703780 B CN 105703780B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/0202—Constructional details or processes of manufacture of the input device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
Abstract
A kind of matrix keyboard Scan orientation circuit is made of matrix keyboard, buffer register, state Code memory, encoder.The circuit is scanned via clock pulses, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, it is converted into the effective status code and invalid state code of same binary length, encoder output and the corresponding effective key number of each effective status code either export invalid key number corresponding with all invalid state codes；Different single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；Button operation function is either adjusted if necessary to increase and decrease button operation function, keyboard scanning circuit structure need not be changed, only need to change encoder according to the conditional code after increase and decrease and the correspondence between key number.The invention circuit does not have to write and run program, reliable operation.
Description
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of matrix keyboard Scan orientation circuit.
Background technology
With the continuous development of embedded technology, current each electronic product generally uses microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by run microcontroller in program come into
Row, encounters interference, program is caused to run fast, and scanner program is by cisco unity malfunction.
Application No. is the patents of invention of CN201010153560.2 " a kind of fast scanning and positioning method of matrix keyboard " to adopt
The Scan orientation process for entering keyboard with the mode that keyboard interrupt triggers is judged using the method that keyboard scan step is repeated several times
Whether button is effective, and the key assignments to being obtained carries out condition adjudgement；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then enters singly-bound tupe；Combination key operation in this way then enters Macintosh tupe.Described in the patent
Method is solved causes the Problem-Errors such as wrong key, continuous touching since keyboard caused by the mechanical property of keyboard itself is shaken,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with key operation is combined；
Not accounting for keyboard state maintains a period of time just to execute the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to change keyboard scan finder structure.
Invention content
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of matrix forms
Keyboard scan positioning circuit is made of matrix keyboard, buffer register, state Code memory, encoder.
The matrix keyboard shares X rows, Y row, is equipped with N bit keyboard status signal outputs；The N bit keyboards state letter
Number be level signal；The N=X+Y.
The buffer register is N binary registers；The positions the N data input pin of buffer register is connected to N keys
Disk status signal output.
The state Code memory is 2 × N binary registers；In the positions the 2 × N data input pin of state Code memory
The positions N be connected to N bit keyboard status signal outputs, the other N positions N data output ends for being connected to buffer register.
The encoder has 2 × N coding input ends, the coding input end 2 × N to be connected to state Code memory
2 × N data output ends；The encoder has M key output ends.
The reception pulse input end of the buffer register and the reception pulse input end of state Code memory are connected to
Clock pulses.
The matrix keyboard is by X row-Y row key-press matrix, row three state buffer, row three state buffer, row Status register
Device, column-shaped state register group at；The line of all key-press matrixs is respectively connected to the output end of row three state buffer, all buttons
Matrix column line is respectively connected to the output end of row three state buffer；All inputs of row three state buffer and row three state buffer
End is connected to low level；The line of all key-press matrixs is respectively connected to the input terminal of row status register, all key-press matrixs
Alignment be respectively connected to the input terminal of row status register；The output end of the row status register and row status register
Output end collectively constitutes keyboard state signal output end.
The matrix keyboard is controlled by sampling pulse and obtains keyboard state signal；The row three state buffer is in sampling arteries and veins
When the low level of punching enables effective, it is desirable that row status register is slow in the rising edge progress data latch of sampling pulse, row tri-state
Enabled effective, the row status register of high level that device is rushed in sampling pulse carries out data latch in the failing edge of sampling pulse；Or
Person is that row three state buffer is when the high level of sampling pulse enables effective, it is desirable that row status register is under sampling pulse
Drop enables effective, row status register in sampling arteries and veins along the latch of progress data, row three state buffer in the low level of sampling pulse
The rising edge of punching carries out data latch.
The buffer register and state Code memory are carried out at the same time data in the rising edge of clock pulses and latch, Huo Zhe
The failing edge of clock pulses is carried out at the same time data latch；2 × N data output ends of the state Code memory export 2 × N
Conditional code；The conditional code is made of effective status code and invalid state code；The key number of the encoder output is by effective key number
It is formed with invalid key number；The effective status code is generated by effective keyboard operation or state, and encoder inputs each effective shape
Output corresponding effectively key number is corresponded to when state code；The invalid state code is generated by invalid keyboard operation or state, and encoder is defeated
Enter all corresponding output invalid key number when all invalid state codes.
The encoder has M key output ends, the selection of M values that should meet 2MMore than or equal to effective key number and invalid key number
The sum of quantity.
The period of the clock pulses is 20~100ms；The period of the sampling pulse is no more than the clock pulses
Period, special case are that the sampling pulse is the clock pulses.
The matrix keyboard Scan orientation circuit further includes oscillator；The oscillator output clock pulses and sampling
Pulse.
The matrix keyboard Scan orientation circuit further includes that keyboard state change pulse generates unit, for judging square
Whether the key number of configuration keyboard output changes, and when the key number of matrix keyboard output changes, exports keyboard state
Change pulse.
The keyboard state change pulse generates unit and is made of M delay buffers, M XOR gate and/or door；M are prolonged
Slow buffer for carrying out signal delay respectively to the positions the M key number that matrix keyboard exports；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
The positions N, 2 × N, M refer both to binary digit data.
The beneficial effects of the invention are as follows：The positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by
Clock pulses scan transformation is handled at the conditional code of same binary length by the way of Unified coding, single key stroke,
Combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If necessary to increase and decrease button operation function or
Person is adjustment button operation function, need not change keyboard scanning circuit structure, only need to be according to the conditional code and key number after increase and decrease
Between correspondence change encoder, re-write the storage content of read-only memory.The invention circuit does not have
Using microcontrollers such as microcontroller, ARM, operation program, reliable operation are not had to.
Description of the drawings
Fig. 1 is matrix keyboard Scan orientation schematic block circuit diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the Scan orientation circuit diagram of the embodiment of the present invention；
Fig. 4 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 5 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific implementation mode
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is matrix keyboard Scan orientation schematic block circuit diagram, by matrix keyboard 400, buffer register 100, shape
State Code memory 200, encoder 300, oscillator 500 form.
Oscillator 500 is multivibrator, is equipped with CP output terminal of clock pulse and CK sampling pulse output ends, CP clock arteries and veins
The period of punching is 20~100ms, and the period of CK sampling pulses is not more than the period of CP clock pulses.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, 2 rows, 2 row is shared, totally 4 buttons, by button
S1, button S2, button S3, button S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, on
Pull-up resistor R4 and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404
Composition.2 output ends Y1, Y2 of row three state buffer 401 are respectively connected to 2 lines, and 2 of row three state buffer 402 are defeated
Outlet Y3, Y4 is respectively connected to 2 alignments；All input terminal X1~X4 of row three state buffer 401 and row three state buffer 402
It is connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of row status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output ends Q41, Q42 of row status register 403 export row state
Signal I1, I2,2 output end Q43, Q44 output row status signals I3, I4 of row status register 404；Row status register
403 2 output ends collectively constitute 4 bit keyboard status signal outputs with 2 output ends of row status register 404, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low levels of row three state buffer 401 are effective, and row three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the CK sampling pulse output ends of oscillator 500.Row status register 403
The CK sampling pulses that oscillator 500 is connected to reception pulse input end CLK3, CLK4 of row status register 404 export
End, row status register 403 carry out data latch in the failing edge of CK sampling pulses, and row status register 404 samples arteries and veins in CK
The rising edge of punching carries out data latch.
When row three state buffer 401 and row three state buffer 402 are using the three state buffer with model, for example, making simultaneously
When with three state buffer 74HC241, the enabled input of 74HC241 is that high level is effective, therefore, CK sampling pulses output end with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With row status register 404 using the data register with model, for example, row status register 403 and row status register 404
When using double D trigger 74HC74 composition data registers, the triggering input of 74HC74 is that rising edge is effective, therefore, in CK
Between sampling pulse output end and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
Buffer register 100, state Code memory 200, encoder 300 in Fig. 1 form Scan orientation circuit, implement
Example circuit diagram is as shown in Figure 3.Matrix keyboard circuit has 4 buttons, and the keyboard state signal of matrix keyboard output is 4 two
Ary codes, therefore, buffer register 100 require deposit 4 bit binary datas, state Code memory 200 require deposit 8 two into
Data processed.4 data input pins of buffer register 100 are connected to I1, I2, I3, I4；8 data of state Code memory 200
In input terminal, 4 data input pins are connected to I1, I2, I3, I4, and in addition 4 data input pins are connected to buffer register 100
4 output ends；8 input terminals of encoder 300 are connected to 8 output ends of state Code memory 200.Encoder 300 is defeated
Go out to be scanned through 4 determining binary system keys number of positioning.
In Fig. 3, trigger 101 forms buffer register 100, trigger 201 forms state Code memory 200.Trigger
101 are made of 4 edge triggered flip flops, and the triggering input terminal of 4 edge triggered flip flops is the reception pulse input of buffer register 100
End, is connected to the CP output terminal of clock pulse of oscillator 500；Trigger 201 is made of 8 edge triggered flip flops, and 8 edges touch
The triggering input terminal for sending out device is the reception pulse input end of state Code memory 200, is connected to the CP clock arteries and veins of oscillator 500
Rush output end.Trigger 101, trigger 201 are preferably made of the d type flip flop of edging trigger, for example, by double D trigger
74HC74,4D trigger 74HC175 compositions.In Fig. 3 embodiments, trigger 101, trigger 201 select rising edge to trigger
8D trigger 74HC273 make the clearing of 74HC273 at this point, unillustrated clear input in Fig. 3 is connected to high level
Function is in invalid state, only has Trigger Function；Trigger 101 only needs 4D triggers, arbitrarily uses selected 8D triggers
4 d type flip flops in 74HC273.Triggering input terminal CLK1, CLK2 of two 8D triggers 74HC273 is connected to CP.
In Fig. 3, read-only memory forms encoder 300.Address input end A7~A0 of read-only memory is encoder 300
Input terminal, data output end D3~D0 of read-only memory is coding output end C3~C0 of encoder 300.
The operation principle of matrix keyboard Scan orientation circuit is as follows：
In Fig. 2,4 buttons of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by CK sampling pulses, using reversal process obtain keyboard state signal I4,
I3、I2、I1.For example, it is 1010 that the keyboard state signal of key pressing, which is not the keyboard state signal that 1111, S1 is pressed, S1, S2
The keyboard state signal pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key assignments.
The control of CK sampling pulses carries out the method that key assignments is read in sampling to matrix keyboard：In the low electricity of CK sampling pulses
It is flat, all lines are controlled by row three state buffer 401 and export low level, row three state buffer 402 exports high-impedance state and opens row
Line；It is sampled by row status register 404 in the rising edge of CK sampling pulses and reads alignment state as the 2 high of key assignments；In CK
The high level of sampling pulse controls all alignments by row three state buffer 402 and exports low level, and row three state buffer 401 is defeated
Go out high-impedance state and opens line；It is sampled by row status register 403 in the failing edge of CK sampling pulses and reads line state as key
Low 2 of value；In cycles, 4 key assignments that row status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from the control of CK sampling pulses and reads the method for key assignments it is found that row three state buffer
401 when the low level of CK sampling pulses enables effective, while requiring row status register 404 in the rising edge of CK sampling pulses
Data latch, row three state buffer 402 are carried out in enabled effective, the row status register 403 of the high level of CK sampling pulses in CK
The failing edge of sampling pulse carries out data latch.In turn, if row three state buffer 401 makes in the high level of CK sampling pulses
When can be effective, while row status register 404 being required to carry out data latch, row three state buffer in the failing edge of CK sampling pulses
402 CK sampling pulses low level is enabled effectively, row status register 403 carries out data lock in the rising edge of CK sampling pulses
It deposits.
During above-mentioned CK sampling pulses control sampling and read key assignments, row status register 403, row status register
404 at the time of precisely row three state buffer 402 is with the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or row status register 404 can be sampled correctly.If it is required that having in certain sequential
Allowance can then postpone, method to being connected to row three state buffer 402 and the CK sampling pulses of row three state buffer 401
Be enable CK sampling pulses by RC retardation ratio circuit be then connected to row three state buffer 401 and row three state buffer 402 EN1,
EN2, delay time are determined by RC retardation ratio circuit, determine that the principle of the delay time of RC retardation ratio circuit is, the CK of delay samples arteries and veins
It rushes phase and is no more than 90 °；Either CK sampling pulses are then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of row three state buffer 402, delay time at this time is the overall delay time of several gate circuits.
Buffer register 100, state Code memory 200 have under the control of CP clock pulses in each period of CP
Effect triggering is along progress data latch.In Fig. 3,74HC273 is that rising edge triggering is effective, therefore, effective triggering of CP clock pulses
Edge is rising edge.
4 data input pin D20~D23 in 8 data input pins of state Code memory 200 are connected directly to matrix
Formula keyboard output status signal I1, I2, I3, I4, in addition 4 data input pin D24~D27 be connected to buffer register 100
Data output end Q10~Q13,4 data input pin D10~D13 of buffer register 100 are connected directly to matrix keyboard
Status signal I1, I2, I3, I4 of output, therefore, on effective triggering edge of CP clock pulses, 8 of state Code memory 200
In data output end, 4 data corresponding with status signal I1, I2, I3, I4 for being connected directly to matrix keyboard output are defeated
The data that outlet Q20~Q23 is latched are the current state of matrix keyboard, and 4 digits are stated to be existing state key assignments；It is slow with being connected to
The data for rushing the corresponding 4 data output ends Q24~Q27 latches of data output end of register 100 are matrix keyboard
Previous state, state key assignments before 4 digits are stated to be.4 existing state key assignments and 4 of 200 data output end of state Code memory output
State key assignments collectively constitutes 8 conditional codes before position.
The current state and mode of operation of 8 conditional codes matrix keyboard for identification.For example, the present embodiment
In, the conditional code of no key pressing is 11111111；The conditional code of S1 key singly-bound pushes is 11111010；S1 key singly-bounds are pressed
And the conditional code maintained is 10101010；The conditional code of S1 key singly-bounds release operation is 10101111；S2 key singly-bound pushes
Conditional code be 11110110；The conditional code of S4 key singly-bound pushes is 11110101；The S1 of S2+S1 combination operations presses behaviour
Make, after expression first presses S2, maintains the state pressed to press the operation of S1 again in S2, the conditional code of the operation is 01100010.
Encoder 300 is used to conditional code being converted to key number.In embodiment, it is equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound push of button S1, key number are 0000；
Operation 1：The singly-bound push of button S2, key number are 0001；
Operation 2：The singly-bound push of button S3, key number are 0010；
Operation 3：Button S3 singly-bounds press after maintenance state, key number be 0011；
Operation 4：After button S4 singly-bounds are pressed, then the combination key operation of S2 is pushed button, key number is 0100；
Operation 5：The singly-bound release operation of button S1, key number is 0101.
The conditional code and key number obtained according to above-mentioned regulation is shown in coding schedule 1：
1 coding schedule of table
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bounds are pressed | 11111010 | 0000 |
| S2 singly-bounds are pressed | 11110110 | 0001 |
| S3 singly-bounds are pressed | 11111001 | 0010 |
| S3 singly-bounds press maintenance | 10011001 | 0011 |
| S4+S2 combination operations | 01010100 | 0100 |
| S1 singly-bounds discharge | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 1.
The encoder 300 of embodiment is preferably made of read-only memory.Read-only memory has 8 bit address, and totally 28A 4 two
System storage unit.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state；By state
Address A7~A0 of the code as read-only memory, in storage unit corresponding with 6 effective status codes, by corresponding key number
As storage data write-in.The conditional code generated except 6 effective keyboard operations and state is invalid state code, i.e., in table 1
Other operation or state caused by be invalid state code；In other storage units, invalid key number, invalid key is all written
Number for a value except 6 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When read-only memory has piece selected control system, data output slow
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase as needed, or subtract
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M values is answered
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has the output of N bit keyboard status signals
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to change table 1 as needed, it will
Modified content re-writes the storage content of read-only memory.
In embodiment, when matrix keyboard S1 singly-bounds are pressed, CP clock pulses of the encoder 300 after S1 singly-bounds are pressed
Effective triggering along starting, to effective triggering edge of next CP clock pulses until, coding output end C3~C0 run-out keies number
0000；When matrix keyboard S2 singly-bounds are pressed, effective triggering edge of CP clock pulses of the encoder 300 after S2 singly-bounds are pressed
Start, until effective triggering edge of next CP clock pulses, run-out key number 0001；After matrix keyboard first presses S4,
S2 is pressed again, and effective triggering edge that encoder 300 combines the CP clock pulses after key pressing in S2 starts, until next CP clocks
Until effective triggering edge of pulse, run-out key number 0100；When matrix keyboard S1 singly-bounds discharge, encoder 300 is in S1 singly-bounds
Effective triggering edge of CP clock pulses after release starts, until effective triggering edge of next CP clock pulses, run-out key
Number 0101；It can therefore be seen that when identification be effective button operation of matrix keyboard when, encoder 300 is effectively pressed at this
Effective triggering edge of CP clock pulses after key operation starts, until effective triggering edge of next CP clock pulses, output
Duration is effective key number of CP width clock cycle.
In embodiment, when matrix keyboard S3 singly-bounds are pressed, CP clock pulses of the encoder 300 after S3 singly-bounds are pressed
Effective triggering along starting, until effective triggering edge of next CP clock pulses, run-out key number 0010；In next CP
Effective triggering edge of clock pulses starts, until the effective of next CP clock pulses after S3 singly-bounds press maintenance state touches
Until sending out edge, 300 run-out key number 0011 of encoder；It can therefore be seen that when identification be the maintenance state of matrix keyboard when,
Encoder 300 exports the duration of effective key number and the duration of the maintenance state is adapted.
When except the state of keyboard or operation being 6 effective keyboard operations and state described in table 1, encoder
300 output invalid keys number 1111.Effective key number, or output invalid key number are either exported, encoder 300 changes output content
At the time of for CP clock pulses effective triggering edge；In embodiment, encoder 300 is CP clock arteries and veins at the time of changing output content
The rising edge of punching.
The period of CP clock pulses is the scan period of matrix keyboard.The keyboard scan period, can in 20ms or more
It has been effectively shielded from the influence of keyboard shake；The keyboard scan period in 100ms or less, is unlikely to omit keyboard operation；
Therefore, the period of CP clock pulses should control in 20~100ms.
The cycle request of CK sampling pulses is not more than the period of CP clock pulses, in this way, each effective in CP clock pulses
When triggering is along acquisition conditional code, it can ensure that 4 key assignments that row status register 404, row status register 403 export are always
The last state of matrix keyboard.The special case of CK sampling pulses is directly to use CP clock pulses as CK sampling pulses.
In embodiment, CP clock pulses, CK sampling pulses are generated and are exported by oscillator 500.CP clock pulses and CK
Sampling pulse can also by except matrix keyboard Scan orientation circuit circuit or device provide.
Fig. 4 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is matrix form
When effective button operation of keyboard, effective triggering edge of CP clock pulses of the encoder 300 after effective button operation starts,
Until effective triggering edge of next CP clock pulses, output duration is the effective of CP width clock cycle
Key number.The device for receiving the matrix keyboard output, needs the output for inquiring matrix keyboard constantly, obtains key number.Inquiry
Period distances be necessarily less than period of CP clock pulses.
Whether key number of the circuit shown in Fig. 4 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, export keyboard state change pulse, be used for the reception device receiving matrix formula of auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 4 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.By only being formed with 4 edge triggered flip flops of Trigger Function, 4 edge triggered flip flops touch delay buffer 601
The reception pulse input end that input terminal is delay buffer 601 is sent out, the CP output terminal of clock pulse of oscillator 500 is connected to；
Delay buffer 601 carries out data latch on effective triggering edge of CP clock pulses.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output end of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output end C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is buffered by delay
After the first-level buffer of device 601, signal ratio C3~C0 postpones CP clock cycles, and Fig. 5 show the embodiment of the present invention
The waveform correlation schematic diagram that effectively operates of keyboard.The sections T1 of CP clock pulses are located at, matrix keyboard exists primary effective
It operates, effective operation of embodiment includes：S1 singly-bounds are pressed, S2 singly-bounds are pressed, S3 singly-bounds are pressed, the S2 of S4+S2 combination operations
It presses, the release of S1 singly-bounds.On the next effective triggering edge once effectively operated, i.e. in Fig. 5 after the sections CP clock pulses T1
Rising edge, encoder 300 export coding C3~C0 change；In the sections T2, encoder 300 exports having for a cycle
Effect coding C3~C0；In T3, T4 and section later, coding C3~C0 that encoder 300 exports changes and enters maintenance again
State, the maintenance state may be that such as S1 singly-bounds press subsequent maintenance state, export invalid key number, it is also possible to S3 singly-bounds
Subsequent maintenance state is pressed, effective key number is exported, until effectively operation next time.
Coding C3~C0 that D6 pulses in Fig. 5 schematically illustrate the output of encoder 300 is to be in maintenance state, is not become
Change, still change, the D6 pulses are not present in actual circuit.As shown in figure 5, D6 pulses are low level, illustrate table
Show that coding C3~C0 that encoder 300 exports is to be in maintenance state, does not change；D6 pulses are high level, schematically illustrate volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 5 reflected is the situation of change of C31~C01, it is clear that
Q6 ratios D6 postpones CP clock cycles.Equally, the Q6 pulses are not present in actual circuit.
In Fig. 5, coding C3~C0 that encoder 300 exports is to be in maintenance state, does not change, still changes,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
At logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output end C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 ratio C0 postpones CP clock cycles, and therefore, when C0 changes, XOR gate 602 exports 1 CP clock
The positive pulse of pulse period width；When C0 is a CP change width clock cycle signal, XOR gate 602 exports 2
The positive pulse of CP width clock cycle.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 sends out respectively
Changing, principle with judge it is identical whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605
Output end is respectively connected to or whether the input terminal of door 606 or door 606 change for comprehensive descision C0~C3, as long as C0
~C3 changes or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D triggers 74HC273 of rising edge triggering.In embodiment, encoder
300 outputs are 4 binary system keys number, therefore, delay buffer 601 needs, 4 d type flip flops.Due to delay buffer 601
In 4 d type flip flops and trigger 101 in the triggering input terminals of 4 d type flip flops be connected to the CP clocks of oscillator 500
Pulse output end, therefore, delay buffer 601 can share a 8D triggers 74HC273 with trigger 101.
Delay buffer 601 can also use other schemes, for example, using RC circuits, using 4 RC circuits respectively to C0
~C3 is postponed；If the delay time of RC circuits is less than CP clock cycles, encoder 300 exports a week
When efficient coding C3~C0 of phase, starts and export efficient coding C3~C0 in output efficient coding C3~C0 and terminate all to generate one
The width of a keyboard state change pulse, keyboard state change pulse is equal to RC circuit delay times；If the delay of RC circuits
Time is more than or equal to CP clock cycles, then when encoder 300 exports efficient coding C3~C0 of a cycle, defeated
Go out one keyboard state change pulse of generation when efficient coding C3~C0 starts, pulse width is more than or equal to 2 CP clock pulses
Period.It is required that the delay time of RC circuits is no more than 2 CP clock cycles, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by CP
Pulse scan transformation is handled at the conditional code of same binary length by the way of Unified coding, single key stroke, combination
Key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If necessary to increase and decrease button operation function either
Button operation function is adjusted, keyboard scanning circuit structure need not be changed, need to only be updated and be encoded according to the state code table after increase and decrease
Device 300, the storage content for re-writing update read-only memory.The invention circuit does not use microcontroller, ARM etc.
Microcontroller does not have to operation program, reliable operation.
Claims (6)
1. a kind of matrix keyboard Scan orientation circuit, which is characterized in that posted by matrix keyboard, buffer register, conditional code
Storage, encoder composition；
The matrix keyboard shares X rows, Y row, is equipped with N bit keyboard status signal outputs；The N bit keyboards status signal is
Level signal；The N=X+Y；
The buffer register is N binary registers；The positions the N data input pin of buffer register is connected to N bit keyboard shapes
State signal output end；
The state Code memory is 2 × N binary registers；N in the positions the 2 × N data input pin of state Code memory
Position is connected to N bit keyboard status signal outputs, in addition the N positions the N data output ends for being connected to buffer register；
The encoder has 2 × N coding input ends, the coding input end 2 × N to be connected to 2 × N of state Code memory
Position data output end；
The reception pulse input end of the buffer register and the reception pulse input end of state Code memory are connected to clock
Pulse；The matrix keyboard is controlled by sampling pulse and obtains N bit keyboard status signals.
2. matrix keyboard Scan orientation circuit according to claim 1, it is characterised in that：The matrix keyboard is by X
Row-Y row key-press matrix, row three state buffer, row three state buffer, row status register, column-shaped state register group at；It is all to press
The line of key matrix is respectively connected to the output end of row three state buffer, and the alignment of all key-press matrixs is respectively connected to row tri-state
The output end of buffer；All input terminals of row three state buffer and row three state buffer are connected to low level；It is all to press bond moment
The line of battle array is respectively connected to the input terminal of row status register, and the alignment of all key-press matrixs is respectively connected to row Status register
The input terminal of device；The output end of the row status register collectively constitutes keyboard state signal with the output end of row status register
Output end.
3. matrix keyboard Scan orientation circuit according to claim 2, it is characterised in that：The row three state buffer exists
When the low level of sampling pulse enables effective, it is desirable that row status register carries out data latch, row in the rising edge of sampling pulse
Three state buffer carries out data lock in enabled effective, the row status register of high level of sampling pulse in the failing edge of sampling pulse
It deposits；Either, row three state buffer is when the high level of sampling pulse enables effective, it is desirable that row status register is in sampling pulse
Failing edge carry out data latches, row three state buffer the low level of sampling pulse is enabled effectively, row status register is taking
The rising edge of sample pulse carries out data latch.
4. matrix keyboard Scan orientation circuit according to claim 1, it is characterised in that：The buffer register and shape
State Code memory is carried out at the same time data in the rising edge of clock pulses and latches, or is carried out at the same time number in the failing edge of clock pulses
According to latch；2 × N data output ends of the state Code memory export 2 × N conditional codes；The conditional code is by effective shape
State code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；Effective shape
State code is generated by effective keyboard operation or state, and encoder corresponds to output corresponding effective key when inputting each effective status code
Number；The invalid state code is generated by invalid keyboard operation or state, and encoder all corresponds to defeated when inputting all invalid state codes
Go out invalid key number.
5. matrix keyboard Scan orientation circuit according to claim 4, it is characterised in that：The encoder has M keys
Number output end, the selection of M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
6. a kind of matrix keyboard Scan orientation circuit according to claim 5, it is characterised in that：It further include keyboard state
Change pulse generates unit, and whether the key number for the output of judgment matrix formula keyboard changes, when matrix keyboard output
When key number changes, keyboard state change pulse is exported.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003614.4A CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
| CN201810660631.4A CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
| CN201810660969.XA CN108880561B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and positioning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003614.4A CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810660969.XA Division CN108880561B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and positioning method |
| CN201810660631.4A Division CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105703780A CN105703780A (en) | 2016-06-22 |
| CN105703780B true CN105703780B (en) | 2018-09-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610003614.4A Active CN105703780B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard Scan orientation circuit |
| CN201810660631.4A Expired - Fee Related CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
| CN201810660969.XA Expired - Fee Related CN108880561B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and positioning method |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810660631.4A Expired - Fee Related CN108874167B (en) | 2016-01-05 | 2016-01-05 | Keyboard state change pulse generating circuit |
| CN201810660969.XA Expired - Fee Related CN108880561B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and positioning method |
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| Country | Link |
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| CN (3) | CN105703780B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1815416A (en) * | 2005-02-01 | 2006-08-09 | 艾默生网络能源系统有限公司 | Keyboard circuit |
| CN1949288A (en) * | 2006-11-24 | 2007-04-18 | 苏州市华芯微电子有限公司 | Variable length coding method and circuit thereof |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
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|---|---|---|---|---|
| SU1005011A1 (en) * | 1981-06-09 | 1983-03-15 | Уфимский Ордена Ленина Авиационный Институт Им.Орджоникидзе | Data input device |
| JPS6062259A (en) * | 1983-09-16 | 1985-04-10 | Hitachi Ltd | Data transmission equipment |
| JPS61161836A (en) * | 1985-01-11 | 1986-07-22 | Nec Corp | Switch signal coding device |
| CN1049415A (en) * | 1989-08-09 | 1991-02-20 | 东少青 | Abacus interface arrangement of general computer |
| US5274371A (en) * | 1991-01-29 | 1993-12-28 | Industrial Technology Research Institute | Extended time-shared scanning keyboard interface |
| JP2950458B2 (en) * | 1993-12-28 | 1999-09-20 | 株式会社河合楽器製作所 | Electronic musical instrument |
| US7177775B2 (en) * | 2005-04-29 | 2007-02-13 | International Business Machines Corporation | Testable digital delay line |
| CN101789793A (en) * | 2010-01-15 | 2010-07-28 | 电子科技大学中山学院 | Determinant linear array coordinate scanning circuit |
| CN106342405B (en) * | 2010-09-14 | 2014-05-14 | 中国航空工业集团公司雷华电子技术研究所 | Digital radar frequency synthesizer controls pulse-generating circuit |
| CN202059394U (en) * | 2011-05-09 | 2011-11-30 | 广州励丰声光科技有限公司 | Matrix keyboard scanning device based on programmable element |
| CN103279197B (en) * | 2013-06-08 | 2015-12-09 | 湖南工业大学 | A kind of Scan orientation method of keyboard |
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2016
- 2016-01-05 CN CN201610003614.4A patent/CN105703780B/en active Active
- 2016-01-05 CN CN201810660631.4A patent/CN108874167B/en not_active Expired - Fee Related
- 2016-01-05 CN CN201810660969.XA patent/CN108880561B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1815416A (en) * | 2005-02-01 | 2006-08-09 | 艾默生网络能源系统有限公司 | Keyboard circuit |
| CN1949288A (en) * | 2006-11-24 | 2007-04-18 | 苏州市华芯微电子有限公司 | Variable length coding method and circuit thereof |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108880561A (en) | 2018-11-23 |
| CN108874167A (en) | 2018-11-23 |
| CN105703780A (en) | 2016-06-22 |
| CN108874167B (en) | 2021-02-26 |
| CN108880561B (en) | 2022-03-18 |
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