CN101789793A - Determinant linear array coordinate scanning circuit - Google Patents
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Abstract
The invention discloses a determinant linear array coordinate scanning circuit, which comprises an m-path pulse distribution circuit, a keystroke event judging circuit, a determinant signal filtering shaping and coordinate latching signal generating circuit, a determinant coordinate encoding circuit and a determinant coordinate value storage circuit. The m-path pulse distribution circuit sequentially outputs low level at row line ports of the m multiplied by n matrix key circuit, meanwhile, the keystroke event indicating circuit judges whether a keystroke event is generated according to the level of a column line end, and the row and column coordinate coding circuit 4 codes the current state values of the row line ports and the column line ports into row and column coordinates; after the keystroke event indication signal is generated, the output result of the current row-column coordinate coding circuit is latched into a coordinate value storage circuit by utilizing a latch signal generated by a row-column signal filtering shaping and coordinate latch signal generating circuit, and the row-column coordinate value of the coordinate value storage circuit is the coordinate of the current pressed key. The invention has the advantages of simple design, convenient implementation, low hardware cost, no loss of generality and the like.
Description
[technical field]
The present invention relates to electronic circuit field, particularly a kind of determinant linear array coordinate scanning circuit of electronic equipment.
[background technology]
Determinant linear array press-key structure circuit is by the horizontal vertical linear array structure that discharges that intersects of m bar line and n bar alignment, be provided with the button that they can be connected in the place that line and alignment intersect, total like this m * n button, be commonly used to the position or the coordinate of measurement plane China and foreign countries point of force application, this structure is widely used in the electronic apparatus application such as planar contacts location, matrix keyboard.The line and the alignment short circuit of application point correspondence when external force acts on the linear array interval.Position of action point changes into the digital coordinates signal and generally adopts scan method, and two kinds of scan methods are arranged traditionally, and software scans method and general-purpose chip scan method, software scans method are to use control program to produce scanning sequence to obtain the method for coordinate.This method needs the outer MPU processing time of occupying volume in order to respond input; Another kind of general-purpose chip scan method is to adopt the universal keyboard interface chip as 8279, yet such chip often needs to carry out the setting of relative complex, and the rank scanning line of support is also very limited.In the electronic system of non-program software control, above-mentioned two kinds of methods are difficult to implement especially.
[summary of the invention]
The present invention has overcome the deficiency of above-mentioned technology, provide a kind of design succinct, implement convenient, hardware cost is cheap and do not lose the coordinate scanning circuit of versatility.
For achieving the above object, the present invention has adopted following technical proposal: a kind of determinant linear array coordinate scanning circuit includes:
M output is to m line input of the m * n matrix press-key circuit m road pulse distributor of output low level signal successively;
The thump incident judging circuit that input is connected with n alignment output of m * n determinant linear array key circuit;
Ranks signal filtering shaping that input is connected with thump incident judging circuit output and coordinate latch signal produce circuit;
The ranks coordinate coding circuit that the n position signal that n alignment output of m road pulse distributor circulation output m position count signal and m * n matrix press-key circuit exported is encoded respectively;
Ranks signal filtering shaping and coordinate latch signal are produced the ranks coordinate figure memory circuit that circuit and ranks coordinate coding circuit output signal are stored.
Described m road pulse distributor is by 2
xThe effective x-m decoder of system counter and low level is formed, wherein
M is a natural number, described 2
xThe terminal count output of system counter is connected with the address choice input of x-m decoder, and the m of an x-m decoder output is connected with m line input of m * n matrix press-key circuit respectively.
Described thump incident judging circuit is the NAND gate with n input, and its n input is connected with n alignment output of m * n matrix press-key circuit respectively.
Described ranks signal filtering shaping and coordinate latch signal produce circuit and include 1 d type flip flop that is triggered by clock signal, and the signal input part of d type flip flop is connected with the output of described NAND gate.
Described ranks coordinate coding circuit is made up of m-x line encoder and n-y alignment encoder, m input of m-x line encoder is connected respectively with m output of the x-m encoder of m road pulse distributor, n input of n-y alignment encoder is connected respectively with n alignment output of m * n matrix press-key circuit, wherein
M, n are natural number.
Described ranks coordinate figure memory circuit is made up of x+y d type flip flop, the input of all d type flip flops respectively with the corresponding connection of output of m-x line encoder and n-y alignment encoder, the output that described ranks signal filtering shaping and coordinate latch signal produce the d type flip flop on the circuit is connected with the clock signal input terminal of x+y d type flip flop.
Described m * n matrix press-key circuit is 4 * 4 matrix press-key circuit, includes 16 buttons;
Described m road pulse distributor is 4 road pulse distributors, and this 4 road pulse distributor is made up of 4 system counters and 2-4 decoder;
Described thump incident judging circuit is the NAND gate with 4 inputs;
Described ranks coordinate coding circuit is made up of 4-2 line encoder and 4-2 alignment encoder;
Described ranks coordinate figure memory circuit is made up of 4 d type flip flops.
It is that 2 continuous outputs of the integrated circuit chip of 16 system counters of 74163 carry out 4 and clap counting that described 4 system counters adopt model, described 2-4 decoder adopts the decoder integrated circuit (IC) chip of model 74139,2 inputs of this decoder integrated circuit (IC) chip are connected with 2 outputs of the integrated circuit chip of 16 system counters respectively, and 4 outputs of this decoder integrated circuit (IC) chip are connected with 4 line inputs of 4 * 4 matrix press-key circuit respectively;
Described NAND gate model is 7420, and its 4 inputs are connected with 4 alignment outputs of 4 * 4 matrix press-key circuit respectively;
Described ranks signal filtering shaping and coordinate latch signal produce circuit to adopt model are 1 d type flip flop in 74171 the integrated circuit (IC) chip, and the input of this d type flip flop is connected with the output of described NAND gate;
Described 4-2 line encoder and 4-2 alignment encoder all adopt model be 74148 8-4 encoder integrated circuit (IC) chip preceding 4 the tunnel as the coding input, 4 coding inputs of a 8-4 encoder integrated circuit (IC) chip are connected with 4 outputs of described decoder integrated circuit (IC) chip respectively, and 4 coding inputs of another 8-4 encoder integrated circuit (IC) chip are connected with 4 alignment outputs of 4 * 4 matrix press-key circuit respectively;
Described ranks coordinate figure memory circuit employing model is 74171 integrated circuit (IC) chip, this integrated circuit (IC) chip contains 4 d type flip flops, and the clock signal input terminal of this integrated circuit (IC) chip is connected with the output that described ranks signal filtering shaping and coordinate latch signal produce the integrated circuit (IC) chip of 74171 on the circuit; The corresponding connection of 2 outputs of the input of 2 d type flip flops and a 8-4 encoder integrated circuit (IC) chip, the corresponding connection of 2 outputs of the input of other 2 d type flip flops and another 8-4 encoder integrated circuit (IC) chip.
The invention has the beneficial effects as follows: during the circuit operation, m road pulse distributor is at row signal line output low level successively, thump incident indicating circuit judges whether column signal line produces the thump incident simultaneously, after thump incident index signal process filter shape and the shaping of ranks coordinate latch signal generation circuit filtering, the result that ranks holding wire coordinate coding circuit is exported is latched in the coordinate figure memory circuit.The present invention is the rank scanning line supported of designing institute according to actual needs, is adapted at during the more planar contacts location of non-program software control, rank scanning linear array, matrix keyboard etc. use, have design succinct, implement conveniently, characteristics that versatility is good.
[description of drawings]
Be described in further detail below in conjunction with accompanying drawing and embodiments of the present invention:
Fig. 1 is the block diagram of the present invention to m * when n matrix press-key circuit scans;
Block diagram when Fig. 2 scans 4 * 4 matrix press-key circuit for the present invention;
The circuit theory diagrams of 4 road pulse distributors that Fig. 3 adopts when for the present invention 4 * 4 matrix press-key circuit being scanned;
The circuit theory diagrams of the thump incident judging circuit that Fig. 4 adopts when for the present invention 4 * 4 matrix press-key circuit being scanned with four inputs;
Ranks signal filtering shaping that Fig. 5 adopts when for the present invention 4 * 4 matrix press-key circuit being scanned and coordinate latch signal produce the circuit theory diagrams of circuit;
The circuit theory diagrams of the ranks coordinate coding circuit that Fig. 6 adopts when for the present invention 4 * 4 matrix press-key circuit being scanned;
The circuit theory diagrams of the ranks coordinate figure memory circuit that Fig. 7 adopts when for the present invention 4 * 4 matrix press-key circuit being scanned.
[embodiment]
Referring to Fig. 1, the present invention is a kind of determinant linear array coordinate scanning circuit, and it includes: m road pulse distributor 1, thump incident judging circuit 2, ranks signal filtering shaping and coordinate latch signal produce circuit 3, ranks coordinate coding circuit 4 and ranks coordinate figure memory circuit.
M shown in Figure 1 * n matrix press-key circuit 6 is that wherein m, n are natural number, are provided with the button that they can be connected in the place that line and alignment intersect, total like this m * n button, line port R by the horizontal vertical linear array structure that discharges that intersects of m bar line and n bar alignment
0～R
M-1Be the line input, both the sweep signal input; Alignment port L
0～L
N-1Be the alignment output, the signal output part that had both scanned; N bar alignment is connected with power supply VCC by pull-up resistor respectively.
Ranks line infall is defeated the short circuit of masterpiece time spent outside, promptly produces the thump incident; When cancelling, external force disconnects.For obtaining the coordinate of contact, circulate to line port R with certain frequency
0～R
M-1Input 0111 ... 1111,10111 ... 111,1101 ... 1111 ..., 1111 ... 1101,1111 ... 1110, both successively to each line cap R
0～R
M-1The input low level signal has only one to be low level signal in each group row signal, and all the other all are high level signals.By reading alignment port L
0～L
N-1State, just can judge position or coordinate that the thump incident produces.When not having outer point of force application, since the existence of pull-up resistor, alignment port L
0～L
N-1The value of reading is high level 1111 entirely ... 1111; When outer point of force application was arranged, because the corresponding ranks line short circuit of this point, therefore when line low level sweep signal was swept to button place capable, the alignment that joins with it also was a low level, and Dui Ying coordinate is promptly definite thus.For example as line R
0～R
M-1Be input as 1111 ... 1011, alignment L
0～L
N-1The value of reading in is 1011 ... 1111, the expression key contacts is in the position of capable the 2nd row of m-2, and its coordinate is (m-2,2).
Circuit when operation, m road pulse distributor 1 (pulse_assign module) the line cap R that is expert at
0～R
M-1Output low level successively, the clock width is 1 sclk clock cycle, thump incident indicating circuit 2 (key_event modules) have judged whether that the thump incident produces simultaneously, if alignment port L
0～L
N-1In a port show as low level, then produce the thump incident.Line port R
0～R
M-1, alignment port L
0～L
N-1The current state value is encoded into the ranks coordinate by ranks coordinate coding circuit 4 (row_line_coder module).After thump incident index signal produces, through producing latch signal behind ranks signal filtering shaping and coordinate latch signal generation circuit 3 (filter_latch module) filter shape, utilize this latch signal that current ranks coordinate coding circuit 4 output results are latched in the coordinate figure memory circuit 5 (storage module), the ranks coordinate figure that coordinate figure memory circuit 5 stores is exactly the current coordinate that pushes button, and just can know that by this coordinate certain button presses.The circuit structure and the principle of each module are described respectively below.
Described m road pulse distributor 1 is by 2
xThe effective x-m decoder of system counter and low level is formed, wherein
X, m are natural number, are the economize on hardware resource, can select to make x to satisfy the integer of the minimum of above-mentioned formula.Described 2
xThe terminal count output of system counter is connected with the address choice input of x-m decoder, the m of an x-m decoder output respectively with the line port R of m * n matrix press-key circuit 6
0～R
M-1(m line input) connects.2
xThe system counter is under clock pulse drives, and output periodically produces counting output result, behind the x-m decoder, successively in the decoder output negative pulse of 1 clock cycle of output, thereby has realized m road pulse distribution.
Described thump incident judging circuit 2 adopts has the NAND gate of n input, n input respectively with the alignment port L of m * n determinant linear array key circuit
0～L
N-1(n alignment output) connects.When external force acted on the linear array interval, the thump incident had promptly taken place in the line of application point correspondence and alignment short circuit.Thump incident judging circuit is used to judge that external force effect keystroke takes place constantly, and notice back one-level circuit is made subsequent treatment.When the thump incident takes place, when the negative pulse of pulse distributor output is assigned to this alignment, the line of application point correspondence and alignment short circuit, this alignment also shows as low level, as long as therefore the thump incident occurred, under the pulse distributor output action, alignment port L
0～L
N-1In always have a holding wire to show as low level, so NAND gate that thump incident judging circuit 2 can be by having n input or have realizing of n input with door.
Described ranks coordinate coding circuit 4 is made up of m-x line encoder and n-y alignment encoder, m input of m-x line encoder is connected respectively with m output of the x-m encoder of m road pulse distributor 1, n input of n-y alignment encoder is connected respectively with n alignment output of m * n matrix press-key circuit 6, wherein
X, m, n, y are natural number.M-x line encoder is encoded to m road pulse distributor 1 circulation output m position count signal, and n-y alignment encoder is encoded to the n position signal of n alignment output output of m * n matrix press-key circuit 6.Usually, line port R
0～R
M-1With alignment port L
0～L
N-1State need the memory space of m+n position altogether, also increase gradually along with the ranks line increases required memory space, to line port R
0～R
M-1With alignment port L
0～L
N-1The alignment state encoding is converted into node actual coordinate value can save memory space, and can increase readability, so the ranks coordinate obtains and can realize by described m-x encoder and n-y encoder respectively.In actual applications, the selection of encoder can be by 2
x-x encoder, 2
y-y encoder is realized.
Table 1 ranks coordinate coding correspondence table
| ?R[0..m-1] | ????RQ[0..x-1] | ?L[0..n-1] | ????LQ[0..y-1] |
| ?0111…1111 | ????0 | ?0111…1111 | ????0 |
| ?1011…1111 | ????1 | ?1011…1111 | ????1 |
| ?1101…1111 | ????2 | ?1101…1111 | ????2 |
| ?…… | ????… | ?…… | ????…… |
| ?1110…1110 | ????x-1 | ?1110…1111 | ????y-1 |
In the above-mentioned table, the 2nd, 4 row formulas adopt 10 systems to represent.
Described ranks signal filtering shaping and coordinate latch signal produce circuit 3 and include 1 d type flip flop that is triggered by clock signal, and the signal input part of d type flip flop is connected with the output of described NAND gate.When thump incident judging circuit generation thump incident index signal, ranks coordinate coding be latched when finishing.If first edge of employing thump incident index signal is as the coordinate latch signal, owing to the delayed action coordinate this moment coding of device is not finished as yet, as latch signal, unclamp the contact as if employing second edge, and key assignments has changed.In actual applications, also need to consider jittering noise.Because the elastic reaction of contact, line and alignment can produce mechanical shaking in closed and disconnected moment, so the thump index signal has comprised that also the virtual voltage waveform has comprised that forward position shake time, back are along shake time and stabilization time.The shake time depends on that the mechanical property of contact (is generally 5～12ms); Then depend primarily on the speed of thump speed and the length of external force action time stabilization time.
The above analysis, after thump incident index signal produces, need design ranks coordinate to latch and filtering shaping circuit, this signal is carried out the digital filtering shaping, simultaneously suitable beat (as 10ms) is delayed on its first edge, latched coordinate in stabilization time at button.The ranks coordinate latchs and filtering shaping circuit requirement circuit not only possesses certain noise removal function, can also do certain delay to the input signal response and handle.The clock cooperation of d type flip flop and appropriate frequency can constitute a kind of ranks coordinate latchs and the filtering shaping circuit scheme, but this circuit filtering is superimposed upon burr, high-frequency signal on the input signal.On circuit design, the output signal of this circuit can be used as interrupt request singal, promptly after keyboard is pressed, produces interrupt signal.
Described ranks coordinate figure memory circuit 5 produces ranks signal filtering shaping and coordinate latch signal that circuit 3 and ranks coordinate coding circuit 4 output signals store.Ranks coordinate figure memory circuit 5 is made up of x+y d type flip flop, the input of all d type flip flops respectively with the corresponding connection of output of m-x line encoder and n-y alignment encoder, the output that described ranks signal filtering shaping and coordinate latch signal produce the d type flip flop on the circuit 3 is connected with the clock signal input terminal of x+y d type flip flop.Ranks coordinate coding circuit is converted into the ranks coordinate with scanning result, for guaranteeing the stable of key assignments, needs the memory circuitry stores by the x+y position.A d type flip flop can be stored 1 bit data, therefore needs x+y d type flip flop.
The present invention can be according to different user demands, with different subsequent process circuit connections.Ranks coordinate figure memory circuit 5 can be connected with CPU, CPU reads the coordinate figure of ranks coordinate figure memory circuit 5 storages, and corresponding actions is carried out in the order of setting then.
Be that example specifies with 4 * 4 matrix press-key circuit below, referring to Fig. 2, shown in 4 * 4 matrix press-key circuit be by the horizontal vertical linear array structures that intersect discharging of 4 lines and 4 alignments, be provided with the button that they can be connected in the place that line and alignment intersect, have 16 buttons like this.
Referring to Fig. 3, according to formula
Because m=4, the smallest positive integral that satisfies this formula is x=2.Therefore just to become be 4 road pulse distributors to described m road pulse distributor 1, and this 4 road pulse distributor is made up of 4 system counters and 2-4 decoder; The 2-4 decoder can be selected integrated circuit modules 2-4 decoder 74139; The address input end of corresponding 2 lines-4 line decoder is 4 bat countings, and two continuous outputs of the integrated circuit modules of 16 system counters (as 74163) can realize that 4 clap counting arbitrarily; 2 inputs of described decoder integrated circuit (IC) chip are connected with 2 outputs of the integrated circuit chip of 16 system counters respectively, and 4 outputs of this decoder integrated circuit (IC) chip are connected with 4 line inputs of 4 * 4 matrix press-key circuit respectively; Act on the output scanning signal 0111,1011,1101,1110 that promptly can circulate by counter 74163 and 2-4 decoder 74139.The sweep signal low level width is set to about 20ms to 50ms, 2T
Clk(T
ClkIt is clock cycle of 74163).
Referring to Fig. 4, it is 7420 to have the NAND gate of 4 inputs that described thump incident judging circuit 2 adopts models, and 4 inputs are connected with 4 alignment outputs of 4 * 4 matrix press-key circuit respectively; When one of them input is a low level, its output is a high level just, has illustrated that keyboard presses, and constitutes keystroke incident indicating circuit thus.
Referring to Fig. 5, ranks signal filtering shaping and coordinate latch signal produce circuit 3 and realize the thump index signal of NAND gate output is carried out filter shape and signal delay.Ranks signal filtering shaping and coordinate latch signal produce circuit 3 and adopt the integrated circuit modules (as 74171) that has comprised 4 d type flip flops, the NAND gate output is connected the wherein input of any one d type flip flop, when the rising edge of clock clk arrived, correspondence was output as and involves 1 signal behind the clk clock delay after filtration.
Referring to Fig. 6, according to formula
Because m=4, the smallest positive integral that satisfies following formula is x=2; According to formula
Because n=4, the smallest positive integral that satisfies following formula is y=2.Therefore can select 4-2 coding integrated circuit modules to constitute ranks coordinate coding circuit.But 4-2 coding integrated circuit modules also is difficult for obtaining, therefore select the 8-4 coding integrated circuit modules 74148 of easily acquisition, 4 line scanning information coding is obtained abscissa and 4 column scan information coding is obtained the ordinate coding circuit as shown in Figure 6, preceding four the tunnel as the coding input, back four tunnel connects high level, and it is as shown in the table for its coding rule.The coding result combination will produce 16 different key assignments thus.4 coding inputs of a 8-4 encoder integrated circuit (IC) chip are connected with 4 outputs of described decoder integrated circuit (IC) chip respectively, and 4 coding inputs of another 8-4 encoder integrated circuit (IC) chip are connected with 4 alignment outputs of 4 * 4 matrix press-key circuit respectively.
The table 2 ranks coordinate 4-2 correspondence table of encoding
| ?R[0..7] | ?RQ[0..1] | ?L[0..7] | ?LQ[0..1] |
| ?0111??1111 | ?11 | ?0111??1111 | ?11 |
| ?1011??1111 | ?10 | ?1011??1111 | ?10 |
| ?1101??1111 | ?01 | ?1101??1111 | ?01 |
| ?1110??1111 | ?00 | ?1110??1111 | ?00 |
Ranks coordinate figure after being encoded comprises that 2 row and 2 rank coordinate, therefore need 4 d type flip flop circuit altogether, state ranks coordinate figure memory circuit 5 and adopt 74171 integrated circuit (IC) chip, this chip is the integrated circuit (IC) chip with 4 d type flip flops, and the clock signal input terminal of this integrated circuit (IC) chip is connected with the output that described ranks signal filtering shaping and coordinate latch signal produce the integrated circuit (IC) chip of 74171 on the circuit 3; The corresponding connection of 2 outputs of the input of 2 d type flip flops and a 8-4 encoder integrated circuit (IC) chip, the corresponding connection of 2 outputs of the input of other 2 d type flip flops and another 8-4 encoder integrated circuit (IC) chip.
Claims (8)
1. determinant linear array coordinate scanning circuit is characterized in that including:
M output is to m line input of m * n matrix press-key circuit (6) the m road pulse distributor (1) of output low level signal successively;
The thump incident judging circuit (2) that input is connected with n alignment output of m * n determinant linear array key circuit;
Ranks signal filtering shaping that input is connected with thump incident judging circuit (2) output and coordinate latch signal produce circuit (3);
The ranks coordinate coding circuit (4) that the n position signal that n alignment output of m road pulse distributor (1) circulation output m position count signal and m * n matrix press-key circuit (6) exported is encoded respectively;
Ranks signal filtering shaping and coordinate latch signal are produced the ranks coordinate figure memory circuit (5) that circuit (3) and ranks coordinate coding circuit (4) output signal are stored.
2. a kind of determinant linear array coordinate scanning circuit according to claim 1 is characterized in that described m road pulse distributor (1) is by 2
xThe effective x-m decoder of system counter and low level is formed, wherein
M is a natural number, described 2
xThe terminal count output of system counter is connected with the address choice input of x-m decoder, and the m of an x-m decoder output is connected with m line input of m * n matrix press-key circuit (6) respectively.
3. a kind of determinant linear array coordinate scanning circuit according to claim 1 and 2, it is characterized in that for to have the NAND gate of n input, its n input is connected with n alignment output of m * n matrix press-key circuit (6) respectively described thump incident judging circuit (2).
4. a kind of determinant linear array coordinate scanning circuit according to claim 3, it is characterized in that described ranks signal filtering shaping and coordinate latch signal produce circuit (3) and include 1 d type flip flop that is triggered by clock signal, the signal input part of d type flip flop is connected with the output of described NAND gate.
5. a kind of determinant linear array coordinate scanning circuit according to claim 4, it is characterized in that described ranks coordinate coding circuit (4) is made up of m-x line encoder and n-y alignment encoder, m input of m-x line encoder is connected respectively with m output of the x-m encoder of m road pulse distributor (1), n input of n-y alignment encoder is connected respectively with n alignment output of m * n matrix press-key circuit (6), wherein
M, n are natural number.
6. a kind of determinant linear array coordinate scanning circuit according to claim 5, it is characterized in that described ranks coordinate figure memory circuit (5) is made up of x+y d type flip flop, the input of all d type flip flops respectively with the corresponding connection of output of m-x line encoder and n-y alignment encoder, the output that described ranks signal filtering shaping and coordinate latch signal produce the d type flip flop on the circuit (3) is connected with the clock signal input terminal of x+y d type flip flop.
7. a kind of determinant linear array coordinate scanning circuit according to claim 6 is characterized in that described m * n matrix press-key circuit (6) is 4 * 4 matrix press-key circuit, includes 16 buttons;
Described m road pulse distributor (1) is 4 road pulse distributors, and this 4 road pulse distributor is made up of 4 system counters and 2-4 decoder;
Described thump incident judging circuit (2) is for having the NAND gate of 4 inputs;
Described ranks coordinate coding circuit (4) is made up of 4-2 line encoder and 4-2 alignment encoder;
Described ranks coordinate figure memory circuit (5) is made up of 4 d type flip flops.
8. a kind of determinant linear array coordinate scanning circuit according to claim 7, it is characterized in that it is that 2 continuous outputs of the integrated circuit chip of 16 system counters of 74163 carry out 4 and clap counting that described 4 system counters adopt model, described 2-4 decoder adopts the decoder integrated circuit (IC) chip of model 74139,2 inputs of this decoder integrated circuit (IC) chip are connected with 2 outputs of the integrated circuit chip of 16 system counters respectively, and 4 outputs of this decoder integrated circuit (IC) chip are connected with 4 line inputs of 4 * 4 matrix press-key circuit respectively;
Described NAND gate model is 7420, and its 4 inputs are connected with 4 alignment outputs of 4 * 4 matrix press-key circuit respectively;
Described ranks signal filtering shaping and coordinate latch signal produce circuit (3) to adopt model are 1 d type flip flop in 74171 the integrated circuit (IC) chip, and the input of this d type flip flop is connected with the output of described NAND gate;
Described 4-2 line encoder and 4-2 alignment encoder all adopt model be 74148 8-4 encoder integrated circuit (IC) chip preceding 4 the tunnel as the coding input, 4 coding inputs of a 8-4 encoder integrated circuit (IC) chip are connected with 4 outputs of described decoder integrated circuit (IC) chip respectively, and 4 coding inputs of another 8-4 encoder integrated circuit (IC) chip are connected with 4 alignment outputs of 4 * 4 matrix press-key circuit respectively;
Described ranks coordinate figure memory circuit (5) employing model is 74171 integrated circuit (IC) chip, this integrated circuit (IC) chip contains 4 d type flip flops, and the clock signal input terminal of this integrated circuit (IC) chip is connected with the output that described ranks signal filtering shaping and coordinate latch signal produce the integrated circuit (IC) chip of 74171 on the circuit (3); The corresponding connection of 2 outputs of the input of 2 d type flip flops and a 8-4 encoder integrated circuit (IC) chip, the corresponding connection of 2 outputs of the input of other 2 d type flip flops and another 8-4 encoder integrated circuit (IC) chip.
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