CN105700695B - Matrix keyboard scanning circuit and coding circuit - Google Patents
Matrix keyboard scanning circuit and coding circuit Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/0202—Constructional details or processes of manufacture of the input device
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Abstract
A kind of matrix keyboard scanning circuit and coding circuit, are made of matrix keyboard, the first shift register, the second shift register, state Code memory, encoder.The scan method of the scanning circuit is, via the control for the scanning pulse, the first shift pulse, the second shift pulse for meeting specific time sequence requirement, by the single key stroke of matrix keyboard, combination key operation, the state either maintained, it is converted into the effective status code and invalid state code of same binary length, output and the corresponding effective key number of each effective status code either output invalid key number corresponding with all invalid state codes after encoder encodes；Different single key stroke, combination key operation, or the state maintained are only embodied in not being same as above for conditional code；Button operation function is either adjusted if necessary to increase and decrease button operation function, keyboard scanning circuit structure need not be changed, only need to change encoder according to the conditional code after increase and decrease and the correspondence between key number.The invention circuit does not have to write and run program, reliable operation.
Description
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of matrix keyboard scanning circuit and coding circuit.
Background technology
With the continuous development of embedded technology, current each electronic product generally uses microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by run microcontroller in program come into
Row, encounters interference, program is caused to run fast, and scanner program is by cisco unity malfunction.
Application No. is the patents of invention of CN201010153560.2 " a kind of fast scanning and positioning method of matrix keyboard " to adopt
The Scan orientation process for entering keyboard with the mode that keyboard interrupt triggers is judged using the method that keyboard scan step is repeated several times
Whether button is effective, and the key assignments to being obtained carries out condition adjudgement；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then enters singly-bound tupe；Combination key operation in this way then enters Macintosh tupe.Described in the patent
Method is solved causes the Problem-Errors such as wrong key, continuous touching since keyboard caused by the mechanical property of keyboard itself is shaken,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with key operation is combined；
Not accounting for keyboard state maintains a period of time just to execute the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to change keyboard scan finder structure.
Invention content
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of matrix forms
Keyboard scanning circuit and coding circuit are deposited by matrix keyboard, the first shift register, the second shift register, conditional code
Device, encoder composition.
The matrix keyboard scanning circuit and coding circuit are by scanning pulse, the first shift pulse, the second shift pulse
Synchronize control.
The matrix keyboard shares X rows, Y row, is equipped with N bit keyboard status signal outputs；The N bit keyboards state letter
Number be level signal；The N=X+Y.
First shift register has the function of N bit synchronizations input and Serial output parallel；Second shift LD
Utensil has serial input and 2 × N parallel-by-bit output functions.
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second displacement
The serial input terminal of register is connected to the serial output terminal of the first shift register；The clock pulses of first shift register is defeated
Entering end and is connected to the first shift pulse, the shift pulse input terminal of the second shift register is connected to the second shift pulse, and first
The parallel input control end of shift register is connected to scanning pulse.
The state Code memory is 2 × N binary registers；The positions the 2 × N data input pin of state Code memory connects
It is connected to 2 × N parallel-by-bit output ends of the second shift register；The reception pulse input end of the state Code memory, which is connected to, to be swept
Retouch pulse.
The encoder has 2 × N coding input ends, the coding input end 2 × N to be connected to state Code memory
2 × N data output ends.
The scanning pulse, the first shift pulse, the second shift pulse sequential meet it is claimed below：
Per 1+N, the first shift pulse is a scan period；
In one scan period, during the 1st the first shift pulse period, scanning pulse is that the first shift register is parallel
Input enables significant level；
In one scan period, during N number of first shift pulse period after the 1st the first shift pulse period, sweep
It is that input enables inactive level to the first shift register parallel to retouch pulse；
In one scan period, the second shift pulse has N number of shift pulse.
The period of the scanning pulse is 20~100ms.
First shift register, the shift pulse edge of the second shift register are effective；Second shift pulse it is N number of
Effective edge of the effective edge of shift pulse along the moment earlier than the first shift pulse N number of shift pulse accordingly is along the moment.
The serial shift of first shift register and input parallel it is preset by the first shift pulse control, first
The effective edge of shift pulse is along realization serial shift or inputs parallel preset.
The positions the 2 × N data output end of the state Code memory exports 2 × N conditional codes；The conditional code is by effective
Conditional code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；It is described effective
Conditional code is generated by effective keyboard operation or state, and encoder corresponds to output when inputting each effective status code corresponding effective
Key number；The invalid state code is generated by invalid keyboard operation or state, and encoder inputs all corresponding when all invalid state codes
Export invalid key number.
The encoder has M key output ends, the selection of M values that should meet 2MMore than or equal to effective key number and invalid key number
The sum of quantity.
The matrix keyboard scanning circuit and coding circuit further include that keyboard state change pulse generates unit, for sentencing
Whether the key number of disconnected matrix keyboard output changes, and when the key number of matrix keyboard output changes, exports keyboard
State change pulse.
The keyboard state change pulse generate unit by or door, M delay buffer and M XOR gate form；M are prolonged
Slow buffer for carrying out signal delay respectively to the positions the M key number that matrix keyboard exports；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
The matrix keyboard by form X rows, Y row key-press matrix, row three state buffer, row three state buffer, row shape
State register, column-shaped state register group at；The line of all key-press matrixs is respectively connected to the output end of row three state buffer, institute
There is the alignment of key-press matrix to be respectively connected to the output end of row three state buffer；The institute of row three state buffer and row three state buffer
There is input terminal to be connected to low level；The line of all key-press matrixs is respectively connected to the input terminal of row status register, all to press
The alignment of key matrix is respectively connected to the input terminal of row status register；The output end of the row status register is posted with column-shaped state
The output end of storage collectively constitutes keyboard state signal output end.
The matrix keyboard is controlled by sampling pulse and obtains keyboard state signal；The sampling pulse selection scanning arteries and veins
One in punching, the first shift pulse, the second shift pulse；The row three state buffer enables to have in the low level of sampling pulse
When effect, it is desirable that row status register carries out data latch, row three state buffer in sampling pulse in the rising edge of sampling pulse
High level is enabled effectively, row status register carries out data latch in the failing edge of sampling pulse；Either, row three state buffer
When the high level of sampling pulse enables effective, it is desirable that row status register the failing edge of sampling pulse carry out data latches,
Row three state buffer carries out data in enabled effective, the row status register of low level of sampling pulse in the rising edge of sampling pulse
It latches.
The positions N, 2 × N, M refer both to binary digit data.
The beneficial effects of the invention are as follows：The scanning of state operation will be maintained to determine single key stroke, combination key operation, keyboard
Position, multiple Pulse Width Controls by meeting specific time sequence requirement are converted into the conditional code of same binary length, using Unified coding
Mode handled, single key stroke, combination key operation, keyboard maintain state operation be only embodied in not being same as above for conditional code；Such as
Fruit needs to increase and decrease button operation function either adjustment button operation function, need not change keyboard scanning circuit structure, only need
According to the conditional code after increase and decrease and the change of the correspondence between key number encoder, re-write in the storage of read-only memory
Appearance.The invention circuit does not use the microcontrollers such as microcontroller, ARM, does not have to operation program, reliable operation.
Description of the drawings
Fig. 1 is matrix keyboard scanning circuit and coding circuit functional block diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the scanning encoding circuit diagram of the embodiment of the present invention；
Fig. 4 is the pulse sequence figure of the embodiment of the present invention；
Fig. 5 is the impulse circuit schematic diagram of the embodiment of the present invention；
Fig. 6 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 7 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific implementation mode
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is matrix keyboard scanning circuit and coding circuit functional block diagram, is posted by the displacement of matrix keyboard 400, first
Storage 100, the second shift register 200, state Code memory 500, encoder 300 form.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, 2 rows, 2 row is shared, totally 4 buttons, by button
S1, button S2, button S3, button S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, on
Pull-up resistor R4 and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404
Composition.2 output ends Y1, Y2 of row three state buffer 401 are respectively connected to 2 lines, and 2 of row three state buffer 402 are defeated
Outlet Y3, Y4 is respectively connected to 2 alignments；All input terminal X1~X4 of row three state buffer 401 and row three state buffer 402
It is connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of row status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output ends Q41, Q42 of row status register 403 export row state
Signal I1, I2,2 output end Q43, Q44 output row status signals I3, I4 of row status register 404；Row status register
403 2 output ends collectively constitute 4 bit keyboard status signal outputs with 2 output ends of row status register 404, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low levels of row three state buffer 401 are effective, and row three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the sampling pulse CK output ends of oscillator.Row status register 403 with
Reception pulse input end CLK3, CLK4 of row status register 404 are connected to the sampling pulse CK output ends of oscillator, row shape
Failing edge of the state register 403 in sampling pulse CK carries out data latch, rising of the row status register 404 in sampling pulse CK
Along progress data latch.
When row three state buffer 401 and row three state buffer 402 are using the three state buffer with model, for example, making simultaneously
When with three state buffer 74HC241, the enabled input of 74HC241 is that high level is effective, therefore, sampling pulse CK output ends with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With row status register 404 using the data register with model, for example, row status register 403 and row status register 404
When using double D trigger 74HC74 composition data registers, the triggering input of 74HC74 is that rising edge is effective, therefore, is being taken
Between sample pulse CK output ends and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
The first shift register 100, the second shift register 200, the composition scanning electricity of state Code memory 500 in Fig. 1
Road, encoder 300 form coding circuit, and embodiment circuit diagram is as shown in Figure 3.The shape of embodiment matrix keyboard circuit output
State signal has 4, and therefore, the first shift register 100 is 4 binary systems with simultaneously and concurrently input, Serial output function
Shift register, the second shift register 200 are 8 binary shift registers with serial input, parallel output function.
4 parallel input terminal L0~L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4, the second shift register 200
Serial input terminal D2 be connected to the serial output terminal Q1 of the first shift register 100.The clock arteries and veins of first shift register 100
It rushes input terminal CLK1 and is connected to the first shift pulse CP1, the shift pulse input terminal CLK2 of the second shift register 200 is connected to
Second shift pulse CP2, the parallel input control end LD of the first shift register 100 are connected to scanning pulse CP3.
State Code memory 500 requires 8 bit binary datas of deposit, 8 data input pin D57~D50 to be connected to the
8 parallel-by-bit output end Q27~Q20 of two shift registers 200；The reception pulse input end CLK5 of state Code memory 500 connects
It is connected to scanning pulse CP3.
8 input terminal A7~A0 of encoder 300 be connected to 8 data output end Q57 of state Code memory 500~
Q50.Encoder 300, which exports, is scanned through 4 determining binary system keys number of coding.
In Fig. 3 embodiments, the first shift register 100, which can select to be had by 74HC166 etc., simultaneously and concurrently to be inputted, is serial
The medium-scale integration shift register of output function forms, or is made of edge triggered flip flop.Second shift register 200 can
To select by 74HC164 etc. to there is the medium-scale integration shift register of serial input, parallel output function to form, or by side
It is formed along trigger.When forming the first shift register 100, the second shift register 200 by edge triggered flip flop, preferably by edge
The d type flip flop of triggering forms.State Code memory 500 is made of edge triggered flip flop, preferably by the d type flip flop group of edging trigger
At for example, either 4D triggers 74HC175 or 8D trigger 74HC273 is formed selection double D trigger 74HC74.
In Fig. 3 embodiments, encoder 300 is read-only memory.Address input end A7~A0 of read-only memory is coding
The input terminal of device 300, data output end D3~D0 of read-only memory are coding output end C3~C0 of encoder 300.
The operation principle of matrix keyboard scanning circuit and coding circuit is as follows：
Scanning circuit scanning pulse CP3, the first shift pulse CP1, the second shift pulse CP2 control under work, phase
The pulse sequence figure of pass is as shown in Figure 4.
The sequential of CP1, CP2, CP3 meet claimed below in embodiment：Every 5 CP1 pulses are a scan period.One
In scan period, the 1st CP1 pulse period is the parallel input control period, and CP3 is the first input parallel of shift register 100
Enabled significant level, the first shift register 100 is inputted preset parallel under the control of the 1st CP1 pulse；It is next
4 CP1 pulse periods are shift cycle, and CP3 is that input enables inactive level, the first displacement to the first shift register 100 parallel
Register 100 carries out serial shift under the control of CP1 pulses.In one scan period, CP2 has 4 shift pulses.
Meeting CP1, CP2, CP3 pulse of timing requirements can be generated by various pulsqe distributors, and Fig. 5 is implementation of the present invention
The impulse circuit schematic diagram of example, is made of oscillator 801, counter 802, pulsqe distributor 803.Clock pulse CP in Fig. 4
It is generated by oscillator, CP send to counter 802 and counted, and counter 802 is 10 system Counters, 10 shapes of result P
State (numerical value) is followed successively by P0 → P9, as shown in Figure 4.Pulsqe distributor 803 in embodiment is using ROM memory realization, herein
Referred to as pulse distribution ROM memory.The address input of pulse distribution ROM memory is connected to the counting output of counter 802, arteries and veins
3 data output ends of punching distribution ROM memory export CP1 pulses, CP2 pulses, CP3 pulses respectively.Pulse distribution ROM storages
The write-in content of device is shown in Table 1.
1 pulse distribution ROM memory tables of data of table
The output of ROM memory address in table 1, i.e. counter is at least 4 binary codes.Under normal circumstances, counter
If 802 is regular using binary addition, corresponding 4 binary codes 0000~1001 of P0~P9 sequences, i.e. ROM memory
The storage content of location ranging from 0000~1001, address 0000~1001 is the corresponding contents of P0~P9 in table 1.
Pulse distribution ROM memory needs 3 data outputs.If the address input of pulse distribution ROM memory has R,
When matrix keyboard has the output of N bit keyboard status signals, the selection of R needs satisfaction 2RMore than or equal to 2 × (N+1).
Oscillator 801 is multivibrator.The period of scanning pulse CP3 is 20~100ms.CP1, CP2, CP3 can also
By except matrix keyboard scanning circuit and coding circuit circuit or device provide.
In Fig. 2,4 buttons of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by sampling pulse CK, using reversal process obtain keyboard state signal I4,
I3、I2、I1.For example, it is 1010 that the keyboard state signal of key pressing, which is not the keyboard state signal that 1111, S1 is pressed, S1, S2
The keyboard state signal pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key assignments.Sampling pulse CK can be with
One in scanning pulse CP3, the first shift pulse CP1, the second shift pulse CP2 is selected, preferably by the first shift pulse CP1
It is used as sampling pulse CK simultaneously.
Sampling pulse CK controls carry out the method that key assignments is read in sampling to matrix keyboard：In the low electricity of sampling pulse CK
It is flat, all lines are controlled by row three state buffer 401 and export low level, row three state buffer 402 exports high-impedance state and opens row
Line；It is sampled by row status register 404 in the rising edge of sampling pulse CK and reads alignment state as the 2 high of key assignments；It is taking
The high level of sample pulse CK controls all alignments by row three state buffer 402 and exports low level, and row three state buffer 401 is defeated
Go out high-impedance state and opens line；It is sampled by row status register 403 in the failing edge of sampling pulse CK and reads line state as key
Low 2 of value；In cycles, 4 key assignments that row status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from sampling pulse CK controls and reads the method for key assignments it is found that row three state buffer
401 when the low level of sampling pulse CK enables effective, while requiring row status register 404 in the rising edge of sampling pulse CK
Carry out data latch, row three state buffer 402 is taking in enabled effective, the row status register 403 of the high level of sampling pulse CK
The failing edge of sample pulse CK carries out data latch.In turn, if high level of the row three state buffer 401 in sampling pulse CK makes
When can be effective, while row status register 404 being required to carry out data latch, row three state buffer in the failing edge of sampling pulse CK
402 sampling pulse CK low level is enabled effectively, rising edge that row status register 403 is in sampling pulse CK carries out data lock
It deposits.
During above-mentioned sampling pulse CK controls sampling and reads key assignments, row status register 403, row status register
404 at the time of precisely row three state buffer 402 is with the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or row status register 404 can be sampled correctly.If it is required that having in certain sequential
Allowance can then postpone, method to being connected to row three state buffer 402 and the sampling pulse CK of row three state buffer 401
Be enable sampling pulse CK by RC retardation ratio circuit be then connected to row three state buffer 401 and row three state buffer 402 EN1,
EN2, delay time are determined by RC retardation ratio circuit, determine that the principle of the delay time of RC retardation ratio circuit is, the sampling pulse of delay
CK phases are no more than 90 °；Either sampling pulse CK is then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of row three state buffer 402, delay time at this time is the overall delay time of several gate circuits.
First shift register 100 is under the control of scanning pulse CP3 and the first shift pulse CP1, to matrix keyboard
Status signal I1, I2, I3, I4 of 400 outputs carry out data input latch, the at this time latch inside the first shift register 100
Data be known as current key assignments.Second shift register 200 in two periods before via the control of 8 CP2 pulses, will before
Two current key assignments are displaced to 200 output end of the second shift register, are first moved into the second shift register 200 output at this time
4 digits are stated to be existing state key assignments, state key assignments before 4 digits moved into afterwards are stated to be.
The existing state key assignments that second shift register 200 exports, preceding state key assignments are latched in conditional code deposit by scanning pulse CP3
The output of the output end of device 500, state Code memory 500 is similarly preceding state key assignments and existing state key assignments.
First shift register 100, the equal edge of shift pulse of the second shift register 200 are effective；Week is scanned at one
In the shift cycle of phase, the effective edge of 4 shift pulses of CP2 is along the effective of moment 4 shift pulses corresponding earlier than CP1
The edge moment.
The serial shift of first shift register 100 and input parallel it is preset by the first shift pulse CP1 control, the
The effective edge of one shift pulse CP1 is along realization serial shift or inputs parallel preset.In embodiment, the first shift register
100 selections are made of 74HC166, and parallel input control is that low level is enabled effective, and therefore, scanning pulse CP3 is low level
When, the first shift register 100 inputted parallel in the rising edge of CP1 it is preset, scanning pulse CP3 be high level when, first
Rising edge of the shift register 100 in CP1 carries out serial shift.
In embodiment, the 4 existing state key assignments and 4 preceding state key assignments of 500 data output end of state Code memory output are common
Form 8 conditional codes.The current state and mode of operation of 8 conditional codes matrix keyboard for identification.For example, this reality
It applies in example, the conditional code of no key pressing is 11111111；The conditional code of S1 key singly-bound pushes is 11111010；S1 key singly-bounds
It presses and the conditional code maintained is 10101010；The conditional code of S1 key singly-bounds release operation is 10101111；S2 key singly-bounds are pressed
The conditional code of operation is 11110110；The conditional code of S4 key singly-bound pushes is 11110101；The S1 of S2+S1 combination operations is pressed
Lower operation after expression first presses S2, presses the operation of S1, the conditional code of the operation is again in the state that S2 maintenances are pressed
01100010。
Encoder 300 is used to conditional code being converted to key number.In embodiment, it is equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound push of button S1, key number are 0000；
Operation 1：The singly-bound push of button S2, key number are 0001；
Operation 2：The singly-bound push of button S3, key number are 0010；
Operation 3：Button S3 singly-bounds press after maintenance state, key number be 0011；
Operation 4：After button S4 singly-bounds are pressed, then the combination key operation of S2 is pushed button, key number is 0100；
Operation 5：The singly-bound release operation of button S1, key number is 0101.
The conditional code and key number obtained according to above-mentioned regulation is shown in coding schedule 2：
2 coding schedule of table
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bounds are pressed | 11111010 | 0000 |
| S2 singly-bounds are pressed | 11110110 | 0001 |
| S3 singly-bounds are pressed | 11111001 | 0010 |
| S3 singly-bounds press maintenance | 10011001 | 0011 |
| S4+S2 combination operations | 01010100 | 0100 |
| S1 singly-bounds discharge | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 2.
The encoder 300 of embodiment is preferably made of read-only memory.Read-only memory has 8 bit address, and totally 28A 4 two
System storage unit.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state；By state
Address A7~A0 of the code as read-only memory, in storage unit corresponding with 6 effective status codes, by corresponding key number
As storage data write-in.The conditional code generated except 6 effective keyboard operations and state is invalid state code, i.e., in table 2
Other operation or state caused by be invalid state code；In other storage units, invalid key number, invalid key is all written
Number for a value except 6 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When read-only memory has piece selected control system, data output slow
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase as needed, or subtract
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M values is answered
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has the output of N bit keyboard status signals
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to change table 2 as needed, it will
Modified content re-writes the storage content of read-only memory.
The edge of scanning pulse CP3 at the time of state Code memory 500 is carried out data latch is known as state latch edge,
It is the rising edge of CP3 in embodiment.In embodiment, when matrix keyboard S1 singly-bounds are pressed, inputted parallel by CP3 Pulse Width Controls
The state latch of preset and next CP3 pulses by conditional code after being latched in state Code memory 500, a CP3 pulse period
It is interior, coding output end C3~C0 run-out keies number 0000；It is defeated parallel by CP3 Pulse Width Controls when matrix keyboard S2 singly-bounds are pressed
Enter the state latch of preset and next CP3 pulses after conditional code is latched in state Code memory 500, a CP3 pulse week
In phase, run-out key number 0001；After matrix keyboard first presses S4, then S2 is pressed, encoder 300 combines key pressing, warp in S2
It crosses CP3 Pulse Width Controls and inputs the state latch of preset and next CP3 pulses parallel along conditional code is latched in state Code memory
After 500, in a CP3 pulse period, run-out key number 0100；When the release of matrix keyboard S1 singly-bounds, simultaneously by CP3 Pulse Width Controls
Row inputs the state latch of preset and next CP3 pulses after conditional code is latched in state Code memory 500, a CP3 arteries and veins
It rushes in the period, run-out key number 0101；It can therefore be seen that when identification be effective button operation of matrix keyboard when, coding
The output duration after effective button operation of device 300 is effective key number of a CP3 periodic width.
In embodiment, when matrix keyboard S3 singly-bounds are pressed, encoder 300 is pressed in S3 singly-bounds, by CP3 pulse controls
System inputs the state latch of preset and next CP3 pulses after conditional code is latched in state Code memory 500 parallel, one
In the CP3 pulse periods, run-out key number 0010；Start on the state latch edge of next CP3, until S3 singly-bounds press maintenance state
Terminate, conditional code is latched in conditional code by the state latch edge for inputting preset and next CP3 pulses parallel by CP3 Pulse Width Controls
After register 500,300 run-out key number 0011 of encoder；It can therefore be seen that work as identification is the maintenance state of matrix keyboard
When, encoder 300 exports the duration of effective key number and the duration of the maintenance state is adapted.
When except the state of keyboard or operation being 6 effective keyboard operations and state described in table 2, encoder
300 output invalid keys number 1111.Effective key number, or output invalid key number are either exported, encoder 300 changes output content
At the time of for CP3 state latch edge；In embodiment, encoder 300 changes the rising edge for CP3 at the time of exporting content.
The period of CP3 is the scan period of matrix keyboard.The keyboard scan period in 20ms or more, can effectively keep away
The influence of key point disk key jitter；The keyboard scan period in 100ms or less, is unlikely to omit keyboard operation；Therefore, CP3
Period should control in 20~100ms.
Since CP3 pulses are preceding state key assignments and existing state along the conditional code of state Code memory 500 is latching in state latch
Key assignments, the current key assignments after button operation need one CP3 pulse period of delay that existing state key assignment combination could be used as to become state
Code, therefore, after key pressing, also there are one the delays of CP3 pulse periods for run-out key No. 300 of encoder.Since button is by artificial
Operation, the time delay of tens ms in operation on not influencing.
Fig. 6 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is matrix form
When effective button operation of keyboard, the state latch edge of CP3 of the encoder 300 after effective button operation starts, until next
Until the state latch edge of a CP3, output duration is effective key number of a CP3 periodic width.Receive the matrix form
The device of keyboard output, needs the output for inquiring matrix keyboard constantly, obtains key number.The period distances of inquiry are necessarily less than
The period of CP3.
Whether key number of the circuit shown in Fig. 6 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, export keyboard state change pulse, be used for the reception device receiving matrix formula of auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 6 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.By only being formed with 4 edge triggered flip flops of Trigger Function, 4 edge triggered flip flops touch delay buffer 601
The reception pulse input end that input terminal is delay buffer 601 is sent out, CP3 is connected to；State of the delay buffer 601 in CP3
It latches along progress data latch.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output end of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output end C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is buffered by delay
After the first-level buffer of device 601, signal ratio C3~C0 postpones a CP3 pulse period, and Fig. 7 show the key of the embodiment of the present invention
The waveform correlation schematic diagram that disk effectively operates.The sections T1 of CP3 pulses are located at, matrix keyboard has primary effectively operation, real
Apply example it is effective operation include：S1 singly-bounds are pressed, S2 singly-bounds are pressed, S3 singly-bounds are pressed, the S1 of S4+S1 combination operations is pressed, S4+
The S2 of S2 combination operations is pressed, S1 singly-bounds discharge.On the next state latch edge once effectively operated, i.e. CP3 pulses in Fig. 7
Rising edge after the sections T1, coding C3~C0 that encoder 300 exports change；In the sections T2, the output of encoder 300 one
Efficient coding C3~C0 of a CP3 pulse periods；In T3, T4 and section later, coding C3~C0 that encoder 300 exports is another
Secondary to change and enter maintenance state, which may be that such as S1 singly-bounds press subsequent maintenance state, export invalid key
Number, it is also possible to S3 singly-bounds press subsequent maintenance state, export effective key number, until effectively operation next time.
Coding C3~C0 that D6 pulses in Fig. 7 schematically illustrate the output of encoder 300 is to be in maintenance state, is not become
Change, still change, the D6 pulses are not present in actual circuit.As shown in fig. 7, D6 pulses are low level, illustrate table
Show that coding C3~C0 that encoder 300 exports is to be in maintenance state, does not change；D6 pulses are high level, schematically illustrate volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 7 reflected is the situation of change of C31~C01, it is clear that
Q6 ratios D6 postpones a CP3 pulse period.Equally, the Q6 pulses are not present in actual circuit.
In Fig. 7, coding C3~C0 that encoder 300 exports is to be in maintenance state, does not change, still changes,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
At logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output end C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 ratio C0 postpone a CP3 pulse period, and therefore, when C0 changes, XOR gate 602 exports 1 CP3 pulse week
The positive pulse of phase width；When C0 is a CP3 pulse period change width signal, XOR gate 602 exports 2 CP3 pulse weeks
The positive pulse of phase width.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 changes respectively, principle with
It is identical to judge whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 output end connect respectively
It is connected to or whether the input terminal of door 606 or door 606 changes for comprehensive descision C0~C3, as long as C0~C3 changes,
Or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D triggers 74HC273 of rising edge triggering.
Delay buffer 601 can also use other schemes, for example, using RC circuits, using 4 RC circuits respectively to C0
~C3 is postponed；If the delay time of RC circuits is less than a CP3 pulse period, encoder 300 exports a cycle
Efficient coding C3~C0 when, output efficient coding C3~C0 start and export efficient coding C3~C0 terminate all generation one
The width of keyboard state change pulse, keyboard state change pulse is equal to RC circuit delay times；If when the delay of RC circuits
Between be more than or equal to a CP3 pulse period, then encoder 300 export a cycle efficient coding C3~C0 when, have in output
Effect coding C3~C0 generates a keyboard state change pulse when starting, which is more than or equal to 2 CP3 pulse periods.
It is required that the delay time of RC circuits is no more than 2 CP3 pulse periods, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by full
2 Pulse Width Controls that sufficient specific time sequence requires are converted into the conditional code of same binary length, by the way of Unified coding into
Row processing, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If necessary to increase
Subtract button operation function and either adjust button operation function, keyboard scanning circuit structure need not be changed, it only need to be according to increase and decrease
The storage content that state code table afterwards updates encoder 300, re-writes update read-only memory.The invention circuit
The microcontrollers such as microcontroller, ARM are not used, operation program, reliable operation are not had to.
Claims (10)
1. a kind of matrix keyboard scanning circuit and coding circuit, which is characterized in that by matrix keyboard, the first shift LD
Device, the second shift register, state Code memory, encoder composition；
The matrix keyboard scanning circuit and coding circuit are carried out by scanning pulse, the first shift pulse, the second shift pulse
Synchronous control；
The matrix keyboard shares X rows, Y row, is equipped with N bit keyboard status signal outputs；The N bit keyboards status signal is
Level signal；The N=X+Y；
First shift register has the function of N bit synchronizations input and Serial output parallel；The second shift LD utensil
There are serial input and 2 × N parallel-by-bit output functions；
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second shift LD
The serial input terminal of device is connected to the serial output terminal of the first shift register；The clock pulse input terminal of first shift register
It is connected to the first shift pulse, the shift pulse input terminal of the second shift register is connected to the second shift pulse, the first displacement
The parallel input control end of register is connected to scanning pulse；
The state Code memory is 2 × N binary registers；The positions the 2 × N data input pin of state Code memory is connected to
2 × N parallel-by-bit output ends of second shift register；The reception pulse input end of the state Code memory is connected to scanning arteries and veins
Punching；
The encoder has 2 × N coding input ends, the coding input end 2 × N to be connected to 2 × N of state Code memory
Position data output end；
The scanning pulse, the first shift pulse, the second shift pulse sequential meet it is claimed below：
Per 1+N, the first shift pulse is a scan period；
In one scan period, during the 1st the first shift pulse period, scanning pulse is that the first shift register inputs parallel
Enabled significant level；
In one scan period, during N number of first shift pulse period after the 1st the first shift pulse period, arteries and veins is scanned
Punching is that input enables inactive level to the first shift register parallel；
In one scan period, the second shift pulse has N number of shift pulse.
2. matrix keyboard scanning circuit according to claim 1 and coding circuit, it is characterised in that：The scanning pulse
Period be 20~100ms.
3. matrix keyboard scanning circuit according to claim 1 and coding circuit, it is characterised in that：First displacement
Register, the shift pulse edge of the second shift register are effective；The effective edge of N number of shift pulse of second shift pulse along when
The effective edge earlier than the first shift pulse N number of shift pulse accordingly is carved along the moment.
4. matrix keyboard scanning circuit according to claim 1 and coding circuit, it is characterised in that：First displacement
The serial shift of register and input parallel it is preset controlled by the first shift pulse, the first shift pulse effective edge along real
Existing serial shift inputs preset parallel.
5. matrix keyboard scanning circuit according to claim 1 and coding circuit, it is characterised in that：The conditional code is posted
The positions the 2 × N data output end of storage exports 2 × N conditional codes；The conditional code is by effective status code and invalid state code character
At；The key number of the encoder output is made of effective key number and invalid key number；The effective status code is by effective keyboard operation
Or state generates, encoder corresponds to output corresponding effectively key number when inputting each effective status code；The invalid state code
It is generated by invalid keyboard operation or state, encoder inputs all corresponding output invalid key number when all invalid state codes.
6. matrix keyboard scanning circuit according to claim 5 and coding circuit, it is characterised in that：The encoder has
The selection of M key output ends, M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
7. matrix keyboard scanning circuit according to claim 6 and coding circuit, it is characterised in that：It further include keyboard shape
State change pulse generates unit, and whether the key number for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, export keyboard state change pulse.
8. matrix keyboard scanning circuit according to claim 7 and coding circuit, it is characterised in that：The keyboard state
Change pulse generate unit by or door, M delay buffer and M XOR gate form；M delay buffers are used for matrix form
The positions the M key number of keyboard output carries out signal delay respectively；The input of M XOR gate is respectively inputting, being defeated for M delay buffers
Go out signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output end output keyboard state of door changes arteries and veins
Punching.
9. matrix keyboard scanning circuit according to claim 1 and coding circuit, it is characterised in that：The matrix form key
Disk by form X rows, Y row key-press matrix, row three state buffer, row three state buffer, row status register, row status register
Composition；The line of all key-press matrixs is respectively connected to the output end of row three state buffer, the alignment difference of all key-press matrixs
It is connected to the output end of row three state buffer；All input terminals of row three state buffer and row three state buffer are connected to low electricity
It is flat；The line of all key-press matrixs is respectively connected to the input terminal of row status register, and the alignment of all key-press matrixs connects respectively
It is connected to the input terminal of row status register；The output end of the row status register and common group of the output end of row status register
At keyboard state signal output end.
10. matrix keyboard scanning circuit according to claim 9 and coding circuit, it is characterised in that：The matrix form
Keyboard is controlled by sampling pulse and obtains keyboard state signal；The sampling pulse selection scanning pulse, the first shift pulse, second
One in shift pulse；The row three state buffer is when the low level of sampling pulse enables effective, it is desirable that row Status register
Device carries out data latch, row three state buffer in enabled effective, the row shape of the high level of sampling pulse in the rising edge of sampling pulse
State register carries out data latch in the failing edge of sampling pulse；Either, high level of the row three state buffer in sampling pulse
When enabled effective, it is desirable that row status register is being sampled in the failing edge progress data latch of sampling pulse, row three state buffer
The low level of pulse is enabled effectively, row status register carries out data latch in the rising edge of sampling pulse.
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| CN201610003060.8A CN105700695B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard scanning circuit and coding circuit |
| CN201810591950.4A CN108874164B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard inversion method scanning method |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108874164A (en) | 2018-11-23 |
| CN108874164B (en) | 2021-03-16 |
| CN105700695A (en) | 2016-06-22 |
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