CN205485933U - Matrix type keyboard scans positioning circuit - Google Patents

Abstract

The utility model provides a matrix type keyboard scans positioning circuit comprises matrix type keyboard, buffer register, state code register, encoder. The circuit scans via clock pulse, and the location of will operate the single bond, the state operation being maintain in key combination operation, keyboard converts active state sign indicating number and the invalid state sign indicating number of same binary system length to, invalid key that effective key that encoder output and each active state sign indicating number correspond number or export corresponds with all invalid state sign indicating numbers number, different single bond operation, key combination operation, keyboards is kept the state operation and is only embodied not the same at the status codes, the keyboard scanning circuit structure need not modifyd to if necessary increase/decrease keys operating function or adjustment button operating function, and it can only to need to change the encoder according to the corresponding relation between the status codes after the increase and decrease and the key number. The utility model circuit need not be compile and operating program, the reliable operation.

Description

A kind of matrix keyboard Scan orientation circuit

Technical field

This utility model relates to the scanning circuit of a kind of keyboard, especially a kind of matrix keyboard Scan orientation circuit.

Background technology

Along with the development of embedded technology, the current commonly used microcontroller of each electronic product is as control core, keyboard As main input equipment, it is widely used.

Current keyboard scan is mainly controlled by microcontroller, needs to be carried out by the program in operation microcontroller, runs into Interference, causes program to run fast, and scanning imaging system is by cisco unity malfunction.

The patent of invention " fast scanning and positioning method of a kind of matrix keyboard " of Application No. CN201010153560.2 uses key The mode of dish down trigger enters the Scan orientation process of keyboard, uses the method that keyboard scan step is repeated several times to judge that button is No effectively, and the key assignments obtained is carried out condition adjudgement；If multiple repairing weld state is identical, then it is in steady statue, key assignments Effectively；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or Macintosh operation need individually to judge, singly-bound in this way Operation, then enter singly-bound tupe；Macintosh operation in this way, then enter Macintosh tupe.Method solution described in this patent Determine the keyboard shake caused due to the mechanical property of keyboard self and cause the wrong Problem-Error such as key, continuous touching, and to group Close key and the support issue of repeat key.But described method single key stroke needs to process respectively with Macintosh operation；Do not account for key Plate-like state maintains a period of time to arrive the rear keyboard operation function just performing effectively operation；Increase and decrease button operation function or adjustment are pressed During key operation function, need to revise keyboard scan finder structure.

Summary of the invention

In order to solve the above-mentioned technical problem that existing keyboard scan localization method exists, this utility model provides a kind of matrix form key Positioning circuit is retouched in sweeping, is made up of matrix keyboard, buffer register, conditional code depositor, encoder.

Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output；Described N bit keyboard state Signal is level signal；Described N=X+Y.

Described buffer register is N position binary register；The N bit data input of buffer register is connected to N bit keyboard Status signal output.

Described conditional code depositor is 2 × N position binary register；In 2 × N bit data input of conditional code depositor N position is connected to N bit keyboard status signal output, and additionally N position is connected to the N bit data outfan of buffer register.

Described encoder have 2 × N position coding input end, described 2 × N position coding input end be connected to conditional code depositor 2 × N bit data outfan；Described encoder has M position key outfan.

The reception pulse input end receiving pulse input end and conditional code depositor of described buffer register is connected to clock arteries and veins Punching.

Described matrix keyboard is provided with sampling pulse input.

Described matrix keyboard is enabled effective row three state buffer by X row-Y row key-press matrix, low level, high level enable has Effect row three state buffer, trailing edge latch effective row status register, rising edge latches effective column-shaped state depositor composition；All The line of key-press matrix is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to row tri-state The outfan of buffer；All inputs of row three state buffer and row three state buffer are connected to low level；All key-press matrixs Line be respectively connecting to the input of row status register, the alignment of all key-press matrixs is respectively connecting to row status register Input；The outfan of described row status register and the outfan of row status register collectively constitute the output of keyboard state signal End.

Described low level enables effective row three state buffer, high level enables the enable control input of effective row three state buffer even It is connected to sampling pulse；Described trailing edge latches effective row status register, the reception arteries and veins of the rising edge effective column-shaped state depositor of latch Rush input and be connected to sampling pulse.

Described buffer register and conditional code depositor carry out data latch at the rising edge of clock pulses simultaneously, or at clock arteries and veins The trailing edge of punching carries out data latch simultaneously；The state of described conditional code depositor 2 × N bit data outfan output 2 × N position Code；Described conditional code is made up of effective status code and disarmed state code；The key number of described encoder output is by effective key number and invalid Key number forms；Described effective status code is produced by effective keyboard operation or state, when encoder inputs each effective status code pair Corresponding effectively key number should be exported；Described disarmed state code is produced by invalid keyboard operation or state, and encoder input is all invalid All corresponding output invalid key number during conditional code.

Described encoder has M position key outfan, and the selection of M value should meet 2^MMore than or equal to effective key number and invalid key number Quantity sum.

The cycle of described clock pulses is 20～100ms；The cycle of described sampling pulse is not more than the cycle of described clock pulses, Its special case be described sampling pulse be described clock pulses.

Described a kind of matrix keyboard Scan orientation circuit also includes agitator；Described agitator output clock pulses and sampling arteries and veins Punching.

Described a kind of matrix keyboard Scan orientation circuit also includes keyboard state change pulse generation unit, for judgment matrix Whether the key number of formula keyboard output changes, when the key number of matrix keyboard output changes, and output keyboard state change Pulse.

Described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form；M prolongs position Buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output late；The input of M XOR gate is respectively The input of M position delay buffer, output signal；The output of M XOR gate is respectively connecting to or the input of door；Or door Outfan output keyboard state change pulse.

Described N position, 2 × N position, M position refer both to binary digit data.

The beneficial effects of the utility model are: the location that will operate single key stroke, Macintosh operation, keyboard maintenance state, by Clock pulses scan conversion becomes the conditional code of same binary length, uses the mode of Unified coding to process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code the most ibid；If need increase and decrease button operation function or To adjust button operation function, it is not necessary to amendment keyboard scanning circuit structure, only need to be according to conditional code and the key number after increase and decrease between Corresponding relation change encoder, i.e. re-write the storage content of read only memory.Described utility model circuit does not make With the microcontroller such as single-chip microcomputer, ARM, program, reliable operation need not be run.

Accompanying drawing explanation

Fig. 1 is a kind of matrix keyboard Scan orientation schematic block circuit diagram；

Fig. 2 is the matrix keyboard circuit diagram of this utility model embodiment；

Fig. 3 is the Scan orientation circuit diagram of this utility model embodiment；

Fig. 4 is the circuit diagram of the keyboard state change pulse generation unit of this utility model embodiment；

Fig. 5 is the waveform correlation schematic diagram that the keyboard of this utility model embodiment effectively operates.

Detailed description of the invention

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Fig. 1 is matrix keyboard Scan orientation schematic block circuit diagram, by matrix keyboard 400, buffer register 100, state Code memory 200, encoder 300, agitator 500 form.

Agitator 500 is multivibrator, is provided with CP output terminal of clock pulse and CK sampling pulse outfan, CP clock arteries and veins The cycle of punching is 20～100ms, and the cycle of CK sampling pulse is not more than the cycle of CP clock pulses.

Fig. 2 is the circuit diagram of the matrix keyboard 400 of this utility model embodiment, have 2 row, 2 row, totally 4 buttons, By button S1, button S2, button S3, button S4 be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, and row three state buffer 401, row three state buffer 402, row Status register Device 403, row status register 404 form.2 outfans Y1, Y2 of row three state buffer 401 are respectively connecting to 2 Line, 2 outfans Y3, Y4 of row three state buffer 402 are respectively connecting to 2 alignments；Row three state buffer 401 He All input X1～X4 of row three state buffer 402 are connected to low level.

2 inputs D41, D42 of row status register 403 are respectively connecting to 2 lines, row status register 404 2 inputs D43, D44 are respectively connecting to 2 alignments；2 outfans Q41, Q42 of row status register 403 are defeated Trip status signal I1, I2,2 outfans Q43, Q44 of row status register 404 export row status signal I3, I4； 2 outfans of row status register 403 and 2 outfans of row status register 404 collectively constitute 4 bit keyboard state letters Number outfan, exports keyboard state signal I1, I2, I3, I4.

In embodiment, the enable input EN1 Low level effective of row three state buffer 401, the enable of row three state buffer 402 Input EN2 high level is effective；EN1 and EN2 is connected to the CK sampling pulse outfan of agitator 500.Row state is posted Storage 403 is connected to the CK of agitator 500 with receive pulse input end CLK3, CLK4 of row status register 404 Sampling pulse outfan, row status register 403 carries out data latch, row status register at the trailing edge of CK sampling pulse 404 carry out data latch at the rising edge of CK sampling pulse.

When row three state buffer 401 and row three state buffer 402 use the three state buffer of same model, such as, use three simultaneously During state buffer 74HC241, the enable input of 74HC241 is effective for high level, therefore, at CK sampling pulse outfan And between the enable input EN1 of row three state buffer 401, need to increase a not gate.Similarly, when row Status register Device 403 and row status register 404 use the data register of same model, and such as, row status register 403 and column-shaped state are posted When storage 404 all uses double D trigger 74HC74 to form data register, the triggering input of 74HC74 has for rising edge Effect, therefore, between the reception pulse input end CLK3 of CK sampling pulse outfan and row status register 403, needs Increase a not gate.

Buffer register 100 in Fig. 1, conditional code depositor 200, encoder 300 form Scan orientation circuit, and it is implemented Example circuit diagram is as shown in Figure 3.Matrix keyboard circuit has 4 buttons, and the keyboard state signal of matrix keyboard output is 4 Binary code, therefore, buffer register 100 requires to deposit 4 bit binary data, and conditional code depositor 200 requires to deposit 8 Bit binary data.4 data input pins of buffer register 100 are connected to I1, I2, I3, I4；Conditional code depositor In 8 data input pins of 200,4 data input pins are connected to I1, I2, I3, I4, and other 4 data input pins connect 4 outfans to buffer register 100；8 inputs of encoder 300 are connected to 8 of conditional code depositor 200 Outfan.Encoder 300 output is scanned through positioning 4 the binary system keys number determined.

In Fig. 3, trigger 101 forms buffer register 100, trigger 201 forms conditional code depositor 200.Trigger 101 are made up of 4 edge triggered flip flops, and the reception pulse that triggering input is buffer register 100 of 4 edge triggered flip flops is defeated Enter end, be connected to the CP output terminal of clock pulse of agitator 500；Trigger 201 is made up of 8 edge triggered flip flops, and 8 The reception pulse input end that triggering input is conditional code depositor 200 of individual edge triggered flip flop, is connected to agitator 500 CP output terminal of clock pulse.Trigger 101, trigger 201 are preferably made up of the d type flip flop of edging trigger, such as, by Double D trigger 74HC74,4D trigger 74HC175 forms.In Fig. 3 embodiment, trigger 101, trigger 201 All select the 8D trigger 74HC273 that rising edge triggers, now, unillustrated clear input in Fig. 3 is connected paramount Level, makes the Protection Counter Functions of 74HC273 be in disarmed state, only has Trigger Function；Trigger 101 has only to 4D and triggers Device, arbitrarily uses 4 d type flip flops in selected 8D trigger 74HC273.Two 8D trigger 74HC273 Triggering input CLK1, CLK2 be connected to CP.

In Fig. 3, read only memory 301 forms encoder 300.Address input end A7～A0 of read only memory 301 is for compiling The input of code device 300, the coding outfan that data output end D3～D0 is encoder 300 of read only memory 301 C3～C0.

The operation principle of matrix keyboard Scan orientation circuit is as follows:

In Fig. 2,4 buttons of matrix keyboard arrange with the matrix form of 2 × 2, and all of line all passes through upper with alignment Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by CK sampling pulse, uses reversal process to obtain keyboard state signal I4、I3、I2、I1.Such as, the keyboard state signal not having key to press is 1111, and the keyboard state signal that S1 presses is 1010, S1, the keyboard state signal that S2 presses simultaneously is 0010.4 binary codes of keyboard state signal are referred to as key assignments.

CK sampling pulse controls to carry out matrix keyboard the method for sampling reading key assignments: at the low electricity of CK sampling pulse Flat, control all line output low levels by row three state buffer 401, row three state buffer 402 exports the open row of high-impedance state Line；Sampled by row status register 404 at the rising edge of CK sampling pulse and read high 2 as key assignments of alignment state；? The high level of CK sampling pulse, controls all alignment output low levels, row three state buffer by row three state buffer 402 The 401 open lines of output high-impedance state；CK sampling pulse trailing edge by row status register 403 sample reading line state Low 2 as key assignments；Said process goes round and begins again, 4 of row status register 404, row status register 403 output Key assignments is always the last state of matrix keyboard.

Knowable to CK sampling pulse controls matrix keyboard is carried out the method that key assignments is read in sampling, row three state buffer 401 exists When the low level of CK sampling pulse enables effective, require that row status register 404 enters at the rising edge of CK sampling pulse simultaneously Row data latch, row three state buffer 402 enables effectively at the high level of CK sampling pulse, row status register 403 exists The trailing edge of CK sampling pulse carries out data latch.In turn, if row three state buffer 401 is at the height of CK sampling pulse When level enables effective, require that row status register 404 carries out data latch, row three at the trailing edge of CK sampling pulse simultaneously State buffer 402 enables effectively in the low level of CK sampling pulse, row status register 403 is in the rising of CK sampling pulse Along carrying out data latch.

During above-mentioned CK sampling pulse controls sampling reading key assignments, row status register 403, row status register 404 moment precisely row three state buffer 402 and the row three state buffers 401 carrying out sampling are carried out the moment of state reversion, just Often the row status register 403 under work or row status register 404 can correctly be sampled.If requiring have in certain sequential Allowance, then can postpone being connected to the row three state buffer 402 CK sampling pulse with row three state buffer 401, side Method makes CK sampling pulse be then connected to row three state buffer 401 and row three state buffer 402 through RC delay circuit EN1, EN2, determined by RC delay circuit time delay, determines that the principle of the time delay of RC delay circuit is, postpones CK sample pulse phase less than 90 °；Or CK sampling pulse is then connected to row after the buffering of several gate circuits Three state buffer 401 and EN1, EN2 of row three state buffer 402, time delay now is the total of described several gate circuit Decay time.

Buffer register 100, conditional code depositor 200 are under CP clock pulses controls, the having of each cycle of CP Effect triggers along carrying out data latch.In Fig. 3,74HC273 is that rising edge triggers effectively, therefore, and CP clock pulses effective Trigger edge for rising edge.

4 data input pin D20～D23 in 8 data input pins of conditional code depositor 200 are connected directly to matrix form Status signal I1, I2, I3, I4 of keyboard output, other 4 data input pin D24～D27 are connected to buffer register Data output end Q10～Q13 of 100,4 data input pin D10～D13 of buffer register 100 are connected directly to square Status signal I1, I2, I3, I4 of configuration keyboard output, therefore, effectively triggers edge in CP clock pulses, and conditional code is posted In 8 data output ends of storage 200, with status signal I1, I2, I3, I4 phase being connected directly to matrix keyboard output The current state that data are matrix keyboard that 4 corresponding data output end Q20～Q23 latch, its 4 bit data is referred to as existing State key assignments；4 data output end Q24～Q27 corresponding with the data output end being connected to buffer register 100 latch Data are the previous state of matrix keyboard, and its 4 bit data is referred to as front state key assignments.Conditional code depositor 200 data output end is defeated The existing state key assignments of 4 gone out and 4 front state key assignments collectively constitute 8 conditional codes.

8 described conditional codes are used for current state and the mode of operation of recognition matrix formula keyboard.Such as, in the present embodiment, nothing The conditional code that key is pressed is 11111111；The conditional code of S1 key singly-bound push is 11111010；S1 key singly-bound is pressed and is tieed up The conditional code held is 10101010；The conditional code of S1 key singly-bound release operation is 10101111；The shape of S2 key singly-bound push State code is 11110110；The conditional code of S4 key singly-bound push is 11110101；The S1 of S2+S1 combination operation presses behaviour Making, represent after first pressing S2, maintain the state pressed to press the operation of S1 again at S2, the conditional code of this operation is 01100010。

Encoder 300 is for being converted to key number by conditional code.In embodiment, it is provided with 6 effective keyboard operations and state, bag Include:

The singly-bound push of operation 0: button S1, key number is 0000；

The singly-bound push of operation 1: button S2, key number is 0001；

The singly-bound push of operation 2: button S3, key number is 0010；

Operation 3: button S3 singly-bound press after maintenance state, key number is 0011；

Operation 4: after button S4 singly-bound is pressed, then the Macintosh operation of the S2 that pushes button, key number is 0100；

The singly-bound release operation of operation 5: button S1, key number is 0101.

The conditional code obtained according to above-mentioned regulation and key number are shown in coding schedule 1:

Table 1 coding schedule

Keyboard operation	Conditional code (address)	Key number (storage data)
			S1 singly-bound is pressed	11111010	0000
S2 singly-bound is pressed	11110110	0001
			S3 singly-bound is pressed	11111001	0010
Maintenance pressed by S3 singly-bound	10011001	0011
			S4+S2 combination operation	01010100	0100
S1 singly-bound discharges	10101111	0101
			Other operation or states	********	1111

Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 1.

The encoder 300 of embodiment is preferably made up of read only memory 301.Read only memory 301 has 8 bit address, and totally 2⁸ Individual 4 binary storage cells.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys with state Number；Using conditional code as address A7～A0 of read only memory 301, in the memory element corresponding with 6 effective status code-phase In, using corresponding key number as storage data write.The conditional code produced outside 6 effective keyboard operations and state is invalid Other operations in conditional code, i.e. table 1 or state produced be disarmed state code；In other memory element, all write Invalid key number, invalid key number is a value outside 6 effective keys number, and in embodiment, invalid key number is 1111.

Read only memory 301 always works at data output state.When read only memory 301 has sheet selected control system, data output During dash-control function, the output of its sheet selected control system, data should be made dash-control to be in effective status.

Key number in embodiment is 4 binary codes.The number of bits of key number can increase as required, or reduces, this Time, only need to select the read only memory 301 matched with this.If the selection that the number of bits of key number is M, M value 2 should be met^MQuantity sum more than or equal to effective key number with invalid key number.When matrix keyboard has N bit keyboard status signal defeated When going out, read only memory 301 needs the input of 2 × N bit address, and M-bit data exports.

If needing increase and decrease button operation function or adjust button operation function, table 1 only need to be revised as required, will amendment After content re-write the storage content of read only memory 301.

In embodiment, when matrix keyboard S1 singly-bound is pressed, the encoder 300 CP clock pulses after S1 singly-bound is pressed Effectively trigger along starting, to next CP clock pulses effectively trigger edge, encode outfan C3～C0 run-out key Number 0000；When matrix keyboard S2 singly-bound is pressed, the encoder 300 CP clock pulses after S2 singly-bound is pressed effective Trigger along starting, to the effectively triggering edge of next CP clock pulses, run-out key number 0001；When matrix keyboard is first pressed After lower S4, then pressing S2, the edge of effectively triggering of the encoder 300 CP clock pulses after S2 Macintosh is pressed starts, extremely Till the effectively triggering edge of next CP clock pulses, run-out key number 0100；When matrix keyboard S1 singly-bound discharges, compile The code device 300 CP clock pulses after S1 singly-bound discharges effectively trigger along starting, effective to next CP clock pulses Till triggering edge, run-out key number 0101；It can therefore be seen that when identify be effective button operation of matrix keyboard time, The edge of effectively triggering of the encoder 300 CP clock pulses after this effective button operation starts, to next CP clock pulses Effectively trigger edge till, output duration is effective key number of CP width clock cycle.

In embodiment, when matrix keyboard S3 singly-bound is pressed, the encoder 300 CP clock pulses after S3 singly-bound is pressed Effectively trigger along starting, to the effectively triggering edge of next CP clock pulses, run-out key number 0010；Ensuing Effectively triggering along starting of CP clock pulses, presses having of the next CP clock pulses after maintenance state terminates to S3 singly-bound Till effect triggers edge, encoder 300 run-out key number 0011；It can therefore be seen that work as identification is the maintenance of matrix keyboard During state, the persistent period of persistent period and this maintenance state that encoder 300 exports effective key number adapts.

When outside the state of keyboard or operation are for 6 effective keyboard operations described in table 1 and state, encoder 300 is defeated Go out invalid key number 1111.Either exporting effective key number, or output invalid key number, encoder 300 changes output content Moment be CP clock pulses effectively trigger edge；In embodiment, the moment of encoder 300 change output content is CP clock The rising edge of pulse.

The cycle of CP clock pulses is the scan period of matrix keyboard.The keyboard scan cycle is when more than 20ms, it is possible to effectively Avoid keyboard shake impact；The keyboard scan cycle, when below 100ms, is unlikely to omit keyboard operation；Cause This, the cycle of CP clock pulses should control 20～100ms.

The cycle request of CK sampling pulse is not more than the cycle of CP clock pulses, so, each the most tactile in CP clock pulses Send out along when obtaining conditional code, it is possible to ensure that 4 key assignments of row status register 404, row status register 403 output are always The last state of matrix keyboard.The special case of CK sampling pulse is directly to use CP clock pulses as CK sampling pulse.

In embodiment, CP clock pulses, CK sampling pulse are produced by agitator 500 and export.CP clock pulses and CK sampling pulse can also be provided by the circuit outside matrix keyboard Scan orientation circuit or device.

Fig. 4 is the circuit diagram of the keyboard state change pulse generation unit of this utility model embodiment.It is matrix form key when identify During effective button operation of dish, the encoder 300 CP clock pulses after this effective button operation effectively trigger along starting, To the effectively triggering edge of next CP clock pulses, output duration is having of CP width clock cycle Effect key number.Receive the device of described matrix keyboard output, need the output of moment inquiry matrix keyboard, obtain key number.Look into The period distances ask is necessarily less than the cycle of CP clock pulses.

Whether circuit shown in Fig. 4 changes for the key number of judgment matrix formula keyboard output, when the key number of matrix keyboard output When changing, exporting keyboard state change pulse, the reception device receiving matrix formula keyboard for auxiliary moment configuration keyboard exports Key number, such as, using keyboard state change pulse as receive device interrupt request singal.

Circuit shown in Fig. 4 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605, Or door 606 forms.Delay buffer 601 is made up of 4 edge triggered flip flops only with Trigger Function, 4 edge triggered flip flops The input that triggers be the reception pulse input end of delay buffer 601, the CP clock pulses being connected to agitator 500 is defeated Go out end；Delay buffer 601 carries out data latch on the edge of effectively triggering of CP clock pulses.

Delay buffer 601 is for carrying out respectively at delay 4 bit data C3 of the coding outfan of encoder 300～C0 Reason.4 data input pin D63～D60 of delay buffer 601 be connected to encoder 300 coding outfan C3～ C0, the data that 4 data output end Q63～Q60 of delay buffer 601 export accordingly are C31～C01；C31～C01 After the first-level buffer of delay buffer 601, its signal postpones a CP clock cycle, Fig. 5 institute than C3～C0 It is shown as the waveform correlation schematic diagram that the keyboard of this utility model embodiment effectively operates.The T1 being located at CP clock pulses is interval, Matrix keyboard existence the most effectively operates, and the effectively operation of embodiment includes: S1 singly-bound is pressed, S2 singly-bound is pressed, S3 is mono- Key is pressed, the S2 of S4+S2 combination operation presses, the release of S1 singly-bound.Effectively trigger once effectively the next of operation Rising edge after CP clock pulses T1 interval in edge, i.e. Fig. 5, coding C3～C0 of encoder 300 output changes Become；Interval at T2, encoder 300 exports efficient coding C3～C0 in a cycle；At T3, T4 and interval afterwards, compile Coding C3～C0 of code device 300 output changes again and enters maintenance state, and this maintenance state is probably such as S1 singly-bound Press maintenance state below, export invalid key number, it is also possible to maintenance state below pressed by S3 singly-bound, exports effective key Number, until the most effectively operating.

D6 pulse in Fig. 5 schematically illustrates coding C3～C0 of encoder 300 output and is in maintenance state, does not become Change, still change, side circuit does not exist described D6 pulse.As it is shown in figure 5, D6 pulse is low level, Coding C3～C0 schematically illustrating encoder 300 output is in maintenance state, is not changed in；D6 pulse is high level, Schematically illustrate encoder 300 and export efficient coding C3～C0 in a cycle.Q6 reflection in Fig. 5 is C31～C01 Situation of change, it is clear that Q6 postpones a CP clock cycle than D6.Equally, side circuit does not exist described Q6 pulse.

In Fig. 5, coding C3～C0 of encoder 300 output is in maintenance state, is not changed in, still changes, Really by 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door 606 logic circuits formed complete.4 XOR gates encode 1 phase in outfan C3～C0 respectively with encoder 300 Correspondence, input is respectively the input of 4 delay buffers 601, output signal.Such as, two input letters of XOR gate 602 Number being respectively C0 and C01, C01 postpones a CP clock cycle than C0, therefore, when C0 changes, different Or door 602 exports the positive pulse of 1 CP width clock cycle；When C0 is CP change width clock cycle During signal, XOR gate 602 exports the positive pulse of 2 CP width clock cycle.XOR gate 603, XOR gate 604, XOR gate 605 judges whether C1～C3 changes respectively, and principle is with to judge whether C0 changes identical.XOR gate 602, XOR gate 603, XOR gate 604, the outfan of XOR gate 605 are respectively connecting to or the input of door 606, or door Whether 606 change for comprehensive descision C0～C3, as long as C0～C3 changes, or door 606 i.e. run-out key plate-like State change pulse F, this pulse is positive pulse.

In embodiment, delay buffer 601 selects the 8D trigger 74HC273 that rising edge triggers.In embodiment, encoder 300 outputs are 4 binary system keys number, and therefore, delay buffer 601 has only to 4 d type flip flops.Owing to postponing buffering The triggering input of 4 d type flip flops in device 601 and 4 d type flip flops in trigger 101 is connected to agitator The CP output terminal of clock pulse of 500, therefore, delay buffer 601 and trigger 101 can share a 8D trigger 74HC273。

Delay buffer 601 can also use other schemes, such as, uses RC circuit, utilizes 4 RC circuit the most right C0～C3 postpones；If the time delay of RC circuit, then encoder 300 exported less than a CP clock cycle During the efficient coding C3 in one cycle～C0, start at output efficient coding C3～C0 and export efficient coding C3～C0 knot Bundle all produces a keyboard state change pulse, and the width of keyboard state change pulse is equal to RC circuit delay time；If The time delay of RC circuit, then encoder 300 exported effective volume in a cycle more than or equal to a CP clock cycle During code C3～C0, producing a keyboard state change pulse when exporting efficient coding C3～C0 and starting, pulse width is more than Equal to 2 CP clock cycles.Require the time delay of RC circuit less than 2 CP clock cycles, in order to avoid Generation is failed to report.

In described utility model circuit, the location that single key stroke, Macintosh operation, keyboard maintenance state will be operated, by CP pulse scan conversion becomes the conditional code of same binary length, uses the mode of Unified coding to process, single key stroke, Macintosh operation, keyboard maintain state operation be only embodied in conditional code the most ibid；If need increase and decrease button operation function or It is to adjust button operation function, it is not necessary to amendment keyboard scanning circuit structure, only need to update coding according to the state code table after increase and decrease Device 300, i.e. re-write update read only memory 301 storage content.Described utility model circuit does not use monolithic The microcontroller such as machine, ARM, need not run program, reliable operation.

Claims (6)

1. a matrix keyboard Scan orientation circuit, it is characterised in that be made up of matrix keyboard, buffer register, conditional code depositor, encoder；

Described matrix keyboard has X row, Y row, is provided with N bit keyboard status signal output outputs level signals；Described N=X+Y；Described matrix keyboard is provided with sampling pulse input；

Described buffer register is N position binary register；The N bit data input of buffer register is connected to N bit keyboard status signal output；

Described conditional code depositor is 2 × N position binary register；N position in 2 × N bit data input of conditional code depositor is connected to N bit keyboard status signal output, and additionally N position is connected to the N bit data outfan of buffer register；

Described encoder has 2 × N position coding input end, described 2 × N position coding input end to be connected to 2 × N bit data outfan of conditional code depositor；Described encoder has M position key outfan；

The reception pulse input end receiving pulse input end and conditional code depositor of described buffer register is connected to clock pulses.

A kind of matrix keyboard Scan orientation circuit the most according to claim 1, it is characterised in that: described matrix keyboard is enabled effective row three state buffer by X row-Y row key-press matrix, low level, high level enables effective row three state buffer, trailing edge latches effective row status register, rising edge latches effective column-shaped state depositor and forms；The line of all key-press matrixs is respectively connecting to the outfan of row three state buffer, and the alignment of all key-press matrixs is respectively connecting to the outfan of row three state buffer；All inputs of row three state buffer and row three state buffer are connected to low level；The line of all key-press matrixs is respectively connecting to the input of row status register, and the alignment of all key-press matrixs is respectively connecting to the input of row status register；The outfan of described row status register and the outfan of row status register collectively constitute keyboard state signal output part.

A kind of matrix keyboard Scan orientation circuit the most according to claim 2, it is characterised in that: described low level enables effective row three state buffer, the enable of the high level effective row three state buffer of enable controls input and is connected to sampling pulse；Described trailing edge latches effective row status register, the reception pulse input end of the rising edge effective column-shaped state depositor of latch is connected to sampling pulse.

A kind of matrix keyboard Scan orientation circuit the most according to claim 1, it is characterised in that: also include keyboard state change pulse generation unit.

A kind of matrix keyboard Scan orientation circuit the most according to claim 4, it is characterised in that: described keyboard state change pulse generation unit by M position delay buffer, M XOR gate and or door form；M position delay buffer is for carrying out signal delay respectively to the M position key number of matrix keyboard output；The input of M XOR gate is respectively the input and output signal of M position delay buffer；The output of M XOR gate is respectively connecting to or the input of door；Or the outfan output keyboard state change pulse of door.

A kind of matrix keyboard Scan orientation circuit the most according to claim 1, it is characterised in that: also include agitator；Described agitator output clock pulses and sampling pulse.