CN105468164B - Matrix keyboard scanner uni coding circuit - Google Patents
Matrix keyboard scanner uni coding circuit Download PDFInfo
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- CN105468164B CN105468164B CN201610003604.0A CN201610003604A CN105468164B CN 105468164 B CN105468164 B CN 105468164B CN 201610003604 A CN201610003604 A CN 201610003604A CN 105468164 B CN105468164 B CN 105468164B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
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Abstract
A kind of matrix keyboard scanner uni coding circuit is made of matrix keyboard, the first buffer register, the second buffer register, state Code memory, encoder, data combination unit.The matrix keyboard scanner uni coding circuit is via clock pulses, the control of scanning pulse, sampling pulse, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, it is converted into the effective status code of same binary length and invalid state code, after encoder encodes, export effective key number corresponding with each effective status code and either export invalid key number corresponding with all invalid state codes；Different single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；Button operation function is either adjusted if necessary to increase and decrease button operation function, does not need to modification keyboard scanning circuit structure, only need to encoder be changed according to the correspondence between the conditional code after increase and decrease and key number.The invention circuit does not have to write and run program, reliable operation.
Description
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of matrix keyboard scanner uni coding circuit.
Background technology
With the continuous development of embedded technology, current each electronic product is generally using microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by run the program in microcontroller come into
Row, encounters interference, program is caused to run fast, and scanning imaging system is by cisco unity malfunction.
Patent of invention " a kind of fast scanning and positioning method of matrix keyboard " application No. is CN201010153560.2 is adopted
Enter the Scan orientation process of keyboard with the mode that keyboard interrupt triggers, judged using the method that keyboard scan step is repeated several times
Whether button is effective, and the key assignments to being obtained carries out condition adjudgement；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then into singly-bound tupe；Key operation is combined in this way, then into Macintosh tupe.Described in the patent
Method solves since keyboard caused by the mechanical property of keyboard itself is shaken and causes the Problem-Errors such as wrong key, continuous touching,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with combining key operation；
Not accounting for keyboard state maintains a period of time just to perform the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to change keyboard scan finder structure.
Invention content
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of matrix forms
Keyboard scan and coding circuit by matrix keyboard, the first buffer register, the second buffer register, state Code memory, are compiled
Code device, data combination unit composition.
The matrix keyboard scanner uni coding circuit synchronizes control by scanning pulse, clock pulses and sampling pulse
System.
The matrix keyboard shares X rows, Y row, equipped with N bit keyboard status signal outputs；The N bit keyboards state letter
Number be level signal；The N=X+Y.
First buffer register and the second buffer register are N binary registers；First buffering is posted
The N positions data input pin of storage is sequentially connected to N bit keyboard status signal outputs；The N digits of second buffer register
N bit keyboard status signal outputs are sequentially connected to according to input terminal.
The reception pulse input end of first buffer register and the second buffer register is connected to scanning pulse.
The data combination unit is equipped with N data input pins of the first via, the second road N data input pin and 2 × N digits
According to output terminal；The first via N data input pins are sequentially connected to the N positions data output end of the first buffer register, and second
Road N data input pin is sequentially connected to the N positions data output end of the second buffer register.
The data combination unit is additionally provided with data select signal end；The data select signal end is connected to scanning arteries and veins
Punching；In the 2 × N positions data output of data combination unit, when the scanning pulse is low level, N data of the first via are preceding, and the
Two road N data are rear；When the scanning pulse is high level, N data of the first via are rear, and second road N data is preceding；Or
Person is, in 2 × N positions data output of data combination unit, when the scanning pulse is low level, N data of the first via rear,
Second road N data is preceding；When the scanning pulse is high level, N data of the first via are preceding, and second road N data is rear.
The state Code memory is 2 × N binary registers；2 × N positions data input pin of state Code memory connects
It is connected to 2 × N positions data output end of data combination unit.
The reception pulse input end of the state Code memory is connected to clock pulses；The matrix keyboard is by sampling arteries and veins
Punching control obtains N bit keyboard status signals；
The encoder has 2 × N coding input ends, and the 2 × N coding input end is connected to state Code memory
2 × N data output ends.
The period of the clock pulses is 20~100ms；The scanning pulse is the two divided-frequency signal of clock pulses；It is described
The period of sampling pulse is not more than the period of the clock pulses.
The invalid triggering edge of the clock pulses control scanning pulse overturning is known as state latch edge；The conditional code is posted
Storage carries out data latch on the state latch edge of clock pulses；First buffer register scanning pulse rising edge into
When row data latch, the second buffer register carries out data latch in the failing edge of scanning pulse；Either, first buffering
Register when the failing edge of scanning pulse carries out data latch, the second buffer register scanning pulse rising edge into line number
According to latch.
2 × N positions data output end of the state Code memory exports the conditional code of 2 × N；The conditional code is by effective
Conditional code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；It is described effective
Conditional code is generated by effective keyboard operation or state, and encoder corresponds to output when inputting each effective status code corresponding effective
Key number；The invalid state code is generated by invalid keyboard operation or state, and encoder inputs all corresponding during all invalid state codes
Export invalid key number.
The encoder has M key output terminals, and the selection of M values should meet 2MMore than or equal to effective key number and invalid key number
The sum of quantity.
The matrix keyboard scanner uni coding circuit further includes keyboard state change pulse and generates unit, for judging square
Whether the key number of configuration keyboard output changes, and when the key number of matrix keyboard output changes, exports keyboard state
Change pulse.
The keyboard state change pulse generate unit by or door, M delay buffer and M XOR gate form；M are prolonged
Slow buffer is used to carry out signal delay respectively to the M positions key number that matrix keyboard exports；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
The matrix keyboard scanner uni coding circuit further includes oscillator；The oscillator output clock pulses, scanning
Pulse and sampling pulse.
The matrix keyboard is by X row-Y row key-press matrix, row three state buffer, row three state buffer, row Status register
Device, column-shaped state register group into；The line of all key-press matrixs is respectively connected to the output terminal of row three state buffer, all buttons
Matrix column line is respectively connected to the output terminal of row three state buffer；All inputs of row three state buffer and row three state buffer
End is connected to low level；The line of all key-press matrixs is respectively connected to the input terminal of row status register, all key-press matrixs
Alignment be respectively connected to the input terminal of row status register；The output terminal of the row status register and row status register
Output terminal collectively constitutes keyboard state signal output end.
The row three state buffer is when the low level of sampling pulse enables effective, it is desirable that row status register is in sampling arteries and veins
The rising edge of punching carries out data latch, row three state buffer enables effective, row status register in the high level of sampling pulse and exists
The failing edge of sampling pulse carries out data latch；Either, row three state buffer is when the high level of sampling pulse enables effective,
It is required that row status register the failing edge of sampling pulse carry out data latches, row three state buffer sampling pulse low level
Enabled effective, row status register carries out data latch in the rising edge of sampling pulse.
The N positions, 2 × N, M refer both to binary digit data.
The beneficial effects of the invention are as follows：State behaviour will be maintained to the single key stroke of matrix keyboard, combination key operation, keyboard
The positioning of work is converted into the conditional code of same binary length by clock pulses, scanning pulse control, using the side of Unified coding
Formula is handled, and single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If it needs
Increase and decrease button operation function and either adjust button operation function, do not need to modification keyboard scanning circuit structure, only need basis
Correspondence between conditional code and key number after increase and decrease changes encoder, re-writes the storage content of read-only memory i.e.
It can.The invention circuit is not using microcontrollers such as microcontroller, ARM, without running program, reliable operation.
Description of the drawings
Fig. 1 is matrix keyboard scanner uni coding circuit functional block diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the Scan orientation circuit diagram of the embodiment of the present invention；
Fig. 4 is the data combination unit circuit diagram of the embodiment of the present invention；
Fig. 5 is the clock pulses of the embodiment of the present invention and scanning pulse oscillogram；
Fig. 6 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 7 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is matrix keyboard scanner uni coding circuit functional block diagram, by matrix keyboard 400, the first buffer register
101st, the second buffer register 102, state Code memory 200, encoder 300, data combination unit 500 form.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, 2 rows, 2 row is shared, totally 4 buttons, by button
S1, button S2, button S3, button S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, on
Pull-up resistor R4 and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404
Composition.2 output terminals Y1, Y2 of row three state buffer 401 are respectively connected to 2 lines, and 2 of row three state buffer 402 are defeated
Outlet Y3, Y4 is respectively connected to 2 alignments；All input terminal X1~X4 of row three state buffer 401 and row three state buffer 402
It is connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of row status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output terminals Q41, Q42 output row state of row status register 403
Signal I1, I2,2 output terminals Q43, Q44 output row status signal I3, I4 of row status register 404；Row status register
403 2 output terminals collectively constitute 4 bit keyboard status signal outputs with 2 output terminals of row status register 404, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low levels of row three state buffer 401 are effective, and row three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the CK sampling pulse output terminals of oscillator 500.Row status register 403
The CK sampling pulses that oscillator 500 is connected to reception pulse input end CLK3, CLK4 of row status register 404 export
End, row status register 403 carry out data latch in the failing edge of CK sampling pulses, and row status register 404 samples arteries and veins in CK
The rising edge of punching carries out data latch.
When row three state buffer 401 and row three state buffer 402 are using the three state buffer with model, for example, making simultaneously
During with three state buffer 74HC241, the enabled input of 74HC241 is effective for high level, therefore, CK sampling pulses output terminal with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With row status register 404 using the data register with model, for example, row status register 403 and row status register 404
When using double D trigger 74HC74 composition data registers, the triggering input of 74HC74 is effective for rising edge, therefore, in CK
Between sampling pulse output terminal and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
The first buffer register 101, the second buffer register 102, state Code memory 200, encoder 300 in Fig. 1,
Data combination unit 500 forms Scan orientation circuit, and embodiment circuit diagram is as shown in Figure 3.Embodiment matrix keyboard circuit
The status signal of output has 4, therefore, the first buffer register 101, the second buffer register 102 require deposit 4 two into
Data processed, 4 data input pin D10~D13 of the first buffer register 101 are sequentially connected to I1, I2, I3, I4, the second buffering
4 data input pin D14~D17 of register 102 are also sequentially connected to I1, I2, I3, I4.
Data combination unit 500 is used to implement the selected and sorted of two-way input data with combining.In embodiment, two-way input
1 tunnel in data is that 4 data J, J include J3, J2, J1, J0；Other 1 tunnel is 4 data K, K include K3, K2, K1,
K0；The output data on 18, tunnel is L.The function of data combination unit 500 is that there are two types of 8 output data L, and sequence is combined, one
Kind of sequence combination is 4 data J preceding, 4 data K rear, that is, export L7~L0 be followed successively by J3, J2, J1, J0, K3, K2, K1,
K0；Another sequence combination is 4 data K preceding, 4 data J rear, that is, export L7~L0 be followed successively by K3, K2, K1, K0,
J3、J2、J1、J0；Two kinds of sequence combinations are controlled by data select signal S.
Data combination unit 500 may be used data selector, three state buffer or other modes and realize.Fig. 4 is
500 embodiment schematic diagram of data combination unit selects 1 data selector 501,502 to form by 242,501,502 data choosing
It selects signal S and is connected to CP2 scanning pulses.When CP2 is low level, 42 select 1 data selector 501,502 selector channels 0,
That is L7~L0 is equal to K3, K2, K1, K0, J3, J2, J1, J0；When CP2 is high level, 42 select 1 data selector 501,502 to select
Channel 1 is selected, i.e. L7~L0 is equal to J3, J2, J1, J0, K3, K2, K1, K0.
Requirement 8 bit binary datas of deposit of state Code memory 200,8 data input pin D27~D20 are connected to number
According to 8 data output end L7~L0 of assembled unit 500；8 input terminal A7~A0 of encoder 300 are connected to conditional code deposit
8 data output end Q27~Q20 of device 200.Encoder 300, which exports, is scanned through 4 determining binary system keys number of positioning.
In Fig. 3 embodiments, the first buffer register 101, the second buffer register 102, state Code memory 200 are by side
It forms along trigger, is preferably made of the d type flip flop of edging trigger, for example, by double D trigger 74HC74,4D trigger
74HC175,8D trigger 74HC273 are formed.The triggering input terminal of 4 edge triggered flip flops in first buffer register 101 connects
The composition that is connected together receives pulse input end, is connected to CP2 scanning pulses, and failing edge carries out data latch；Second buffer stock
The triggering input terminal of 4 edge triggered flip flops in device 102, which links together to form, receives pulse input end, is connected to CP2 scannings
Pulse, rising edge carry out data latch；The triggering input terminal of 8 edge triggered flip flops of state Code memory 200 links together
Composition receives pulse input end, is connected to CP1 clock pulses, and rising edge carries out data latch.
In Fig. 3 embodiments, the first buffer register 101, the second buffer register 102, state Code memory 200 are by upper
The 8D trigger 74HC273 along triggering are risen, since the first buffer register 101 requires failing edge to carry out data latch,
CP2 scanning pulses are needed after a NOT gate reverse phase, are then connected to the reception pulse input end of the first buffer register 101；
In addition, the Protection Counter Functions of the 74HC273 to be made to be in invalid state, ensure the first buffer register 101, the second buffer stock
Device 102, state Code memory 200 have Trigger Function.
In Fig. 3 embodiments, encoder 300 is read-only memory.Address input end A7~A0 of read-only memory is coding
The input terminal of device 300, data output end D3~D0 of read-only memory are coding output terminal C3~C0 of encoder 300.
Embodiment be not drawn into generating CP1 clock pulses, CP2 scanning pulses, CK sampling pulses oscillator, oscillator is more
Harmonic oscillator, output CP1 clock pulses, CP2 scanning pulses and CK sampling pulses, period of CP1 clock pulses for 20~
100ms, CP2 scanning pulse are the two divided-frequency signal of CP1 clock pulses, and the waveform of CP1, CP2 are as shown in Figure 5.CP1 clock arteries and veins
Punching, CP2 scanning pulses and CK sampling pulses can also be by the circuits or device except matrix keyboard scanner uni coding circuit
It provides.
The operation principle of matrix keyboard scanner uni coding circuit is as follows：
In Fig. 2,4 buttons of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by CK sampling pulses, using reversal process obtain keyboard state signal I4,
I3、I2、I1.For example, the keyboard state signal that the keyboard state signal of no key pressing, which is 1111, S1, to be pressed is 1010, S1, S2
The keyboard state signal pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key assignments.
The control of CK sampling pulses carries out matrix keyboard the method that key assignments is read in sampling：In the low electricity of CK sampling pulses
It is flat, all lines is controlled to export low level by row three state buffer 401, row three state buffer 402 exports high-impedance state and opens row
Line；It is sampled in the rising edge of CK sampling pulses by row status register 404 and reads alignment state as the 2 high of key assignments；In CK
The high level of sampling pulse controls all alignments to export low level by row three state buffer 402, and row three state buffer 401 is defeated
Go out high-impedance state and open line；It is sampled in the failing edge of CK sampling pulses by row status register 403 and reads line state as key
Low 2 of value；In cycles, 4 key assignments that row status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from the control of CK sampling pulses and reads the method for key assignments it is found that row three state buffer
401 when the low level of CK sampling pulses enables effective, while requires row status register 404 in the rising edge of CK sampling pulses
Carry out data latch, row three state buffer 402 enables effective, row status register 403 in CK in the high level of CK sampling pulses
The failing edge of sampling pulse carries out data latch.In turn, if row three state buffer 401 makes in the high level of CK sampling pulses
When can be effective, while row status register 404 be required to carry out data latch, row three state buffer in the failing edge of CK sampling pulses
402 CK sampling pulses low level enable effectively, row status register 403 CK sampling pulses rising edge carry out data lock
It deposits.
During above-mentioned CK sampling pulses control sampling to read key assignments, row status register 403, row status register
404 at the time of precisely row three state buffer 402 is with the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or row status register 404 can be sampled correctly.If it is required that have in certain sequential
Allowance can then postpone, method to being connected to row three state buffer 402 and the CK sampling pulses of row three state buffer 401
Be enable CK sampling pulses by RC retardation ratio circuit be then connected to row three state buffer 401 and row three state buffer 402 EN1,
EN2, delay time are determined that determining the principle of the delay time of RC retardation ratio circuit is by RC retardation ratio circuit, the CK sampling arteries and veins of delay
Phase is rushed no more than 90 °；Either CK sampling pulses are then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of row three state buffer 402, overall delay time of the delay time for several gate circuits at this time.
First buffer register 101, the second buffer register 102 are under the control of CP2 scanning pulses, alternately to matrix form key
Status signal I1, I2, I3, I4 of disk output carry out data latch；The output of the buffer register of newest latch data is known as
Existing state key assignments, state key assignments before the output of the buffer register of latch data is known as slightly before, therefore, the first buffer register 101, the
Two buffer registers 102 alternately export existing state key assignments and preceding state key assignments under the control of CP2 scanning pulses.
After Fig. 3 and Fig. 5, CP2 scanning pulse failing edge in conjunction with the embodiments, in the low level state of CP2 scanning pulses,
The existing state key assignments of first buffer register 101 output is connected to input terminal J3, J2, J1, J0 of data combination unit 500, and second
The preceding state key assignments that buffer register 102 exports is connected to input terminal K3, K2, K1, K0 of data combination unit 500, and counts at this time
Be connected to CP2 scanning pulses according to selection signal S, be low level, output L7~L0 of data combination unit 500 be equal to K3, K2,
K1, K0, J3, J2, J1, J0, i.e., preceding state key assignments is preceding, and existing state key assignments is rear；After CP2 scanning pulse rising edges, scanned in CP2
The high level state of pulse, the preceding state key assignments of the first buffer register 101 output are connected to the input terminal of data combination unit 500
J3, J2, J1, J0, the second buffer register 102 output existing state key assignments be connected to data combination unit 500 input terminal K3,
K2, K1, K0, and data select signal S is connected to CP2 scanning pulses at this time, for high level, the output of data combination unit 500
L7~L0 is equal to J3, J2, J1, J0, K3, K2, K1, K0, is equally preceding state key assignments preceding, and existing state key assignments is rear.
CP2 scanning pulses state before the first buffer register 101, the second buffer register 102 is controlled alternately to latch output
At the time of key assignments, existing state key assignments and data combination unit 500 carry out data selected and sorted with combining, what can be formed is of short duration
Nondeterministic statement.The effect of state Code memory 200 is to eliminate the influence of the nondeterministic statement.
The input of state Code memory 200 is the preceding state key assignments that data combination unit 500 exports and existing state key assignments, and output is same
Sample is preceding state key assignments and existing state key assignments.The edge of CP1 clock pulses at the time of state Code memory 200 to carry out to data latch
Referred to as state latch edge is the rising edge of CP1 in embodiment；CP2 scanning pulses are the two divided-frequency signal of CP1 clock pulses, will
Effective triggering edge of the CP1 clock pulses of control CP2 scanning pulse overturnings is known as status scan edge；In embodiment, state is swept
It retouches along the failing edge for being CP1 clock pulses, i.e. the first buffer register 101, the second buffer register 102, data combination unit
Failing edge before 500 latch outputs at the time of state key assignments, existing state key assignments in CP1 clock pulses, therefore, in CP1 clock pulses
Rising edge, the preceding state key assignments of the output of data combination unit 500, existing state key assignments come into stable state, eliminate aforementioned do not know
The influence of state.
If Clock pulse CP 1 controls effective edge that triggers of scanning pulse CP2 overturnings as failing edge, clock pulses
The invalid triggering edge of CP1 control scanning pulse CP2 overturnings is rising edge；If Clock pulse CP 1 controls scanning pulse CP2 to turn over
The effective triggering edge turned is rising edge, then Clock pulse CP 1 controls the invalid triggering edge of scanning pulse CP2 overturnings to decline
Edge.The invalid triggering edge that Clock pulse CP 1 controls scanning pulse CP2 to overturn is known as state latch edge；In embodiment, state
Along the failing edge for being CP1 clock pulses, state latch edge is the rising edge of CP1 clock pulses for scanning.
The 4 existing state key assignments and 4 preceding state key assignments of 200 data output end of state Code memory output collectively constitute 8 shapes
State code.
8 conditional codes are used for the current state and mode of operation of recognition matrix formula keyboard.For example, the present embodiment
In, the conditional code of no key pressing is 11111111；The conditional code of S1 key singly-bound pushes is 11111010；S1 key singly-bounds are pressed
And the conditional code maintained is 10101010；The conditional code of S1 keys singly-bound release operation is 10101111；S2 key singly-bound pushes
Conditional code be 11110110；The conditional code of S4 key singly-bound pushes is 11110101；The S1 of S2+S1 combination operations presses behaviour
Make, after expression first presses S2, press the operation of S1 again in the state that S2 maintenances are pressed, the conditional code of the operation is 01100010.
Encoder 300 is used to conditional code being converted to key number.In embodiment, equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound push of button S1, key number are 0000；
Operation 1：The singly-bound push of button S2, key number are 0001；
Operation 2：The singly-bound push of button S3, key number are 0010；
Operation 3：Button S3 singly-bounds press after maintenance state, key number be 0011；
Operation 4：After button S4 singly-bounds are pressed, then the combination key operation of S2 is pushed button, key number is 0100；
Operation 5：The singly-bound release operation of button S1, key number is 0101.
The conditional code and key number obtained according to above-mentioned regulation is shown in coding schedule 1：
1 coding schedule of table
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bounds are pressed | 11111010 | 0000 |
| S2 singly-bounds are pressed | 11110110 | 0001 |
| S3 singly-bounds are pressed | 11111001 | 0010 |
| S3 singly-bounds press maintenance | 10011001 | 0011 |
| S4+S2 combination operations | 01010100 | 0100 |
| S1 singly-bounds discharge | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 1.
The encoder 300 of embodiment is preferably made of read-only memory.Read-only memory has 8 bit address, and totally 28A 4 two
System storage unit.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state；By state
Address A7~A0 of the code as read-only memory, in 6 corresponding storage units of effective status code, by corresponding key number
As storage data write-in.The conditional code generated except 6 effective keyboard operations and state is invalid state code, i.e., in table 1
Other operation or state caused by be invalid state code；In other storage units, invalid key number, invalid key is all written
Number for a value except 6 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When there is read-only memory piece selected control system, data output to delay
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase or subtract as needed
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M values should
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has the output of N bit keyboards status signal
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to change table 1 as needed, it will
Modified content re-writes the storage content of read-only memory.
In embodiment, when matrix keyboard S1 singly-bounds are pressed, CP1 clock arteries and veins of the encoder 300 after S1 singly-bounds are pressed
The state latch edge of punching starts, and until the state latch edge of next CP1 clock pulses, encodes output terminal C3~C0 run-out keies
Number 0000；When matrix keyboard S2 singly-bounds are pressed, the status lock of CP1 clock pulses of the encoder 300 after S2 singly-bounds are pressed
Edge is deposited to start, until the state latch edge of next CP1 clock pulses, run-out key number 0001；When matrix keyboard is first pressed
After S4, then S2 is pressed, the state latch edge that encoder 300 combines the CP1 clock pulses after key pressing in S2 starts, until next
Until the state latch edge of CP1 clock pulses, run-out key number 0100；When matrix keyboard S1 singly-bounds discharge, encoder 300 exists
The state latch edge of CP1 clock pulses after the release of S1 singly-bounds starts, until the state latch edge of next CP1 clock pulses is
Only, run-out key number 0101；It can therefore be seen that when identification be effective button operation of matrix keyboard when, encoder 300 exists
The state latch edge of CP1 clock pulses after effective button operation starts, until the state latch edge of next CP1 clock pulses
Until, effective key number of the output duration for CP1 width clock cycle.
In embodiment, when matrix keyboard S3 singly-bounds are pressed, CP1 clock arteries and veins of the encoder 300 after S3 singly-bounds are pressed
The state latch edge of punching starts, until the state latch edge of next CP1 clock pulses, run-out key number 0010；Following
CP1 clock pulses state latch along starting, until next CP1 clock pulses after S3 singly-bounds press maintenance state
Until state latch edge, 300 run-out key number 0011 of encoder；It can therefore be seen that work as identification is the maintenance of matrix keyboard
During state, encoder 300 exports the duration of effective key number and the duration of the maintenance state is adapted.
When except the state of keyboard or operation is 6 effective keyboard operations described in table 1 and states, encoder
300 output invalid keys number 1111.Effective key number or output invalid key number are either exported, encoder 300 changes output content
At the time of state latch edge for CP1 clock pulses；In embodiment, encoder 300 is CP1 clocks at the time of changing output content
The rising edge of pulse.
The period of CP1 clock pulses is the scan period of matrix keyboard.The keyboard scan period, can in more than 20ms
It has been effectively shielded from the influence of keyboard shake；The keyboard scan period in below 100ms, is unlikely to omit keyboard operation；
Therefore, the period of CP1 clock pulses should be controlled in 20~100ms.
The cycle request of CK sampling pulses is not more than the period of CP1 clock pulses, in this way, in the two divided-frequency signal CP2 of CP1
Each triggering of scanning pulse when obtaining conditional code, can ensure row status register 404, row shape along key assignments is alternately obtained
4 key assignments that state register 403 exports are always the last state of matrix keyboard.The special case of CK sampling pulses is directly to use
CP1 clock pulses is as CK sampling pulses.
Fig. 6 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is matrix form
During effective button operation of keyboard, the state latch edge of CP1 clock pulses of the encoder 300 after effective button operation is opened
Begin, until the state latch edge of next CP1 clock pulses, output duration is CP1 width clock cycle
Effective key number.The device of the matrix keyboard output is received, needs to inquire the output of matrix keyboard constantly, obtains key
Number.The period distances of inquiry are necessarily less than the period of CP1 clock pulses.
Whether key number of the circuit shown in Fig. 6 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, keyboard state change pulse is exported, for the reception device receiving matrix formula of auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 6 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.Delay buffer 601 is made of 4 edge triggered flip flops only with Trigger Function, and 4 edge triggered flip flops touch
The reception pulse input end that input terminal is delay buffer 601 is sent out, is connected to the CP1 output terminal of clock pulse of oscillator 500；
Delay buffer 601 carries out data latch on the state latch edge of CP1 clock pulses.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output terminal of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output terminal C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is buffered by delay
After the first-level buffer of device 601, signal postpones CP1 clock cycles than C3~C0, and Fig. 7 show the embodiment of the present invention
The waveform correlation schematic diagram that effectively operates of keyboard.The T1 sections of CP1 clock pulses are located at, matrix keyboard exists primary effective
Operation, effective operation of embodiment include：S1 singly-bounds are pressed, S2 singly-bounds are pressed, S3 singly-bounds are pressed, the S1 of S4+S1 combination operations
It presses, the S2 of S4+S2 combination operations is pressed, the release of S1 singly-bounds.On the next state latch edge once effectively operated, i.e. Fig. 7
Rising edge after middle CP1 clock pulses T1 sections, coding C3~C0 that encoder 300 exports change；In T2 sections, compile
Code device 300 exports efficient coding C3~C0 of a cycle；In T3, T4 and section later, coding C3 that encoder 300 exports~
C0 changes and again into maintenance state, which may be that such as S1 singly-bounds press maintenance state below, output
Invalid key number, it is also possible to which S3 singly-bounds press maintenance state below, export effective key number, until effectively operation next time.
Coding C3~C0 that D6 pulses in Fig. 7 schematically illustrate the output of encoder 300 is in maintenance state, is not become
Change, still change, the D6 pulses are not present in actual circuit.As shown in fig. 7, D6 pulses are low level, illustrate table
Show that coding C3~C0 that encoder 300 exports is in maintenance state, do not change；D6 pulses are high level, schematically illustrate volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 7 reflected is the situation of change of C31~C01, it is clear that
Q6 postpones CP1 clock cycles than D6.Equally, the Q6 pulses are not present in actual circuit.
In Fig. 7, coding C3~C0 that encoder 300 exports is in maintenance state, does not change, still changes,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
Into logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output terminal C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 postpone CP1 clock cycles than C0, therefore, when C0 changes, when XOR gate 602 exports 1 CP1
The positive pulse of clocked pulse period width；When C0 is a CP1 change width clock cycle signal, the output of XOR gate 602 2
The positive pulse of a width CP1 clock cycles.Whether XOR gate 603, XOR gate 604, XOR gate 605 judge C1~C3 respectively
It changes, principle is with judging it is identical whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605
Output terminal be respectively connected to or whether the input terminal of door 606 or door 606 change for comprehensive descision C0~C3, as long as
C0~C3 changes or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D triggers 74HC273 of rising edge triggering.
Delay buffer 601 can also use other schemes, for example, using RC circuits, using 4 RC circuits respectively to C0
~C3 is postponed；If the delay time of RC circuits is less than CP1 clock cycles, encoder 300 exports one
During the efficient coding C3~C0 in period, start and export efficient coding C3~C0 in output efficient coding C3~C0 and terminate all to generate
One keyboard state change pulse, the width of keyboard state change pulse are equal to RC circuit delay times；If RC circuits prolong
The slow time is more than or equal to CP1 clock cycles, then when encoder 300 exports efficient coding C3~C0 of a cycle,
A keyboard state change pulse is generated when exporting efficient coding C3~C0 and starting, pulse width is more than or equal to 2 CP1 clocks
Pulse period.It is required that the delay time of RC circuits is no more than 2 CP1 clock cycles, failed to report in order to avoid generating.
In embodiment, the first buffer register 101 carries out data latch, the second buffering in the failing edge of CP2 scanning pulses
Register 102 carries out data latch in the rising edge of CP2 scanning pulses.It can also be swept using the first buffer register 101 in CP2
The rising edge for retouching pulse carries out data latch, and the second buffer register 102 carries out data latch in the failing edge of CP2 scanning pulses
Mode, at this point, the output of data combination unit 500 forms conditional code in a manner that existing state key assignments is posterior in preceding, preceding state key assignments.
Existing state key assignments is equally applicable to the present invention in the conditional code that preceding, the preceding posterior mode of state key assignments forms.
In embodiment, the input connection mode of change data assembled unit 500 equally can be with existing state key assignments preceding, preceding
The posterior mode of state key assignments forms conditional code.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by CP1
Clock pulses, the control of CP2 scanning pulses are converted into the conditional code of same binary length, by the way of Unified coding
Reason, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；It is pressed if necessary to increase and decrease
Key operation function either adjust button operation function, do not need to modification keyboard scanning circuit structure, only need to be according to increase and decrease after
State code table update encoder 300, the storage content for re-writing update read-only memory.The invention circuit does not have
Using microcontrollers such as microcontroller, ARM, without running program, reliable operation.
Claims (10)
1. a kind of matrix keyboard scanner uni coding circuit, which is characterized in that by matrix keyboard, the first buffer register,
Two buffer registers, state Code memory, encoder, data combination unit composition；
The matrix keyboard scanner uni coding circuit synchronizes control by scanning pulse and clock pulses；
The matrix keyboard shares X rows, Y row, equipped with N bit keyboard status signal outputs；The N bit keyboards status signal is
Level signal；The N=X+Y；
First buffer register and the second buffer register are N binary registers；First buffer register
N positions data input pin be sequentially connected to N bit keyboard status signal outputs；The N positions data of second buffer register are defeated
Enter end and be sequentially connected to N bit keyboard status signal outputs；
The reception pulse input end of first buffer register and the second buffer register is connected to scanning pulse；
It is defeated that the data combination unit is equipped with N data input pins of the first via, the second road N data input pin and 2 × N data
Outlet；The first via N data input pins are sequentially connected to the N positions data output end of the first buffer register, second road N
Data input pin is sequentially connected to the N positions data output end of the second buffer register；
The data combination unit is additionally provided with data select signal end；The data select signal end is connected to scanning pulse；Number
According in 2 × N positions data output of assembled unit, when the scanning pulse is low level, N data of the first via are in preceding, the second road N
Position data are rear；When the scanning pulse is high level, N data of the first via are rear, and second road N data is preceding；Either,
In the 2 × N positions data output of data combination unit, when the scanning pulse is low level, N data of the first via are rear, and second
Road N data are preceding；When the scanning pulse is high level, N data of the first via are preceding, and second road N data is rear；
The state Code memory is 2 × N binary registers；2 × N positions data input pin of state Code memory is connected to
2 × N positions data output end of data combination unit；
The reception pulse input end of the state Code memory is connected to clock pulses；The matrix keyboard is by sampling pulse control
System obtains N bit keyboard status signals；
The encoder has 2 × N coding input ends, and the 2 × N coding input end is connected to 2 × N of state Code memory
Position data output end.
2. matrix keyboard scanner uni coding circuit according to claim 1, it is characterised in that：The week of the clock pulses
Phase is 20~100ms；The scanning pulse is the two divided-frequency signal of clock pulses；The period of the sampling pulse is no more than described
The period of clock pulses.
3. matrix keyboard scanner uni coding circuit according to claim 2, it is characterised in that：The clock pulses control
The invalid triggering edge of scanning pulse overturning is known as state latch edge；The state Code memory is in the state latch of clock pulses
Along progress data latch；First buffer register when the rising edge of scanning pulse carries out data latch, post by the second buffering
Storage carries out data latch in the failing edge of scanning pulse；Either, first buffer register is in the decline of scanning pulse
Along when carrying out data latch, the second buffer register carries out data latch in the rising edge of scanning pulse.
4. matrix keyboard scanner uni coding circuit according to claim 1, it is characterised in that：The state Code memory
2 × N positions data output ends export the conditional code of 2 × N；The conditional code is made of effective status code and invalid state code；
The key number of the encoder output is made of effective key number and invalid key number；The effective status code is by effective keyboard operation or shape
State generates, and encoder corresponds to output corresponding effectively key number when inputting each effective status code；The invalid state code is by nothing
It imitates keyboard operation or state generates, encoder inputs all corresponding output invalid key number during all invalid state codes.
5. matrix keyboard scanner uni coding circuit according to claim 4, it is characterised in that：The encoder has M
Key output terminal, the selection of M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
6. matrix keyboard scanner uni coding circuit according to claim 5, it is characterised in that：Further include keyboard state change
Change impulse generating unit, whether the key number for the output of judgment matrix formula keyboard changes, when the key of matrix keyboard output
When number changing, keyboard state change pulse is exported.
7. matrix keyboard scanner uni coding circuit according to claim 6, it is characterised in that：The keyboard state variation
Impulse generating unit by or door, M delay buffer and M XOR gate form；M delay buffers are used for matrix keyboard
The M positions key number of output carries out signal delay respectively；The input of M XOR gate is respectively the input of M delay buffers, output letter
Number；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output terminal output keyboard state change pulse of door.
8. matrix keyboard scanner uni coding circuit according to claim 1, it is characterised in that：Further include oscillator；Institute
State oscillator output clock pulses, scanning pulse and sampling pulse.
9. matrix keyboard scanner uni coding circuit according to claim 1, it is characterised in that：The matrix keyboard by
X row-Y row key-press matrix, row three state buffer, row three state buffer, row status register, column-shaped state register group into；It is all
The line of key-press matrix is respectively connected to the output terminal of row three state buffer, and the alignment of all key-press matrixs is respectively connected to row three
The output terminal of state buffer；All input terminals of row three state buffer and row three state buffer are connected to low level；All buttons
The line of matrix is respectively connected to the input terminal of row status register, and the alignment of all key-press matrixs is respectively connected to column-shaped state and posts
The input terminal of storage；The output terminal of the row status register collectively constitutes keyboard state letter with the output terminal of row status register
Number output terminal.
10. matrix keyboard scanner uni coding circuit according to claim 9, it is characterised in that：The row Three-State
Device is when the low level of sampling pulse enables effective, it is desirable that row status register carries out data lock in the rising edge of sampling pulse
It deposits, row three state buffer enables effective, row status register in the high level of sampling pulse and carried out in the failing edge of sampling pulse
Data latch；Either, row three state buffer is when the high level of sampling pulse enables effective, it is desirable that row status register is taking
The failing edge of sample pulse carries out data latch, row three state buffer enables effective, row Status register in the low level of sampling pulse
Device carries out data latch in the rising edge of sampling pulse.
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| CN201810338494.2A CN108536306B (en) | 2016-01-05 | 2016-01-05 | Matrix type keyboard scanning and coding method |
| CN201610003604.0A CN105468164B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard scanner uni coding circuit |
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| CN201610003604.0A CN105468164B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard scanner uni coding circuit |
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| CN106549676B (en) * | 2016-10-28 | 2019-09-17 | 青岛海信电器股份有限公司 | The power switch circuit of low-power consumption matrix keyboard and the application matrix keyboard |
| CN110441150B (en) * | 2019-09-09 | 2020-08-04 | 浙江大学 | Double-movable-arm material tensile test method and test machine thereof |
| CN113327412B (en) * | 2021-08-04 | 2021-11-16 | 深圳宇凡微电子有限公司 | Wireless signal decoding method, device, equipment and system |
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| CN101510127A (en) * | 2009-03-30 | 2009-08-19 | 北京中星微电子有限公司 | Method, apparatus and chip for implementing keyboard module composite key function |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
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| US4414538A (en) * | 1981-12-07 | 1983-11-08 | Teletype Corporation | Keyboard sense gate |
| CN101510127A (en) * | 2009-03-30 | 2009-08-19 | 北京中星微电子有限公司 | Method, apparatus and chip for implementing keyboard module composite key function |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
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| CN108536306A (en) | 2018-09-14 |
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