CN105677055B - matrix keyboard scanning circuit and method - Google Patents
matrix keyboard scanning circuit and method Download PDFInfo
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- CN105677055B CN105677055B CN201610003734.4A CN201610003734A CN105677055B CN 105677055 B CN105677055 B CN 105677055B CN 201610003734 A CN201610003734 A CN 201610003734A CN 105677055 B CN105677055 B CN 105677055B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
- G06F3/0202—Constructional details or processes of manufacture of the input device
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Abstract
A kind of matrix keyboard scanning circuit is made of matrix keyboard, the first shift register, the second shift register, state Code memory, encoder.The scan method of the scanning circuit is, via the control for the scanning pulse, shift pulse for meeting specific time sequence requirement, by the single key stroke of matrix keyboard, combination key operation, the state either maintained, the effective status code of same binary length and invalid state code are converted into, effective key number corresponding with each effective status code is exported after encoder encodes and either exports invalid key number corresponding with all invalid state codes；Different single key stroke, combination key operation or the states of maintenance are only embodied in not being same as above for conditional code；Button operation function is either adjusted if necessary to increase and decrease button operation function, does not need to modification keyboard scanning circuit structure, only need to encoder be changed according to the correspondence between the conditional code after increase and decrease and key number.The invention circuit does not have to write and run program, reliable operation.
Description
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of matrix keyboard scanning circuit and method.
Background technology
With the continuous development of embedded technology, current each electronic product is generally using microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by run the program in microcontroller come into
Row, encounters interference, program is caused to run fast, and scanning imaging system is by cisco unity malfunction.
Patent of invention " a kind of fast scanning and positioning method of matrix keyboard " application No. is CN201010153560.2 is adopted
Enter the Scan orientation process of keyboard with the mode that keyboard interrupt triggers, judged using the method that keyboard scan step is repeated several times
Whether button is effective, and the key assignments to being obtained carries out condition adjudgement；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then into singly-bound tupe；Key operation is combined in this way, then into Macintosh tupe.Described in the patent
Method solves since keyboard caused by the mechanical property of keyboard itself is shaken and causes the Problem-Errors such as wrong key, continuous touching,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with combining key operation；
Not accounting for keyboard state maintains a period of time just to perform the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to change keyboard scan finder structure.
Invention content
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of matrix forms
Keyboard scanning circuit and method, the matrix keyboard scanning circuit is by matrix keyboard, the first shift register, the second displacement
Register, state Code memory, encoder composition.
The matrix keyboard scanning circuit synchronizes control by scanning pulse, shift pulse.
The matrix keyboard shares X rows, Y row, equipped with N bit keyboard status signal outputs；The N bit keyboards state letter
Number be level signal；The N=X+Y.
First shift register has the function of the input of N parallel-by-bits and Serial output；The second shift LD utensil
There are serial input and 2 × N parallel-by-bit output functions.
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second displacement
The serial input terminal of register is connected to the serial output terminal of the first shift register；First shift register, the second displacement are posted
The shift pulse input terminal of storage is connected to shift pulse, and the presetting pulse input terminal of the first shift register is connected to scanning
Pulse.The presetting pulse of first shift register is used to carry out the N parallel-by-bits input data of the first shift register defeated
Enter to latch.
The state Code memory is 2 × N binary registers；2 × N positions data input pin of state Code memory connects
It is connected to 2 × N parallel-by-bit output terminals of the second shift register；The reception pulse input end of the state Code memory, which is connected to, to be swept
Retouch pulse.
The encoder has 2 × N coding input ends, and the 2 × N coding input end is connected to state Code memory
2 × N data output ends.
The scanning pulse, shift pulse sequential meet it is claimed below：In one cycle, scanning pulse has 1 arteries and veins
Punching, shift pulse have N number of pulse；The scanning pulse, shift pulse are all according to the sequence of 1 scanning pulse, N number of shift pulse
And it renews.
The period of the scanning pulse is 20~100ms.
First shift register, the shift pulse edge of the second shift register are effective.
The presetting pulse of first shift register is effective for edge；Either, the preset arteries and veins of the first shift register
Rush for high level it is effective when, it is desirable that scanning pulse is positive pulse；When the presetting pulse of first shift register is that low level is effective,
It is required that scanning pulse is negative pulse.
2 × N positions data output end of the state Code memory exports the conditional code of 2 × N；The conditional code is by effective
Conditional code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；It is described effective
Conditional code is generated by effective keyboard operation or state, and encoder corresponds to output when inputting each effective status code corresponding effective
Key number；The invalid state code is generated by invalid keyboard operation or state, and encoder inputs all corresponding during all invalid state codes
Export invalid key number.
The encoder has M key output terminals, and the selection of M values should meet 2MMore than or equal to effective key number and invalid key number
The sum of quantity.
The matrix keyboard scanning circuit further includes keyboard state change pulse and generates unit, for judgment matrix formula key
Whether the key number of disk output changes, when the key number of matrix keyboard output changes, output keyboard state variation arteries and veins
Punching.
The keyboard state change pulse generates unit and is made of M delay buffers, M XOR gate and/or door；M are prolonged
Slow buffer is used to carry out signal delay respectively to the M positions key number that matrix keyboard exports；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
The matrix keyboard by form X rows, Y row key-press matrix, row three state buffer, row three state buffer, row shape
State register, column-shaped state register group into；The line of all key-press matrixs is respectively connected to the output terminal of row three state buffer, institute
The alignment for having key-press matrix is respectively connected to the output terminal of row three state buffer；The institute of row three state buffer and row three state buffer
There is input terminal to be connected to low level；The line of all key-press matrixs is respectively connected to the input terminal of row status register, all to press
The alignment of key matrix is respectively connected to the input terminal of row status register；The output terminal of the row status register is posted with column-shaped state
The output terminal of storage collectively constitutes keyboard state signal output end.
The matrix keyboard is controlled by sampling pulse and obtains keyboard state signal；The sampling pulse selection scanning arteries and veins
One in punching, shift pulse；The row three state buffer is when the low level of sampling pulse enables effective, it is desirable that column-shaped state is posted
Storage is the rising edge of sampling pulse carries out data latches, row three state buffer enables effective, row in the high level of sampling pulse
Status register carries out data latch in the failing edge of sampling pulse；Either, row three state buffer is in the height electricity of sampling pulse
When flat enabled effective, it is desirable that row status register is the failing edge of sampling pulse carries out data latch, row three state buffer is taking
The low level of sample pulse enables effective, row status register and carries out data latch in the rising edge of sampling pulse.
The N positions, 2 × N, M refer both to binary digit data.
The beneficial effects of the invention are as follows：The scanning of state operation will be maintained to determine single key stroke, combination key operation, keyboard
Position, scanning pulse, the shift pulse required by meeting specific time sequence control the conditional code for being converted into same binary length, use
The mode of Unified coding is handled, and single key stroke, combination key operation, keyboard maintain state operation to be only embodied in conditional code not
Ibid；Button operation function is either adjusted if necessary to increase and decrease button operation function, does not need to modification keyboard scanning circuit knot
Structure need to only change encoder according to the correspondence between the conditional code after increase and decrease and key number, re-write read-only memory
Storage content.The invention circuit is not using microcontrollers such as microcontroller, ARM, and without running program, work can
It leans on.
Description of the drawings
Fig. 1 is matrix keyboard scanning circuit functional block diagram；
Fig. 2 is the matrix keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the scanning encoding circuit diagram of the embodiment of the present invention；
Fig. 4 is the pulse sequence figure of the embodiment of the present invention；
Fig. 5 is the impulse circuit schematic diagram of the embodiment of the present invention；
Fig. 6 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 7 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is matrix keyboard scanning circuit functional block diagram, by matrix keyboard 400, the first shift register 100,
Two shift registers 200, state Code memory 500, encoder 300 form.
Fig. 2 is the circuit diagram of the matrix keyboard 400 of the embodiment of the present invention, 2 rows, 2 row is shared, totally 4 buttons, by button
S1, button S2, button S3, button S4 and be connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, on
Pull-up resistor R4 and row three state buffer 401, row three state buffer 402, row status register 403, row status register 404
Composition.2 output terminals Y1, Y2 of row three state buffer 401 are respectively connected to 2 lines, and 2 of row three state buffer 402 are defeated
Outlet Y3, Y4 is respectively connected to 2 alignments；All input terminal X1~X4 of row three state buffer 401 and row three state buffer 402
It is connected to low level.
2 input terminals D41, D42 of row status register 403 are respectively connected to 2 lines, and the 2 of row status register 404
A input terminal D43, D44 are respectively connected to 2 alignments；2 output terminals Q41, Q42 output row state of row status register 403
Signal I1, I2,2 output terminals Q43, Q44 output row status signal I3, I4 of row status register 404；Row status register
403 2 output terminals collectively constitute 4 bit keyboard status signal outputs with 2 output terminals of row status register 404, export
Keyboard state signal I1, I2, I3, I4.
In embodiment, the enabled input EN1 low levels of row three state buffer 401 are effective, and row three state buffer 402 enables
It is effective to input EN2 high level；EN1 and EN2 is connected to the sampling pulse CK output terminals of oscillator.Row status register 403 with
Reception pulse input end CLK3, CLK4 of row status register 404 are connected to the sampling pulse CK output terminals of oscillator, row shape
Failing edge of the state register 403 in sampling pulse CK carries out data latch, and row status register 404 is in the rising of sampling pulse CK
Along progress data latch.
When row three state buffer 401 and row three state buffer 402 are using the three state buffer with model, for example, making simultaneously
During with three state buffer 74HC241, the enabled input of 74HC241 is effective for high level, therefore, sampling pulse CK output terminals with
Between the enabled input terminal EN1 of row three state buffer 401, need to increase a NOT gate.Similarly, when row status register 403
With row status register 404 using the data register with model, for example, row status register 403 and row status register 404
When using double D trigger 74HC74 composition data registers, the triggering input of 74HC74 is effective for rising edge, therefore, is taking
Between sample pulse CK output terminals and the reception pulse input end CLK3 of row status register 403, need to increase a NOT gate.
The first shift register 100, the second shift register 200, state Code memory 500, encoder 300 in Fig. 1
Scanning circuit is formed, embodiment circuit diagram is as shown in Figure 3.The status signal of embodiment matrix keyboard circuit output has 4,
Therefore, the first shift register 100 be have the function of to input parallel, 4 binary shift registers of Serial output, second moves
Bit register 200 is 8 binary shift registers for having the function of serial input, parallel output.First shift register 100
4 parallel input terminal L0~L3 be sequentially connected to I1, I2, I3, I4, the serial input terminal D2 of the second shift register 200 connects
It is connected to the serial output terminal Q1 of the first shift register 100.The displacement of first shift register 100, the second shift register 200
Pulse input end CLK1, CLK2 are connected to shift pulse CP2, the presetting pulse input terminal CLK0 of the first shift register 100
It is connected to scanning pulse CP1.
Requirement 8 bit binary datas of deposit of state Code memory 500,8 data input pin D57~D50 are connected to the
8 parallel-by-bit output terminal Q27~Q20 of two shift registers 200；The reception pulse input end CLK5 of state Code memory 500 connects
It is connected to scanning pulse CP1.
8 input terminal A7~A0 of encoder 300 be connected to 8 data output end Q57 of state Code memory 500~
Q50.Encoder 300, which exports, is scanned through 4 determining binary system keys number of coding.
In Fig. 3 embodiments, the first shift register 100 can select have parallel input, Serial output by 74HC165 etc.
The medium-scale integration shift register of function is formed or is made of edge triggered flip flop.Second shift register 200 can select
Select by 74HC164 etc. there is serial input, the medium-scale integration shift register of parallel output forms or is touched by edge
Send out device composition.When forming the first shift register 100, the second shift register 200 by edge triggered flip flop, preferably by edging trigger
D type flip flop composition.State Code memory 500 is made of edge triggered flip flop, is preferably made of the d type flip flop of edging trigger, example
Such as, either 4D triggers 74HC175 or 8D trigger 74HC273 is formed selection double D trigger 74HC74.
In Fig. 3 embodiments, encoder 300 is read-only memory.Address input end A7~A0 of read-only memory is coding
The input terminal of device 300, data output end D3~D0 of read-only memory are coding output terminal C3~C0 of encoder 300.
The scan method and operation principle of matrix keyboard scanning circuit are as follows：
Scanning encoding circuit scanning pulse CP1, shift pulse CP2 control under work, relevant pulse sequence figure is such as
Shown in Fig. 4.
The sequential of CP1, CP2 meet claimed below in embodiment：In one cycle, CP1 has 1 pulse, and CP2 has 4
Pulse；Each pulse according to 1 CP1 pulse, 4 CP2 pulses sequence in cycles.
Meeting CP1, CP2 pulse of timing requirements can be generated by various pulsqe distributors, and Fig. 5 is the embodiment of the present invention
Impulse circuit schematic diagram is made of oscillator 801, counter 802, pulsqe distributor 803.Clock pulse CP in Fig. 4 is by shaking
Device generation is swung, CP send to counter 802 and counted, and counter 802 is 10 system Counters, and 10 states of result P (count
Value) P0 → P9 is followed successively by, as shown in Figure 4.Pulsqe distributor 803 in embodiment is realized using ROM memory, hereon referred to as arteries and veins
Punching distribution ROM memory.The address input of pulse distribution ROM memory is connected to the counting output of counter 802, pulse distribution
2 data output ends of ROM memory are exported respectively as CP1 pulses, CP2 pulses.The write-in content of pulse distribution ROM memory
It is shown in Table 1.
1 pulse distribution ROM memory tables of data of table
The output of ROM memory address in table 1, i.e. counter is at least 4 binary codes.Under normal circumstances, counter
If 802 is regular using binary addition, corresponding 4 binary codes 0000~1001 of P0~P9 sequences, i.e. ROM memory
Location ranging from 0000~1001, the storage content of address 0000~1001 is the corresponding contents of P0~P9 in table 1.
Pulse distribution ROM memory needs 2 data outputs.If the address input of pulse distribution ROM memory has R,
When matrix keyboard has the output of N bit keyboards status signal, the selection of R needs satisfaction 2RMore than or equal to 2 × (N+1).
Oscillator 801 is multivibrator.The period of scanning pulse CP1 is 20~100ms.CP1, CP2 can also be by squares
Circuit or device except configuration keyboard scanning circuit provide.
In Fig. 2,4 buttons of matrix keyboard are arranged with 2 × 2 matrix form, and all lines and alignment all pass through
Pull-up resistor is connected to power supply+VCC.Matrix keyboard is controlled by sampling pulse CK, using reversal process obtain keyboard state signal I4,
I3、I2、I1.For example, the keyboard state signal that the keyboard state signal of no key pressing, which is 1111, S1, to be pressed is 1010, S1, S2
The keyboard state signal pressed simultaneously is 0010.4 binary codes of keyboard state signal are known as key assignments.Sampling pulse CK can be with
One in scanning pulse CP1, shift pulse CP2 is selected, preferably using shift pulse CP2 simultaneously as sampling pulse CK.
Sampling pulse CK controls carry out matrix keyboard the method that key assignments is read in sampling：In the low electricity of sampling pulse CK
It is flat, all lines is controlled to export low level by row three state buffer 401, row three state buffer 402 exports high-impedance state and opens row
Line；It is sampled in the rising edge of sampling pulse CK by row status register 404 and reads alignment state as the 2 high of key assignments；It is taking
The high level of sample pulse CK controls all alignments to export low level by row three state buffer 402, and row three state buffer 401 is defeated
Go out high-impedance state and open line；It is sampled in the failing edge of sampling pulse CK by row status register 403 and reads line state as key
Low 2 of value；In cycles, 4 key assignments that row status register 404, row status register 403 export are always the above process
The last state of matrix keyboard.
Sampling is carried out to matrix keyboard from sampling pulse CK controls and reads the method for key assignments it is found that row three state buffer
401 when the low level of sampling pulse CK enables effective, while requires row status register 404 in the rising edge of sampling pulse CK
Carry out data latch, row three state buffer 402 enables effective, row status register 403 in the high level of sampling pulse CK and taking
The failing edge of sample pulse CK carries out data latch.In turn, if high level of the row three state buffer 401 in sampling pulse CK makes
When can be effective, while failing edge of the row status register 404 in sampling pulse CK be required to carry out data latch, row three state buffer
402 sampling pulse CK low level enable effectively, row status register 403 sampling pulse CK rising edge carry out data lock
It deposits.
During above-mentioned sampling pulse CK controls sampling to read key assignments, row status register 403, row status register
404 at the time of precisely row three state buffer 402 is with the 401 carry out state reversion of row three state buffer at the time of sampled, just
Often the row status register 403 under work or row status register 404 can be sampled correctly.If it is required that have in certain sequential
Allowance can then postpone, method to being connected to row three state buffer 402 and the sampling pulse CK of row three state buffer 401
Be enable sampling pulse CK by RC retardation ratio circuit be then connected to row three state buffer 401 and row three state buffer 402 EN1,
EN2, delay time are determined that determining the principle of the delay time of RC retardation ratio circuit is, the sampling pulse of delay by RC retardation ratio circuit
CK phases are no more than 90 °；Either sampling pulse CK is then connected to row three state buffer 401 after the buffering of several gate circuits
With EN1, EN2 of row three state buffer 402, overall delay time of the delay time for several gate circuits at this time.
First shift register 100 is under the control of scanning pulse CP1, to the status signal of the output of matrix keyboard 400
I1, I2, I3, I4 carry out data input latch, and the data of the latch inside the first shift register 100 are known as current key at this time
Value.Second shift register 200, via the control of 8 CP2 pulses, the first two current key assignments is shifted in two periods before
To 200 output terminal of the second shift register, 4 digits first moved into the second shift register 200 output at this time are stated to be existing state
Key assignments, state key assignments before 4 digits moved into afterwards are stated to be.
Existing state key assignments that scanning pulse CP1 exports the second shift register 200, preceding state key assignments are latched in conditional code deposit
The output terminal of device 500, the output of state Code memory 500 are similarly preceding state key assignments and existing state key assignments.
First shift register 100, the equal edge of shift pulse of the second shift register 200 are effective, and therefore, CP2 can be with
It is positive pulse or negative pulse.
When the presetting pulse of first shift register 100 is that edge is effective, scanning pulse CP1 can be negative pulse, also may be used
Think positive pulse；When the presetting pulse of first shift register 100 is that high level is effective, it is desirable that scanning pulse CP1 is positive pulse；
When the presetting pulse of first shift register 100 is that low level is effective, it is desirable that scanning pulse CP1 is negative pulse.For example, first moves
When bit register 100 selects to be made of 74HC165, presetting pulse is effective for low level, and therefore, scanning pulse CP1 is negative arteries and veins
Punching.
In embodiment, the 4 existing state key assignments and 4 preceding state key assignments of 500 data output end of state Code memory output are common
Form 8 conditional codes.8 conditional codes are used for the current state and mode of operation of recognition matrix formula keyboard.For example, this reality
It applies in example, the conditional code of no key pressing is 11111111；The conditional code of S1 key singly-bound pushes is 11111010；S1 key singly-bounds
The conditional code pressed and maintained is 10101010；The conditional code of S1 keys singly-bound release operation is 10101111；S2 key singly-bounds are pressed
The conditional code of operation is 11110110；The conditional code of S4 key singly-bound pushes is 11110101；The S1 of S2+S1 combination operations is pressed
Lower operation after expression first presses S2, presses the operation of S1, the conditional code of the operation is again in the state that S2 maintenances are pressed
01100010。
Encoder 300 is used to conditional code being converted to key number.In embodiment, equipped with 6 effective keyboard operations and state,
Including：
Operation 0：The singly-bound push of button S1, key number are 0000；
Operation 1：The singly-bound push of button S2, key number are 0001；
Operation 2：The singly-bound push of button S3, key number are 0010；
Operation 3：Button S3 singly-bounds press after maintenance state, key number be 0011；
Operation 4：After button S4 singly-bounds are pressed, then the combination key operation of S2 is pushed button, key number is 0100；
Operation 5：The singly-bound release operation of button S1, key number is 0101.
The conditional code and key number obtained according to above-mentioned regulation is shown in coding schedule 2：
2 coding schedule of table
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bounds are pressed | 11111010 | 0000 |
| S2 singly-bounds are pressed | 11110110 | 0001 |
| S3 singly-bounds are pressed | 11111001 | 0010 |
| S3 singly-bounds press maintenance | 10011001 | 0011 |
| S4+S2 combination operations | 01010100 | 0100 |
| S1 singly-bounds discharge | 10101111 | 0101 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, designs circuit, meets the logical relation of table 2.
The encoder 300 of embodiment is preferably made of read-only memory.Read-only memory has 8 bit address, and totally 28A 4 two
System storage unit.6 effective keyboard operations have 6 effective status codes, corresponding 6 effective keys number with state；By state
Address A7~A0 of the code as read-only memory, in 6 corresponding storage units of effective status code, by corresponding key number
As storage data write-in.The conditional code generated except 6 effective keyboard operations and state is invalid state code, i.e., in table 2
Other operation or state caused by be invalid state code；In other storage units, invalid key number, invalid key is all written
Number for a value except 6 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When there is read-only memory piece selected control system, data output to delay
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase or subtract as needed
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M values should
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When matrix keyboard has the output of N bit keyboards status signal
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to change table 2 as needed, it will
Modified content re-writes the storage content of read-only memory.
The edge of scanning pulse CP1 at the time of state Code memory 500 is carried out data latch is known as state latch edge,
It is the rising edge of CP1 in embodiment.It is preset and next by CP1 pulses when matrix keyboard S1 singly-bounds are pressed in embodiment
The state latch of CP1 pulses by conditional code along after being latched in state Code memory 500, in a CP1 pulse period, coding output
Hold C3~C0 run-out keies number 0000；When matrix keyboard S2 singly-bounds are pressed, by the shape of the preset and next CP1 pulses of CP1 pulses
State is latched along after conditional code is latched in state Code memory 500, in a CP1 pulse period, run-out key number 0001；Work as matrix
After formula keyboard first presses S4, then S2 is pressed, encoder 300 combines key pressing in S2, by the preset and next CP1 arteries and veins of CP1 pulses
The state latch of punching by conditional code along after being latched in state Code memory 500, in a CP1 pulse period, run-out key number 0100；
When matrix keyboard S1 singly-bounds discharge, conditional code is latched in by the state latch edge by the preset and next CP1 pulses of CP1 pulses
After state Code memory 500, in a CP1 pulse period, run-out key number 0101；It can therefore be seen that when what is identified is matrix
During effective button operation of formula keyboard, the output duration after effective button operation of encoder 300 is wide for a CP1 period
Effective key number of degree.
In embodiment, when matrix keyboard S3 singly-bounds are pressed, encoder 300 is pressed in S3 singly-bounds, pre- by CP1 pulses
It puts with the state latch of next CP1 pulses along after conditional code is latched in state Code memory 500, in a CP1 pulse period,
Run-out key number 0010；Start on the state latch edge of next CP1, terminate until S3 singly-bounds press maintenance state, by CP1 arteries and veins
The state latch of preset and next CP1 pulses is rushed along after conditional code is latched in state Code memory 500, encoder 300 exports
Key number 0011；It can therefore be seen that when identification be the maintenance state of matrix keyboard when, encoder 300 exports effective key number
Duration and the duration of the maintenance state be adapted.
When except the state of keyboard or operation is 6 effective keyboard operations described in table 2 and states, encoder
300 output invalid keys number 1111.Effective key number or output invalid key number are either exported, encoder 300 changes output content
At the time of state latch edge for CP1；In embodiment, rising edge at the time of encoder 300 changes output content for CP1.
The period of CP1 is the scan period of matrix keyboard.The keyboard scan period in more than 20ms, can effectively keep away
The influence of key point disk key jitter；The keyboard scan period in below 100ms, is unlikely to omit keyboard operation；Therefore, CP1
Period should be controlled in 20~100ms.
Due to CP1 pulses in state latch along being latching to the conditional code of state Code memory 500 as preceding state key assignments and existing state
Key assignments, the current key assignments after button operation need one CP1 pulse period of delay that existing state key assignment combination could be used as to become state
Code, therefore, after key pressing, also there are one the delays of CP1 pulse periods for run-out key No. 300 of encoder.Since button is by artificial
Operation, the time delay of tens ms in operation on not influencing.
Fig. 6 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is matrix form
During effective button operation of keyboard, the state latch edge of CP1 of the encoder 300 after effective button operation starts, until next
Until the state latch edge of a CP1, effective key number of the output duration for a CP1 periodic width.Receive the matrix form
The device of keyboard output, needs to inquire the output of matrix keyboard constantly, obtains key number.The period distances of inquiry are necessarily less than
The period of CP1.
Whether key number of the circuit shown in Fig. 6 for the output of judgment matrix formula keyboard changes, when matrix keyboard exports
Key number when changing, keyboard state change pulse is exported, for the reception device receiving matrix formula of auxiliary moment configuration keyboard
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 6 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.Delay buffer 601 is made of 4 edge triggered flip flops only with Trigger Function, and 4 edge triggered flip flops touch
The reception pulse input end that input terminal is delay buffer 601 is sent out, is connected to CP1；Delay buffer 601 is in the state of CP1
It latches along progress data latch.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output terminal of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output terminal C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is buffered by delay
After the first-level buffer of device 601, signal postpones a CP1 pulse period than C3~C0, and Fig. 7 show the key of the embodiment of the present invention
The waveform correlation schematic diagram that disk effectively operates.The T1 sections of CP1 pulses are located at, matrix keyboard has primary effectively operation, real
The effective operation for applying example includes：S1 singly-bounds are pressed, S2 singly-bounds are pressed, S3 singly-bounds are pressed, the S1 of S4+S1 combination operations is pressed, S4+
The S2 of S2 combination operations is pressed, the release of S1 singly-bounds.On the next state latch edge once effectively operated, i.e. CP1 pulses in Fig. 7
Rising edge after T1 sections, coding C3~C0 that encoder 300 exports change；In T2 sections, the output of encoder 300 one
Efficient coding C3~C0 of a CP1 pulse periods；In T3, T4 and section later, coding C3~C0 that encoder 300 exports is another
Secondary change and enter maintenance state, which may be that such as S1 singly-bounds press maintenance state below, export invalid key
Number, it is also possible to S3 singly-bounds press maintenance state below, export effective key number, until effectively operation next time.
Coding C3~C0 that D6 pulses in Fig. 7 schematically illustrate the output of encoder 300 is in maintenance state, is not become
Change, still change, the D6 pulses are not present in actual circuit.As shown in fig. 7, D6 pulses are low level, illustrate table
Show that coding C3~C0 that encoder 300 exports is in maintenance state, do not change；D6 pulses are high level, schematically illustrate volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 7 reflected is the situation of change of C31~C01, it is clear that
Q6 postpones a CP1 pulse period than D6.Equally, the Q6 pulses are not present in actual circuit.
In Fig. 7, coding C3~C0 that encoder 300 exports is in maintenance state, does not change, still changes,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
Into logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output terminal C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 postpone a CP1 pulse period than C0, and therefore, when C0 changes, XOR gate 602 exports 1 CP1 pulses week
The positive pulse of phase width；When C0 is a CP1 pulse period change width signal, XOR gate 602 exports 2 CP1 pulses weeks
The positive pulse of phase width.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 changes respectively, principle with
It is identical to judge whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 output terminal connect respectively
It is connected to or whether the input terminal of door 606 or door 606 changes for comprehensive descision C0~C3, as long as C0~C3 changes,
Or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D triggers 74HC273 of rising edge triggering.
Delay buffer 601 can also use other schemes, for example, using RC circuits, using 4 RC circuits respectively to C0
~C3 is postponed；If the delay time of RC circuits is less than a CP1 pulse period, encoder 300 exports a cycle
Efficient coding C3~C0 when, output efficient coding C3~C0 start and export efficient coding C3~C0 terminate all generation one
Keyboard state change pulse, the width of keyboard state change pulse are equal to RC circuit delay times；If during the delay of RC circuits
Between be more than or equal to a CP1 pulse period, then encoder 300 export a cycle efficient coding C3~C0 when, have in output
Effect coding C3~C0 generates a keyboard state change pulse when starting, which is more than or equal to 2 CP1 pulse periods.
It is required that the delay time of RC circuits is no more than 2 CP1 pulse periods, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by full
2 Pulse Width Controls of sufficient specific time sequence requirement are converted into the conditional code of same binary length, by the way of Unified coding into
Row processing, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If necessary to increase
Subtract button operation function and either adjust button operation function, do not need to modification keyboard scanning circuit structure, it only need to be according to increase and decrease
State code table afterwards updates encoder 300, the storage content for re-writing update read-only memory.The invention circuit
Not using microcontrollers such as microcontroller, ARM, without running program, reliable operation.
Claims (10)
1. a kind of matrix keyboard scanning circuit, which is characterized in that by matrix keyboard, the first shift register, the second displacement
Register, state Code memory, encoder composition；
The matrix keyboard scanning circuit synchronizes control by scanning pulse, shift pulse；
The matrix keyboard shares X rows, Y row, equipped with N bit keyboard status signal outputs；The N bit keyboards status signal is
Level signal；The N=X+Y；
First shift register has the function of the input of N parallel-by-bits and Serial output；Second shift register has string
Row input and 2 × N parallel-by-bit output functions；
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second shift LD
The serial input terminal of device is connected to the serial output terminal of the first shift register；First shift register, the second shift register
Shift pulse input terminal be connected to shift pulse, the presetting pulse input terminal of the first shift register is connected to scanning arteries and veins
Punching；
The state Code memory is 2 × N binary registers；2 × N positions data input pin of state Code memory is connected to
2 × N parallel-by-bit output terminals of second shift register；The reception pulse input end of the state Code memory is connected to scanning arteries and veins
Punching；
The encoder has 2 × N coding input ends, and the 2 × N coding input end is connected to 2 × N of state Code memory
Position data output end；
The scanning pulse, shift pulse sequential meet it is claimed below：In one cycle, scanning pulse has 1 pulse, moves
Digit pulse has N number of pulse；The scanning pulse, shift pulse are according to 1 scanning pulse, the sequence Zhou Erfu of N number of shift pulse
Begin.
2. matrix keyboard scanning circuit according to claim 1, it is characterised in that：The period of the scanning pulse is 20
~100ms.
3. matrix keyboard scanning circuit according to claim 1, it is characterised in that：First shift register,
The shift pulse edge of two shift registers is effective；The presetting pulse of first shift register is effective for edge.
4. matrix keyboard scanning circuit according to claim 1, it is characterised in that：First shift register,
The shift pulse edge of two shift registers is effective；It, when the presetting pulse of first shift register is that high level is effective
It is positive pulse to seek scanning pulse；When the presetting pulse of first shift register is that low level is effective, it is desirable that scanning pulse is negative arteries and veins
Punching.
5. matrix keyboard scanning circuit according to claim 1, it is characterised in that：2 × N of the state Code memory
Position data output end exports the conditional code of 2 × N；The conditional code is made of effective status code and invalid state code；The volume
The key number of code device output is made of effective key number and invalid key number；The effective status code is produced by effective keyboard operation or state
Raw, encoder corresponds to output corresponding effectively key number when inputting each effective status code；The invalid state code is by invalid key
Disk operates or state generates, and encoder inputs all corresponding output invalid key number during all invalid state codes.
6. matrix keyboard scanning circuit according to claim 5, it is characterised in that：The encoder has the M keys number defeated
Outlet, the selection of M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
7. matrix keyboard scanning circuit according to claim 6, it is characterised in that：Further include keyboard state change pulse
Unit is generated, whether the key number for the output of judgment matrix formula keyboard changes, when the key number of matrix keyboard output occurs
During change, keyboard state change pulse is exported.
8. matrix keyboard scanning circuit according to claim 7, it is characterised in that：The keyboard state change pulse production
Raw unit is made of M delay buffers, M XOR gate and/or door；M delay buffers are used for what matrix keyboard was exported
M keys number carry out signal delay respectively；The input of M XOR gate is respectively the input of M delay buffers, output signal；M
The output of XOR gate is respectively connected to or the input terminal of door；Or the output terminal output keyboard state change pulse of door.
9. matrix keyboard scanning circuit according to claim 1, it is characterised in that：The matrix keyboard is by forming X
Row, Y row key-press matrixs, row three state buffer, row three state buffer, row status register, column-shaped state register group into；It is all
The line of key-press matrix is respectively connected to the output terminal of row three state buffer, and the alignment of all key-press matrixs is respectively connected to row three
The output terminal of state buffer；All input terminals of row three state buffer and row three state buffer are connected to low level；All buttons
The line of matrix is respectively connected to the input terminal of row status register, and the alignment of all key-press matrixs is respectively connected to column-shaped state and posts
The input terminal of storage；The output terminal of the row status register collectively constitutes keyboard state letter with the output terminal of row status register
Number output terminal.
10. matrix keyboard scanning circuit according to claim 9, it is characterised in that：The matrix keyboard is by sampling
Pulse Width Control obtains keyboard state signal；One in the sampling pulse selection scanning pulse, shift pulse；The row tri-state
Buffer is when the low level of sampling pulse enables effective, it is desirable that row status register carries out data in the rising edge of sampling pulse
Latch, row three state buffer the high level of sampling pulse enable effectively, row status register sampling pulse failing edge into
Row data latch；Either, row three state buffer is when the high level of sampling pulse enables effective, it is desirable that row status register exists
The failing edge of sampling pulse carries out data latch, row three state buffer enables effective, row state in the low level of sampling pulse and posts
Storage carries out data latch in the rising edge of sampling pulse.
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| CN201610003734.4A CN105677055B (en) | 2016-01-05 | 2016-01-05 | matrix keyboard scanning circuit and method |
| CN201810337458.4A CN108519827B (en) | 2016-01-05 | 2016-01-05 | A kind of matrix keyboard scan method |
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| CN201810337458.4A Expired - Fee Related CN108519827B (en) | 2016-01-05 | 2016-01-05 | A kind of matrix keyboard scan method |
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| CN107301726A (en) * | 2017-07-03 | 2017-10-27 | 惠州市天泽盈丰物联网科技股份有限公司 | Intelligent card data acquisition terminal, keyboard scanning system and method |
| CN116566398A (en) * | 2023-07-12 | 2023-08-08 | 上海灵动微电子股份有限公司 | Keyboard scanning method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0188151B1 (en) * | 1984-12-20 | 1990-03-28 | Automobiles Peugeot | Keyboard device |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
| CN101943948A (en) * | 2009-07-07 | 2011-01-12 | 扬智科技股份有限公司 | Keyboard scanning device and keyboard scanning method |
| CN103226391A (en) * | 2013-05-22 | 2013-07-31 | 湖南工业大学 | Scan locating method for independent keyboard |
| CN103279197A (en) * | 2013-06-08 | 2013-09-04 | 湖南工业大学 | Keyboard scanning positioning method |
-
2016
- 2016-01-05 CN CN201610003734.4A patent/CN105677055B/en active Active
- 2016-01-05 CN CN201810337458.4A patent/CN108519827B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0188151B1 (en) * | 1984-12-20 | 1990-03-28 | Automobiles Peugeot | Keyboard device |
| CN101943948A (en) * | 2009-07-07 | 2011-01-12 | 扬智科技股份有限公司 | Keyboard scanning device and keyboard scanning method |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
| CN103226391A (en) * | 2013-05-22 | 2013-07-31 | 湖南工业大学 | Scan locating method for independent keyboard |
| CN103279197A (en) * | 2013-06-08 | 2013-09-04 | 湖南工业大学 | Keyboard scanning positioning method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108519827B (en) | 2019-10-18 |
| CN105677055A (en) | 2016-06-15 |
| CN108519827A (en) | 2018-09-11 |
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