YU39168B - Process for the preparation of a palladium catalyst process for the deposition of a combined layer of heteroepitaxial silicon on a heated substrate of sapphire or spine - Google Patents

Process for the preparation of a palladium catalyst process for the deposition of a combined layer of heteroepitaxial silicon on a heated substrate of sapphire or spine

Info

Publication number
YU39168B
YU39168B YU02236/74A YU223674A YU39168B YU 39168 B YU39168 B YU 39168B YU 02236/74 A YU02236/74 A YU 02236/74A YU 223674 A YU223674 A YU 223674A YU 39168 B YU39168 B YU 39168B
Authority
YU
Yugoslavia
Prior art keywords
spine
sapphire
deposition
preparation
palladium catalyst
Prior art date
Application number
YU02236/74A
Other languages
English (en)
Other versions
YU223674A (en
Inventor
J F Corboy
G W Clullen
G W Cullen
N Pastal
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of YU223674A publication Critical patent/YU223674A/xx
Publication of YU39168B publication Critical patent/YU39168B/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/025—Deposition multi-step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/129—Pulse doping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
YU02236/74A 1973-08-17 1974-08-15 Process for the preparation of a palladium catalyst process for the deposition of a combined layer of heteroepitaxial silicon on a heated substrate of sapphire or spine YU39168B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US389192A US3885061A (en) 1973-08-17 1973-08-17 Dual growth rate method of depositing epitaxial crystalline layers

Publications (2)

Publication Number Publication Date
YU223674A YU223674A (en) 1982-05-31
YU39168B true YU39168B (en) 1984-08-31

Family

ID=23537232

Family Applications (1)

Application Number Title Priority Date Filing Date
YU02236/74A YU39168B (en) 1973-08-17 1974-08-15 Process for the preparation of a palladium catalyst process for the deposition of a combined layer of heteroepitaxial silicon on a heated substrate of sapphire or spine

Country Status (14)

Country Link
US (1) US3885061A (xx)
JP (1) JPS547556B2 (xx)
BE (1) BE814071A (xx)
CA (1) CA1025334A (xx)
CH (1) CH590084A5 (xx)
DE (1) DE2422508C3 (xx)
FR (1) FR2245406B1 (xx)
GB (1) GB1459839A (xx)
IN (1) IN141844B (xx)
IT (1) IT1012165B (xx)
NL (1) NL7406548A (xx)
SE (1) SE401463B (xx)
SU (1) SU612610A3 (xx)
YU (1) YU39168B (xx)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986192A (en) * 1975-01-02 1976-10-12 Bell Telephone Laboratories, Incorporated High efficiency gallium arsenide impatt diodes
US4201604A (en) * 1975-08-13 1980-05-06 Raytheon Company Process for making a negative resistance diode utilizing spike doping
US4265991A (en) * 1977-12-22 1981-05-05 Canon Kabushiki Kaisha Electrophotographic photosensitive member and process for production thereof
DE2943634C2 (de) * 1979-10-29 1983-09-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Epitaxiereaktor
US4279688A (en) * 1980-03-17 1981-07-21 Rca Corporation Method of improving silicon crystal perfection in silicon on sapphire devices
US4596208A (en) * 1984-11-05 1986-06-24 Spire Corporation CVD reaction chamber
GB2185758B (en) * 1985-12-28 1990-09-05 Canon Kk Method for forming deposited film
US4838983A (en) * 1986-07-03 1989-06-13 Emcore, Inc. Gas treatment apparatus and method
US4772356A (en) * 1986-07-03 1988-09-20 Emcore, Inc. Gas treatment apparatus and method
US4775641A (en) * 1986-09-25 1988-10-04 General Electric Company Method of making silicon-on-sapphire semiconductor devices
CA1332039C (en) * 1987-03-26 1994-09-20 Takao Yonehara Ii - vi group compound crystal article and process for producing the same
JPS63237517A (ja) * 1987-03-26 1988-10-04 Canon Inc ３−５族化合物膜の選択形成方法
US5281283A (en) * 1987-03-26 1994-01-25 Canon Kabushiki Kaisha Group III-V compound crystal article using selective epitaxial growth
CA1321121C (en) * 1987-03-27 1993-08-10 Hiroyuki Tokunaga Process for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same
US5304820A (en) * 1987-03-27 1994-04-19 Canon Kabushiki Kaisha Process for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same
JPH01161826A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 気相エピタキシャル成長法
US5104690A (en) * 1990-06-06 1992-04-14 Spire Corporation CVD thin film compounds
USH1145H (en) 1990-09-25 1993-03-02 Sematech, Inc. Rapid temperature response wafer chuck
JP2000223419A (ja) 1998-06-30 2000-08-11 Sony Corp 単結晶シリコン層の形成方法及び半導体装置の製造方法、並びに半導体装置
RU2618279C1 (ru) * 2016-06-23 2017-05-03 Акционерное общество "Эпиэл" Способ изготовления эпитаксиального слоя кремния на диэлектрической подложке
CN116884832B (zh) * 2023-09-06 2023-12-15 合肥晶合集成电路股份有限公司 半导体器件及其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189494A (en) * 1963-08-22 1965-06-15 Texas Instruments Inc Epitaxial crystal growth onto a stabilizing layer which prevents diffusion from the substrate
US3663319A (en) * 1968-11-20 1972-05-16 Gen Motors Corp Masking to prevent autodoping of epitaxial deposits
US3669769A (en) * 1970-09-29 1972-06-13 Ibm Method for minimizing autodoping in epitaxial deposition
US3765960A (en) * 1970-11-02 1973-10-16 Ibm Method for minimizing autodoping in epitaxial deposition
JPS5113607B2 (xx) * 1971-08-24 1976-05-01

Also Published As

Publication number Publication date
US3885061A (en) 1975-05-20
DE2422508C3 (de) 1979-08-02
SE7406350L (xx) 1975-02-18
CH590084A5 (xx) 1977-07-29
DE2422508B2 (de) 1978-11-23
IN141844B (xx) 1977-04-23
IT1012165B (it) 1977-03-10
SU612610A3 (ru) 1978-06-25
YU223674A (en) 1982-05-31
SE401463B (sv) 1978-05-16
FR2245406A1 (xx) 1975-04-25
AU6895474A (en) 1975-11-20
DE2422508A1 (de) 1975-03-13
CA1025334A (en) 1978-01-31
GB1459839A (en) 1976-12-31
FR2245406B1 (xx) 1982-09-24
JPS5046481A (xx) 1975-04-25
JPS547556B2 (xx) 1979-04-07
BE814071A (fr) 1974-08-16
NL7406548A (nl) 1975-02-19

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