US3885061A - Dual growth rate method of depositing epitaxial crystalline layers - Google Patents

Dual growth rate method of depositing epitaxial crystalline layers Download PDF

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Publication number
US3885061A
US3885061A US389192A US38919273A US3885061A US 3885061 A US3885061 A US 3885061A US 389192 A US389192 A US 389192A US 38919273 A US38919273 A US 38919273A US 3885061 A US3885061 A US 3885061A
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United States
Prior art keywords
hydrogen
mixture
layer
silane
growth rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US389192A
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English (en)
Inventor
John Francis Corboy
Glenn Wherry Cullen
Nicholas Pastal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
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RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Priority to US389192A priority Critical patent/US3885061A/en
Priority to IN819/CAL/74A priority patent/IN141844B/en
Priority to BE143512A priority patent/BE814071A/xx
Priority to GB1906074A priority patent/GB1459839A/en
Priority to IT22445/74A priority patent/IT1012165B/it
Priority to DE2422508A priority patent/DE2422508C3/de
Priority to CA199,858A priority patent/CA1025334A/en
Priority to AU68954/74A priority patent/AU479429B2/en
Priority to JP5529974A priority patent/JPS547556B2/ja
Priority to CH673774A priority patent/CH590084A5/xx
Priority to NL7406548A priority patent/NL7406548A/xx
Priority to SU742025410A priority patent/SU612610A3/ru
Priority to FR7417303A priority patent/FR2245406B1/fr
Priority to SE7406350A priority patent/SE401463B/xx
Priority to YU02236/74A priority patent/YU39168B/xx
Application granted granted Critical
Publication of US3885061A publication Critical patent/US3885061A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/025—Deposition multi-step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/129—Pulse doping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Definitions

  • PATENTEB HAYZU I975 SHEET 10F 2 GASES OUT cour'se'of or under contract No.”F336l-C-l695 with the Department of the Air Force.
  • each active device occupies a separate island of single crystal semiconductor material deposited on an appropriate insulating substrate.
  • single crystal silicon films for example, single crystal sapphire or spinel (magnesium aluminate) has proved to be a satisfactory substrate material.
  • SOS silicon-on-sapphire or silicon-on-spinel
  • transistors in SOS work pieces which have all electrical characteristics as good as those of transistors made in bulk silicon work pieces. It has also been found that transistors in SOS work pieces vary widely in characteristics as growth parameters of the silicon films in which they are formed, are varied. This latter is due to the fact that properties of the grown silicon film, such as degree of crystalline perfection, vary with growth parameters such as growth rate of the film.
  • Heteroepitaxial silicon films are usually grown by passing a mixture of silane (SiH and hydrogen over a heated sapphire or spinel substrate. These deposition constituents (including silicon) react with these substrates and form gaseous reaction products which tend to contaminate the crystalline deposit. At slower growth rates, the increased time of exposure leads to a higher degree of contamination.
  • growth temperature Another factor which influences contamination of the grown film is growth temperature. As growth temperatures increase, autodoping with contaminants from the substrate also increases.
  • Active device characteristics tend to be most desirable when the mobility of the charge carriers (Hall mobility) is relatively high, leakage currents are relatively low, and minority carrier lifetime is relatively high. Best MOS/SOS transistor characteristics have been obtained on films 0.8 pm thick. In general, however, the epitaxial layer thickness should be as thin as possible consistent with acceptable electrical characteristics, since reduced film thickness reduces metallization failure along the film edges where vapor deposited leads are utilized to connect to the electrode regions.
  • the present invention is an improved method of depositing an'epitaxial film on a crystalline substrate. This is accomplished by depositing a film in two stages by an improved technique.
  • the first stage is the deposition of a very thin film (i.e., one having a thickness of about 500-2000 A) using a burst technique. Using the burst technique an average growth rate of 4-6 ,um/min can be achieved.
  • the second stage is the deposition of the remainder of the film at a slower rate (i.e., not over about 0.5 um/min). By this method, a satisfactory silicon film 0.5 urn thick can be deposited in 1-4 minutes.
  • FIG. 1 is an elevation view, partly in section, of a reaction chamber that can be used in the present method.
  • FIG. 2 is a schematic diagram of a gas supply and mixing system which can be used to carry out the method of the present invention.
  • a suitable reactor may comprise a reaction chamber 2 which is generally bell-shaped.
  • the chamber 2 has inner walls 4 and outer walls 6 so that water may be circulated between the walls to keep the inner walls 4 cool when the chamber is in use.
  • the top of the chamber 2 is provided with a gas inlet port 8.
  • a disc-shaped gas deflection means 10 Suspended from the top of the chamber is a disc-shaped gas deflection means 10. The gas deflection means 10 is disposed near the top of the chamber so as to direct incoming gases toward the walls of the chamber.
  • the chamber 2 is mounted on a hollow base plate 12 through which cooling water maybe circulated by means of an inlet port 14 and an outlet port 16.
  • a susceptor 20 Rotatably mounted within the chamber 2 on a vertical spindle 18 is a susceptor 20 which may be made of carbon.
  • the susceptor 20 is shaped like a hexagonal truncated prism, and each of its six sloping faces 22 is provided with a ledge 24 on which a semiconductor wafer 26 may be placed for treatment.
  • the spindle I8 is mounted on a vertically disposed shaft 28 housed within a sleeve 30 and provided with a bearing 32.
  • the lower end of the shaft 28 is provided with a pulley 34 which is driven through a belt 36 by a variable speed motor 38.
  • the susceptor 20 is slowly rotated as gases are circulated through the chamber 2.
  • a mixture of reaction gases is delivered to the reaction chamber 2 using the mixing and delivery system 40 as shown in FIG. 2.
  • the invention will be described as applied to deposition of an epitaxial silicon film from a doped mixture of silane and hydrogen.
  • the system 40 includes 3 gas input lines 42, 44 and 46 for delivering a dopant, silane and hydrogen, respectively.
  • the lines 42, 44 and 46 are each provided with gas flow monitoring means 48, 50 and 52, respectively, control valves 54, 56 and 58, respectively, and pressure regulating valves 60, 62 and 64, respectively.
  • the input lines 42, 44 and 46 are all connected through a control valve 66 to one end of a burst chamber 68 which is provided with a pressure gauge 70.
  • the burst chamber is inches long and has a diameter of 2 inches.
  • an outlet orifice 72 Connected to the opposite end of the burst chamber is an outlet orifice 72 of known diameter. In this example, the diameter of the-outlet orifice is 0.050 inch.
  • a control valve 76 Connected into an outlet line 74 from the outlet orifice 72 is a control valve 76.
  • An exhaust line 78 is connected to the outlet line 74 and an exhaust valve 80 controls gas flow through the exhaust line 78.
  • a branch line 82 connects the outlet from control valve 76 to the gas inlet port 8 of the reaction chamber 2 (HO. 1).
  • Another input line 84 connects the single output of a second series of inlet lines (not shown) to the line 84 through a control-valve 86.
  • the above described system may be used to deposit a two-stage composite coating as will now be explained.
  • the burst chamber 68 is made ready for the film growth process by flushing it with the gases to be used.
  • Valves 66 and 80 are opened, valve 76 is closed, and valves 54, 56 and 58 are opened to permit flow of dopant gas from the line 42, silane from the line 44 and hydrogen from the line 46, to the burst chamber 68.
  • Gas flow-rates are controlled so as to admit a mixture having the proportions 100 cc of dopant gas, which comprises hydrogen, having suspended therein 100 p.p.m. of diborane or arsine (depending upon whether p type or n type doping is desired), 5000 cc of 6% silane in hydrogen and 25,000 cc of hydrogen.
  • the susceptor is then heated to l000C by means of rf heating.
  • the susceptpor is also rotated at a speed of 18 rpm.
  • the valve 76 is then opened and the gases from the burst" chamber 68 are suddenly emptied into and through the reaction chamber 2.
  • the gases pass over the heated substrate wafers 26 and begin to deposit an epitaxial layer of silicon thereon.
  • a single crystal layer of silicon approximately 1000 A thick is deposited in l to 1.5 seconds.
  • valve 76 is closed, thus sealing off the burst chamber 68 and its associated piping system from the remainder of the system.
  • the second stage of growth can be continued for as long as desired to produce a desired total thickness of silicon.
  • the slower growth rate may be kept between 0.1 and 0.5 ,um/min and the total film thickness may be 0.5 pm.
  • Both film stages may be doped the same, n type or p type, or one may be doped n type and the other p type.
  • the first stage film may be more highly doped as in this example. In this example, the first stage is doped to about 10 to 10 atoms/cc and the second stage is doped to about 10 atoms/cc.
  • a method of comprising a composite layer of heteroepitaxial silicon on a heated sapphire or spinel substrate comprising:
  • first portion of said layer having a thickness of about 500-2000 A at an average growth rate of about 4-6 am/min and the remainder of said layer at a rate of not more than about 0.5 sm/min.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
US389192A 1973-08-17 1973-08-17 Dual growth rate method of depositing epitaxial crystalline layers Expired - Lifetime US3885061A (en)

Priority Applications (15)

Application Number Priority Date Filing Date Title
US389192A US3885061A (en) 1973-08-17 1973-08-17 Dual growth rate method of depositing epitaxial crystalline layers
IN819/CAL/74A IN141844B (xx) 1973-08-17 1974-04-11
BE143512A BE814071A (fr) 1973-08-17 1974-04-23 Procede de depot de couches epitaxiales a deux vitesses de croissance
GB1906074A GB1459839A (en) 1973-08-17 1974-05-01 Dual growth rate method of depositing epitaxial crystalline layers
IT22445/74A IT1012165B (it) 1973-08-17 1974-05-08 Metodo per depositare epitassialmen te strati cristallini adottando due velocita di accrescimento
DE2422508A DE2422508C3 (de) 1973-08-17 1974-05-09 Verfahren zum epitaktischen Aufwachsen einer kristallinen Schicht
CA199,858A CA1025334A (en) 1973-08-17 1974-05-14 Dual growth rate method of depositing epitaxial crystalline layers
AU68954/74A AU479429B2 (en) 1973-08-17 1974-05-15 Dual growth rate method of depositing epitaxial crystalline layers
JP5529974A JPS547556B2 (xx) 1973-08-17 1974-05-16
CH673774A CH590084A5 (xx) 1973-08-17 1974-05-16
NL7406548A NL7406548A (nl) 1973-08-17 1974-05-16 Werkwijze voor het neerslaan van epitaxiale kristallijne lagen.
SU742025410A SU612610A3 (ru) 1973-08-17 1974-05-16 Способ получени эпитаксиальных слоев кремни
FR7417303A FR2245406B1 (xx) 1973-08-17 1974-05-17
SE7406350A SE401463B (sv) 1973-08-17 1974-07-13 Forfarande for epitaktisk paleggning i tva steg av ett kristallint skikt pa ett upphettat kristallint substrat
YU02236/74A YU39168B (en) 1973-08-17 1974-08-15 Process for the preparation of a palladium catalyst process for the deposition of a combined layer of heteroepitaxial silicon on a heated substrate of sapphire or spine

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Application Number Priority Date Filing Date Title
US389192A US3885061A (en) 1973-08-17 1973-08-17 Dual growth rate method of depositing epitaxial crystalline layers

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US3885061A true US3885061A (en) 1975-05-20

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US389192A Expired - Lifetime US3885061A (en) 1973-08-17 1973-08-17 Dual growth rate method of depositing epitaxial crystalline layers

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US (1) US3885061A (xx)
JP (1) JPS547556B2 (xx)
BE (1) BE814071A (xx)
CA (1) CA1025334A (xx)
CH (1) CH590084A5 (xx)
DE (1) DE2422508C3 (xx)
FR (1) FR2245406B1 (xx)
GB (1) GB1459839A (xx)
IN (1) IN141844B (xx)
IT (1) IT1012165B (xx)
NL (1) NL7406548A (xx)
SE (1) SE401463B (xx)
SU (1) SU612610A3 (xx)
YU (1) YU39168B (xx)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4106959A (en) * 1975-01-02 1978-08-15 Bell Telephone Laboratories, Incorporated Producing high efficiency gallium arsenide IMPATT diodes utilizing a gas injection system
US4201604A (en) * 1975-08-13 1980-05-06 Raytheon Company Process for making a negative resistance diode utilizing spike doping
US4279688A (en) * 1980-03-17 1981-07-21 Rca Corporation Method of improving silicon crystal perfection in silicon on sapphire devices
US4419332A (en) * 1979-10-29 1983-12-06 Licentia Patent-Verwaltungs-G.M.B.H. Epitaxial reactor
US4596208A (en) * 1984-11-05 1986-06-24 Spire Corporation CVD reaction chamber
US4772356A (en) * 1986-07-03 1988-09-20 Emcore, Inc. Gas treatment apparatus and method
US4775641A (en) * 1986-09-25 1988-10-04 General Electric Company Method of making silicon-on-sapphire semiconductor devices
US4838983A (en) * 1986-07-03 1989-06-13 Emcore, Inc. Gas treatment apparatus and method
US4894349A (en) * 1987-12-18 1990-01-16 Kabushiki Kaisha Toshiba Two step vapor-phase epitaxial growth process for control of autodoping
US5010033A (en) * 1987-03-27 1991-04-23 Canon Kabushiki Kaisha Process for producing compound semiconductor using an amorphous nucleation site
US5104690A (en) * 1990-06-06 1992-04-14 Spire Corporation CVD thin film compounds
US5118365A (en) * 1987-03-26 1992-06-02 Canon Kabushiki Kaisha Ii-iv group compound crystal article and process for producing same
USH1145H (en) 1990-09-25 1993-03-02 Sematech, Inc. Rapid temperature response wafer chuck
US5281283A (en) * 1987-03-26 1994-01-25 Canon Kabushiki Kaisha Group III-V compound crystal article using selective epitaxial growth
US5304820A (en) * 1987-03-27 1994-04-19 Canon Kabushiki Kaisha Process for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same
US5425808A (en) * 1987-03-26 1995-06-20 Canon Kabushiki Kaisha Process for selective formation of III-IV group compound film
EP1018758A1 (en) * 1998-06-30 2000-07-12 Sony Corporation Method for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
CN116884832A (zh) * 2023-09-06 2023-10-13 合肥晶合集成电路股份有限公司 半导体器件及其制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU530905B2 (en) * 1977-12-22 1983-08-04 Canon Kabushiki Kaisha Electrophotographic photosensitive member
GB2185758B (en) * 1985-12-28 1990-09-05 Canon Kk Method for forming deposited film
RU2618279C1 (ru) * 2016-06-23 2017-05-03 Акционерное общество "Эпиэл" Способ изготовления эпитаксиального слоя кремния на диэлектрической подложке

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189494A (en) * 1963-08-22 1965-06-15 Texas Instruments Inc Epitaxial crystal growth onto a stabilizing layer which prevents diffusion from the substrate
US3663319A (en) * 1968-11-20 1972-05-16 Gen Motors Corp Masking to prevent autodoping of epitaxial deposits
US3669769A (en) * 1970-09-29 1972-06-13 Ibm Method for minimizing autodoping in epitaxial deposition
US3765960A (en) * 1970-11-02 1973-10-16 Ibm Method for minimizing autodoping in epitaxial deposition

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5113607B2 (xx) * 1971-08-24 1976-05-01

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189494A (en) * 1963-08-22 1965-06-15 Texas Instruments Inc Epitaxial crystal growth onto a stabilizing layer which prevents diffusion from the substrate
US3663319A (en) * 1968-11-20 1972-05-16 Gen Motors Corp Masking to prevent autodoping of epitaxial deposits
US3669769A (en) * 1970-09-29 1972-06-13 Ibm Method for minimizing autodoping in epitaxial deposition
US3765960A (en) * 1970-11-02 1973-10-16 Ibm Method for minimizing autodoping in epitaxial deposition

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4106959A (en) * 1975-01-02 1978-08-15 Bell Telephone Laboratories, Incorporated Producing high efficiency gallium arsenide IMPATT diodes utilizing a gas injection system
US4201604A (en) * 1975-08-13 1980-05-06 Raytheon Company Process for making a negative resistance diode utilizing spike doping
US4419332A (en) * 1979-10-29 1983-12-06 Licentia Patent-Verwaltungs-G.M.B.H. Epitaxial reactor
US4279688A (en) * 1980-03-17 1981-07-21 Rca Corporation Method of improving silicon crystal perfection in silicon on sapphire devices
US4596208A (en) * 1984-11-05 1986-06-24 Spire Corporation CVD reaction chamber
US4772356A (en) * 1986-07-03 1988-09-20 Emcore, Inc. Gas treatment apparatus and method
US4838983A (en) * 1986-07-03 1989-06-13 Emcore, Inc. Gas treatment apparatus and method
US4775641A (en) * 1986-09-25 1988-10-04 General Electric Company Method of making silicon-on-sapphire semiconductor devices
US5425808A (en) * 1987-03-26 1995-06-20 Canon Kabushiki Kaisha Process for selective formation of III-IV group compound film
US5118365A (en) * 1987-03-26 1992-06-02 Canon Kabushiki Kaisha Ii-iv group compound crystal article and process for producing same
US5281283A (en) * 1987-03-26 1994-01-25 Canon Kabushiki Kaisha Group III-V compound crystal article using selective epitaxial growth
US5010033A (en) * 1987-03-27 1991-04-23 Canon Kabushiki Kaisha Process for producing compound semiconductor using an amorphous nucleation site
US5304820A (en) * 1987-03-27 1994-04-19 Canon Kabushiki Kaisha Process for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same
US4894349A (en) * 1987-12-18 1990-01-16 Kabushiki Kaisha Toshiba Two step vapor-phase epitaxial growth process for control of autodoping
US5104690A (en) * 1990-06-06 1992-04-14 Spire Corporation CVD thin film compounds
USH1145H (en) 1990-09-25 1993-03-02 Sematech, Inc. Rapid temperature response wafer chuck
EP1018758A1 (en) * 1998-06-30 2000-07-12 Sony Corporation Method for forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
EP1018758A4 (en) * 1998-06-30 2002-01-02 Sony Corp METHOD FOR PRODUCING A MONOCRISTALLINE SILICONE LAYER AND A SEMICONDUCTOR ARRANGEMENT
US6399429B1 (en) 1998-06-30 2002-06-04 Sony Corporation Method of forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device
CN116884832A (zh) * 2023-09-06 2023-10-13 合肥晶合集成电路股份有限公司 半导体器件及其制作方法
CN116884832B (zh) * 2023-09-06 2023-12-15 合肥晶合集成电路股份有限公司 半导体器件及其制作方法

Also Published As

Publication number Publication date
YU39168B (en) 1984-08-31
DE2422508A1 (de) 1975-03-13
NL7406548A (nl) 1975-02-19
GB1459839A (en) 1976-12-31
FR2245406B1 (xx) 1982-09-24
BE814071A (fr) 1974-08-16
FR2245406A1 (xx) 1975-04-25
JPS5046481A (xx) 1975-04-25
SE401463B (sv) 1978-05-16
IT1012165B (it) 1977-03-10
DE2422508C3 (de) 1979-08-02
SE7406350L (xx) 1975-02-18
YU223674A (en) 1982-05-31
DE2422508B2 (de) 1978-11-23
IN141844B (xx) 1977-04-23
SU612610A3 (ru) 1978-06-25
CH590084A5 (xx) 1977-07-29
CA1025334A (en) 1978-01-31
AU6895474A (en) 1975-11-20
JPS547556B2 (xx) 1979-04-07

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