WO2026016708A1 - 封装体结构及其制备方法、电子设备 - Google Patents

封装体结构及其制备方法、电子设备

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Publication number
WO2026016708A1
WO2026016708A1 PCT/CN2025/101555 CN2025101555W WO2026016708A1 WO 2026016708 A1 WO2026016708 A1 WO 2026016708A1 CN 2025101555 W CN2025101555 W CN 2025101555W WO 2026016708 A1 WO2026016708 A1 WO 2026016708A1
Authority
WO
WIPO (PCT)
Prior art keywords
glass substrate
initial
chip
conductive layer
partition groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/101555
Other languages
English (en)
French (fr)
Inventor
张童龙
李效儒
吴声豪
杜见第
刘思言
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of WO2026016708A1 publication Critical patent/WO2026016708A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P58/00—Singulating wafers or substrates into multiple chips, i.e. dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections

Definitions

  • This application relates to the field of package structure, specifically to a package structure and its preparation method, and electronic devices.
  • package structures typically require cutting a single board into multiple individual boards for assembly into electronic devices.
  • interface delamination easily occurs between the conductive layer and the substrate of the package structure, which may damage the circuit structure of the conductive layer and lead to circuit board failure.
  • the embodiments of this application provide a package structure and its preparation method, as well as an electronic device, which can reduce the number of cracks in the substrate of the package structure and improve the structural stability of the package structure.
  • this application provides a package structure including a glass substrate, a chip, and a conductive layer.
  • the glass substrate has opposing first and second surfaces, and a first side surface connected between the first and second surfaces, the first side surface being convex.
  • the chip is connected to the first surface of the glass substrate, and the chip includes a second side surface, which is disposed on the same side as the first side surface of the glass substrate, and the second side surface is recessed relative to the first side surface.
  • the conductive layer is connected to the second surface of the glass substrate, and the conductive layer includes a third side surface, which is disposed on the same side as the first side surface, and the third side surface is recessed relative to the first side surface.
  • the heat generated during the glass substrate cutting process is basically not transferred to the chip, avoiding interface separation between the chip and the glass substrate.
  • the heat generated during the glass substrate cutting process is basically not transferred to the conductive layer, avoiding interface separation between the conductive layer and the glass substrate, improving the production yield of the package structure, increasing the production efficiency of the package structure, reducing material waste in the production process of the package structure, thereby saving production costs of raw materials, processing energy, and labor.
  • the first side surface includes a first chamfered surface and a second chamfered surface, the first chamfered surface and the second chamfered surface are arranged sequentially along the thickness direction of the glass substrate, and both the first chamfered surface and the second chamfered surface are curved surfaces;
  • the first chamfered surface is smoothly connected to the second chamfered surface, the side of the first chamfered surface away from the second chamfered surface is smoothly connected to the first surface, and the side of the second chamfered surface away from the first chamfered surface is smoothly connected to the second surface.
  • the sharp edges of the glass substrate can be removed by the chamfered surface, thereby avoiding stress concentration at the sharp edges of the glass substrate. This prevents the glass substrate from cracking, breaking, or deforming due to the inability to evenly distribute stress at the sharp edges when subjected to external force.
  • this application also provides a method for preparing a package structure, comprising:
  • An initial package structure includes an initial glass substrate, an initial chip layer and an initial conductive layer, the initial glass substrate has a first surface and a second surface opposite to each other along the thickness direction, the initial chip layer is connected to the first surface and the initial conductive layer is connected to the second surface;
  • the initial chip layer is cut to form a chip, and the cut surface of the chip is the second side surface;
  • the initial conductive layer is cut to form a conductive layer, and the cut surface of the conductive layer is the third side surface.
  • the initial glass substrate is cut to form a glass substrate.
  • the cut surface of the glass substrate is the first side surface, which is connected between the first surface and the second surface.
  • the first side surface is convex.
  • the first side surface of the glass substrate is disposed on the same side as the second side surface of the chip and the third side surface of the conductive layer.
  • the second side surface of the chip is recessed relative to the first side surface of the glass substrate, and the third side surface of the conductive layer is recessed relative to the first side surface of the glass substrate.
  • the initial package structure can be understood as a single-board structure.
  • a larger initial package structure may include multiple smaller package structure regions.
  • the initial package structure needs to be cut into multiple package structures for assembly into electronic devices.
  • the initial chip layer and the initial conductive layer may melt at high temperatures. After structural changes occur in the initial chip layer and the initial conductive layer, they are prone to delamination at the interface with the initial glass substrate. This results in unstable circuit structure in the cut package structure, affecting the accuracy and speed of signal transmission.
  • the initial chip layer and the initial conductive layer can be cut before cutting the initial glass substrate, and the initial chip layer is divided into multiple chips.
  • the initial conductive layer is divided into multiple conductive layers.
  • the separation positions can expose part of the surface of the initial glass substrate.
  • the surface of the initial glass substrate exposed by the separation grooves can be cut directly, so that the chips and conductive layers do not contact the cut positions of the initial glass substrate, avoiding heat transfer from the cut positions of the initial glass substrate to the chips and conductive layers. This also avoids interface separation between the chips and conductive layers and the glass substrate.
  • Improving the production yield of packaging structures, increasing the production efficiency of packaging structures, and reducing the waste of raw materials in the production process of packaging structures can save production costs of raw materials, processing energy, and labor.
  • dicing the initial chip layer to form a chip includes:
  • the initial chip layer is cut to form a first separation groove.
  • the first separation groove penetrates the initial chip layer to expose a portion of the first surface of the initial glass substrate.
  • the first separation groove separates the initial chip layer to form a chip.
  • Cutting the initial conductive layer to form the conductive layer includes:
  • the initial conductive layer is cut to form a second partition groove.
  • the second partition groove penetrates the initial conductive layer to expose a portion of the second surface of the initial glass substrate.
  • the second partition groove separates the initial conductive layer to form a conductive layer.
  • Cutting an initial glass substrate to form a glass substrate includes:
  • a third partition groove is formed by cutting the first surface exposed by the first partition groove, the depth of the third partition groove being less than the thickness of the initial glass substrate;
  • a fourth partition groove is formed by cutting the second surface exposed by the second partition groove.
  • the fourth partition groove is connected to the third partition groove.
  • the third partition groove and the fourth partition groove separate the initial package structure to form the package structure.
  • the glass substrate is cut once on each side.
  • the depth of each cut partition groove (the third partition groove and the fourth partition groove) is less than the initial thickness of the glass substrate.
  • the depth of each cut partition groove (the third partition groove and the fourth partition groove) is greater than half the thickness of the initial glass substrate. Therefore, the cutting speed is relatively fast, and the opening position of the partition groove is subjected to force by the cutting equipment for a shorter time, so cracks are less likely to occur at the opening edge of the partition groove.
  • the preparation method further includes:
  • the wall of the third dividing groove is ground to form the first chamfered surface
  • the walls of the fourth dividing groove are polished to form a second chamfered surface.
  • the walls of the first and third partition grooves are polished to form chamfers, so that the groove walls can be smoothly connected to the two surfaces in the thickness direction of the glass substrate. Polishing can eliminate the initial micro-cracks at the cut edge of the glass substrate.
  • the smooth chamfer structure can reduce stress concentration problems and reduce the risk of glass cracking and crack propagation.
  • the opening width of the third dividing groove on the initial glass substrate surface is smaller than the minimum width of the first dividing groove.
  • the walls of the first and third partition grooves are at a certain distance to provide operating space for the cutting equipment, avoid the cutting equipment from contacting the chip, and prevent the chip from being affected by the pressure of the cutting equipment, thus affecting its structural integrity.
  • the width of the third separator gradually decreases in the direction from the initial chip layer toward the initial glass substrate.
  • the opposite walls of the third partition groove are also the first side surfaces of the two package structures.
  • the gradually decreasing width of the third partition groove ensures that the first side surface can be convex, thereby maximizing the angle between the first side surface and the first surface and avoiding excessively sharp edges on the glass substrate.
  • grinding the wall of the third partition groove to form a first chamfered surface includes:
  • the wall of the third partition groove is polished using methods such as grinding wheels, sandpaper, or wet etching to form a first chamfered surface.
  • forming the third partition groove by recessing the first surface exposed by the first partition groove includes:
  • the third partition groove is formed by recessing the first surface exposed by the first partition groove through methods such as knife cutting, laser cutting, or etching.
  • the depths of both the third and fourth partition grooves are greater than half the thickness of the initial glass substrate.
  • this application also provides an electronic device, including a circuit board and a package structure as described above, wherein the circuit board and the package structure are electrically connected.
  • Figure 1 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application.
  • Figure 2 is a cross-sectional schematic diagram of the package structure shown in Figure 1;
  • Figure 3 is a schematic diagram of the structure of the glass substrate shown in Figure 2;
  • Figure 4 is a flowchart illustrating the first method for preparing the package structure provided in this application embodiment
  • Figure 5 is a cross-sectional view of the structure formed after S100 in the preparation method of the package structure.
  • Figure 6 is a cross-sectional view of the encapsulation structure after S300 in the preparation method of the encapsulation structure
  • Figure 7 is a cross-sectional schematic diagram formed during the S400 process in the preparation method of the package structure
  • Figure 8 is a cross-sectional view of the structure formed after S400 in the preparation method of the package structure
  • Figure 9 is a flowchart illustrating the second method for preparing the package structure provided in the embodiments of this application.
  • Figure 10 is a cross-sectional schematic diagram of the package structure after step S500.
  • Multiple refers to two or more.
  • connection should be interpreted broadly.
  • the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through an intermediary.
  • FIG 1 is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of this application.
  • the electronic device 100 includes a circuit board 10 and a package structure 20 (Printed Circuit Board, PCB).
  • the circuit board 10 and the package structure 20 are electrically connected.
  • the electronic device 100 can be an electronic product such as a computer, network equipment, communication equipment, consumer electronic devices, medical devices, industrial control and automation equipment, automotive electronic products, aerospace equipment, or household appliances. This application does not limit the application scenarios of the electronic device.
  • the circuit board 10 provides electrical connections for the electronic components of the electronic device 100 to realize the circuit functions of the electronic device 100.
  • the main function of the package structure 20 is to house, fix, seal, and protect the chip, as well as ensure the circuit stability of the chip.
  • Figure 2 is a cross-sectional schematic diagram of the package structure 20 shown in Figure 1.
  • the package structure 20 provided in this application can avoid interface delamination between the conductive layer and the glass substrate.
  • the package structure 20 may include a glass substrate 21, a chip 22, and a conductive layer 23.
  • the chip 22 and the conductive layer 23 are respectively connected to opposite sides of the glass substrate 21 in the thickness direction.
  • Figure 2 is intended only to schematically illustrate the connection relationship between the glass substrate 21, the chip 22, and the conductive layer 23, and is not intended to specifically limit the connection positions, specific structures, or quantities of each device.
  • the structures illustrated in the embodiments of this application do not constitute a specific limitation on the package structure 20.
  • the package structure 20 may include more or fewer components than illustrated, or combine certain components, or split certain components, or have different component arrangements.
  • the glass substrate 21 serves as the base structure of the package structure 20, primarily providing support.
  • the glass substrate 21 provides a stable mounting position for the chip 22 within the package structure 20.
  • the glass substrate 21 generally possesses excellent thermal stability and high mechanical strength, maintaining stability under high temperature and high humidity environments, thus reducing the failure rate of electronic components. Simultaneously, the glass substrate 21 can also reduce mutual interference between electronic components, lowering noise and electromagnetic radiation from these components.
  • Figure 3 is a schematic diagram of the structure of the glass substrate 21 shown in Figure 2.
  • the glass substrate 21 includes a first surface 211, a second surface 212, and a first side surface 213.
  • the first surface 211 and the second surface 212 are opposite each other in the thickness direction of the glass substrate 21.
  • the first side surface 213 connects the edge of the first surface 211 and the edge of the second surface 212.
  • the first side surface 213 is convex.
  • the first side surface 213 is the cut side surface of the glass substrate 21 of each package structure 20 after the whole plate is cut into multiple package structures 20.
  • the glass substrate 21 can be approximately rectangular, and two of the four sides of the glass substrate 21 can be cut surfaces. Each cut surface can be convex.
  • each cut surface can be described in the following description of the structure of the first side surface 213.
  • three of the four sides of the glass substrate 21 can be cut surfaces.
  • all sides of the glass substrate 21 can be cut surfaces.
  • one side of the glass substrate 21 can be a cut surface.
  • the position and number of the cut surfaces of the glass substrate 21 can be set according to the cutting method required in the actual production process. This application does not impose specific restrictions on the position and number of the cut surfaces of the glass substrate 21.
  • the first side surface 213 of the glass substrate 21 includes a first chamfered surface 2131 and a second chamfered surface 2132.
  • the first chamfered surface 2131 and the second chamfered surface 2132 are sequentially arranged along the thickness direction of the glass substrate 21, with the first chamfered surface 2131 inclined relative to the second chamfered surface 2132.
  • the included angle between the first chamfered surface 2131 and the second chamfered surface 2132 can be an obtuse angle.
  • the side of the first chamfered surface 2131 away from the second chamfered surface 2132 is connected to the edge of the first surface 211.
  • the included angle between the first chamfered surface 2131 and the first surface 211 can be an obtuse angle.
  • the side of the second chamfered surface 2132 away from the first chamfered surface 2131 is connected to the edge of the second surface 212.
  • the included angle between the second chamfered surface 2132 and the second surface 212 can be an obtuse angle.
  • the glass substrate 21 can remove the sharp edges of the glass substrate 21 by using a chamfered surface, thereby avoiding stress concentration at the sharp edge of the glass substrate 21 and preventing the glass substrate 21 from cracking, breaking or deforming due to the inability to evenly distribute stress at the sharp edge when subjected to external force.
  • the first chamfered surface 2131 and the second chamfered surface 2132 can be curved surfaces.
  • the first chamfered surface 2131 and the second chamfered surface 2132 can be smoothly connected.
  • the first chamfered surface 2131 can be smoothly connected to the first surface 211.
  • the second chamfered surface 2132 can be smoothly connected to the second surface 212.
  • the first chamfered surface 2131 and the second chamfered surface 2132 can be formed by grinding. During the grinding process of the first side surface 213 of the glass substrate 21, cracks generated at the edge of the glass substrate 21 during the cutting process can be removed, preventing crack propagation in the package structure 20 during further high-temperature processing or use, which would affect the structural strength of the package structure 20. At the same time, removing the sharp edges of the glass substrate 21 can also avoid stress concentration at the edge of the glass substrate 21, further improving the structural stability of the glass substrate 21.
  • chip 22 is connected to the first surface 211 of glass substrate 21.
  • Chip 22 includes a second side surface 221.
  • the second side surface 221 is the cut side surface of chip 22 after the whole board is cut into multiple package structures 20.
  • the second side surface 221 of chip 22 is located on the same side of package structure 20 as the first side surface 213, and the second side surface 221 is recessed relative to the first side surface 213.
  • the second side surface 221 is spaced apart from the first chamfered surface 2131.
  • the second side surface 221 of chip 22 is recessed relative to the first side surface 213 of glass substrate 21, which means that glass substrate 21 extends further than chip 22 in the horizontal direction.
  • Chip 22 is connected to the middle region of glass substrate 21, and the edge of chip 22 and glass substrate 21 are a certain distance apart in the horizontal direction.
  • the cutting tool acts on the cutting location of the glass substrate, and the cutting process generally generates heat.
  • the accumulation of heat at the cutting location of the glass substrate leads to localized overheating of the glass substrate.
  • the thermal expansion coefficients of the glass substrate and the chip are different, the chip is prone to melting after being heated, resulting in interface delamination with the glass substrate. This causes instability in the circuit structure of the package structure, affecting the accuracy and speed of signal transmission.
  • the heat generated during the cutting process of the glass substrate 21 is basically not transferred to the chip 22, avoiding interface separation between the chip 22 and the glass substrate 21, improving the production yield of the package structure 20, increasing the production efficiency of the package structure 20, reducing the waste of raw materials in the production process of the package structure 20, thereby saving production costs of raw materials, processing energy and labor.
  • the conductive layer 23 is a metal layer in the package structure 20 used for circuit connection and signal transmission.
  • the conductive layer 23 is connected to the second surface 212 of the glass substrate 21.
  • the conductive layer 23 can be a redistribution layer (RDL) or an electroplated metal layer.
  • the RDL can redistribute the circuitry on the chip 22 to match external connection points.
  • the RDL can achieve complex circuit redistribution to adapt to different packaging requirements.
  • the electroplated metal layer provides reliable electrical connection between the chip 22 and external circuitry.
  • the number and type of conductive layers 23 in this embodiment are merely illustrative. In all other embodiments, the number of conductive layers 23 can be multiple, and the type of conductive layer 23 can be any conductive film structure in the package structure 20.
  • the conductive layer 23 includes a third side surface 231.
  • the third side surface 231 is the cut side surface of the conductive layer 23 after the whole board is cut into multiple package structures 20.
  • the third side surface 231 and the second side surface 221 are located on the same side of the package structure 20, and the third side surface 231 is recessed relative to the second side surface 221.
  • the third side surface 231 and the second chamfered surface 2132 are spaced apart.
  • the heat generated during the cutting process of the glass substrate 21 is basically not transferred to the conductive layer 23, avoiding interface separation between the conductive layer 23 and the glass substrate 21, improving the production yield of the package structure 20, increasing the production efficiency of the package structure 20, reducing the waste of raw materials in the production process of the package structure 20, thereby saving production costs of raw materials, processing energy and labor.
  • FIG 4 is a flowchart illustrating the first method for fabricating the package structure 20 provided in this application embodiment.
  • This application also provides a method for fabricating the package structure 20. This method is used to fabricate the package structure 20 described above.
  • the fabrication method provided in this application embodiment can reduce the occurrence of interface delamination in the package structure 20.
  • the fabrication method includes, but is not limited to, steps S100, S200, S300, S400, and S500. A detailed description of steps S100, S200, S300, S400, and S500 is as follows. Step S100 will be described below with reference to Figure 5, which is a cross-sectional view formed after step S100 in the method for fabricating the package structure 20.
  • the initial package structure 200 includes an initial glass substrate 210, an initial chip layer 220 and an initial conductive layer 230, the initial glass substrate 210 has a first surface 211 and a second surface 212 opposite to each other along the thickness direction, the initial chip layer 220 is connected to the first surface 211 and the initial conductive layer 230 is connected to the second surface 212.
  • Steps S200 and S300 will be described below with reference to Figure 6, which is a cross-sectional view of the package structure 20 after step S300.
  • S200 Cut the initial chip layer 220 to form chip 22, the cut surface of chip 22 is the second side surface 221.
  • cutting the initial chip layer 220 to form the chip 22 includes: cutting the initial chip layer 220 to form a first partition groove 2200, the first partition groove 2200 penetrating the initial chip layer 220 to expose a portion of the first surface 211 of the initial glass substrate 210, and the first partition groove 2200 separating the initial chip layer 220 to form the chip 22.
  • the first separation groove 2200 can be formed on the initial chip layer 220 by means of knife cutting, laser cutting, dry etching or wet etching.
  • S300 Cut the initial conductive layer 230 to form a conductive layer 23, the cut surface of the conductive layer 23 being the third side surface 231.
  • the step of cutting the initial conductive layer 230 to form the conductive layer 23 includes:
  • the initial conductive layer 230 is cut to form a second partition groove 2300.
  • the second partition groove 2300 penetrates the initial conductive layer 230 to expose a portion of the second surface 212 of the initial glass substrate 210.
  • the second partition groove 2300 separates the initial conductive layer 230 to form a conductive layer 23.
  • the second partition groove 2300 can be formed on the initial conductive layer 230 by means of knife cutting, laser cutting, dry etching or wet etching.
  • Step S400 will be described below with reference to Figures 7 and 8.
  • Figure 7 is a cross-sectional view formed during step S400 in the method for fabricating the package structure 20.
  • Figure 8 is a cross-sectional view formed after step S400 in the method for fabricating the package structure 20.
  • S400 Cut the initial glass substrate 210 to form a glass substrate 21.
  • the cut surface of the glass substrate 21 is the first side surface 213.
  • the first side surface 213 is connected between the first surface 211 and the second surface 212.
  • the first side surface 213 is a convex surface.
  • the first side surface 213 of the glass substrate 21 is disposed on the same side as the second side surface 221 of the chip 22 and the third side surface 231 of the conductive layer 23.
  • the second side surface 221 of the chip 22 is recessed relative to the first side surface 213 of the glass substrate 21, and the third side surface 231 of the conductive layer 23 is recessed relative to the first side surface 213 of the glass substrate 21.
  • the step of cutting the initial glass substrate 210 to form the glass substrate 21 includes:
  • a third partition groove 2101 is formed by cutting the first surface 211 exposed by the first partition groove 2200, the depth of the third partition groove 2101 being less than the thickness of the initial glass substrate 210;
  • a fourth partition groove 2102 is formed by cutting the second surface 212 exposed by the second partition groove 2300.
  • the fourth partition groove 2102 communicates with the third partition groove 2101.
  • the third partition groove 2101 and the fourth partition groove 2102 separate the initial package structure 200 to form the package structure 20.
  • the depth of the third dividing groove 2101 is less than the thickness of the initial glass substrate 210.
  • the initial package structure 200 can be understood as a single-board structure.
  • the larger initial package structure 200 may include multiple smaller package structure 20 regions.
  • the initial package structure 200 needs to be cut into multiple package structures 20 for assembly and use by the electronic device 100.
  • the initial chip layer and the initial conductive layer may melt at high temperatures. After structural changes occur in the initial chip layer and the initial conductive layer, they are prone to delamination at the interface with the initial glass substrate. This results in unstable circuit structure in the cut package structure, affecting the accuracy and speed of signal transmission.
  • the initial chip layer 220 and the initial conductive layer 230 can be cut before cutting the initial glass substrate 210.
  • the cut initial chip layer 220 forms a first partition groove 2200, which divides the initial chip layer 220 into multiple chips 22.
  • the initial conductive layer 230 is divided into multiple conductive layers 23 by a second partition groove 2300.
  • the first partition groove 2200 and the second partition groove 2300 can expose a portion of the surface of the initial glass substrate 210.
  • the surface of the initial glass substrate 210 exposed by the partition groove can be cut directly, so that the chips 22 and the conductive layer 23 do not contact the cut position of the initial glass substrate 210, thus avoiding heat transfer from the cut position of the initial glass substrate 210 to the chips 22 and the conductive layer 23. This also prevents interface separation between the chips 22 and the conductive layer 23 and the glass substrate 21.
  • Improve the production yield of the package structure 20 increase the production efficiency of the package structure 20, and reduce the waste of raw materials in the production process of the package structure 20, thereby saving production costs of raw materials, processing energy and labor.
  • the glass substrate 21 is cut once on each side.
  • the depth of the dividing grooves (third dividing groove 2101 and fourth dividing groove 2102) cut in each step is less than the thickness of the initial glass substrate 210.
  • the depth of the dividing grooves (third dividing groove 2101 and fourth dividing groove 2102) cut in each step is greater than half the thickness of the initial glass substrate 210. Therefore, the cutting speed is relatively fast, and the opening position of the dividing groove is subjected to force by the cutting equipment for a shorter time, so cracks are less likely to occur at the opening edge of the dividing groove.
  • S400 Cut the initial glass substrate 210 to form a glass substrate 21.
  • the cut surface of the glass substrate 21 is the first side surface 213.
  • the first side surface 213 is connected between the first surface 211 and the second surface 212.
  • the first side surface 213 is a convex surface.
  • the first side surface 213 of the glass substrate 21 is disposed on the same side as the second side surface 221 of the chip 22 and the third side surface 231 of the conductive layer 23.
  • the second side surface 221 of the chip 22 is recessed relative to the first side surface 213 of the glass substrate 21, and the third side surface 231 of the conductive layer 23 is recessed relative to the first side surface 213 of the glass substrate 21.
  • the step of cutting the initial glass substrate 210 to form the glass substrate 21 includes:
  • a third partition groove 2101 is formed by cutting the first surface 211 exposed by the first partition groove 2200, the depth of the third partition groove 2101 being less than the thickness of the initial glass substrate 210;
  • a fourth partition groove 2102 is formed by cutting the second surface 212 exposed by the second partition groove 2300.
  • the fourth partition groove 2102 communicates with the third partition groove 2101.
  • the third partition groove 2101 and the fourth partition groove 2102 separate the initial package structure 200 to form the package structure 20.
  • the opening width of the third partition groove 2101 on the surface of the initial glass substrate 210 is smaller than the minimum width of the first partition groove 2200.
  • the width of the third partition groove 2101 gradually decreases in the direction from the initial chip layer 220 toward the initial glass substrate 210.
  • the third partition groove 2101 can be formed on the initial glass substrate 210 by methods such as knife cutting, laser cutting, dry etching, or wet etching.
  • the cutting position of the initial glass substrate 210 is at a certain distance from the chip 22, thereby further preventing the heat of the initial glass substrate 210 from being transferred to the chip 22 during the cutting process, and preventing the chip 22 from melting and separating from the glass substrate 210 at the interface.
  • the gradually decreasing width of the third dividing groove 2101 can make the angle between the groove wall of the third dividing groove 2101 and the surface of the glass substrate 21 larger, thus avoiding sharp corners on the glass substrate 21. This prevents stress concentration at the sharp edges of the glass substrate 21 and avoids the glass substrate 21 from cracking, breaking, or plastic deformation due to the inability to evenly distribute stress at the sharp edges when subjected to external force.
  • the fourth partition groove 2102 can be formed on the initial glass substrate 210 by methods such as knife cutting, laser cutting, dry etching, or wet etching.
  • the depth of the fourth partition groove 2102 is less than the thickness of the initial glass substrate 210.
  • the depth of the fourth partition groove 2102 can be greater than half the thickness of the initial glass substrate 210.
  • the opening width of the fourth partition groove 2102 on the surface of the initial glass substrate 210 is smaller than the minimum width of the second partition groove 2300.
  • the width of the fourth partition groove 2102 gradually decreases in the direction from the initial chip layer 220 toward the initial glass substrate 210.
  • Figure 9 is a schematic flowchart of the second preparation method of the package structure 20 provided in the embodiment of this application.
  • the contents that are the same as those in the first preparation method will not be repeated.
  • the difference between the first preparation method and the first preparation method is that, in addition to S100, S200, S300 and S400, the preparation method of the package structure 20 may also include at least S500, which is described in detail below.
  • Step S500 will be described below with reference to Figure 10, which is a cross-sectional view of the preparation method of the package structure 20 after step S500.
  • S500 Grind the wall of the third partition groove 2101 to form a first chamfered surface 2131, and grind the wall of the fourth partition groove 2102 to form a second chamfered surface 2132.

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  • Dicing (AREA)
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Abstract

本申请提供一种封装体结构及其制备方法、电子设备。封装体结构包括玻璃基板、芯片和导电层。玻璃基板具有相对的第一表面和第二表面、及连接于第一表面和第二表面之间的第一侧面，第一侧面为凸面。芯片连接于玻璃基板的第一表面，芯片包括第二侧面，芯片的第二侧面与玻璃基板的第一侧面同侧设置，第二侧面相对第一侧面凹陷。导电层连接于玻璃基板的第二表面，导电层包括第三侧面，第三侧面与第一侧面同侧设置，第三侧面相对第一侧面凹陷。本申请实施例能够避免导电层与玻璃基板之间发生分层，提高封装体结构的加工可靠性。

Description

封装体结构及其制备方法、电子设备
本申请要求在2024年07月16日提交中国国家知识产权局、申请号为202410955029.9的中国专利申请的优先权，发明名称为“封装体结构及其制备方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及封装体结构领域，具体涉及一种封装体结构及其制备方法、电子设备。
背景技术
封装体结构在制备过程中一般需要将整板切割为多个单板以供电子设备装配。目前，封装体结构在切割过程中，封装体结构的导电层和基板之间容易发生界面分层，从而可能导致导电层的电路结构被破坏，致使电路板失效。
发明内容
本申请的实施例提供一种封装体结构及其制备方法、电子设备，能够较少封装体结构的基板的裂纹，提高封装体结构的结构稳定性。
第一方面，本申请提供一种封装体结构，包括玻璃基板、芯片和导电层。玻璃基板具有相对的第一表面和第二表面、及连接于第一表面和第二表面之间的第一侧面，第一侧面为凸面。芯片连接于玻璃基板的第一表面，芯片包括第二侧面，芯片的第二侧面与玻璃基板的第一侧面同侧设置，第二侧面相对第一侧面凹陷。导电层连接于玻璃基板的第二表面，导电层包括第三侧面，第三侧面与第一侧面同侧设置，第三侧面相对第一侧面凹陷。
在本实施例中，在水平方向上，芯片的第二侧面与玻璃基板的第一侧面之间具有一定距离。因此，在玻璃基板切割的过程中产生的热量基本不会传递至芯片，避免芯片与玻璃基板之间发生界面分离。在水平方向上，导电层的第三侧面与玻璃基板的第二侧面之间具有一定距离。因此，在玻璃基板切割的过程中产生的热量基本不会传递至导电层，避免导电层与玻璃基板之间发生界面分离，提升封装体结构的生产良率，提高封装体结构的生产效率，减少封装体结构在生产过程中的原料浪费，从而节省原料、加工能源和人工的生产成本。
一种可能的实施方式中，第一侧面包括第一倒角面和第二倒角面，第一倒角面与第二倒角面沿玻璃基板的厚度方向依次设置，第一倒角面与第二倒角面均为弧面；
第一倒角面与第二倒角面平滑连接，第一倒角面背离第二倒角面的一侧与第一表面的平滑连接，第二倒角面背离第一倒角面的一侧与第二表面平滑连接。
在本实施例中，玻璃基板通过倒角面可以去除玻璃基板的尖锐边缘，从而避免在玻璃基板的尖锐的边缘位置处出现应力集中，避免玻璃基板在受到外力时，尖锐的边缘处无法均匀分散应力而导致玻璃基板的结构出现裂纹、断裂或者塑形变形等情况。
第二方面，本申请还提供一种封装体结构的制备方法，包括：
提供初始封装体结构，初始封装体结构包括初始玻璃基板、初始芯片层和初始导电层，初始玻璃基板具有沿厚度方向相对的第一表面和第二表面，初始芯片层连接于第一表面，初始导电层连接于第二表面；
切割初始芯片层以形成芯片，芯片的切割面为第二侧面；
切割初始导电层以形成导电层，导电层的切割面为第三侧面；
切割初始玻璃基板以形成玻璃基板，玻璃基板的切割面为第一侧面，第一侧面连接于第一表面与第二表面之间，第一侧面为凸面，玻璃基板的第一侧面与芯片的第二侧面、导电层的第三侧面同侧设置，芯片的第二侧面相对玻璃基板的第一侧面凹陷，导电层的第三侧面相对玻璃基板的第一侧面凹陷。
在本实施例中，初始封装体结构可以理解为整板结构。面积较大的初始封装体结构可以包括多个面积较小的封装体结构区域。初始封装体结构在加工过程中，需要将初始封装体结构进行切割，以分割为多个封装体结构，从而供电子设备装配使用。
初始封装体结构在切割过程中，切割设备与初始封装体结构的切割位置会累积大量的热量，由于初始芯片层、初始导电层与初始玻璃基板的热膨胀系数不同，在高温下，初始芯片层和初始导电层可能会发生熔融，初始芯片层、初始导电层发生结构变化后容易与初始玻璃基板发生界面分层。致使切割后的封装体结构的电路结构不稳定，影响信号传输的准确性和速度。
本申请实施例提供的封装体结构的制备方法中，可以在切割初始玻璃基板之前，对初始芯片层和初始导电层进行切割，初始芯片层被分隔为多个芯片。初始导电层被分隔为多个导电层。分隔位置可以暴露部分初始玻璃基板的表面。切割初始玻璃基板的过程中，可以直接对分隔槽暴露的初始玻璃基板的表面进行切割，以使芯片和导电层不接触初始玻璃基板的切割位置，避免初始玻璃基板的切割位置的热量传递至芯片和导电层。避免芯片和导电层与玻璃基板之间发生界面分离。
提升封装体结构的生产良率，提高封装体结构的生产效率，减少封装体结构在生产过程中的原料浪费，从而节省原料、加工能源和人工的生产成本。
一种可能的实施方式中，切割初始芯片层以形成芯片包括：
切割初始芯片层，形成第一分隔槽，第一分隔槽贯穿初始芯片层，以暴露部分初始玻璃基板的第一表面，第一分隔槽将初始芯片层分隔形成芯片；
切割初始导电层以形成导电层包括：
切割初始导电层，形成第二分隔槽，第二分隔槽贯穿初始导电层，以暴露部分初始玻璃基板的第二表面，第二分隔槽将初始导电层分隔形成导电层；
切割初始玻璃基板以形成玻璃基板包括：
在第一分隔槽暴露的第一表面切割形成第三分隔槽，第三分隔槽的深度小于初始玻璃基板的厚度；及
在第二分隔槽暴露的第二表面切割形成第四分隔槽，第四分隔槽与第三分隔槽连通，第三分隔槽和第四分隔槽将初始封装体结构分隔，以形成封装体结构。
在本申请实施例中，玻璃基板的两侧各进行一次切割。每次切割的分隔槽(第三分隔槽和第四分隔槽)的深度小于初始玻璃基板的厚度。示例性的，每次切割的分隔槽(第三分隔槽和第四分隔槽)的深度大于初始玻璃基板的一半厚度。因此，每次切割过程的速度较快，分隔槽的开口位置被切割设备的受力时间较短，因此分隔槽的开口棱边处不易产生裂痕。
一种可能的实施方式中，制备方法还包括：
对第三分隔槽的槽壁进行打磨，以形成第一倒角面；及
对第四分隔槽的槽壁进行打磨，以形成第二倒角面。
在本实施例中，对第一分隔槽的槽壁和第三分隔槽的槽壁进行打磨形成倒角，以使槽壁可以与玻璃基板厚度方向的两个表面平滑连接，并且打磨可以消除玻璃基板的切割边缘的初始细微裂纹，平滑倒角结构可降低应力集中问题，降低玻璃开裂及裂纹扩展风险。
一种可能的实施方式中，第三分隔槽在初始玻璃基板表面的开口宽度小于第一分隔槽的最小宽度。
在本实施例中，第一分隔槽与第三分隔槽的槽壁具有一定距离，以为切割设备工作提供操作空间，避免切割设备接触芯片，防止芯片受到切割设备的压力而影响结构完整性。
一种可能的实施方式中，在初始芯片层朝向初始玻璃基板的方向上，第三分隔槽的宽度逐渐减小。
在本实施例中，第三分隔槽两侧相对的槽壁也即为两个封装体结构的第一侧面。第三分隔槽的宽度逐渐减小可以保证第一侧面可以为凸面，从而尽量增加第一侧面与第一表面的夹角，避免玻璃基板边缘的棱角过于尖锐。
一种可能的实施方式中，对第三分隔槽的槽壁进行打磨，以形成第一倒角面包括：
通过砂轮、砂纸或者湿法刻蚀等方法对第三分隔槽的槽壁进行打磨，以形成第一倒角面。一种可能的实施方式中，在第一分隔槽暴露的第一表面凹陷形成第三分隔槽包括：
通过刀切、激光切割或者刻蚀的方法在第一分隔槽暴露的第一表面凹陷形成第三分隔槽。
一种可能的实施方式中，第三分隔槽和第四分隔槽的深度均大于初始玻璃基板的一半厚度。
第三方面，本申请还提供一种电子设备，包括电路板和如上所述的封装体结构，电路板与封装体结构电连接。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本申请实施例提供的电子设备的结构示意图；
图2是图1所示的封装体结构的截面示意图；
图3是图2所示的玻璃基板的结构示意图；
图4是本申请实施例提供的封装体结构的第一种制备方法的流程示意图；
图5是封装体结构的制备方法中S100后形成的剖面示意图；
图6是封装体结构的制备方法中S300后形成的剖面示意图；
图7是封装体结构的制备方法中S400过程中形成的剖面示意图；
图8是封装体结构的制备方法中S400后形成的剖面示意图；
图9是本申请实施例提供的封装体结构的第二种制备方法的流程示意图；
图10是封装体结构的制备方法的S500后形成的剖面示意图。
具体实施方式
下面将参照附图更详细地描述本申请的具体实施方式。虽然附图中显示了本申请的示例性实施方式，但应当理解的是，还可以采用不同于在此描述的其他方式来实施本申请，因此，本申请不受下面这些实施方式的限制。
为了方便理解，首先对本申请的实施例所涉及的术语进行解释。
多个：是指两个或多于两个。
连接：应做广义理解，例如，A与B连接，可以是A与B直接相连，也可以是A与B通过中间媒介间接相连。
下面将结合附图，对本申请的具体实施方式进行清楚地描述。
请参阅图1，图1是本申请实施例提供的电子设备100的结构示意图。电子设备100包括电路板10和封装体结构20(Printed Circuit Board，PCB)。电路板10与封装体结构20电连接。
其中，电子设备100可以为计算机等电子产品、网络设备、通信设备、消费电子设备、医疗设备、工业控制和自动化设备、汽车电子产品、航空航天设备或家用电器等。本申请不对电子设备的使用场景进行限制。
电路板10可以为电子设备100的电子元器件提供电气连接，以实现电子设备100的电路功能。封装体结构20的主要作用是安放、固定、密封、保护芯片，以及确保芯片的电路稳定性。
在常规的封装体结构的生产过程中，一般在一块整板上预设数个或数十个封装体结构单体区域，对整板进行切割，以使整板切割为多个封装体结构，每一封装体结构可供电子设备装配使用。但在切割整板的过程中，封装体结构的导电层和玻璃基板之间容易发生界面分层，从而可能导致导电层的电路结构被破坏，致使封装体结构失效。
基于此，请参阅图2，图2是图1所示的封装体结构20的截面示意图。本申请提供的封装体结构20可以避免导电层与玻璃基板之间发生界面分层。
封装体结构20可以包括玻璃基板21、芯片22和导电层23。芯片22和导电层23分别连接于玻璃基板21厚度方向的相背两侧。
需说明的是，图2的目的仅在于示意性的描述玻璃基板21、芯片22和导电层23的连接关系，并非是对各个设备的连接位置、具体构造及数量做具体限定。而本申请实施例示意的结构并不构成对封装体结构20的具体限定。在本申请另一些实施例中，封装体结构20可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。
在本实施例中，玻璃基板21作为封装体结构20的底板结构，主要提供支撑作用。玻璃基板21可以为封装体结构20的芯片22提供稳定安装位置。玻璃基板21一般具有优异的热稳定性和较高机械强度，能够在高温和高湿度环境下保持稳定性，降低电子元器件的故障率。同时，玻璃基板21还可以减少电子元器件之间的相互干扰，降低电子元器件的噪声和电磁辐射等。
请结合参阅图2和图3，图3是图2所示的玻璃基板21的结构示意图。玻璃基板21包括第一表面211、第二表面212和第一侧面213。第一表面211和第二表面212在玻璃基板21的厚度方向上相对。第一侧面213连接于第一表面211的边缘与第二表面212边缘。第一侧面213为凸面。其中，第一侧面213为整板切割为多个封装体结构20后，每一封装体结构20的玻璃基板21的切割侧面。玻璃基板21可以大致为矩形，玻璃基板21的四个侧面中，可以有二个侧面为切割面。每一切割面均可以为凸面。每一切割面的结构可以参见下文对第一侧面213的结构描述。或者玻璃基板21的四个侧面中，可以有三个侧面为切割面。再或者，玻璃基板21的侧面可以均为切割面。又或者，玻璃基板21的侧面可以有一个切割面。玻璃基板21的切割面的位置和数量可以根据实际生产过程中所需的切割方式进行设置，本申请不对玻璃基板21的切割面的位置和数量进行具体限制。
玻璃基板21的第一侧面213包括第一倒角面2131和第二倒角面2132。第一倒角面2131与第二倒角面2132沿玻璃基板21的厚度方向依次设置，第一倒角面2131相对第二倒角面2132倾斜。第一倒角面2131和第二倒角面2132之间的夹角可以为钝角。第一倒角面2131远离第二倒角面2132的一侧与第一表面211的边缘连接。第一倒角面2131和第一表面211之间的夹角可以为钝角。第二倒角面2132远离第一倒角面2131的一侧与第二表面212的边缘连接。第二倒角面2132和第二表面212之间的夹角可以为钝角。
在本实施例中，玻璃基板21通过倒角面可以去除玻璃基板21的尖锐边缘，从而避免在玻璃基板21的尖锐的边缘位置处出现应力集中，避免玻璃基板21在受到外力时，尖锐的边缘处无法均匀分散应力而导致玻璃基板21的结构出现裂纹、断裂或者塑形变形等情况。
在一些可能的实施例中，第一倒角面2131和第二倒角面2132可以弧面。第一倒角面2131和第二倒角面2132可以平滑过渡连接。第一倒角面2131与第一表面211可以平滑过渡连接。第二倒角面2132可以与第二表面212平滑过渡连接。
第一倒角面2131和第二倒角面2132可以通过打磨的方式形成。在对玻璃基板21的第一侧面213打磨的过程中，可以去除玻璃基板21边缘在切割过程中产生的裂纹，防止封装体结构20在进一步高温加工或者使用过程中，出现裂纹扩展进而影响封装体结构20的结构强度。同时去除玻璃基板21边缘存在的棱角，还可以避免玻璃基板21边缘出现应力集中，进一步提高玻璃基板21的结构稳定性。
请再参阅图2，芯片22连接于玻璃基板21的第一表面211。芯片22包括第二侧面221。第二侧面221为整板切割为多个封装体结构20后，芯片22的切割侧面。芯片22的第二侧面221与第一侧面213位于封装体结构20的同一侧，第二侧面221相对第一侧面213凹陷设置。第二侧面221与第一倒角面2131间隔设置。其中，芯片22的第二侧面221相对玻璃基板21的第一侧面213凹陷是指玻璃基板21在水平方向比芯片22延伸的更远。芯片22连接于玻璃基板21的中间区域，芯片22与玻璃基板21的边缘在水平方向上具有一定距离。
目前在玻璃基板切割的过程中，切割器具作用于玻璃基板的切割位置，切割过程一般会产生热量。热量在玻璃基板的切割位置累积导致玻璃基板的局部过热，由于玻璃基板与芯片的热膨胀系数不同，因此，芯片容易在受热后可能熔融而与玻璃基板产生界面分层，致使封装体结构的电路结构不稳定，影响信号传输的准确性和速度。
在本实施例中，在水平方向上，芯片22的第二侧面221与玻璃基板21的第一侧面213之间具有一定距离。因此，在玻璃基板21切割的过程中产生的热量基本不会传递至芯片22，避免芯片22与玻璃基板21之间发生界面分离，提升封装体结构20的生产良率，提高封装体结构20的生产效率，减少封装体结构20在生产过程中的原料浪费，从而节省原料、加工能源和人工的生产成本。
导电层23是封装体结构20中用于实现电路连接和信号传输的金属层。导电层23连接于玻璃基板21的第二表面212。示例性的，导电层23可以为重分布层(Redistribution Layer，RDL)或电镀金属层。RDL能够重新布线芯片22上的电路，使之与外部连接点匹配。RDL可以实现复杂的电路重布线，以适应不同的封装需求。电镀金属层用于供芯片22与外部电路进行可靠的电气连接。需要说明的是，本申请实施例中的导电层23的数量和种类仅为示意性说明。在一切其他的实施例中，导电层23的数量可以为多个，导电层23的种类可以为封装体结构20中的任意起导电作用的膜层结构。
导电层23包括第三侧面231。第三侧面231为整板切割为多个封装体结构20后，导电层23的切割侧面。第三侧面231与第二侧面221位于封装体结构20的同一侧，第三侧面231相对第二侧面221凹陷设置。第三侧面231与第二倒角面2132间隔设置。
在本实施例中，在水平方向上，导电层23的第三侧面231与玻璃基板21的第二侧面221之间具有一定距离。因此，在玻璃基板21切割的过程中产生的热量基本不会传递至导电层23，避免导电层23与玻璃基板21之间发生界面分离，提升封装体结构20的生产良率，提高封装体结构20的生产效率，减少封装体结构20在生产过程中的原料浪费，从而节省原料、加工能源和人工的生产成本。
请参阅图4，图4是本申请实施例提供的封装体结构20的第一种制备方法的流程示意图。本申请还提供一种封装体结构20的制备方法。该方法用于制备上文所述封装体结构20。本申请实施例提供的制备方法能够减少封装体结构20出现界面分层的情况。所述制备方法包括但不限于步骤S100、S200、S300、S400和S500，关于步骤S100、S200、S300、S400和S500的详细描述如下。以下将结合图5来描述步骤S100，图5是封装体结构20的制备方法中S100后形成的剖面示意图。
S100：提供初始封装体结构200，初始封装体结构200包括初始玻璃基板210、初始芯片层220和初始导电层230，初始玻璃基板210具有沿厚度方向相对的第一表面211和第二表面212，初始芯片层220连接于第一表面211，初始导电层230连接于第二表面212。
以下将结合图6来描述步骤S200和S300，图6是封装体结构20的制备方法中S300后形成的剖面示意图。
S200：切割初始芯片层220以形成芯片22，芯片22的切割面为第二侧面221。
具体而言，切割初始芯片层220以形成芯片22包括：切割初始芯片层220，形成第一分隔槽2200，第一分隔槽2200贯穿初始芯片层220，以暴露部分初始玻璃基板210的第一表面211，第一分隔槽2200将初始芯片层220分隔形成芯片22。
其中，可以通过刀切、激光切割、干法刻蚀或湿法刻蚀等方式在初始芯片层220上形成第一分隔槽2200。
S300：切割初始导电层230以形成导电层23，导电层23的切割面为第三侧面231。
其中，切割初始导电层230以形成导电层23包括：
切割初始导电层230，形成第二分隔槽2300，第二分隔槽2300贯穿初始导电层230，以暴露部分初始玻璃基板210的第二表面212，第二分隔槽2300将初始导电层230分隔形成导电层23。
其中，可以通过刀切、激光切割、干法刻蚀或湿法刻蚀等方式在初始导电层230上形成第二分隔槽2300。
以下将结合图7和图8来描述步骤S400，图7是封装体结构20的制备方法中S400过程中形成的剖面示意图。图8是封装体结构20的制备方法中S400后形成的剖面示意图。
S400：切割初始玻璃基板210以形成玻璃基板21，玻璃基板21的切割面为第一侧面213，第一侧面213连接于第一表面211与第二表面212之间，第一侧面213为凸面，玻璃基板21的第一侧面213与芯片22的第二侧面221、导电层23的第三侧面231同侧设置，芯片22的第二侧面221相对玻璃基板21的第一侧面213凹陷，导电层23的第三侧面231相对玻璃基板21的第一侧面213凹陷。
其中，切割初始玻璃基板210以形成玻璃基板21包括：
在第一分隔槽2200暴露的第一表面211切割形成第三分隔槽2101，第三分隔槽2101的深度小于初始玻璃基板210的厚度；及
在第二分隔槽2300暴露的第二表面212切割形成第四分隔槽2102，第四分隔槽2102与第三分隔槽2101连通，第三分隔槽2101和第四分隔槽2102将初始封装体结构200分隔，以形成封装体结构20。
其中，第三分隔槽2101的深度小于初始玻璃基板210的厚度。
在本实施例中，初始封装体结构200可以理解为整板结构。面积较大的初始封装体结构200可以包括多个面积较小的封装体结构20区域。初始封装体结构200在加工过程中，需要将初始封装体结构200进行切割，以分割为多个封装体结构20，从而供电子设备100装配使用。
初始封装体结构在切割过程中，切割设备与初始封装体结构的切割位置会累积大量的热量，由于初始芯片层、初始导电层与初始玻璃基板的热膨胀系数不同，在高温下，初始芯片层和初始导电层可能会发生熔融，初始芯片层、初始导电层发生结构变化后容易与初始玻璃基板发生界面分层。致使切割后的封装体结构的电路结构不稳定，影响信号传输的准确性和速度。
本申请实施例提供的封装体结构20的制备方法中，可以在切割初始玻璃基板210之前，对初始芯片层220和初始导电层230进行切割，切割后的初始芯片层220形成第一分隔槽2200，初始芯片层220被第一分隔槽2200分隔为多个芯片22。初始导电层230被第二分隔槽2300分隔为多个导电层23。第一分隔槽2200和第二分隔槽2300可以暴露部分初始玻璃基板210的表面。切割初始玻璃基板210的过程中，可以直接对分隔槽暴露的初始玻璃基板210的表面进行切割，以使芯片22和导电层23不接触初始玻璃基板210的切割位置，避免初始玻璃基板210的切割位置的热量传递至芯片22和导电层23。避免芯片22和导电层23与玻璃基板21之间发生界面分离。
提升封装体结构20的生产良率，提高封装体结构20的生产效率，减少封装体结构20在生产过程中的原料浪费，从而节省原料、加工能源和人工的生产成本。
本申请实施例对玻璃基板21的两侧各进行一次切割。每次切割的分隔槽(第三分隔槽2101和第四分隔槽2102)的深度小于初始玻璃基板210的厚度。示例性的，每次切割的分隔槽(第三分隔槽2101和第四分隔槽2102)的深度大于初始玻璃基板210的一半厚度。因此，每次切割过程的速度较快，分隔槽的开口位置被切割设备的受力时间较短，因此分隔槽的开口棱边处不易产生裂痕。
以下将对各个步骤分别进行进一步的描述。
S400：切割初始玻璃基板210以形成玻璃基板21，玻璃基板21的切割面为第一侧面213，第一侧面213连接于第一表面211与第二表面212之间，第一侧面213为凸面，玻璃基板21的第一侧面213与芯片22的第二侧面221、导电层23的第三侧面231同侧设置，芯片22的第二侧面221相对玻璃基板21的第一侧面213凹陷，导电层23的第三侧面231相对玻璃基板21的第一侧面213凹陷。
其中，切割初始玻璃基板210以形成玻璃基板21包括：
在第一分隔槽2200暴露的第一表面211切割形成第三分隔槽2101，第三分隔槽2101的深度小于初始玻璃基板210的厚度；及
在第二分隔槽2300暴露的第二表面212切割形成第四分隔槽2102，第四分隔槽2102与第三分隔槽2101连通，第三分隔槽2101和第四分隔槽2102将初始封装体结构200分隔，以形成封装体结构20。具体而言，第三分隔槽2101在初始玻璃基板210表面的开口宽度小于第一分隔槽2200的最小宽度。在初始芯片层220朝向初始玻璃基板210的方向上，第三分隔槽2101的宽度逐渐减小。其中，可以通过刀切、激光切割、干法刻蚀或湿法刻蚀等方式在初始玻璃基板210上形成第三分隔槽2101。
在本实施例中，切割初始玻璃基板210的过程中，初始玻璃基板210的切割位置与芯片22具有一定间隔，从而进一步避免初始玻璃基板210在切割过程中的热量传递至芯片22，避免芯片22发生熔融而与玻璃基板21发生界面分离。
第三分隔槽2101的宽度逐渐减小可以使第三分隔槽2101的槽壁与玻璃基板21的表面形成的夹角角度较大，避免玻璃基板21出现较为尖锐的尖角，从而避免在玻璃基板21尖锐的边缘位置处出现应力集中，避免玻璃基板21在受到外力时，尖锐的边缘处无法均匀分散应力而导致玻璃基板21的结构出现裂纹、断裂或者塑性变形等情况。
可以通过刀切、激光切割、干法刻蚀或湿法刻蚀等方式在初始玻璃基板210上形成第四分隔槽2102。第四分隔槽2102的深度小于初始玻璃基板210的厚度。示例性的，第四分隔槽2102的深度可以大于初始玻璃基板210的厚度的一半。
第四分隔槽2102在初始玻璃基板210表面的开口宽度小于第二分隔槽2300的最小宽度。在初始芯片层220朝向初始玻璃基板210的方向上，第四分隔槽2102的宽度逐渐减小。
请参阅图9，图9是本申请实施例提供的封装体结构20的第二种制备方法的流程示意图。与前述第一种制备方法相同的内容不再赘述，与第一种制备方法不同的是，封装体结构20的制备方法除S100、S200、S300和S400外，至少还可以包括S500，详细描述如下。
以下将结合图10来描述步骤S500，图10是封装体结构20的制备方法的S500后形成的剖面示意图。
S500：对第三分隔槽2101的槽壁进行打磨，以形成第一倒角面2131，对第四分隔槽2102的槽壁进行打磨，以形成第二倒角面2132。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种封装体结构，其特征在于，包括：
    玻璃基板，具有相对的第一表面和第二表面、及连接于所述第一表面和所述第二表面之间的第一侧面，所述第一侧面为凸面；
    芯片，连接于所述玻璃基板的第一表面，所述芯片包括第二侧面，所述芯片的第二侧面与所述玻璃基板的第一侧面同侧设置，所述第二侧面相对所述第一侧面凹陷；
    导电层，连接于所述玻璃基板的第二表面，所述导电层包括第三侧面，所述导电层的第三侧面与所述玻璃基板的第一侧面同侧设置，所述第三侧面相对所述第一侧面凹陷。
  2. 根据权利要求1所述的封装体结构，其特征在于，所述第一侧面包括第一倒角面和第二倒角面，所述第一倒角面与所述第二倒角面沿所述玻璃基板的厚度方向依次设置，所述第一倒角面与所述第二倒角面均为弧面；
    所述第一倒角面与所述第二倒角面平滑连接，所述第一倒角面背离所述第二倒角面的一侧与所述第一表面的平滑连接，所述第二倒角面背离所述第一倒角面的一侧与所述第二表面平滑连接。
  3. 一种封装体结构的制备方法，其特征在于，包括：
    提供初始封装体结构，所述初始封装体结构包括初始玻璃基板、初始芯片层和初始导电层，所述初始玻璃基板具有沿厚度方向相对的第一表面和第二表面，所述初始芯片层连接于所述第一表面，所述初始导电层连接于所述第二表面；
    切割所述初始芯片层以形成芯片，所述芯片的切割面为第二侧面；
    切割所述初始导电层以形成导电层，所述导电层的切割面为第三侧面；
    切割所述初始玻璃基板以形成玻璃基板，所述玻璃基板的切割面为第一侧面，所述第一侧面连接于所述第一表面与所述第二表面之间，所述第一侧面为凸面，所述玻璃基板的第一侧面与所述芯片的第二侧面、所述导电层的第三侧面同侧设置，所述芯片的第二侧面相对所述玻璃基板的第一侧面凹陷，所述导电层的第三侧面相对所述玻璃基板的第一侧面凹陷。
  4. 根据权利要求3所述的封装体结构的制备方法，其特征在于，所述切割所述初始芯片层以形成芯片包括：
    切割所述初始芯片层，形成第一分隔槽，所述第一分隔槽贯穿所述初始芯片层，以暴露部分所述初始玻璃基板的第一表面，所述第一分隔槽将所述初始芯片层分隔形成芯片；
    所述切割所述初始导电层以形成导电层包括：
    切割所述初始导电层，形成第二分隔槽，所述第二分隔槽贯穿所述初始导电层，以暴露部分所述初始玻璃基板的第二表面，所述第二分隔槽将所述初始导电层分隔形成导电层；
    所述切割所述初始玻璃基板以形成玻璃基板包括：
    在所述第一分隔槽暴露的所述第一表面切割形成第三分隔槽，所述第三分隔槽的深度小于所述初始玻璃基板的厚度；及
    在所述第二分隔槽暴露的所述第二表面切割形成第四分隔槽，所述第四分隔槽与所述第三分隔槽连通，所述第三分隔槽和所述第四分隔槽将所述初始封装体结构分隔，以形成所述封装体结构。
  5. 根据权利要求4所述的封装体结构的制备方法，其特征在于，所述制备方法还包括：
    对所述第三分隔槽的槽壁进行打磨，以形成第一倒角面；及
    对所述第四分隔槽的槽壁进行打磨，以形成第二倒角面。
  6. 根据权利要求4或5所述的制备方法，其特征在于，所述第三分隔槽在所述初始玻璃基板表面的开口宽度小于所述第一分隔槽的最小宽度。
  7. 根据权利要求6所述的制备方法，其特征在于，在所述初始芯片层朝向所述初始玻璃基板的方向上，所述第三分隔槽的宽度逐渐减小。
  8. 根据权利要求7所述的制备方法，其特征在于，所述在所述第一分隔槽暴露的所述第一表面凹陷形成第三分隔槽包括：
    通过刀切、激光切割或者刻蚀的方法在所述第一分隔槽暴露的所述第一表面凹陷形成第三分隔槽。
  9. 根据权利要求3或4所述的制备方法，其特征在于，所述第三分隔槽和所述第四分隔槽的深度均大于所述初始玻璃基板的一半厚度。
  10. 一种电子设备，其特征在于，包括电路板和如权利要求1或2任一项所述的封装体结构，所述电路板与所述封装体结构电连接。
PCT/CN2025/101555 2024-07-16 2025-06-17 封装体结构及其制备方法、电子设备 Pending WO2026016708A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040166654A1 (en) * 2002-10-04 2004-08-26 Seiko Epson Corporation Panel, liquid crystal projector, image pickup device, and digital image recognition device
JP2017073424A (ja) * 2015-10-05 2017-04-13 日本特殊陶業株式会社 配線基板及びその製造方法
CN111739876A (zh) * 2020-05-20 2020-10-02 甬矽电子(宁波)股份有限公司 封装天线结构、其制作方法和电子设备
CN111863791A (zh) * 2020-07-28 2020-10-30 南通通富微电子有限公司 一种半导体封装体和芯片封装体
CN113439331A (zh) * 2019-01-16 2021-09-24 凸版印刷株式会社 封装用基板及其制造方法

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JP2017073424A (ja) * 2015-10-05 2017-04-13 日本特殊陶業株式会社 配線基板及びその製造方法
CN113439331A (zh) * 2019-01-16 2021-09-24 凸版印刷株式会社 封装用基板及其制造方法
CN111739876A (zh) * 2020-05-20 2020-10-02 甬矽电子(宁波)股份有限公司 封装天线结构、其制作方法和电子设备
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