WO2023000656A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023000656A1
WO2023000656A1 PCT/CN2022/076309 CN2022076309W WO2023000656A1 WO 2023000656 A1 WO2023000656 A1 WO 2023000656A1 CN 2022076309 W CN2022076309 W CN 2022076309W WO 2023000656 A1 WO2023000656 A1 WO 2023000656A1
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Prior art keywords
hole
connection hole
layer
semiconductor structure
connection
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PCT/CN2022/076309
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English (en)
French (fr)
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张志伟
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长鑫存储技术有限公司
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Priority to US17/954,259 priority Critical patent/US20230013953A1/en
Publication of WO2023000656A1 publication Critical patent/WO2023000656A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

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  • the embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure.
  • the semiconductor structure includes a substrate and a wiring layer arranged on the substrate.
  • the wiring layer is a circuit pattern with a certain shape.
  • a contact pad is provided on the side of the substrate away from the wiring layer; a connection hole is provided on the substrate, and a connection layer is provided in the connection hole.
  • the connection layer is used to connect the wiring layer and the contact pad arranged on both sides of the substrate.
  • connection holes are relatively rough, which affects the performance of subsequent connection holes, and more seriously affects the performance of the overall semiconductor structure.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including:
  • a base is provided, the base has a connection hole; the wall of the connection hole has ring-shaped protrusions and ring-shaped grooves arranged alternately along a direction parallel to the centerline of the connection hole;
  • a connection layer is formed inside the connection hole.
  • filling the blocking blocks in each of the annular grooves includes:
  • connection hole Filling the connection hole with a barrier material, the barrier material filling the connection hole;
  • Part of the barrier material is removed to form a through hole, the centerline of the through hole is collinear with the centerline of the connection hole, and the hole wall of the through hole is engaged with the annular protrusion.
  • part of the barrier material is removed to form the through hole, and at the same time, the end of the annular protrusion facing the centerline of the connection hole is removed.
  • the blocking material includes photoresist.
  • part of the barrier material is removed by exposure and development, so as to form the through hole.
  • filling the connection hole with the barrier material, and filling the connection hole with the barrier material includes:
  • the barrier material also covers the surface of the substrate
  • the method further includes: removing the barrier material on the surface of the substrate.
  • etching the annular protrusion along a direction perpendicular to the wall of the connecting hole includes:
  • the annular protrusion is removed by wet etching.
  • the preset depth is 1 nm-10 nm.
  • connection layer in the connection hole includes:
  • connection layer is formed by electroplating the conductive seed layer on the hole wall of the connection hole.
  • forming the conductive seed layer on the hole wall of the connection hole includes;
  • the conductive seed layer is formed by sputtering.
  • connection holes includes:
  • the mask layer having etching holes
  • the mask layer as a mask to etch the protective layer and the substrate corresponding to the bottom of the groove to increase the depth of the groove;
  • connection layer after the connection layer is formed in the connection hole, it further includes:
  • a wiring layer joined to the connection layer is formed on one side of the substrate.
  • connection layer after the connection layer is formed in the connection hole, it further includes:
  • connection pads bonded to the connection layer are formed on the other side of the substrate.
  • the embodiment of the present application also provides a semiconductor structure, which is manufactured by the above-mentioned manufacturing method of the semiconductor structure.
  • the manufacturing method of the semiconductor structure specifically includes: providing a substrate, the substrate has connection holes; The ring-shaped protrusion and the ring-shaped groove; fill the blocking block in each ring-shaped groove; remove the ring-shaped protrusion along the direction perpendicular to the wall of the connecting hole; remove the blocking block; form a connecting layer in the connecting hole.
  • the hole wall roughness of the connection hole after removing the annular protrusion is reduced, which can prevent faults in the conductive seed layer, thereby avoiding the generation of voids in the connection layer, and improving the performance of the semiconductor structure.
  • FIG. 1 is a schematic flow diagram of a method for fabricating a semiconductor structure provided in an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view of a connection hole of a semiconductor structure provided by an embodiment of the present application
  • FIG. 3 is a schematic cross-sectional view of filling a connection hole with a barrier material provided by an embodiment of the present application
  • Fig. 4 is a schematic cross-sectional view of forming a blocking block in a connection hole provided by an embodiment of the present application
  • Fig. 5 is a schematic cross-sectional view of removing an annular protrusion provided by an embodiment of the present application
  • FIG. 6 is a schematic cross-sectional view of a removal blocking block provided by an embodiment of the present application.
  • connection hole is usually formed by Bosch (Bosch) etching process. Specifically, it is necessary to first form a mask layer with etching holes on the substrate, and then use the mask layer as a mask to etch the substrate. A groove is formed on the substrate; a protective layer is then deposited on the sidewall and bottom of the groove, and the protective layer at the bottom of the groove and the part of the substrate extending toward the bottom of the groove are etched using the mask layer as a mask to increase the The depth of the large groove. By alternating etching and deposition steps, the depth of the grooves is increased.
  • connection hole After forming the connection hole, in order to connect the wiring layer and the contact pad in the semiconductor structure, it is also necessary to form a combination layer on the hole wall of the connection hole.
  • the combination layer includes but is not limited to sequentially forming an insulating layer, a barrier layer and a conductive seed layer, and then passing The conductive seed layer is electroplated on the hole wall of the connection hole to form a connection layer.
  • connection holes are alternately performed to form connection holes, so that the hole wall of the connection hole has annular protrusions and annular grooves alternately arranged along the centerline of the connection hole, the roughness is high, and the hole wall with high roughness will The difficulty of forming the combination layer is increased, which in turn causes the combination layer to be faulted, so that the connection layer of subsequent electroplating enters the fault and affects the performance of the semiconductor structure.
  • the embodiment of the present application provides a method for manufacturing a semiconductor structure and a semiconductor structure.
  • the manufacturing method of the semiconductor structure provided in the embodiment of the present application includes:
  • Step S101 providing a substrate with connection holes; the walls of the connection holes have ring-shaped protrusions and ring-shaped grooves arranged alternately along a direction parallel to the centerline of the connection holes.
  • the substrate 10 can be a semiconductor substrate, such as silicon or silicon germanium (SiGe) of monocrystalline silicon, polycrystalline silicon or amorphous structure, or a mixed semiconductor structure, such as silicon carbide, antimony Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof, which are not limited in this embodiment.
  • a semiconductor substrate such as silicon or silicon germanium (SiGe) of monocrystalline silicon, polycrystalline silicon or amorphous structure, or a mixed semiconductor structure, such as silicon carbide, antimony Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof, which are not limited in this embodiment.
  • the surface of the substrate 10 is covered with a film layer structure 12, which can be formed after the connection hole 11 is formed, and the film layer structure 12 can include, for example, an isolation layer to protect tiny circuits from scratches, contamination, and moisture.
  • connection holes 11 are arranged perpendicular to the extending direction of the base 10 , and the connection holes 11 penetrate through the base 10 .
  • the connection hole 11 in this embodiment can be formed by Bosch etching process, of course, in some examples, the connection hole 11 can also be formed by conventional wet etching, conventional dry etching, photo-assisted electrochemical etching, laser drilling, etc. The process is formed, and no specific limitation is made here.
  • connection hole 11 is formed using a Bosch etching process
  • the substrate 10 is provided, and the step of having the connection hole 11 on the substrate 10 includes: forming a mask layer on the substrate 10, and the mask layer has an etching hole, so that The substrate 10 facing the etching hole is removed to form the connection hole 11 .
  • the material of the mask layer may include photoresist, amorphous carbon, silicon dioxide and the like.
  • the step of forming the connection holes 11 further includes: etching the substrate 10 using the mask layer as a mask to form grooves on the substrate 10 .
  • an etching gas may be introduced into the etching hole, the etching gas is decomposed into plasma, and the substrate 10 opposite to the etching hole is etched to form a groove.
  • the etching gas can be, for example, SF6.
  • the step of forming the connection hole 11 further includes: forming a protective layer on the groove bottom and the groove wall of the groove.
  • the deposition gas can be passed into the groove, and the deposition gas is decomposed into plasma, and then forms a polymer on the groove bottom and groove wall of the groove, and the polymer is a protection that can protect the subsequent groove wall from being etched layer.
  • the deposition gas may include C4F8, for example.
  • the step of forming the connection hole 11 further includes: using the mask layer as a mask to etch the corresponding protective layer and the substrate 10 at the bottom of the groove to increase the depth of the groove.
  • the above-mentioned etching process may be used to remove the protective layer covering the bottom of the groove and part of the substrate 10 covered by the bottom of the groove, thereby further increasing the depth of the groove.
  • the step of forming the connection hole 11 further includes: repeatedly forming the protective layer and etching the protective layer and the substrate 10 corresponding to the bottom of the groove until the groove penetrates the substrate 10 to form Connection hole 11.
  • the depth of the groove can be gradually increased until it penetrates the substrate 10 to form the connection hole 11 .
  • the connection hole 11 may not be disposed through the base 10, and it is not limited here. It should be noted that the depth of the groove can be controlled by controlling the times of deposition and etching, and then form the connection hole 11 with a certain depth according to actual process requirements.
  • the hole wall of the connecting hole 11 has a plurality of annular curved surfaces, the centerline of the curved surface coincides with the centerline of the connecting hole 11, the center of the curved surface is located in the inside of the connecting hole 11, and the plurality of curved surfaces along the connecting hole 11
  • the center line of the connecting hole 11 is connected in turn, so that the end of the curved surface close to the center line of the connecting hole 11 is the annular protrusion 115 of the connecting hole 11, and the end of the curved surface away from the center line of the connecting hole 11 is the annular groove 113 of the connecting hole 11.
  • the annular protrusions 115 and the annular grooves 113 are alternately arranged along the direction parallel to the centerline of the connecting hole 11.
  • the centerlines of the annular protrusions 115 and the annular grooves 113 coincide with the centerline of the connecting hole 11 .
  • Step S102 filling blocking blocks in each annular groove.
  • each blocking block 112 covers its corresponding annular groove 113 to expose the annular protrusion 115 .
  • the blocking block 112 is also an annular structure, the centerline of the blocking block 112 coincides with the centerline of the connecting hole 11, and the end of the blocking block 112 close to the side wall of the connecting hole 11 has an annular groove 113 As for the matching curved surface, the center of the curved surface is located inside the connecting hole 11 .
  • Step S103 removing the ring-shaped protrusion along a direction perpendicular to the wall of the connecting hole.
  • the removed annular protrusion 115 extends from the wall of the connection hole 11 to the outside of the connection hole 11 in a direction perpendicular to the centerline of the connection hole 11 .
  • the annular protrusion 115 can be removed by wet etching.
  • wet etching is a method of removing materials by using chemical reagents.
  • the chemical reagents may use hot phosphoric acid, hot SC1 cleaning solution, fluorine-containing liquid, gas, and the like. Removing the ring-shaped protrusion 115 by means of wet etching is beneficial to reduce operation difficulty and production cost, thereby facilitating mass production.
  • the annular protrusion 115 has a high etching selectivity ratio relative to the blocking block 112, so that when the annular protrusion 115 is removed by wet etching, the annular protrusion 115 is etched away before the blocking block 112,
  • the blocking block 112 can always cover the annular groove 113 , thereby avoiding the etching of the annular groove 113 , thereby reducing the roughness of the wall of the connecting hole 11 .
  • Step S104 removing the blocking block.
  • the blocking block 112 After the blocking block 112 is removed, that is, the blocking material 111 covered on the hole wall of the connection hole 11 is removed, so that the hole wall of the connection hole 11 is completely exposed.
  • the hole wall roughness of the connecting hole 11 is reduced compared with that in Fig.
  • the center lines coincide, the center of the curved surface is located inside the connecting hole 11 , and multiple curved surfaces are sequentially connected along the center line of the connecting hole 11 .
  • the distance between the farthest end and the closest end of the curved surface from the center line of the connecting hole 11 along the direction perpendicular to the wall of the connecting hole 11 is smaller than the first distance L1, which is beneficial for subsequent covering of the hole wall with other materials and reduces manufacturing difficulty.
  • Step S105 forming a connection layer inside the connection hole.
  • connection layer may include a conductive material, so as to electrically connect the structures at both ends of the connection hole 11 through the connection hole 11 .
  • a conductive seed layer may be formed on the hole wall of the connection hole 11 first, and then the connection layer is formed by electroplating using the conductive seed layer as an electrode.
  • the method further includes: forming an insulating layer on a hole wall of the connection hole 11 .
  • an insulating layer may be formed on the hole wall of the connection hole 11 through a deposition process.
  • the material of the insulating layer may include oxides such as silicon dioxide, for example.
  • the silicon atoms on the wall surface of the connection hole 11 can be completely reacted into silicon dioxide by means of thermal oxidation diffusion under high temperature conditions.
  • the insulating layer After the insulating layer is formed on the hole wall of the connection hole 11 , it further includes: forming a diffusion barrier layer covering the insulating layer.
  • the diffusion barrier layer is used to prevent the material of the connecting layer from diffusing through the insulating layer.
  • the diffusion barrier layer may use one or more materials of Ta, TaN, Ti, and TiN as target materials through an ion implantation process. In the case of using multiple materials, one target may include multiple materials at the same time, or multiple targets may be used, wherein each target includes one or more materials.
  • the step of forming the connection layer in the connection hole 11 includes: forming a conductive seed layer in the connection hole 11 for subsequent formation of the connection layer.
  • the conductive seed layer may be formed by a sputtering process, so as to subsequently form a connection layer on the basis of the conductive seed layer.
  • the material of the conductive seed layer may include copper, silver, titanium, nickel and the like.
  • the step of forming a connection layer in the connection hole 11 further includes: forming a connection layer in the connection hole 11 by electroplating the conductive seed layer.
  • the electroplating process is fast in manufacturing speed and low in cost, and it is easy to control the thickness of the electroplating material by controlling the electroplating process parameters.
  • the connection layer is formed by an electroplating process, the material of the connection layer is the same as that of the conductive seed layer.
  • the connection layer can also be formed by electroless plating or vacuum evaporation plating.
  • the manufacturing method of the semiconductor structure specifically includes: providing a substrate 10, the substrate 10 has connection holes 11; Lift 115 and annular groove 113; Fill blocking block 112 in each annular groove 113; Along the direction perpendicular to the hole wall of connecting hole 11, remove annular protrusion 115; Remove blocking block 112; In connecting hole 11 Form the connection layer.
  • the hole wall roughness of the connection hole 11 after the ring-shaped protrusion 115 is removed is reduced, preventing the conduction seed layer from being broken, thereby avoiding the generation of voids in the connection layer, and improving the performance of the semiconductor structure.
  • filling the barrier block 112 in each annular groove 113 includes: filling the barrier material 111 in the connection hole 11 , and the barrier material 111 fills the connection hole 11 completely.
  • a coating process may be used to fill the barrier material 111 in the connection hole 11 , so that the barrier material 111 adheres to the wall of the connection hole 11 .
  • the connection hole 11 is filled with a barrier material 111 .
  • the barrier material 111 fills the connection hole 11 , it also includes: the barrier material 111 also covers the surface of the substrate 10 .
  • the barrier material 111 When the barrier material 111 is filled by a coating process, the barrier material 111 can be directly formed on the surface of the substrate 10, so that the barrier material 111 can be filled in the connection hole 11, and can also cover the surface of the substrate 10 outside the connection hole 11 In fact, it is beneficial to improve the efficiency of processing, reduce the difficulty of processing, and facilitate the realization of large-scale production.
  • the blocking material 111 includes photoresist, and subsequent removal of the photoresist material is simple, which facilitates the subsequent formation of the through hole 13 and improves processing efficiency.
  • filling the barrier block 112 in each annular groove 113 also includes: removing part of the barrier material 111 to form a through hole 13, and the centerline of the through hole 13 and the connection hole The central lines of 11 are collinear, and the hole wall of the through hole 13 is engaged with the annular protrusion 115 .
  • the ring-shaped protrusions 115 are arranged at intervals on the walls of the through holes 13 .
  • the blocking material 111 to form the through hole 13 when removing part of the blocking material 111 to form the through hole 13 , it also includes: removing the end portion of the annular protrusion 115 facing the centerline of the connection hole 11 to form the remaining portion 119 .
  • the end of the remaining portion 119 close to the centerline of the connecting hole 11 is flush with the wall of the through hole 13 , and the end of the remaining portion 119 close to the centerline of the connecting hole 11 is aligned with the end of the blocking block 112 near the centerline of the connecting hole 11 .
  • One end is flush, that is, the remaining portion 119 is exposed between two adjacent blocking blocks 112 , which is beneficial for subsequent removal of the remaining portion 119 .
  • the end of the ring-shaped projection 115 facing the centerline of the connection hole 11 may not be removed, so that the hole wall of the formed through hole 13
  • the end of the ring-shaped protrusion 115 towards the centerline of the connecting hole 11 protrudes from between two adjacent blocking blocks.
  • the ring-shaped protrusion 115 is subsequently removed, because the ring-shaped protrusion 115 has a high etching selectivity with respect to the blocking block 112, the ring-shaped protrusion 115 is etched away before the blocking block 112, so that the blocking block 112 can always cover the ring-shaped protrusion 112.
  • part of the blocking material 111 may be removed by exposure and development, so as to form the through hole 13 .
  • the blocking material 111 is a positive photoresist, and a photomask with a positive pattern is formed on the surface of the photoresist, and the opening of the positive pattern exposes part of the connection holes 11 . Further, the projection of the opening of the positive pattern on the substrate 10 covers part of the connection hole 11 .
  • the positive photoresist is exposed through a photomask, that is, part of the barrier material 111 inside the connection hole 11 is exposed and melted into a positive developer, thereby forming the through hole 13 .
  • removing the end of the ring-shaped protrusion 115 towards the centerline of the connection hole 11, along the direction perpendicular to the wall of the connection hole 11, before etching the remaining part 119 it also includes: removing the In order to affect the removal of the remaining portion 119 , removing the barrier material 111 on the surface of the substrate 10 is also beneficial to avoid subsequent formation of other film layers on the surface of the substrate 10 .
  • etching the remaining part 119 along a direction perpendicular to the wall of the connection hole 11 includes: The remaining portion 119 is etched in a direction to form an annular depression 117 on the wall of the connection hole 11 ; so that the depth of the depression 117 and the annular groove 113 is not greater than a predetermined depth.
  • the annular recess 117 is an annular curved surface, the centerline of the curved surface coincides with the centerline of the connecting hole 11, the center of the curved surface is located inside the connecting hole 11, and the plurality of curved surfaces along the The centerlines of the connection holes 11 are sequentially connected, and the curved surface of the concave portion 117 has a third distance L3 between the farthest end and the nearest end of the centerline of the connection hole 11 in a direction perpendicular to the wall of the connection hole 11.
  • the third distance L3 That is, the depth of the recessed portion 117 .
  • the curved surface of the annular groove 113 has a second distance L2 between the farthest end and the nearest end of the center line of the connecting hole 11 in a direction perpendicular to the wall of the connecting hole 11, and the second distance L2 is annular.
  • the depth of the groove 113 It should be noted that the depths of the recessed portion 117 and the annular groove 113 are not greater than a predetermined depth, so as to avoid affecting subsequent formation of other film layers on the hole wall.
  • the preset depth is 1 nm-10 nm, so as to further avoid affecting the fabrication of other processes on the wall of the subsequent hole, and further improve the performance of the connection hole 11 .
  • the method further includes: forming a wiring layer joined to the connection layer on one side of the substrate 10 .
  • the wiring layer can be formed by electroplating or deposition, and electrically connects the semiconductor structure with external devices through the wiring layer, thereby realizing the function of the semiconductor structure.
  • the method further includes: forming a contact pad bonded with the connection layer on the other side of the substrate 10 .
  • the material of the contact pad can include tungsten or copper, etc., and the contact pad can be used as a soldering point of the chip package.
  • connection hole 11 is not provided through the substrate 10
  • the side of the substrate 10 away from the connection hole 11 can be thinned to expose the connection layer in the connection hole 11 , and then form a contact pad bonded to the connection layer on the other side of the substrate 10, so that the contact pad is connected to the wiring layer through the connection layer.
  • the substrate 10 may be thinned by etching or chemical mechanical polishing.
  • the embodiment of the present application also provides a semiconductor structure, which is fabricated by using the above semiconductor structure fabrication method.
  • the semiconductor structure includes a substrate 10, the substrate 10 has a connection hole 11, the hole wall of the connection hole 11 has recesses 117 and annular grooves 113 arranged alternately along the direction parallel to the centerline of the connection hole 11, the hole of the connection hole 11 There is also a connecting layer on the wall.
  • the hole wall of the connecting hole 11 has annular protrusions 115 and annular grooves 113 arranged alternately along the direction parallel to the centerline of the connecting hole 11, filling in each annular groove 113
  • For the blocking block 112 remove the ring-shaped protrusion 115 on the connecting hole 11 along a direction perpendicular to the wall of the connecting hole 11 , and then remove the blocking block 112 to form a recess 117 .
  • the hole wall roughness of the connection hole 11 after the ring-shaped protrusion 115 is removed is reduced, preventing the conduction seed layer from being broken, thereby avoiding the generation of voids in the connection layer, and improving the performance of the semiconductor structure.

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Abstract

本申请实施例属于半导体结构作技术领域，具体涉及一种半导体结构的制作方法及半导体结构。包括：提供基底，基底上具有连接孔；连接孔的孔壁上具有沿平行于连接孔中心线方向交替设置的环状凸起和环状凹槽；在各环状凹槽内填充阻挡块；沿垂直于连接孔孔壁的方向，去除环状凸起；去除阻挡块；在连接孔内形成连接层。去除环状凸起以后的连接孔的孔壁粗糙度降低，防止导电种子层出现断层，从而避免连接层中产生空隙，提高半导体结构的性能。

Description

半导体结构的制作方法及半导体结构
本申请要求于2021年07月19日提交中国专利局、申请号为202110811858.6、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构的制作方法及半导体结构。
背景技术
存储器等电子设备上一般具有半导体结构。半导体结构包括基底以及设置在基底上的布线层，布线层为具有一定形状的线路图形，基底背离布线层的侧面上一般设置有接触垫；基底上设置有连接孔，连接孔内设置有连接层，连接层用于连接设置在基底两侧的布线层和接触垫。
然而，相关技术中，连接孔的孔壁较为粗糙，这对后续连接孔的性能产生影响，更严重影响整体半导体结构的性能。
发明内容
一方面，本申请实施例提供一种半导体结构的制作方法，包括：
提供基底，所述基底上具有连接孔；所述连接孔的孔壁上具有沿平行于所述连接孔中心线方向交替设置的环状凸起和环状凹槽；
在各所述环状凹槽内填充阻挡块；
沿垂直于所述连接孔孔壁的方向，去除所述环状凸起；
去除所述阻挡块；
在所述连接孔内形成连接层。
在一种可实现方式中，在各所述环状凹槽内填充阻挡块包括：
在所述连接孔内填充阻挡材料，所述阻挡材料填充满所述连接孔；
去除部分所述阻挡材料以形成通孔，所述通孔的中心线与所述连接孔的中心线共线，所述通孔的孔壁与所述环状凸起接合。
在一种可实现方式中，去除部分所述阻挡材料，以形成通孔的同时，去除所述环状凸起朝向所述连接孔中心线的端部。
在一种可实现方式中，所述阻挡材料包括光阻。
在一种可实现方式中，通过曝光显影的方式去除部分所述阻挡材料，以形成所述通孔。
在一种可实现方式中，在所述连接孔内填充所述阻挡材料，所述阻挡材料充满所述连接孔包括：
所述阻挡材料还覆盖在所述基底的表面上；
沿垂直于所述连接孔孔壁的方向，蚀刻所述环状凸起之前还包括：去除位于所述基底表面上的所述阻挡材料。
在一种可实现方式中，沿垂直于所述连接孔孔壁的方向，蚀刻所述环状凸起包括：
沿垂直于所述连接孔孔壁的方向蚀刻所述环状凸起，以在所述连接孔的孔壁形成环状凹陷部；使得所述凹陷部和所述环状凹槽的深度不大于预设深度。
在一种可实现方式中，通过湿法蚀刻的方式去除所述环状凸起。
在一种可实现方式中，所述预设深度为1nm-10nm。
在一种可实现方式中，在所述连接孔内形成所述连接层包括：
在所述连接孔孔内形成导电种子层；
通过所述导电种子层在所述连接孔的孔壁上电镀形成所述连接层。
在一种可实现方式中，在所述连接孔的孔壁上形成所述导电种子层包括；
通过溅射的工艺形成所述导电种子层。
在一种可实现方式中，提供基底，所述基底上具有连接孔包括：
在所述基底上形成掩膜层，所述掩膜层具有蚀刻孔；
以所述掩膜层为掩膜蚀刻所述基底，以在所述基底上形成凹槽；
在所述凹槽的槽底和槽壁上形成保护层；
以所述掩膜层为掩膜蚀刻所述凹槽槽底对应的所述保护层和所述基底，以提高所述凹槽的深度；
重复形成所述保护层和蚀刻所述凹槽槽底对应的所述保护层和所述基底，直至所述凹槽贯穿所述基底，以形成所述连接孔。
在一种可实现方式中，在所述连接孔内形成连接层之后还包括：
在所述基底的一侧形成与所述连接层接合的布线层。
在一种可实现方式中，在所述连接孔内形成连接层之后还包括：
在所述基底的另一侧形成与所述连接层接合的接触垫。
另一方面，本申请实施例还提供一种半导体结构，通过上述的半导体结构的制作方法制作而成。
本申请实施例提供的半导体结构的制作方法及半导体结构中，半导体结构的制作方法具体包括：提供基底，基底上具有连接孔；连接孔的孔壁上具有沿平行于连接孔中心线方向交替设置的环状凸起和环状凹槽；在各环状凹槽内填充阻挡块；沿垂直于连接孔孔壁的方向，去除环状凸起；去除阻挡块；在连接孔内形成连接层。去除环状凸起以后的连接孔的孔壁粗糙度降低，能够防止导电种子层出现断层，从而避免连接层中产生空隙，提高半导体结构的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种半导体结构的制作方法的流程示意图；
图2为本申请实施例提供的一种半导体结构的连接孔的剖面示意图；
图3为本申请实施例提供的一种在连接孔内填充阻挡材料的剖面示意图；
图4为本申请实施例提供的一种在连接孔内形成阻挡块的剖面示意图；
图5为本申请实施例提供的一种去除环状凸起的剖面示意图；
图6为本申请实施例提供的一种去除阻挡块的剖面示意图。
具体实施方式
为了清楚理解本申请的技术方案，首先对相关技术的方案进行详细介绍。
相关技术中，在制作连接孔时，通常是采用博世(Bosch)蚀刻工艺形成，具体来说：需要先在基底上形成具有蚀刻孔洞的掩膜层，然后以掩膜层为掩膜蚀刻基底，在基底上形成凹槽；之后在凹槽的侧壁和槽底沉积保护层，再以掩膜层为掩膜蚀刻凹槽槽底的保护层以及向凹槽槽底延伸的部分基底，以增大凹槽的深度。通过采用蚀刻和沉积步骤交替进行的方法，使得凹槽的深度增大。在形成连接孔之后，为连接半导体结构中的布线层和接触垫，还需要在连接孔的孔壁形成组合层，组合层包括但不限于依次形成绝缘层、阻挡层及导电种子层，然后通过导电种子层在连接孔的孔壁上电镀形成连接层。
然而，交替进行蚀刻和沉积以形成连接孔，使得连接孔的孔壁具有沿连接孔中心线方向交替设置的环状凸起和环状凹槽，粗糙度较高，粗糙度高的孔壁会增大组合层的形成难度，进而造成组合层断层，使得后续电镀的连接层进入断层中，影响半导体结构的性能。
针对上述问题，本申请实施例提供一种半导体结构的制作方法及半导体结构，通过去除连接孔孔壁的环状凸起，降低连接孔孔壁的粗糙度，防止导电种子层出现断层，从而避免连接层中产生空隙。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
如图1所示，本申请实施例提供的半导体结构的制作方法包括：
步骤S101、提供基底，基底上具有连接孔；连接孔的孔壁上具有沿平行于连接孔中心线方向交替设置的环状凸起和环状凹槽。
请参照图2，本实施例中，基底10可以为半导体基底，例如单晶硅、多晶硅或非晶结构的硅或硅锗(SiGe)，也可以为混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合，本实施例在此不对其进行限制。
基底10表面覆盖有膜层结构12，膜层结构12可以在形成连接孔11之后形成，膜层结构12例如可以包括保护微小电路免受刮擦、污染、受潮的隔离层。
示例性的，继续参照图2，连接孔11垂直于基底10的延伸方向设置，连接孔11贯穿基底10。本实施例中的连接孔11可以采用博世蚀刻工艺形成，当然，在一些示例中，连接孔11还可以采用常规的湿法蚀刻、常规的干法蚀刻、光辅助电化学蚀刻、激光钻孔等工艺形成，在此不做具体的限定。
可选的，在采用博世蚀刻工艺形成连接孔11的实施例中，提供基底10，基底10上具有连接孔11的步骤包括：在基底10上形成掩膜层，掩膜层具有蚀刻孔，以便去除蚀刻孔正对的基底10，进而形成连接孔11。掩膜层的材质可以包括光刻胶、无定形碳、二氧化硅等。
形成蚀刻孔以后，形成连接孔11的步骤还包括：以掩膜层为掩膜蚀刻基底10，以在基底10上形成凹槽。具体的，可以在蚀刻孔内通入蚀刻气体，蚀刻气体被分解为等离子体，对蚀刻孔正对的基底10进行蚀刻，以形成凹槽。蚀刻气体例如可以为SF6.
在基底10上形成凹槽以后，形成连接孔11的步骤还包括：在凹槽的槽底和槽壁上形成保护层。具体的，可以在凹槽内通入沉积气体，沉积气体被分解为等离子体，进而在凹槽的槽底和槽壁形成聚合物，该聚合物即为能够保护后续槽壁不被蚀刻的保护层。沉积气体例如可以包括C4F8。
形成保护层以后，形成连接孔11的步骤还包括：以掩膜层为掩膜蚀刻凹槽槽底对应的保护层和基底10，以增大凹槽的深度。具体的，可以采用上述的蚀刻工艺，去除槽底上覆盖的保护层以及槽底覆盖的部分基底10，进而使得凹槽的深度进一步增大。
蚀刻凹槽槽底对应的保护层和基底10以后，形成连接孔11的步骤还包括：重复形成保护层和蚀刻凹槽槽底对应的保护层和基底10，直至凹槽贯穿基底10，以形成连接孔11。通过重复上述沉积与蚀刻过程，可以使凹槽的深度逐步增大，直到贯穿基底10，以形成连接孔11。当然，连接孔11也可以不贯穿基底10设置，此处不进行限定。需要说明的是，可以通过控制沉积与蚀刻的次数，控制凹槽的深度，进而根据实际的工艺需求，形成一定深度的连接孔11。
如图2所示，连接孔11的孔壁具有多个环状的曲面，曲面的中心线与连接孔11的中心线重合，曲面的圆心位于连接孔11的内部，多个曲面沿连接孔11的中心线依次连接，以使曲面靠近连接孔11的中心线一端即为连接孔11的环状凸起115，曲面远离连接孔11的中心线一端即为连接孔11的环状凹槽113，环状凸起115和环状凹槽113沿平行于连接孔11中心线的方向交替设置，具体的，环状凸起115与环状凹槽113的中心线均与连接孔11的中心线重合。曲面沿垂直于连接孔11孔壁的方向距离连接孔11的中心线的最远端与最近端之间具有第一距离L1。
步骤S102、在各环状凹槽内填充阻挡块。
本实施例中，阻挡块112具有多个，每个阻挡块112均覆盖在其对应的环状凹槽113，以使环状凸起115暴露出来。示例性的，参照图4，阻挡块112也为环状结构，阻挡块112的中心线与连接孔11的中心线重合，阻挡块112靠近连接孔11侧壁的一端具有与环状凹槽113配合的曲面，曲面的圆心位于连接孔11的内部。
步骤S103、沿垂直于连接孔孔壁的方向，去除环状凸起。
参照图5，去除的环状凸起115由连接孔11的孔壁沿垂直于连接孔11中心线的方向向连接孔11外部延伸。
可选的，可以通过湿法蚀刻的方式去除环状凸起115。具体的，湿法蚀刻是一种通过化学试剂去除材料的方式，本实施例中，化学试剂可以使用热磷酸、热SC1清洗液、含氟的液体以及气体等。通过湿法蚀刻的方式去除环状凸起115，有利于降低操作难度，降低生产成本，进而有利于实现大批量生产。
需要说明的是，环状凸起115相对于阻挡块112具有高蚀刻选择比，以使在通过湿法蚀刻去除环状凸起115时，环状凸起115先于阻挡块112被蚀刻掉，使得阻挡块112能够始终覆盖在环状凹槽113上，进而避免环状凹槽113发生蚀刻，从而降低连接孔11孔壁的粗糙度。
步骤S104、去除阻挡块。
去除阻挡块112以后，也即去除了连接孔11的孔壁上覆盖的阻挡材料111，使得连接孔11的孔壁全部暴露出来。参照图6，连接孔11的孔壁相对于图2中的孔壁粗糙度降低，具体来说，连接孔11的孔壁具有多个环状的曲面，曲面的中心线均与连接孔11的中心线重合，曲面的圆心位于连接孔11的内部，多个曲面沿连接孔11的中心线依次连接。曲面沿垂直于连接孔11孔壁的方向距离连接孔11的中心线的最远端与最近端之间的距离小于第一距离L1，有利于后续在孔壁上覆盖其他材料，降低制作难度。
步骤S105、在连接孔内上形成连接层。
连接层的材质可以包括导电材料，以便通过连接孔11电连接连接孔11两端的结构。在一种可实现的方式中，可以先在连接孔11的孔壁上形成导电种子层，再以导电种子层为电极通过电镀形成连接层。
可选的，在连接孔11内形成连接层之前，还包括：在连接孔11的孔壁上形成绝缘层。在一种可能的实现方式中，可以通过沉积的工艺，在连接孔11的孔壁上形成绝缘层。绝缘层的材质例如可以包括二氧化硅等氧化物。此外，还可以通过热氧化扩散的方式，在高温条件下，将连接孔11孔壁表面的硅原子完全反应变为二氧化硅。
在连接孔11的孔壁上形成绝缘层以后，还包括：形成扩散阻挡层，扩散阻挡层覆盖绝缘层。扩散阻挡层用于阻挡连接层的材料扩散透过绝缘层。扩散阻挡层可以通过离子注入的工艺，使用Ta、TaN、Ti、TiN的一种或者多种材料作为靶材。在采用多种材料的情况下，可以在一个靶材中同时包括多种材料，也可以使用多个靶材，其中各个靶材包括一种或多种材料。
可选的，本实施例中，在形成扩散阻挡层之后，在连接孔11内形成连接层的步骤包括：在连接孔11内形成导电种子层，以便后续连接层的形成。
在一种可能的实现方式中，可以通过溅射的工艺形成导电种子层，以便后续在导电种子层的基础上形成连接层。在一种可能的实现方式中，导电种子层的材质可以包括铜、银、钛、镍等。
在形成导电种子层以后，在连接孔11内形成连接层的步骤还包括：通过导电种子层在连接孔11内电镀形成连接层。需要说明的是，电镀的工艺制作速度快、成本低，易于通过控制电镀的过程参数控制电镀材料的厚度。需要说明的是，采用电镀工艺形成连接层时，连接层的材质与导电种子层的材质相同。例如，在导电种子层为铜种子层的实施例中，需要以铜种子层作为电极，电镀铜以形成连接层。当然，在一些其他 的示例中，还可以采用化学镀或者真空蒸发镀的工艺形成连接层。
本申请实施例提供的半导体结构的制作方法，具体包括：提供基底10，基底10上具有连接孔11；连接孔11的孔壁上具有沿平行于连接孔11中心线方向交替设置的环状凸起115和环状凹槽113；在各环状凹槽113内填充阻挡块112；沿垂直于连接孔11孔壁的方向，去除环状凸起115；去除阻挡块112；在连接孔11内形成连接层。去除环状凸起115以后的连接孔11的孔壁粗糙度降低，防止导电种子层出现断层，从而避免连接层中产生空隙，提高半导体结构的性能。
可选的，本实施例提供的半导体结构的制作方法中，在各环状凹槽113内填充阻挡块112包括：在连接孔11内填充阻挡材料111，阻挡材料111填充满连接孔11。
通过填充阻挡材料111，便于后续去除部分阻挡材料111以形成阻挡块112。本实施例中，可以采用涂布的工艺在连接孔11内填充阻挡材料111，使得阻挡材料111与连接孔11的孔壁贴合。
示例性的，如图3所示，在连接孔11内填充阻挡材料111，阻挡材料111填充满连接孔11的同时，还包括：阻挡材料111还覆盖在基底10的表面上。
当采用涂布工艺填充阻挡材料111时，可以直接在基底10的表面形成阻挡材料111，进而使得阻挡材料111既能够填充在连接孔11内，也可以覆盖在连接孔11外部的基底10的表面上，有利于提高加工的效率，降低加工的难度，有利于实现大规模生产。
可选的，阻挡材料111包括光阻，光阻材料后续去除的操作简单，有利于后续形成通孔13，提高加工效率。
可选的，在连接孔11内填充阻挡材料111以后，在各环状凹槽113内填充阻挡块112还包括：去除部分阻挡材料111以形成通孔13，通孔13的中心线与连接孔11的中心线共线，通孔13的孔壁与环状凸起115接合。
示例性的，环状凸起115间隔的设置在通孔13的孔壁上，通过形成通孔13，有利于后续通过去除通孔13的部分孔壁，进而平坦化连接孔11的孔壁。
可选的，去除部分阻挡材料111，以形成通孔13的同时，还包括：去除环状凸起115朝向连接孔11中心线的端部，以形成剩余部119。示例性的，参照图4，剩余部119靠近连接孔11中心线的一端与通孔13的孔壁平齐，且剩余部119靠近连接孔11中心线的一端与阻挡块112靠近连接孔11中心线的一端平齐，也即去剩余部119暴露在相邻的两个阻挡块112之间，进而有利于后续继续去除剩余部119。
在环状凸起115相对于阻挡块112具有高蚀刻选择比的实施例中，还可以不去除环状凸起115朝向连接孔11中心线的端部，则形成的通孔13的孔壁上，环状凸起115朝向连接孔11中心线的端部从相邻的两个阻挡块之间伸出。在后续去除环状凸起115时，由于环状凸起115相对于阻挡块112具有高蚀刻选择比，环状凸起115先于阻挡块112被蚀刻掉，使得阻挡块112能够始终覆盖在环状凹槽113上，进而避免环状凹槽113发生蚀刻，从而降低连接孔11孔壁的粗糙度。
可选的，在阻挡材料111包括光阻的实施例中，可以通过曝光显影的方式去除部分阻挡材料111，以形成通孔13。
具体的，阻挡材料111为正性光阻，在光阻表面形成具有正性图形的光罩，正性 图形的开口以使部分连接孔11暴露出来。进一步的，正性图案的开口在基底10上的投影覆盖部分连接孔11。通过光罩对正性光阻进行曝光，也即连接孔11内部的部分阻挡材料111进行曝光，并融于正性显影液中，进而形成通孔13。
可选的，去除环状凸起115朝向连接孔11中心线的端部的实施例中，沿垂直于连接孔11孔壁的方向，蚀刻剩余部119之前，还包括：去除位于基底10表面上的阻挡材料111，以便影响剩余部119的去除，去除基底10表面上的阻挡材料111还有利于避免后续在基底10表面形成其他膜层。
可选的，去除环状凸起115朝向连接孔11中心线的端部的实施例中，沿垂直于连接孔11孔壁的方向，蚀刻剩余部119包括：沿垂直于连接孔11孔壁的方向蚀刻剩余部119，以在连接孔11的孔壁形成环状凹陷部117；使得凹陷部117和环状凹槽113的深度不大于预设深度。
参照图5和图6，示例性的，环状凹陷部117为环状的曲面，曲面的中心线均与连接孔11的中心线重合，曲面的圆心位于连接孔11的内部，多个曲面沿连接孔11的中心线依次连接，凹陷部117的曲面沿垂直于连接孔11孔壁的方向距离连接孔11的中心线的最远端与最近端之间具有第三距离L3，第三距离L3即为凹陷部117的深度。相似的，环状凹槽113的曲面沿垂直于连接孔11孔壁的方向距离连接孔11的中心线的最远端与最近端之间具有第二距离L2，第二距离L2即为环状凹槽113的深度。需要说明的是，凹陷部117和环状凹槽113的深度不大于预设深度，以避免影响后续在孔壁上形成其他膜层。
可选的，预设深度为1nm-10nm，从而进一步避免影响后续孔壁上进行其他工艺的制作，进而进一步提高连接孔11的性能。
可选的，在连接孔11内形成连接层之后还包括：在基底10的一侧形成与连接层接合的布线层。布线层可以通过电镀或者沉积等方式形成，通过布线层将半导体结构与外部器件电连接，进而实现半导体结构的功能。
可选的，在连接孔11内形成连接层之后还包括：在基底10的另一侧形成与连接层接合的接触垫。接触垫的材质可以包括钨或者铜等，接触垫能够作为芯片封装的焊接点。
在连接孔11没有贯穿基底10设置的实施例中，可以在形成一定深度的连接孔11之后，对基底10远离连接孔11的一侧进行减薄处理，以暴露出连接孔11内的连接层，然后在基底10的另一侧形成与连接层接合的接触垫，以便接触垫通过连接层与布线层连接。具体的，可以采用蚀刻或者化学机械研磨的方式对基底10进行减薄处理。
本申请实施例还提供一种半导体结构，该半导体结构使用上述的半导体结构制作方法制作。
该半导体结构包括基底10，基底10上具有连接孔11，连接孔11的孔壁上具有沿平行于连接孔11中心线方向交替设置的凹陷部117和环状凹槽113，连接孔11的孔壁上还具有连接层。其中凹陷部117的形成过程为：连接孔11的孔壁上具有沿平行于连接孔11中心线方向交替设置的环状凸起115和环状凹槽113，在各环状凹槽113内填充阻挡块112，沿垂直于连接孔11孔壁的方向，去除连接孔11上的环状凸起115， 然后去除阻挡块112以形成凹陷部117。去除环状凸起115以后的连接孔11的孔壁粗糙度降低，防止导电种子层出现断层，从而避免连接层中产生空隙，提高半导体结构的性能。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (14)

  1. 一种半导体结构的制作方法，包括：
    提供基底，所述基底上具有连接孔；所述连接孔的孔壁上具有沿平行于所述连接孔中心线方向交替设置的环状凸起和环状凹槽；
    在各所述环状凹槽内填充阻挡块；
    沿垂直于所述连接孔孔壁的方向，去除所述环状凸起；
    去除所述阻挡块；
    在所述连接孔内形成连接层。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，在各所述环状凹槽内填充阻挡块包括：
    在所述连接孔内填充阻挡材料，所述阻挡材料填充满所述连接孔；
    去除部分所述阻挡材料以形成通孔，所述通孔的中心线与所述连接孔的中心线共线，所述通孔的孔壁与所述环状凸起接合。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，去除部分所述阻挡材料，以形成通孔的同时，去除所述环状凸起朝向所述连接孔中心线的端部。
  4. 根据权利要求2所述的半导体结构的制作方法，其中，所述阻挡材料包括光阻。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，通过曝光显影的方式去除部分所述阻挡材料，以形成所述通孔。
  6. 根据权利要求2所述的半导体结构的制作方法，其中，在所述连接孔内填充所述阻挡材料，所述阻挡材料充满所述连接孔包括：
    所述阻挡材料还覆盖在所述基底的表面上；
    沿垂直于所述连接孔孔壁的方向，蚀刻所述环状凸起之前还包括：去除位于所述基底表面上的所述阻挡材料。
  7. 根据权利要求1所述的半导体结构的制作方法，其中，沿垂直于所述连接孔孔壁的方向，蚀刻所述环状凸起包括：
    沿垂直于所述连接孔孔壁的方向蚀刻所述环状凸起，以在所述连接孔的孔壁形成环状凹陷部；使得所述凹陷部和所述环状凹槽的深度不大于预设深度。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，通过湿法蚀刻的方式去除所述环状凸起。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，所述预设深度为1nm-10nm。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，在所述连接孔内形成所述连接层包括：
    在所述连接孔孔内通过溅射的工艺形成导电种子层；
    以所述导电种子层为电极在所述连接孔的孔壁上电镀形成所述连接层。
  11. 根据权利要求1所述的半导体结构的制作方法，其中，提供基底，所述基底上具有连接孔包括：
    在所述基底上形成掩膜层，所述掩膜层具有蚀刻孔；
    以所述掩膜层为掩膜蚀刻所述基底，以在所述基底上形成凹槽；
    在所述凹槽的槽底和槽壁上形成保护层；
    以所述掩膜层为掩膜蚀刻所述凹槽槽底对应的所述保护层和所述基底，以提高所述凹槽的深度；
    重复形成所述保护层和蚀刻所述凹槽槽底对应的所述保护层和所述基底，直至所述凹槽贯穿所述基底，以形成所述连接孔。
  12. 根据权利要求1所述的半导体结构的制作方法，其中，在所述连接孔孔内形成连接层之后还包括：
    在所述基底的一侧形成与所述连接层接合的布线层。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，在所述连接孔内形成连接层之后还包括：
    在所述基底的另一侧形成与所述连接层接合的接触垫。
  14. 一种半导体结构，通过权利要求1-13任一项所述的半导体结构的制作方法制作而成。
PCT/CN2022/076309 2021-07-19 2022-02-15 半导体结构的制作方法及半导体结构 WO2023000656A1 (zh)

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CN103871956A (zh) * 2012-12-10 2014-06-18 中微半导体设备(上海)有限公司 一种深孔硅刻蚀方法
CN104282619A (zh) * 2013-07-03 2015-01-14 中芯国际集成电路制造(上海)有限公司 硅通孔的形成方法
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