WO2026001111A1 - Bga芯片封装结构和测试方法 - Google Patents

Bga芯片封装结构和测试方法

Info

Publication number
WO2026001111A1
WO2026001111A1 PCT/CN2025/083224 CN2025083224W WO2026001111A1 WO 2026001111 A1 WO2026001111 A1 WO 2026001111A1 CN 2025083224 W CN2025083224 W CN 2025083224W WO 2026001111 A1 WO2026001111 A1 WO 2026001111A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
substrate
bga chip
chip
probe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/083224
Other languages
English (en)
French (fr)
Inventor
陈峰跃
王英娜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Metabrain Intelligent Technology Co Ltd
Original Assignee
Suzhou Metabrain Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Metabrain Intelligent Technology Co Ltd filed Critical Suzhou Metabrain Intelligent Technology Co Ltd
Publication of WO2026001111A1 publication Critical patent/WO2026001111A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Definitions

  • This application relates to the field of chip packaging and testing technology, and in particular, to a BGA chip packaging structure and testing method.
  • Servers are incredibly complex systems comprised of numerous computing, storage, and management chips, requiring a PCB (Printed Circuit Board) to connect these functional modules.
  • PCB Print Circuit Board
  • the signal processing speed of network server chips has increased exponentially, as has the computing speed, but power consumption has also risen accordingly.
  • Server chassis structures cannot be expanded blindly; they must meet industry standards, thus limiting internal space.
  • PCB area remains constant, the ever-increasing number of electronic components and connectors must be systematically placed on the PCB surface.
  • the industry has introduced numerous BGA-packaged chips to reduce their footprint on the PCB.
  • soldering quality verification and impedance testing direct measurements cannot be taken at the chip's contacts.
  • these contact tests are conducted indirectly, such as non-destructive X-ray testing (as shown in Figure 5) to confirm solder quality, or destructive testing by grinding the chip to expose the solder.
  • Impedance testing can only confirm contacts on the PCB side; the solder-to-chip ball grid contact point can only be confirmed through simulation, or by reserving test points on the PCB for testing. It cannot directly test the solder quality.
  • Contacts under BGA (Ball Grid Array) chips cannot be measured without reserving test points on the PCB via solder, causing significant challenges for design verification.
  • this application provides a BGA chip packaging structure and testing method to solve the problem of difficulty in testing the soldering quality of the ball grid solder joints between the BGA chip and the PCB chip.
  • a BGA chip packaging structure comprising: a BGA chip substrate; ball grid soldering contacts are provided on the bottom surface of the BGA chip substrate for connection to a PCB board; a BGA chip body and lead contacts are provided on the top surface of the BGA chip substrate; the BGA chip body is connected to the lead contacts via segmented connecting leads on its surface facing away from the BGA chip substrate; the lead contacts and ball grid soldering contacts are connected one-to-one via traces inside the BGA chip substrate; wherein, the segmented connecting leads include: a substrate end lead; the substrate end lead is a rigid lead, including an upright section and a horizontal section; the upright section of the substrate end lead is perpendicular to the surface of the BGA chip substrate and connected to the lead contacts; a chip end lead; the chip end lead is a flexible lead, one end of which is connected to the BGA chip body, and the other end is detachably connected to the horizontal section of the substrate end lead; the chip end lead is
  • the BGA chip packaging structure further includes: a support filler layer; the support filler layer is disposed on the top surface of the BGA chip substrate and surrounds the side of the BGA chip body; the horizontal section of the substrate end lead and the portion of the chip end lead exposed in the BGA chip body are located on the surface of the support filler layer facing away from the BGA chip substrate; the support filler layer is an elastic adhesive layer suitable for allowing the chip end lead to elastically return to the connected state after the external force is removed after the substrate end lead is disconnected.
  • the BGA chip package structure further includes: an encapsulating adhesive layer; the encapsulating adhesive layer is disposed on the top surface of the BGA chip substrate, surrounding and covering the BGA chip body, lead contacts, supporting filler adhesive layer, and segmented connecting leads.
  • a release probe; the release probe is movably disposed in the encapsulating adhesive layer, adapted to contact the chip end leads, thereby separating the chip end leads from the substrate end leads.
  • the encapsulating adhesive layer has release probe holes that penetrate the encapsulating adhesive layer in the thickness direction, exposing the chip end leads; the release probe is disposed in the release probe holes and adapted to move along the extension direction of the release probe holes.
  • the end of the stripping probe away from the chip lead is an inverted cone structure; the opening of the stripping probe hole is a funnel-shaped opening; and elastic plastic is filled between the stripping probe and the stripping probe hole, with the elastic plastic located at least between the conical surface of the inverted cone of the stripping probe and the wall surface of the funnel-shaped opening of the stripping probe hole.
  • the size difference between the size of the stripping probe and the diameter of the stripping probe hole at any corresponding position is greater than 0.1 mm and less than 0.5 mm.
  • the BGA chip package structure further includes: a test probe; the test probe is movably disposed in the encapsulating adhesive layer, adapted to contact the horizontal section of the substrate end lead, and connects to the substrate end lead to test the lead contact.
  • the encapsulating adhesive layer is provided with a test probe hole, the test probe hole penetrating the encapsulating adhesive layer in the thickness direction to expose the horizontal section of the substrate end lead; the test probe is disposed in the test probe hole and adapted to move along the extension direction of the test probe hole.
  • the end of the test probe away from the substrate lead is an inverted cone structure; the opening of the test probe hole is a funnel-shaped opening; and an elastic plastic is filled between the test probe and the test probe hole, with the elastic plastic located at least between the conical surface of the inverted cone of the test probe and the wall surface of the funnel-shaped opening of the test probe hole.
  • the size difference between the test probe and the test probe hole at any corresponding position is greater than 0.1 mm and less than 0.5 mm.
  • the spacing between the test probe hole and the stripping probe hole is 0.5 mm to 1.5 mm.
  • the spacing between adjacent lead contacts is 0.5 mm to 1.5 mm.
  • the elastic plastic filling between the peeling probe and the peeling probe hole has an allowable elastic deformation of greater than 0.3 mm and less than 0.5 mm when the peeling probe is pressed down; the elastic plastic filling between the test probe and the test probe hole has an allowable elastic deformation of greater than 0.3 mm and less than 0.5 mm when the test probe is pressed down; and the support filling adhesive layer has an allowable elastic deformation of greater than 0.3 mm and less than 0.5 mm when the peeling probe is pressed down.
  • a testing method for a BGA chip package structure is also provided.
  • the BGA chip package structure is as provided in this application.
  • the testing method includes the following steps: using external force to separate the chip-end leads and the substrate-end leads, connecting the substrate-end leads, and testing the lead contacts; after the test is completed, removing the external force to allow the chip-end leads to spring back and reconnect with the substrate-end leads.
  • the BGA chip package structure includes an encapsulating adhesive layer; the encapsulating adhesive layer is disposed on the top surface of the BGA chip substrate, surrounding and covering the BGA chip body, lead contacts, and segmented connection leads; the BGA chip package structure also includes a release probe; the release probe is movably disposed in the encapsulating adhesive layer, adapted to contact the chip end lead, so as to separate the chip end lead from the substrate end lead; the testing method includes: before connecting the substrate end lead, pressing down the release probe to separate the chip end lead from the substrate end lead; after the test is completed, releasing the release probe, so that the chip end lead springs back and reconnects with the substrate end lead.
  • the BGA chip package structure includes an encapsulating adhesive layer; the encapsulating adhesive layer is disposed on the top surface of the BGA chip substrate, surrounding and covering the BGA chip body, lead contacts, and segmented connecting leads; the BGA chip package structure also includes a test probe; the test probe is movably disposed in the encapsulating adhesive layer, adapted to contact the horizontal segment of the substrate end lead, and connects to the substrate end lead to test the lead contacts; the testing method includes: after the substrate end lead and the chip end lead are separated, pressing down the test probe, connecting to the horizontal segment of the substrate end lead, and connecting the lead contacts through the substrate end lead to perform testing.
  • the pressure of pressing down the stripping probe is 1N to 3N.
  • the BGA chip packaging structure provided in this application includes a BGA chip body and lead contacts surrounding the BGA chip body on the top surface of the BGA chip substrate.
  • the BGA chip body is connected to the lead contacts via segmented connecting leads on its surface facing away from the BGA chip substrate.
  • the lead contacts and ball grid bonding contacts are connected one-to-one via traces inside the BGA chip substrate.
  • the segmented connecting leads include: a substrate-end lead, which is a rigid lead and includes an upright section and a horizontal section; the upright section of the substrate-end lead is perpendicular to the surface of the BGA chip substrate and is connected to the lead contacts; and a chip-end lead, which is a flexible lead, with one end connected to the BGA chip body and the other end detachably connected to the horizontal section of the substrate-end lead.
  • the chip-end lead is adapted to separate from the substrate-end lead under external force and to spring back to its original position after the external force is removed.
  • the chip-side leads and substrate-side leads can be separated by external force, and the substrate-side leads can be connected separately for testing the lead contacts and their connected ball grid solder joints.
  • the chip-side leads on one side of the chip are disconnected, the chip side will not affect or interfere with the test, nor will the test damage the chip.
  • the connection can be springbacked back after the test, without affecting the subsequent normal use of the chip. Therefore, the BGA chip packaging structure provided in this application can solve the problem of difficulty in testing the soldering quality of the ball grid solder joints between BGA chips and PCB chips.
  • the testing method includes the following steps: separating the chip-end leads and the substrate-end leads using external force, connecting the substrate-end leads, and testing the lead contacts; after the test, removing the external force, allowing the chip-end leads to spring back and reconnect with the substrate-end leads.
  • the connecting leads between the chip body and the lead contacts as segmented connecting leads, the chip-end leads and substrate-end leads can be separated, suitable for separation under external force, and suitable for springback reconnection after the external force is removed.
  • the chip-end leads and substrate-end leads can be separated by external force first, and the substrate-end leads can be connected separately for testing the lead contacts. Therefore, since the chip-end leads on one side of the chip are already disconnected during testing, it will not affect the test, nor will the test affect the chip. Furthermore, the chip can spring back and reconnect after the test, without affecting the subsequent normal use of the chip. Therefore, the BGA chip packaging structure provided in this application can solve the problem of difficulty in testing the soldering quality of the ball grid solder joints between the BGA chip and the PCB chip.
  • Figure 1 is a three-dimensional structural diagram of the back of a BGA chip in the related technology
  • Figure 2 is a schematic diagram of the structure when the BGA chip of the related technology is connected to the PCB board;
  • Figure 3 is a top view of the BGA chip of the related technology
  • Figure 4 is a side view of the BGA chip of the related technology.
  • Figure 5 is a schematic diagram of the results of X-ray irradiation test of BGA chip related technologies
  • Figure 6 is a schematic diagram of the segmented connection leads in a BGA chip package structure according to an embodiment of this application.
  • the above figures include the following reference numerals: 100. PCB board; 210. BGA chip substrate; 220. Ball grid solder contact point; 230. BGA chip body; 240. Lead contact; 251. Chip-end lead; 252. Substrate-end lead; 260. Support filler layer; 270. Encapsulation layer; 271. Test probe hole; 272. Elastic plastic; 280. Peel-off probe; 290. Test probe.
  • the BGA packaged chip includes a BGA chip substrate 210.
  • the bottom surface of the BGA chip substrate 210 has ball grid solder contacts 220 for connection to the PCB board 100.
  • the top surface of the BGA chip substrate 210 has a BGA chip body 230 and lead contacts 240 surrounding the BGA chip body 230.
  • the BGA chip body 230 is connected to the lead contacts 240 via connecting leads on its surface facing away from the BGA chip substrate 210.
  • the lead contacts 240 and the ball grid solder contacts 220 are connected one-to-one via internal traces within the BGA chip substrate 210.
  • the BGA chip body connects to the PCB board's wiring via leads-lead contacts-ball grid solder contacts, accessing the circuit and transmitting signals through this path during operation. Because the ball grid solder contacts 220 are obscured by the BGA chip substrate 210, direct contact measurement is difficult. If measurement is taken directly from the lead contact 240 side, it's difficult to determine whether the result obtained is from the lead contact-ball gate solder contact side or the lead contact-chip body side, since the lead contact 240 is also connected to the BGA chip body 230. Furthermore, the test results may be interfered with by the lead connection to the chip body, or the presence of the lead connection during testing may adversely affect the internal components of the chip body. Therefore, the soldering quality of the ball gate solder contact 220 is difficult to measure directly.
  • this application provides a BGA chip packaging structure and testing method.
  • the BGA chip packaging structure includes: a BGA chip substrate; ball grid soldering contacts are provided on the bottom surface of the BGA chip substrate for connection to a PCB board; a BGA chip body and lead contacts surrounding the BGA chip body are provided on the top surface of the BGA chip substrate; the BGA chip body is connected to the lead contacts via segmented connecting leads on its surface facing away from the BGA chip substrate; the lead contacts and ball grid soldering contacts are connected one-to-one via traces inside the BGA chip substrate; wherein, the segmented connecting leads include: a substrate end lead; the substrate end lead is a rigid lead, including an upright section and a horizontal section; the upright section of the substrate end lead is perpendicular to the surface of the BGA chip substrate and is connected to the lead contacts; a chip end lead; the chip end lead is a flexible lead, one end of which is connected to the BGA chip body, and the other end is detachably connected to the horizontal section of the substrate end lead; the chip end lead is suitable for separation from
  • test method for the BGA chip package structure includes the following steps: using external force to separate the chip end lead and the substrate end lead, connecting the substrate end lead, and testing the lead contact; after the test is completed, removing the external force, allowing the chip end lead to spring back and reconnect with the substrate end lead.
  • this application provides a BGA chip package structure, including:
  • the BGA chip substrate 210 is provided with ball grid soldering contacts 220 for connection with the PCB board; the top surface of the BGA chip substrate 210 is provided with a BGA chip body 230 and lead contacts 240 surrounding the BGA chip body 230; the lead contacts 240 and the ball grid soldering contacts 220 are connected one-to-one by the internal wiring of the BGA chip substrate 210; the BGA chip body 230 is connected to the lead contacts 240 by segmented connecting leads on its surface facing away from the BGA chip substrate 210; wherein
  • the segmented connection leads include: a substrate end lead 252; the substrate end lead 252 is a rigid lead, including an upright section and a horizontal section; the upright section of the substrate end lead 252 is perpendicular to the surface of the BGA chip substrate 210 and is connected to the lead contact 240; a chip end lead 251; the chip end lead 251 is a flexible lead, one end of which is connected to the BGA chip body 230, and
  • the BGA chip packaging structure provided in this application includes a BGA chip body 230 and lead contacts 240 surrounding the BGA chip body 230 on the top surface of the BGA chip substrate 210.
  • the BGA chip body 230 is connected to the lead contacts 240 via segmented connecting leads on its surface facing away from the BGA chip substrate 210.
  • the segmented connecting leads include: a substrate end lead 252, which is a rigid lead and includes an upright section and a horizontal section.
  • the upright section of the substrate end lead 252 is perpendicular to the surface of the BGA chip substrate 210 and is connected to the lead contacts 240; and a chip end lead 251, which is a flexible lead.
  • the chip end lead 251 is connected to the BGA chip body 230, and the other end is detachably connected to the horizontal section of the substrate end lead 252.
  • the chip end lead 251 is adapted to separate from the substrate end lead 252 under external force and is adapted to spring back to its original position after the external force is removed.
  • the connection leads between the chip body and the lead contacts 240 as segmented leads, the chip-side lead 251 and the substrate-side lead 252 can be separated. This allows for separation under external force and springback reconnection after the force is removed.
  • the chip-side lead 251 and substrate-side lead 252 can be separated by external force, and the substrate-side lead 252 can be connected separately for testing the lead contacts 240. Since the chip-side lead 251 on one side of the chip is disconnected during testing, it does not affect the test or the chip itself. Furthermore, the connection can spring back after testing, without affecting the chip's subsequent normal use. Therefore, the BGA chip packaging structure provided in this application solves the problem of difficulty in testing the soldering quality of the ball grid solder joints 220 between the BGA chip and the PCB chip.
  • the radial dimension of the substrate end lead 252 is larger than the radial dimension of the chip end lead 251. Since the chip end lead 251 is the moving end when separated, making the substrate end lead 252, which is the stationary end, relatively slightly larger can reduce the difficulty of reconnecting the two during elastic recovery and reduce the probability of failure to reconnect due to misalignment during reconnection.
  • the horizontal segment of the substrate end lead 252 is a flat sheet to reduce the difficulty of restoring the connection with the chip end lead 251 during elastic recovery.
  • the BGA chip packaging structure further includes: a supporting filler layer 260; the supporting filler layer 260 is disposed on the top surface of the BGA chip substrate 210, surrounding the side of the BGA chip body 230; the horizontal section of the substrate end lead 252 and the portion of the chip end lead 251 exposed in the BGA chip body 230 are located on the surface of the supporting filler layer 260 facing away from the BGA chip substrate 210; the supporting filler layer 260 is an elastic adhesive layer suitable for allowing the chip end lead 251 to elastically return to the connected state after the external force is removed after the substrate end lead 252 is disconnected.
  • the filler layer itself has a certain degree of elasticity and compressibility, it normally acts as a support layer supporting the horizontal section of the chip end lead 251 and the substrate end lead 252. During testing, it deforms along with the chip end lead 251 under pressure, and when the external force is removed, its own elastic force helps the chip end lead 251 elastically return to the connected state with the substrate end lead 252. This allows for a separable connection between the two.
  • the BGA chip packaging structure further includes: an encapsulating adhesive layer 270; the encapsulating adhesive layer 270 is disposed on the top surface of the BGA chip substrate 210, surrounding and covering the BGA chip body 230, lead contacts 240, supporting filler adhesive layer 260, and segmented connecting leads.
  • the encapsulating adhesive layer protects the surface structure of the BGA packaging substrate from moisture erosion and physical damage.
  • the BGA chip packaging structure also includes a release probe 280; the release probe 280 is movably disposed in the encapsulating adhesive layer 270, adapted to contact the chip end lead 251, thereby separating the chip end lead 251 from the substrate end lead 252.
  • the release probe 280 By providing the release probe 280, external force can be easily applied to the chip end lead 251 to achieve separation from the substrate end lead 252.
  • the encapsulating adhesive layer 270 is provided with a release probe hole, which penetrates the encapsulating adhesive layer 270 in the thickness direction, exposing the chip terminal lead 251; the release probe 280 is disposed in the release probe hole and is adapted to move along the extension direction of the release probe hole. This facilitates the separation of the chip terminal lead 251 from the substrate terminal lead 252 by the release probe 280 with minimal displacement, minimizing lead displacement during the separation process, reducing the difficulty of reconnection, and lowering the probability of reconnection failure.
  • the end of the stripping probe 280 furthest from the chip lead 251 is an inverted cone structure; the opening of the stripping probe hole is funnel-shaped; and elastic plastic 272 is filled between the stripping probe and the stripping probe hole, with the elastic plastic 272 located at least between the conical surface of the inverted cone of the stripping probe and the wall surface of the funnel-shaped opening of the stripping probe hole.
  • the end of the inverted cone facilitates the application of force to the probe, reducing the difficulty of displacement of the stripping probe 280.
  • the size difference between the stripping probe 280 and the diameter of the stripping probe hole at any corresponding position is greater than 0.1 mm and less than 0.5 mm. If the size difference is less than 0.1 mm, there is essentially no room for the probe to move, making it difficult to achieve probe pressing down and lifting reset; if the size difference is greater than 0.5 mm, the probe has too much room to move within the hole, making it prone to loosening, and the probability of failure to separate the chip-end lead and the substrate-end lead due to deviation in the pressing direction is too high. Therefore, a size difference within the range of greater than 0.1 mm and less than 0.5 mm can achieve a balance between sufficient room for movement and not too much room for movement.
  • the BGA chip packaging structure also includes a test probe 290; the test probe 290 is movably disposed in the encapsulating adhesive layer 270, adapted to contact the horizontal segment of the substrate end lead 252, and connect to the substrate end lead 252 to test the lead contact 240.
  • the test probe 290 By setting the test probe 290, it is easy to make contact with the horizontal segment of the substrate end lead 252 for connection testing.
  • the encapsulating adhesive layer 270 is provided with a test probe hole 271, which penetrates the encapsulating adhesive layer 270 in the thickness direction, exposing the horizontal segment of the substrate end lead 252; the test probe 290 is disposed in the test probe hole 271 and is adapted to move along the extension direction of the test probe hole 271.
  • the provision of the test probe hole 271 facilitates the test probe 290 to make contact with the substrate end lead 252 with minimal displacement, minimizing lead displacement during the contact process, reducing the difficulty of reconnection, and lowering the probability of reconnection failure.
  • the end of the test probe 290 furthest from the substrate lead 252 is an inverted cone structure; the opening of the test probe hole 271 is funnel-shaped; and elastic plastic is filled between the test probe 290 and the test probe hole 271, with the elastic plastic located at least between the conical surface of the inverted cone of the test probe and the wall surface of the funnel-shaped opening of the test probe hole.
  • the end of the inverted cone facilitates the application of force to the probe, reducing the difficulty of displacement of the test probe 290.
  • the elastic plastic combined with the funnel-shaped opening of the test probe hole 271, can assist in applying a rebound force in all directions, minimizing deviation during probe reset, and thus minimizing possible offset or deformation of the substrate lead due to changes in the substrate conditions. This reduces the difficulty of elastically restoring the connection between the substrate lead 252 and the chip lead 251, and reduces the probability of connection failure due to offset during the restoration process.
  • the size difference between the test probe and the diameter of the test probe hole at any corresponding position is greater than 0.1 mm and less than 0.5 mm, for example, it can be 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, or 0.5 mm. If the size difference is less than 0.1 mm, there is basically no room for the probe to move, making it difficult to achieve probe pressing down and lifting reset; if the size difference is greater than 0.5 mm, the probe has too much room to move within the hole, making it prone to loosening, and the probability of failure to separate the chip-end lead and the substrate-end lead due to deviation in the pressing direction is too high. Therefore, a size difference within the range of greater than 0.1 mm and less than 0.5 mm can achieve a balance between sufficient room for movement and not too much room for movement.
  • the distance between the test probe hole and the stripping probe hole is 0.5mm to 1.5mm, for example, it can be 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, or 1.5mm.
  • the distance between the test probe hole and the stripping probe hole is less than 0.1mm, on the one hand, the distance is too small to process, and on the other hand, when operating the stripping probe and the test probe simultaneously, they are prone to squeezing each other's operating space, making the operation too difficult; if the distance is greater than 0.5mm, the stripping probe is too close to the chip end, which can easily lead to insufficient force, and the chip end lead is not completely separated from the substrate end lead, resulting in deviation in the test results. Therefore, a distance of 0.5mm to 1.5mm between the test probe hole and the stripping probe hole can achieve a balance between lower processing difficulty, lower operation difficulty, and meeting the force application conditions.
  • the spacing between adjacent lead contacts is 0.5mm to 1.5mm, for example, it can be 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, or 1.5mm. If the spacing between adjacent lead contacts is too small, crosstalk is likely to occur, and testing between adjacent contacts can easily encroach on each other's operating space; if the spacing is too large, it will affect the chip size. Therefore, a spacing between adjacent lead contacts within the range of 0.5mm to 1.5mm can achieve a balance between avoiding crosstalk, facilitating testing, and chip miniaturization.
  • the elastic plastic filling between the peeling probe and the peeling probe hole has an allowable elastic deformation of greater than 0.3 mm and less than 0.5 mm when the peeling probe is pressed down; for example, it can be 0.3 mm, 0.4 mm, or 0.5 mm.
  • the elastic plastic filling between the test probe and the test probe hole also has an allowable elastic deformation of greater than 0.3 mm and less than 0.5 mm when the test probe is pressed down; for example, it can be 0.3 mm, 0.4 mm, or 0.5 mm.
  • the allowable elastic deformation is the deformation that the elastic plastic and the support filling layer can undergo at the pressing position during the probe being pressed down.
  • the above-mentioned deformation range can achieve a balance between meeting the requirements of complete separation and meeting the requirements of connection recovery.
  • the BGA chip packaging structure includes an encapsulating adhesive layer 270; the encapsulating adhesive layer 270 is disposed on the top surface of the BGA chip substrate 210, surrounding and covering the BGA chip body 230, lead contacts 240, and segmented connecting leads; the BGA chip packaging structure also includes a peeling probe; the peeling probe is movably disposed in the encapsulating adhesive layer 270, adapted to contact the chip end lead 251, so that the chip end lead 251 is separated from the substrate end lead 252; the testing method includes: before connecting the substrate end lead 252, pressing down the peeling probe to separate the chip end lead 251 from the substrate end lead 252; after the test is completed, releasing the peeling probe, so that the chip end lead 251 springs back and reconnects with the substrate end lead 252.
  • the BGA chip packaging structure includes an encapsulating adhesive layer 270; the encapsulating adhesive layer 270 is disposed on the top surface of the BGA chip substrate 210, surrounding and covering the BGA chip body 230, lead contacts 240, and segmented connecting leads; the BGA chip packaging structure also includes a test probe; the test probe is movably disposed in the encapsulating adhesive layer 270, adapted to contact the horizontal segment of the substrate end lead 252, and connects the substrate end lead 252 to test the lead contacts 240; the testing method includes: after the substrate end lead 252 is separated from the chip end lead 251, pressing down the test probe, connecting the horizontal segment of the substrate end lead 252, and connecting the lead contacts 240 through the substrate end lead 252 to perform the test.
  • the pressure of the stripping probe is 1N to 3N, for example, 1N, 2N, or 3N. If the pressure is less than 1N, the probe travels too short a distance, resulting in insufficient force on the chip-end lead and incomplete separation; if the pressure is greater than 3N, the probe travels too far, and when the pressure is removed and the elastic recovery occurs, it is easy to misalign, resulting in connection restoration failure. Therefore, a pressure of 1N to 3N for the stripping probe can achieve a balance between the lead separation requirement and the lead restoration requirement.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

本申请涉及芯片封装及测试技术领域，具体涉及一种BGA芯片封装结构和测试方法。BGA芯片封装结构包括：BGA芯片基板，底面设置有球栅焊接触点，顶面设置有BGA芯片主体和环绕BGA芯片主体设置的引线触点；BGA芯片主体通过自身背向BGA芯片基板一侧表面的分段式连接引线连接引线触点；引线触点和球栅焊接触点通过BGA芯片基板内部的走线一一对应连接；分段式连接引线包括：基板端引线和芯片端引线，芯片端引线适于在外力作用下与基板端引线分离，且适于在外力撤除后回弹恢复连接。本申请的制造方法可以制造深度方向孔径一致的直通孔。本申请可解决BGA芯片与PCB芯片间的球栅焊接触点难以测试焊接质量的问题。

Description

BGA芯片封装结构和测试方法
相关申请的交叉引用
本申请要求于2024年6月28日提交中国专利局，申请号为202410853953.6，申请名称为“一种BGA芯片封装结构和测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片封装及测试技术领域，特别的，涉及一种BGA芯片封装结构和测试方法。
背景技术
服务器是由大量运算、存储、管理芯片组成的超级复杂的系统，需要PCB(Printed Circuit Board)板作为支撑将众多功能模块之间联系起来。伴随云计算技术的发展，网络服务器芯片处理的信号的速率成倍增长，芯片计算的速度同比增长，功耗也随之增加。服务器机箱结构不能盲目扩大，要满足行业标准，因此服务器机箱内部的空间有限。PCB板的面积不增加，但不断新增的电子器件、连接器等都要有序的设置在PCB板表面，行业内为解决此问题引入大量BGA封装的芯片来缩小芯片在PCB板上占用的面积。由此带来一些难以解决的问题，具体的：芯片与PCB板上对应的触点之间用焊锡形成球栅焊接触点实现连接，在进行焊接质量确认、阻抗测试时都不能直接对芯片端的触点进行测量。通常情况下这些触点的测试都是通过其他间接的手段进行，如焊接质量确认通过照X光进行非破坏性测试(如图5所示)或者通过破坏性试验将芯片磨平露出焊锡进行确认；阻抗测试只能确认PCB端的触点，焊锡到芯片的球栅焊接触点部分只能通过仿真确认，或者在PCB板上预留测试点，通过预留测试点测试，不能直接测试其焊接质量。BGA(Ball Grid Array)芯片下方的触点如果不通过焊锡在PCB板上预留测试点，则无法测量，给设计验证带来很多困扰。
发明内容
有鉴于此，本申请提供一种BGA芯片封装结构和测试方法，解决BGA芯片与PCB芯片间的球栅焊接触点难以测试焊接质量的问题。
根据本申请的第一方面，提供一种BGA芯片封装结构，包括：BGA芯片基板；BGA芯片基板底面设置有球栅焊接触点，用于与PCB板连接；BGA芯片基板顶面设置有BGA芯片主体和环绕BGA芯片主体设置的引线触点；BGA芯片主体通过自身背向BGA芯片基板一侧表面的分段式连接引线连接引线触点；引线触点和球栅焊接触点通过BGA芯片基板内部的走线一一对应连接；其中，分段式连接引线包括：基板端引线；基板端引线为硬质引线，包括直立段和水平段；基板端引线的直立段垂直于BGA芯片基板表面，与引线触点连接；芯片端引线；芯片端引线为软质引线，一端连接BGA芯片主体，另一端可分离的连接基板端引线的水平段；芯片端引线适于在外力作用下与基板端引线分离，且适于在外力撤除后回弹恢复连接。
在一个实施方式中，BGA芯片封装结构还包括：支撑填充胶层；支撑填充胶层设置于BGA芯片基板顶面，包围BGA芯片主体的侧部；基板端引线的水平段和芯片端引线露出BGA芯片主体的部分位于支撑填充胶层背向BGA芯片基板一侧表面；支撑填充胶层为弹性胶层适于使芯片端引线与基板端引线断开后，在外力撤去后弹性回复至连接状态。
在一个实施方式中，BGA芯片封装结构还包括：封装胶层；封装胶层设置于BGA芯片基板顶面，包围并覆盖BGA芯片主体、引线触点、支撑填充胶层和分段式连接引线。剥离探针；剥离探针可活动的设置于封装胶层中，适于抵触芯片端引线，使芯片端引线与基板端引线分离。封装胶层设置有剥离探针孔，剥离探针孔在厚度方向上贯穿封装胶层，暴露芯片端引线；剥离探针设置于剥离探针孔中，适于沿剥离探针孔的延伸方向移动。
在一个实施方式中，剥离探针远离芯片端引线一端为倒椎体结构；剥离探针孔的开口呈漏斗状开口；剥离探针与剥离探针孔之间填充有弹性塑胶，弹性塑胶至少位于剥离探针的倒椎体的锥面与剥离探针孔的漏斗状开口的壁面之间。
在一个实施方式中，剥离探针的尺寸与剥离探针孔的孔径之间，在任意对应位置处的尺寸差大于0.1mm且小于0.5mm。
在一个实施方式中，BGA芯片封装结构还包括：测试探针；测试探针可活动的设置于封装胶层中，适于抵触基板端引线的水平段，连接基板端引线对引线触点进行测试。封装胶层设置有测试探针孔，测试探针孔在厚度方向上贯穿封装胶层，暴露基板端引线的水平段；测试探针设置于测试探针孔中，适于沿测试探针孔的延伸方向移动。
在一个实施方式中，测试探针远离基板端引线一端为倒椎体结构；测试探针孔的开口呈漏斗状开口；测试探针与测试探针孔之间填充有弹性塑胶，弹性塑胶至少位于测试探针的倒椎体的锥面与测试探针孔的漏斗状开口的壁面之间。
在一个实施方式中，测试探针的尺寸与测试探针孔的孔径之间，在任意对应位置处的尺寸差大于0.1mm且小于0.5mm。
在一个实施方式中，测试探针孔与剥离探针孔之间的间距为0.5mm至1.5mm。
在一个实施方式中，相邻引线触点之间的间距为0.5mm～1.5mm。
在一个实施方式中，剥离探针与剥离探针孔之间填充的弹性塑胶，在剥离探针下压时的容许弹性形变量大于0.3mm小于0.5mm；测试探针与测试探针孔之间填充的弹性塑胶，在测试探针下压时的容许弹性形变量大于0.3mm小于0.5mm；支撑填充胶层在剥离探针下压时容许的弹性形变量大于0.3mm小于0.5mm。
根据本申请的第二方面，还提供一种BGA芯片封装结构的测试方法，BGA芯片封装结构为如本申请提供的BGA芯片封装结构；测试方法包括以下步骤：使用外力将芯片端引线和基板端引线分离，连接基板端引线，测试引线触点；测试完成后，撤除外力，使芯片端引线回弹与基板端引线恢复连接。
在一个实施方式中，BGA芯片封装结构包括封装胶层；封装胶层设置于BGA芯片基板顶面，包围并覆盖BGA芯片主体、引线触点和分段式连接引线；BGA芯片封装结构还包括，剥离探针；剥离探针可活动的设置于封装胶层中，适于抵触芯片端引线，使芯片端引线与基板端引线分离；测试方法包括：连接基板端引线前，下压剥离探针，使芯片端引线与基板端引线分离；测试完成后，松开剥离探针，使芯片端引线回弹与基板端引线恢复连接。
在一个实施方式中，BGA芯片封装结构包括封装胶层；封装胶层设置于BGA芯片基板顶面，包围并覆盖BGA芯片主体、引线触点和分段式连接引线；BGA芯片封装结构还包括，测试探针；测试探针可活动的设置于封装胶层中，适于抵触基板端引线的水平段，连接基板端引线对引线触点进行测试；测试方法包括：在基板端引线与芯片端引线分离后，下压测试探针，连接基板端引线的水平段，通过基板端引线连接引线触点进行测试。
在一个实施方式中，下压剥离探针，使芯片端引线与基板端引线分离的步骤中，下压剥离探针的压力为1N～3N。
本申请的有益效果在于：
本申请提供的BGA芯片封装结构，BGA芯片基板顶面设置有BGA芯片主体和环绕BGA芯片主体设置的引线触点；BGA芯片主体通过自身背向BGA芯片基板一侧表面的分段式连接引线连接引线触点；引线触点和球栅焊接触点通过BGA芯片基板内部的走线一一对应连接；其中，分段式连接引线包括：基板端引线；基板端引线为硬质引线，包括直立段和水平段；基板端引线的直立段垂直于BGA芯片基板表面，与引线触点连接；芯片端引线；芯片端引线为软质引线，一端连接BGA芯片主体，另一端可分离的连接基板端引线的水平段；芯片端引线适于在外力作用下与基板端引线分离，且适于在外力撤除后回弹恢复。通过将芯片主体与引线触点之间的连接引线设置为分段式连接引线，芯片端引线和基板端引线可分离的连接，适于在外力作用下分离，且适于在外力撤除后回弹恢复连接，可以在测试触点的焊接质量时，先将芯片端引线与基板端引线使用外力分离，单独连接基板端引线，对引线触点及其连接的球栅焊接触点进行测试。在测试时由于芯片一侧的芯片端引线已经断开，芯片一侧不会影响和干扰测试，也不会因测试对芯片造成影响。同时在测试后可以回弹恢复连接，不影响芯片后续正常使用。由此，本申请提供的BGA芯片封装结构可以解决BGA芯片与PCB芯片间的球栅焊接触点难以测试焊接质量的问题。
本申请提供一种BGA芯片封装结构和封装方法，使用本申请提供的BGA芯片封装结构，测试方法包括以下步骤：使用外力将芯片端引线和基板端引线分离，连接基板端引线，测试引线触点；测试完成后，撤除外力，使芯片端引线回弹与基板端引线恢复连接。通过将芯片主体与引线触点之间的连接引线设置为分段式连接引线，芯片端引线和基板端引线可分离的连接，适于在外力作用下分离，且适于在外力撤除后回弹恢复连接，可以在测试引线触点的焊接质量时，先将芯片端引线与基板端引线使用外力分离，单独连接基板端引线，对引线触点进行测试，从而在测试时由于芯片一侧的芯片端引线已经断开，不会影响测试，也不会因测试对芯片造成影响。并且在测试后可以回弹恢复连接，不影响芯片后续正常使用。由此，本申请提供的BGA芯片封装结构可以解决BGA芯片与PCB芯片间的球栅焊接触点难以测试焊接质量的问题。
附图说明
为了更清楚地说明本申请具体实施方式或相关技术中的技术方案，下面将对具体实施方式或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术的BGA芯片的背面的立体结构示意图；
图2为相关技术的BGA芯片与PCB板连接时的结构示意图；
图3为相关技术的BGA芯片的俯视结构示意图；
图4为相关技术的BGA芯片的侧视结构示意图；
图5为相关技术的BGA芯片X光照射测试的结果示意图；
图6为本申请一实施例的BGA芯片封装结构中分段式连接引线处的结构示意图。
其中，上述附图包括以下附图标记：
100、PCB板；210、BGA芯片基板；220、球栅焊接触点；230、BGA芯片主体；
240、引线触点；251、芯片端引线；252、基板端引线；260、支撑填充胶层；270、封装胶层；271、测试探针孔；272、弹性塑胶；280、剥离探针；290、测试探针。
具体实施方式
参考图1-图4，BGA封装的芯片包括BGA芯片基板210，BGA芯片基板210底面设置有球栅焊接触点220，用于与PCB板100连接；BGA芯片基板210顶面设置有BGA芯片主体230和环绕BGA芯片主体230设置的引线触点240；BGA芯片主体230通过自身背向BGA芯片基板210一侧表面的连接引线连接引线触点240；引线触点240和球栅焊接触点220通过BGA芯片基板210内部的走线一一对应连接。如此，BGA芯片主体通过引线-引线触点-球栅焊接触点连接PCB板上的连接线路，接入电路，工作时，通过这一路径传输信号。由于球栅焊接触点220被BGA芯片基板210遮挡，难以直接接触测量。如直接从引线触点240一侧接触测量，由于引线触点240同时有引线连接BGA芯片主体230，因此一方面难以确认得到的结果具体是引线触点-球栅焊接触点一侧的结果，还是引线触点-芯片主体一侧的结果。另一方面，测试结果也会由于引线连接芯片主体一端，可能对结果造成干扰，或者，由于测试时存在引线连接，测试时可能对芯片主体内部的器件产生不良影响。因此球栅焊接触点220的焊接质量，难以直接测量。
为解决BGA芯片与PCB芯片间的球栅焊接触点难以测试焊接质量的问题，本申请提供一种BGA芯片封装结构和测试方法。
本申请提供的BGA芯片封装结构，包括：BGA芯片基板；BGA芯片基板底面设置有球栅焊接触点，用于与PCB板连接；BGA芯片基板顶面设置有BGA芯片主体和环绕BGA芯片主体设置的引线触点；BGA芯片主体通过自身背向BGA芯片基板一侧表面的分段式连接引线连接引线触点；引线触点和球栅焊接触点通过BGA芯片基板内部的走线一一对应连接；其中，分段式连接引线包括：基板端引线；基板端引线为硬质引线，包括直立段和水平段；基板端引线的直立段垂直于BGA芯片基板表面，与引线触点连接；芯片端引线；芯片端引线为软质引线，一端连接BGA芯片主体，另一端可分离的连接基板端引线的水平段；芯片端引线适于在外力作用下与基板端引线分离，且适于在外力撤除后回弹恢复连接。
本申请提供的BGA芯片封装结构的测试方法，BGA芯片封装结构为如本申请提供的BGA芯片封装结构；测试方法包括以下步骤：使用外力将芯片端引线和基板端引线分离，连接基板端引线，测试引线触点；测试完成后，撤除外力，使芯片端引线回弹与基板端引线恢复连接。
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。在本申请的描述中，需要说明的是，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
实施例1
参考图6以及图3和图4，本申请提供一种BGA芯片封装结构，包括：
BGA芯片基板210；BGA芯片基板210底面设置有球栅焊接触点220，用于与PCB板连接；BGA芯片基板210顶面设置有BGA芯片主体230和环绕BGA芯片主体230设置的引线触点240；引线触点240和球栅焊接触点220通过BGA芯片基板210内部的走线一一对应连接；BGA芯片主体230通过自身背向BGA芯片基板210一侧表面的分段式连接引线连接引线触点240；其中，分段式连接引线包括：基板端引线252；基板端引线252为硬质引线，包括直立段和水平段；基板端引线252的直立段垂直于BGA芯片基板210表面，与引线触点240连接；芯片端引线251；芯片端引线251为软质引线，一端连接BGA芯片主体230，另一端可分离的连接基板端引线252的水平段；芯片端引线251适于在外力作用下与基板端引线252分离，且适于在外力撤除后回弹恢复连接。
本申请提供的BGA芯片封装结构，BGA芯片基板210顶面设置有BGA芯片主体230和环绕BGA芯片主体230设置的引线触点240；BGA芯片主体230通过自身背向BGA芯片基板210一侧表面的分段式连接引线连接引线触点240；其中，分段式连接引线包括：基板端引线252；基板端引线252为硬质引线，包括直立段和水平段；基板端引线252的直立段垂直于BGA芯片基板210表面，与引线触点240连接；芯片端引线251；芯片端引线251为软质引线，一端连接BGA芯片主体230，另一端可分离的连接基板端引线252的水平段；芯片端引线251适于在外力作用下与基板端引线252分离，且适于在外力撤除后回弹恢复。通过将芯片主体与引线触点240之间的连接引线设置为分段式连接引线，芯片端引线251和基板端引线252可分离的连接，适于在外力作用下分离，且适于在外力撤除后回弹恢复连接，可以在测试引线触点240的焊接质量时，先将芯片端引线251与基板端引线252使用外力分离，单独连接基板端引线252，对引线触点240进行测试，从而在测试时由于芯片一侧的芯片端引线251已经断开，不会影响测试，也不会因测试对芯片造成影响。并且在测试后可以回弹恢复连接，不影响芯片后续正常使用。由此，本申请提供的BGA芯片封装结构可以解决BGA芯片与PCB芯片间的球栅焊接触点220难以测试焊接质量的问题。
在一些实施例中，基板端引线252的径向尺寸大于芯片端引线251的径向尺寸。由于分离时芯片端引线251为移动端，使作为静止端的基板端引线252尺寸相对略大，可降低弹性恢复时两者恢复连接的难度，减少恢复连接时偏移造成恢复连接失败的几率。
或者，在其他一些实施例中，基板端引线252的水平段为扁平片状，以降低弹性恢复时与芯片端引线251的恢复连接的难度。
进一步的，在本实施例中，BGA芯片封装结构还包括：支撑填充胶层260；支撑填充胶层260设置于BGA芯片基板210顶面，包围BGA芯片主体230的侧部；基板端引线252的水平段和芯片端引线251露出BGA芯片主体230的部分位于支撑填充胶层260背向BGA芯片基板210一侧表面；支撑填充胶层260为弹性胶层适于使芯片端引线251与基板端引线252断开后，在外力撤去后弹性回复至连接状态。由于填充胶层本身具有一定弹性和可压缩性，平时作为支撑层支撑芯片端引线251和基板端引线252的水平段，测试时受压力随芯片端引线251一起变形，当外力撤去时自身恢复形状的弹力支撑芯片端引线251弹性恢复至与基板端引线252连接的状态。从而可以实现两者可分离的连接。
进一步的，在本实施例中，BGA芯片封装结构还包括：封装胶层270；封装胶层270设置于BGA芯片基板210顶面，包围并覆盖BGA芯片主体230、引线触点240、支撑填充胶层260和分段式连接引线。封装胶层对BGA封装基板表面的结构进行保护，避免水汽的侵蚀和物理性的外力损伤。
进一步的，在本实施例中，BGA芯片封装结构还包括：剥离探针280；剥离探针280可活动的设置于封装胶层270中，适于抵触芯片端引线251，使芯片端引线251与基板端引线252分离。通过设置剥离探针280，可以方便的对芯片端引线251施加外力，实现与基板端引线252的分离。
进一步的，在本实施例中，封装胶层270设置有剥离探针孔，剥离探针孔在厚度方向上贯穿封装胶层270，暴露芯片端引线251；剥离探针280设置于剥离探针孔中，适于沿剥离探针孔的延伸方向移动。可以便于剥离探针280以最小的位移实现芯片端引线251与基板端引线252的分离，使分离过程的引线位移尽量小，减少恢复连接的难度，降低恢复连接失败的几率。
进一步的，在本实施例中，剥离探针280远离芯片端引线251一端为倒椎体结构；剥离探针孔的开口呈漏斗状开口；剥离探针与剥离探针孔之间填充有弹性塑胶272，弹性塑胶272至少位于剥离探针的倒椎体的锥面与剥离探针孔的漏斗状开口的壁面之间。倒椎体的端头便于向探针施力，降低剥离探针280位移的难度。同时，配合剥离探针孔的漏斗状开口，设置弹性塑胶272，可以全方向的辅助施加回弹力，使探针的复位尽可能的不发生偏向，从而可以降低芯片端引线251弹性恢复连接的难度，降低恢复过程中发生偏移导致恢复连接失败的几率。
进一步的，在本实施例中，剥离探针280的尺寸与剥离探针孔的孔径之间，在任意对应位置处的尺寸差大于0.1mm且小于0.5mm。若尺寸差小于0.1mm，则基本没有探针的活动空间，难以实现探针的下压和上抬复位；若尺寸差大于0.5mm，则探针在孔内活动空间过大，容易松动，出现下压方向偏差导致芯片端引线和基板端引线分离失败的几率过大。因此尺寸差在大于0.1mm且小于0.5mm的范围内，可以在足够的活动空间和不过大的活动空间之间取得平衡。
进一步的，在本实施例中，BGA芯片封装结构还包括：测试探针290；测试探针290可活动的设置于封装胶层270中，适于抵触基板端引线252的水平段，连接基板端引线252对引线触点240进行测试。通过设置测试探针290，可以方便的与基板端引线252的水平段实现接触进行连接测试。
进一步的，在本实施例中，封装胶层270设置有测试探针孔271，测试探针孔271在厚度方向上贯穿封装胶层270，暴露基板端引线252的水平段；测试探针290设置于测试探针孔271中，适于沿测试探针孔271的延伸方向移动。通过测试探针孔271的设置，可以便于测试探针290以最小的位移实现与基板端引线252的接触，使接触过程造成的引线位移尽量小，减少恢复连接的难度，降低恢复连接失败的几率。
进一步的，在本实施例中，测试探针290远离基板端引线252一端为倒椎体结构；测试探针孔271的开口呈漏斗状开口；测试探针290与测试探针孔271之间填充有弹性塑胶，弹性塑胶至少位于测试探针的倒椎体的锥面与测试探针孔的漏斗状开口的壁面之间。倒椎体的端头便于向探针施力，降低测试探针290位移的难度。同时，配合测试探针孔271的漏斗状开口，设置弹性塑胶，可以全方向的辅助施加回弹力，使探针的复位尽可能的不发生偏向，进而尽可能的减少基板端引线因受理情况发生变化而可能发生的偏移或变形，从而可以降低基板端引线252与芯片端引线251弹性恢复连接的难度，降低恢复过程中发生偏移导致恢复连接失败的几率。
进一步的，在本实施例中，测试探针的尺寸与测试探针孔的孔径之间，在任意对应位置处的尺寸差大于0.1mm且小于0.5mm，例如可以为0.1mm、0.2mm、0.3mm、0.4mm、0.5mm。若尺寸差小于0.1mm，则基本没有探针的活动空间，难以实现探针的下压和上抬复位；若尺寸差大于0.5mm，则探针在孔内活动空间过大，容易松动，出现下压方向偏差导致芯片端引线和基板端引线分离失败的几率过大。因此尺寸差在大于0.1mm且小于0.5mm的范围内，可以在足够的活动空间和不过大的活动空间之间取得平衡。
进一步的，在本实施例中，测试探针孔与剥离探针孔之间的间距为0.5mm至1.5mm，例如可以为0.5mm、0.6mm、0.7mm、0.8mm、0.9mm、1.0mm、1.1mm、1.2mm、1.3mm、1.4mm、1.5mm。测试探针孔与剥离探针孔之间的间距若小于0.1mm，一方面间距过小难以加工，另一方面同时操作剥离探针和测试探针时容易相互挤压操作空间，使作业难度过大；间距若大于0.5mm，则剥离探针过于靠近芯片端，容易导致施力不够，芯片端引线未与基板端引线完全分离，造成测试结果偏差。因此测试探针孔与剥离探针孔之间的间距为0.5mm至1.5mm，可以在较低的加工难度、作业难度和满足施力条件之间取得平衡。
进一步的，在本实施例中，相邻引线触点之间的间距为0.5mm～1.5mm，例如可以为0.5mm、0.6mm、0.7mm、0.8mm、0.9mm、1.0mm、1.1mm、1.2mm、1.3mm、1.4mm、1.5mm。相邻引线触点之间若间距过小，则容易出现串扰，且进行相邻触点间的测试容易互相挤占操作空间；若间距过大则影响芯片尺寸。因此相邻引线触点之间的间距在0.5mm～1.5mm的范围内，可以在避免串扰，利于测试和芯片小型化之间取得平衡。
进一步的，在本实施例中，剥离探针与剥离探针孔之间填充的弹性塑胶，在剥离探针下压时的容许弹性形变量大于0.3mm小于0.5mm，例如可以为0.3mm、0.4mm、0.5mm。测试探针与测试探针孔之间填充的弹性塑胶，在测试探针下压时的容许弹性形变量大于0.3mm小于0.5mm，例如可以为0.3mm、0.4mm、0.5mm。支撑填充胶层在剥离探针下压时容许的弹性形变量大于0.3mm小于0.5mm，例如可以为0.3mm、0.4mm、0.5mm。容许弹性形变量即探针受力下压的过程中弹性塑胶、支撑填充胶层在下压位置可发生的形变量。若该形变量过小，则探针的可移动距离过短，同时芯片端引线的可移动距离过短，容易发生不完全分离的情况；若该形变量过大，则容易在弹性恢复时对不准基板端引线造成恢复连接失败的情况。因此上述型变量的范围，可以在满足完全分离的要求和满足恢复连接的要求之间取得平衡。
实施例2
本实施例提供一种BGA芯片封装结构的测试方法，BGA芯片封装结构为上述实施例1提供的BGA芯片封装结构；测试方法包括以下步骤：使用外力将芯片端引线251和基板端引线252分离，连接基板端引线252，测试引线触点240；测试完成后，撤除外力，使芯片端引线251回弹与基板端引线252恢复连接。
本申请提供一种BGA芯片封装结构和封装方法，使用本申请提供的BGA芯片封装结构，测试方法包括以下步骤：使用外力将芯片端引线251和基板端引线252分离，连接基板端引线252，测试引线触点240；测试完成后，撤除外力，使芯片端引线251回弹与基板端引线252恢复连接。通过将芯片主体与引线触点240之间的连接引线设置为分段式连接引线，芯片端引线251和基板端引线252可分离的连接，适于在外力作用下分离，且适于在外力撤除后回弹恢复连接，可以在测试引线触点240的焊接质量时，先将芯片端引线251与基板端引线252使用外力分离，单独连接基板端引线252，对引线触点240进行测试，从而在测试时由于芯片一侧的芯片端引线251已经断开，不会影响测试，也不会因测试对芯片造成影响。并且在测试后可以回弹恢复连接，不影响芯片后续正常使用。由此，本申请提供的BGA芯片封装结构可以解决BGA芯片与PCB芯片间的球栅焊接触点220难以测试焊接质量的问题。
进一步的，在本实施例中，BGA芯片封装结构包括封装胶层270；封装胶层270设置于BGA芯片基板210顶面，包围并覆盖BGA芯片主体230、引线触点240和分段式连接引线；BGA芯片封装结构还包括，剥离探针；剥离探针可活动的设置于封装胶层270中，适于抵触芯片端引线251，使芯片端引线251与基板端引线252分离；测试方法包括：连接基板端引线252前，下压剥离探针，使芯片端引线251与基板端引线252分离；测试完成后，松开剥离探针，使芯片端引线251回弹与基板端引线252恢复连接。
进一步的，在本实施例中，BGA芯片封装结构包括封装胶层270；封装胶层270设置于BGA芯片基板210顶面，包围并覆盖BGA芯片主体230、引线触点240和分段式连接引线；BGA芯片封装结构还包括，测试探针；测试探针可活动的设置于封装胶层270中，适于抵触基板端引线252的水平段，连接基板端引线252对引线触点240进行测试；测试方法包括：在基板端引线252与芯片端引线251分离后，下压测试探针，连接基板端引线252的水平段，通过基板端引线252连接引线触点240进行测试。
进一步的，在本实施例中，下压剥离探针，使芯片端引线与基板端引线分离的步骤中，下压剥离探针的压力为1N～3N，例如可以为1N、2N、3N。若压力小于1N，则探针移动距离过短，使得对芯片端引线施力不足，容易发生不完全分离的情况；若压力大于3N，则探针移动距离过大，撤除压力弹性恢复时，容易对不准，发生恢复连接失败的情况。因此下压剥离探针的压力在1N～3N的范围内，可以在引线分离需求和引线恢复连接需求之间取得平衡。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请创造的保护范围之中。

Claims (21)

  1. 一种BGA芯片封装结构，其特征在于，包括：
    BGA芯片基板；所述BGA芯片基板底面设置有球栅焊接触点，被配置为与PCB板连接；所述BGA芯片基板顶面设置有BGA芯片主体和环绕所述BGA芯片主体设置的引线触点；所述BGA芯片主体通过自身背向所述BGA芯片基板一侧表面的分段式连接引线连接所述引线触点；所述引线触点和所述球栅焊接触点通过所述BGA芯片基板内部的走线一一对应连接；
    其中，所述分段式连接引线包括：
    基板端引线；所述基板端引线为硬质引线，包括直立段和水平段；所述基板端引线的所述直立段垂直于所述BGA芯片基板表面，与所述引线触点连接；
    芯片端引线；所述芯片端引线为软质引线，一端连接所述BGA芯片主体，另一端可分离的连接所述基板端引线的所述水平段；
    所述芯片端引线适于在外力作用下与所述基板端引线分离，且适于在外力撤除后回弹恢复连接。
  2. 根据权利要求1所述的BGA芯片封装结构，其特征在于，还包括：
    支撑填充胶层；所述支撑填充胶层设置于所述BGA芯片基板顶面，包围所述BGA芯片主体的侧部；所述基板端引线的水平段和所述芯片端引线露出所述BGA芯片主体的部分位于所述支撑填充胶层背向所述BGA芯片基板一侧表面；所述支撑填充胶层为弹性胶层适于使所述芯片端引线与所述基板端引线断开后，在外力撤去后弹性回复至连接状态。
  3. 根据权利要求2所述的BGA芯片封装结构，其特征在于，还包括：
    封装胶层；所述封装胶层设置于所述BGA芯片基板顶面，包围并覆盖所述BGA芯片主体、所述引线触点、所述支撑填充胶层和所述分段式连接引线；
    剥离探针；所述剥离探针可活动的设置于所述封装胶层中，适于抵触所述芯片端引线，使所述芯片端引线与所述基板端引线分离；
    所述封装胶层设置有剥离探针孔，所述剥离探针孔在厚度方向上贯穿所述封装胶层，暴露所述芯片端引线；所述剥离探针设置于所述剥离探针孔中，适于沿所述剥离探针孔的延伸方向移动。
  4. 根据权利要求3所述的BGA芯片封装结构，其特征在于，
    所述剥离探针远离所述芯片端引线一端为倒椎体结构；和/或
    所述剥离探针孔的开口呈漏斗状开口。
  5. 根据权利要求4所述的BGA芯片封装结构，其特征在于，
    所述剥离探针与所述剥离探针孔之间填充有弹性塑胶，所述弹性塑胶至少位于所述剥离探针的倒椎体的锥面与所述剥离探针孔的漏斗状开口的壁面之间。
  6. 根据权利要求3所述的BGA芯片封装结构，其特征在于，
    所述剥离探针的尺寸与所述剥离探针孔的孔径之间，在任意对应位置处的尺寸差大于0.1mm且小于0.5mm。
  7. 根据权利要求3所述的BGA芯片封装结构，其特征在于，还包括：
    测试探针；所述测试探针可活动的设置于所述封装胶层中，适于抵触所述基板端引线的水平段，连接所述基板端引线对所述引线触点进行测试；
    所述封装胶层设置有测试探针孔，所述测试探针孔在厚度方向上贯穿所述封装胶层，暴露所述基板端引线的水平段；所述测试探针设置于所述测试探针孔中，适于沿所述测试探针孔的延伸方向移动。
  8. 根据权利要求7所述的BGA芯片封装结构，其特征在于，
    所述测试探针远离所述基板端引线一端为倒椎体结构；和/或
    所述测试探针孔的开口呈漏斗状开口。
  9. 根据权利要求7所述的BGA芯片封装结构，其特征在于，
    所述测试探针与所述测试探针孔之间填充有弹性塑胶，所述弹性塑胶至少位于所述测试探针的倒椎体的锥面与所述测试探针孔的漏斗状开口的壁面之间。
  10. 根据权利要求7所述的BGA芯片封装结构，其特征在于，
    所述测试探针的尺寸与所述测试探针孔的孔径之间，在任意对应位置处的尺寸差大于0.1mm且小于0.5mm。
  11. 根据权利要求10所述的BGA芯片封装结构，其特征在于，
    所述测试探针孔与所述剥离探针孔之间的间距为0.5mm至1.5mm。
  12. 根据权利要求1所述的BGA芯片封装结构，其特征在于，
    相邻所述引线触点之间的间距为0.5mm～1.5mm。
  13. 根据权利要求5所述的BGA芯片封装结构，其特征在于，
    所述剥离探针与所述剥离探针孔之间填充的所述弹性塑胶，在所述剥离探针下压时的容许弹性形变量大于0.3mm小于0.5mm。
  14. 根据权利要求9所述的BGA芯片封装结构，其特征在于，
    所述测试探针与所述测试探针孔之间填充的所述弹性塑胶，在所述测试探针下压时的容许弹性形变量大于0.3mm小于0.5mm。
  15. 根据权利要求3所述的BGA芯片封装结构，其特征在于，
    所述支撑填充胶层在所述剥离探针下压时容许的弹性形变量大于0.3mm小于0.5mm。
  16. 根据权利要求1至15中任一项所述的BGA芯片封装结构，其特征在于，所述基板端引线的径向尺寸大于所述芯片端引线的径向尺寸。
  17. 根据权利要求1至15中任一项所述的BGA芯片封装结构，其特征在于，所述基板端引线的水平段为扁平片状。
  18. 一种BGA芯片封装结构的测试方法，其特征在于，所述BGA芯片封装结构为如权利要求1至17任一项所述的BGA芯片封装结构；
    所述测试方法包括以下步骤：
    使用外力将所述芯片端引线和所述基板端引线分离，连接所述基板端引线，测试所述引线触点；
    测试完成后，撤除外力，使所述芯片端引线回弹与所述基板端引线恢复连接。
  19. 根据权利要求18所述的BGA芯片封装结构的测试方法，其特征在于，
    所述BGA芯片封装结构包括封装胶层；所述封装胶层设置于所述BGA芯片基板顶面，包围并覆盖所述BGA芯片主体、所述引线触点和所述分段式连接引线；
    所述BGA芯片封装结构还包括，剥离探针；所述剥离探针可活动的设置于所述封装胶层中，适于抵触所述芯片端引线，使所述芯片端引线与所述基板端引线分离；
    所述测试方法还包括：连接所述基板端引线前，下压所述剥离探针，使所述芯片端引线与所述基板端引线分离；
    测试完成后，松开所述剥离探针，使所述芯片端引线回弹与所述基板端引线恢复连接。
  20. 根据权利要求18所述的BGA芯片封装结构的测试方法，其特征在于，
    所述BGA芯片封装结构包括封装胶层；所述封装胶层设置于所述BGA芯片基板顶面，包围并覆盖所述BGA芯片主体、所述引线触点和所述分段式连接引线；
    所述BGA芯片封装结构还包括，测试探针；所述测试探针可活动的设置于所述封装胶层中，适于抵触所述基板端引线的水平段，连接所述基板端引线对所述引线触点进行测试；
    所述测试方法包括：在所述基板端引线与芯片端引线分离后，下压所述测试探针，连接所述基板端引线的水平段，通过所述基板端引线连接所述引线触点进行测试。
  21. 根据权利要求19所述的BGA芯片封装结构的测试方法，其特征在于，
    下压所述剥离探针，使所述芯片端引线与所述基板端引线分离的步骤中，下压所述剥离探针的压力为1N～3N。
PCT/CN2025/083224 2024-06-28 2025-03-18 Bga芯片封装结构和测试方法 Pending WO2026001111A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410853953.6A CN118398589B (zh) 2024-06-28 2024-06-28 一种bga芯片封装结构和测试方法
CN202410853953.6 2024-06-28

Publications (1)

Publication Number Publication Date
WO2026001111A1 true WO2026001111A1 (zh) 2026-01-02

Family

ID=91985176

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2025/083224 Pending WO2026001111A1 (zh) 2024-06-28 2025-03-18 Bga芯片封装结构和测试方法

Country Status (2)

Country Link
CN (1) CN118398589B (zh)
WO (1) WO2026001111A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118398589B (zh) * 2024-06-28 2024-09-17 苏州元脑智能科技有限公司 一种bga芯片封装结构和测试方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070073233A (ko) * 2006-01-04 2007-07-10 삼성전자주식회사 Ｂｇａ 패키지용 테스트 소켓
US20120182699A1 (en) * 2011-01-14 2012-07-19 Qualcomm Incorporated Modular surface mount package for a system on a chip
CN115332195A (zh) * 2022-10-13 2022-11-11 江苏长电科技股份有限公司 双面SiP封装结构及其制作方法
CN117832099A (zh) * 2024-01-05 2024-04-05 成都电科星拓科技有限公司 一种能够实现双面焊接的bga封装方法
CN118398589A (zh) * 2024-06-28 2024-07-26 苏州元脑智能科技有限公司 一种bga芯片封装结构和测试方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214544B1 (ko) * 1996-12-28 1999-08-02 구본준 볼 그리드 어레이 반도체 패키지
CN105023849A (zh) * 2015-06-18 2015-11-04 长电科技（滁州）有限公司 无基板单层电镀封装结构及其制作方法
CN109801906A (zh) * 2018-12-28 2019-05-24 江苏长电科技股份有限公司 一种Wettable Flank封装结构及其制备方法
CN110692135B (zh) * 2019-06-14 2021-03-19 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备
CN117268250B (zh) * 2023-11-17 2024-02-20 苏州元脑智能科技有限公司 一种pcb板的检测装置、检测方法以及pcb板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070073233A (ko) * 2006-01-04 2007-07-10 삼성전자주식회사 Ｂｇａ 패키지용 테스트 소켓
US20120182699A1 (en) * 2011-01-14 2012-07-19 Qualcomm Incorporated Modular surface mount package for a system on a chip
CN115332195A (zh) * 2022-10-13 2022-11-11 江苏长电科技股份有限公司 双面SiP封装结构及其制作方法
CN117832099A (zh) * 2024-01-05 2024-04-05 成都电科星拓科技有限公司 一种能够实现双面焊接的bga封装方法
CN118398589A (zh) * 2024-06-28 2024-07-26 苏州元脑智能科技有限公司 一种bga芯片封装结构和测试方法

Also Published As

Publication number Publication date
CN118398589B (zh) 2024-09-17
CN118398589A (zh) 2024-07-26

Similar Documents

Publication Publication Date Title
CN100550331C (zh) 螺旋接触器制造方法
JP2710544B2 (ja) プローブ構造、プローブ構造の形成方法
JP4402954B2 (ja) マルチダイ相互接続システムおよびマルチダイ相互接続方法
US6939143B2 (en) Flexible compliant interconnect assembly
WO2026001111A1 (zh) Bga芯片封装结构和测试方法
JP2001281300A (ja) 半導体チップ又はパッケージ検査装置及びその検査方法
JPH1164425A (ja) 電子部品における導通検査方法及び装置
KR101990458B1 (ko) 프로브 카드 및 그 제조방법
JP2004347591A (ja) 集積回路用プローブ・カード
TWI393201B (zh) 探測裝置製造方法
US6703851B1 (en) Test socket interposer
JP2000183483A (ja) 電子部品の検査用基板及びその製造方法並びに電子部品の検査方法
JP3921163B2 (ja) スパイラルコンタクタ及びその製造方法、並びにそれを用いた半導体検査装置、及び電子部品
CN108152544A (zh) 集成电路之测试探针卡
TW202514119A (zh) 測試裝置及測試設備
CN217133316U (zh) 芯片测试工具及芯片测试装置
CN115453438B (zh) 探针卡测试装置
CN100474545C (zh) 用于高频系统级测试的测试板
KR102124550B1 (ko) 전기 특성의 검사 방법
JP3610919B2 (ja) 回路基板の検査用治具、検査方法、および製造方法
JP4486248B2 (ja) プローブカード及びその製造方法
KR101109401B1 (ko) 기판의 코이닝-전기검사 장치
CN115297604A (zh) 一种双层电路板结构及其焊接方法
TWI898794B (zh) 測試轉板模組化結構
KR20120014752A (ko) 기판의 코이닝-전기검사 장치