WO2025191704A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ

Info

Publication number
WO2025191704A1
WO2025191704A1 PCT/JP2024/009640 JP2024009640W WO2025191704A1 WO 2025191704 A1 WO2025191704 A1 WO 2025191704A1 JP 2024009640 W JP2024009640 W JP 2024009640W WO 2025191704 A1 WO2025191704 A1 WO 2025191704A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode layer
region
coverage
internal electrode
opposing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/009640
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
諒 錦織
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to PCT/JP2024/009640 priority Critical patent/WO2025191704A1/ja
Priority to EP24929676.5A priority patent/EP4685832A1/en
Priority to CN202480029716.6A priority patent/CN121039766A/zh
Priority to KR1020257037929A priority patent/KR20250168680A/ko
Priority to JP2025512144A priority patent/JP7816637B2/ja
Publication of WO2025191704A1 publication Critical patent/WO2025191704A1/ja
Priority to US19/347,927 priority patent/US20260031273A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • Multilayer ceramic capacitors are sometimes required to withstand high voltages.
  • a known type of multilayer ceramic capacitor that achieves high voltages is a multilayer ceramic capacitor with a structure in which multiple capacitor sections are connected in series, known as a series structure (see Patent Document 1).
  • the series connection capacitance improves voltage resistance, but reduces capacitance accordingly. However, even in series-structure multilayer ceramic capacitors, there are cases where improved capacitance is required.
  • the object of the present invention is to provide a multilayer ceramic capacitor that can increase capacitance without increasing the size of the multilayer ceramic capacitor, even in high-voltage multilayer ceramic capacitors.
  • the multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in the lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction, a first external electrode arranged on the first end surface, and a second external electrode arranged on the second end surface, wherein the plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, and the first internal electrode layer has a first lead-out portion, one end of which is led out to the first end surface and connected to the first external electrode, and an intermediate electrode layer, one end of which is connected to the first lead-out portion and adjacent to the first external electrode in the lamination direction.
  • the second internal electrode layer has a second extension portion, one end of which is extended to the second end face and connected to the second external electrode, and a second extension portion connected to the second extension portion and facing the internal electrode layer arranged adjacent to it in the stacking direction.
  • the intermediate electrode layer is not connected to either the first external electrode or the second external electrode and is an internal electrode layer that forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer.
  • the coverage of at least a portion of the intermediate electrode layer is higher than the coverage of the area of the first end face side of the first opposing portion of the first internal electrode layer and is also higher than the coverage of the area of the second end face side of the second opposing portion of the second internal electrode layer.
  • the present invention provides a multilayer ceramic capacitor that can increase capacitance without increasing the size of the multilayer ceramic capacitor, even in high-voltage multilayer ceramic capacitors.
  • FIG. 1 is an external perspective view of a dual-structure multilayer ceramic capacitor according to a first embodiment
  • 2 is a cross-sectional view taken along line II-II of FIG. 1, illustrating the schematic configuration of a double-structure laminate according to the first embodiment.
  • FIG. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and is a diagram for mainly explaining the relationship between the thicknesses of the various parts in the double-structure laminate according to the first embodiment.
  • 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a view mainly for explaining the region of the internal electrode layer of the double-structure laminate according to the first embodiment.
  • FIG. FIG. 2B is a cross-sectional view taken along line III-III of FIG. 2A.
  • FIG. 2B is a cross-sectional view taken along the line IVA-IVA in FIG. 2A, along the first internal electrode layer and the second internal electrode layer.
  • 4B is a cross-sectional view taken along the line IVB-IVB of FIG. 2A, taken along the intermediate electrode layer.
  • FIG. 10 is a diagram illustrating an example of an enlarged SEM image of a cross section of an exposed inner layer portion.
  • 1 is a schematic diagram showing a cross section of a dielectric sheet when a conductive paste P1 is printed.
  • FIG. 7 is a schematic diagram showing a cross section of the dielectric sheet when the conductive paste P2 is printed on the dielectric sheet of FIG. 6.
  • FIG. 2 is a schematic diagram showing a portion of a laminate sheet in which a portion that will become a first main surface side outer layer portion and a portion that will become a second main surface side outer layer portion are formed above and below a portion that will become an inner layer portion.
  • FIG. 10 is a diagram for explaining the schematic configuration of a triplet stack according to a second embodiment, and corresponds to FIG. 2A in the first embodiment. 10 is a schematic diagram showing a portion of a laminated sheet in which a portion that will become a first main surface side outer layer portion and a portion that will become a second main surface side outer layer portion are formed above and below a portion that will become an inner layer portion in the second embodiment.
  • FIG. 11 is a schematic diagram for explaining the range of a high coverage portion of a triple-structure laminate according to a third embodiment.
  • FIG. 10 is a schematic diagram showing a portion of a laminated sheet in which a portion that will become a first main surface side outer layer portion and a portion that will become a second main surface side outer layer portion are formed above and below a portion that will become an inner layer portion in the third embodiment.
  • FIG. 10 is a schematic diagram for explaining the range of a high coverage portion of a four-layer structure laminate according to a fourth embodiment.
  • FIG. 13 is a schematic diagram for explaining the range of a high coverage portion of a four-layer structure laminate according to a fifth embodiment.
  • FIG. 10 is a schematic diagram showing a portion of a laminated sheet in which a portion that will become a first main surface side outer layer portion and a portion that will become a second main surface side outer layer portion are formed above and below a portion that will become an inner layer portion in the fifth embodiment.
  • FIG. 1 is an external perspective view of the duplex multilayer ceramic capacitor 1 according to the first embodiment.
  • FIG. 2A is a cross-sectional view taken along line II-II of FIG. 1 , illustrating a schematic configuration of a duplex multilayer body according to the first embodiment.
  • FIG. 2B is a cross-sectional view taken along line II-II of FIG. 1 , mainly illustrating the relationship between thicknesses of various parts within the duplex multilayer body according to the first embodiment.
  • FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2A.
  • 4A is a cross-sectional view taken along line IVA-IVA of FIG. 2A , illustrating a cross-sectional view taken along line IVB-IVB of FIG. 2A , illustrating a cross-sectional view taken along line IVB-IVB of FIG. 2A , illustrating a cross-sectional view taken along the intermediate electrode layer.
  • the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape.
  • the multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.
  • arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10.
  • arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T.
  • arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L.
  • a pair of external electrodes 40 are respectively arranged at one end and the other end of the length direction L of the laminate 10.
  • FIG. 1 An XYZ Cartesian coordinate system is shown in Figures 1 to 4B and Figure 9, which will be described later.
  • the length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction.
  • the width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction.
  • the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction.
  • the cross sections shown in Figures 2A, 2B, and 9 are also referred to as LT cross sections.
  • the cross section shown in Figure 3 is also referred to as WT cross section.
  • the cross sections shown in Figures 4A and 4B are also referred to as LW cross sections.
  • the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face in the length direction L that is perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face in the width direction W that is perpendicular to the stacking direction T and the length direction L.
  • the laminate 10 has a substantially rectangular parallelepiped shape.
  • the dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W.
  • the corners and ridges of the laminate 10 are preferably rounded.
  • a corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect.
  • unevenness may be formed on some or all of the surfaces constituting the laminate 10.
  • the multilayer ceramic capacitor 1 according to this embodiment has a first recess DE1 formed as a recess on the first main surface TS1 as shown in FIGS. 1 to 2C.
  • the multilayer ceramic capacitor 1 according to this embodiment has a second recess DE2 formed as a recess on the second main surface TS2 as shown in FIGS. 2A to 2C.
  • the recess need not be formed.
  • the dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is the L dimension, then it is preferable that the L dimension be 0.2 mm or more and 6 mm or less. Furthermore, if the dimension in the stacking direction T of the laminate 10 is the T dimension, then it is preferable that the T dimension be 0.05 mm or more and 5 mm or less. Furthermore, if the dimension in the width direction W of the laminate 10 is the W dimension, then it is preferable that the W dimension be 0.1 mm or more and 5 mm or less.
  • the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.
  • the inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked alternately in the stacking direction T.
  • the inner layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2.
  • the multiple internal electrode layers 30 are arranged facing each other with the dielectric layer 20 interposed therebetween.
  • the inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.
  • the thickness of the inner layer portion 11 in the stacking direction T varies along the length direction L in accordance with the shapes of the internal electrode layer 30 located closest to the first main surface TS1 and the internal electrode layer 30 located closest to the second main surface TS2.
  • the plurality of dielectric layers 20 are made of a dielectric material.
  • the dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3 , CaTiO3 , SrTiO3 , or CaZrO3 .
  • the dielectric material may also be one in which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components. It is particularly preferable that the dielectric material be a material containing BaTiO3 as the main component.
  • the thickness of the dielectric layer 20 is preferably 0.2 ⁇ m or more and 10 ⁇ m or less.
  • the number of laminated dielectric layers 20 is preferably 15 or more and 1,200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.
  • the multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and intermediate electrode layers 33.
  • the first internal electrode layers 31 and second internal electrode layers 32 are arranged adjacent to each other with a space between them in the longitudinal direction L, and the first internal electrode layers 31 and second internal electrode layers 32 and the intermediate electrode layers 33 are arranged alternately in the stacking direction T with dielectric layers 20 sandwiched between them.
  • the first internal electrode layer 31 is extended to the first end surface LS1 and connected to the first external electrode 40A described below.
  • the second internal electrode layer 32 is extended to the second end surface LS2 and connected to the second external electrode 40B described below.
  • the intermediate electrode layer 33 is not extended to either the first end surface LS1 or the second end surface LS2, and is not connected to either the first external electrode 40A or the second external electrode 40B described below.
  • the first internal electrode layer 31, intermediate electrode layer 33, and second internal electrode layer 32 included in the multiple internal electrode layers 30 form a series-connected capacitor element.
  • the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.
  • the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1.
  • the first opposing portion EA is an area facing the intermediate electrode layer 33 arranged adjacent to it in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10.
  • the first internal electrode layer 31 has the first opposing portion EA connected to the first lead portion D1 and facing the internal electrode layer 30 arranged adjacent to it in the stacking direction T.
  • the first lead portion D1 is a portion that extends from the first opposing portion EA to the first end face LS1 and is exposed at the first end face LS1.
  • the first internal electrode layer 31 has the first lead portion D1, one end of which is extended to the first end face LS1 and connected to the first external electrode 40A.
  • the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2.
  • the second opposing portion EB is a region facing the intermediate electrode layer 33 arranged adjacent to it in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10.
  • the second internal electrode layer 32 has a second opposing portion EB that is connected to the second lead portion D2 and faces the internal electrode layer 30 arranged adjacent to it in the stacking direction T.
  • the second lead portion D2 is a portion that extends from the second opposing portion EB to the second end face LS2 and is exposed at the second end face LS2.
  • the second internal electrode layer 32 has a second lead portion D2, one end of which is extended to the second end face LS2 and connected to the second external electrode 40B.
  • the intermediate electrode layer 33 has a first electrode layer side facing portion ECA, a second electrode layer side facing portion ECB, and a connecting portion E0.
  • the first electrode layer side facing portion ECA is an area facing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10.
  • the second electrode layer side facing portion ECB is an area facing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10.
  • the connecting portion E0 is a portion that connects the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB, and is located between the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB.
  • the end of the intermediate electrode layer 33 on the first end face LS1 side is positioned away from the first end face LS1.
  • the end of the intermediate electrode layer 33 on the first end face LS1 side is positioned closer to the first end face LS1 than the end face 40AE of the first external electrode 40A described below.
  • the end of the intermediate electrode layer 33 on the second end face LS2 side is positioned away from the second end face LS2.
  • the end of the intermediate electrode layer 33 on the second end face LS2 side is positioned closer to the second end face LS2 than the end 40BE of the second external electrode 40B described below.
  • the first internal electrode layer 31 and the second internal electrode layer 32 are arranged adjacent to each other in the longitudinal direction L.
  • the first internal electrode layer 31 and the second internal electrode layer 32 are stacked alternately with the intermediate electrode layer 33 interposed between them, with the dielectric layer 20 interposed therebetween.
  • the first opposing portion EA and the first electrode layer side opposing portion ECA face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion).
  • the second opposing portion EB and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 including the first electrode layer side opposing portion ECA face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion).
  • the connecting portion E0 connects the capacitances CAP1 and CAP2 in series.
  • the multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called double series structure in which two capacitor portions connected in series are formed.
  • the shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.
  • the shapes of the first lead-out portion D1 and the second lead-out portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.
  • the shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.
  • the width direction W dimension of the first opposing portion EA and the width direction W dimension of the first lead-out portion D1 may be the same dimension, or one of the dimensions may be smaller.
  • the width direction W dimension of the second opposing portion EB and the width direction W dimension of the second lead-out portion D2 may be the same dimension, or one of the dimensions may be smaller.
  • the width direction W dimension of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the width direction W dimension of the connecting portion E0 may be the same dimension, or one of the dimensions may be smaller.
  • the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. If an alloy is used, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be made of, for example, an Ag-Pd alloy.
  • each of the first internal electrode layer 31, second internal electrode layer 32, and intermediate electrode layer 33 is preferably, for example, 0.2 ⁇ m or more and 2.0 ⁇ m or less.
  • the total number of first internal electrode layers 31, second internal electrode layers 32, and intermediate electrode layers 33 is preferably 15 or more and 1,000 or less.
  • the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10.
  • the first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1.
  • the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10.
  • the second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2.
  • the dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.
  • the laminate 10 has a series capacitor-forming portion 11E.
  • the series capacitor-forming portion 11E includes a portion where the first opposing portion EA of the first internal electrode layer 31 faces the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 (a portion forming capacitance CAP1), a portion where the second opposing portion EB of the second internal electrode layer 32 faces the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 (a portion forming capacitance CAP2), and a portion connecting capacitances CAP1 and CAP2 in series.
  • the series capacitor-forming portion 11E is configured as part of the inner layer portion 11.
  • Figures 4A and 4B show the width direction W and length direction L of the series capacitor-forming portion 11E.
  • the portion of the series capacitor-forming portion 11E where capacitance CAP1 is formed (first capacitor portion) and the portion where capacitance CAP2 is formed (second capacitor portion) are also referred to as effective capacitor portions.
  • the laminate 10 has side surface outer layer portions.
  • the side surface outer layer portions include a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2.
  • the first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the series capacitor forming portion 11E and the first side surface WS1.
  • the second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the series capacitor forming portion 11E and the second side surface WS2.
  • Figures 3, 4A, and 4B show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2.
  • the side surface outer layer portions are also called W gaps or side gaps.
  • the laminate 10 has an end face side outer layer portion.
  • the end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2.
  • the first end face side outer layer portion LG1 is a portion located between the series capacitor forming portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion D1. That is, the first end face side outer layer portion LG1 is an assembly of the portions of the multiple dielectric layers 20 on the first end face LS1 side and the multiple first lead portions D1.
  • the second end face side outer layer portion LG2 is a portion located between the series capacitor forming portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion D2.
  • the second end face side outer layer portion LG2 is an assembly of the portions of the multiple dielectric layers 20 on the second end face LS2 side and the multiple second lead portions D2.
  • 2A, 2B, 4A, and 4B show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2.
  • the end surface side outer layer portion is also referred to as an L gap or end gap.
  • the series capacitor forming portion 11E of the laminate 10 has a series connection region.
  • the series connection region is a portion that includes the dielectric layer 20 and the connecting portion E0, located between the portion that forms the capacitance CAP1 and the portion that forms the capacitance CAP2.
  • the series connection region is a collection of the central portions of multiple dielectric layers 20 in the length direction L and multiple connecting portions E0.
  • the series connection region is also referred to as an intermediate gap.
  • the external electrode 40 has a first external electrode 40A arranged on the first end surface LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end surface LS2 side of the laminate 10.
  • the first external electrode 40A and the second external electrode 40B have the same basic configuration. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are roughly plane-symmetrical with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, hereinafter, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.
  • the first external electrode 40A is disposed on the first end face LS1.
  • the first external electrode 40A is in contact with the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31.
  • the first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the second external electrode 40B is disposed on the second end face LS2.
  • the second external electrode 40B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32.
  • the second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion).
  • the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion).
  • the connecting portion E0 connects the capacitances CAP1 and CAP2 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.
  • the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.
  • the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.
  • the first base electrode layer 50A is disposed on the first end face LS1.
  • the first base electrode layer 50A is connected to the first lead portions D1 of each of the multiple first internal electrode layers 31 exposed at the first end face LS1.
  • the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the second base electrode layer 50B is disposed on the second end face LS2.
  • the second base electrode layer 50B is in contact with the second lead portions D2 of each of the multiple second internal electrode layers 32 exposed at the second end face LS2.
  • the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.
  • the first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baked layer, a thin film layer, etc.
  • the first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers.
  • the baked layers preferably contain a metal component and either a glass component or a ceramic component, or both.
  • the metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.
  • the glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc.
  • the ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material.
  • the ceramic component includes, for example, at least one selected from BaTiO 3 , CaTiO 3 , (Ba, Ca)TiO 3 , SrTiO 3 , CaZrO 3 , etc.
  • the baked layer is formed, for example, by applying a conductive paste containing glass and metal to the laminate 10 and baking it.
  • the baked layer can be formed by simultaneously baking a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, and a conductive paste applied to the laminate chip.
  • the baked layer can be formed by first firing the laminate chip to obtain the laminate 10, and then applying a conductive paste to the laminate 10 and baking it.
  • it is preferable to form the baked layer by baking a material to which a ceramic material has been added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material.
  • the baked layer may be multiple layers.
  • the thickness of the first base electrode layer 50A located on the first end surface LS1 in the length direction L is preferably, for example, approximately 3 ⁇ m or more and 200 ⁇ m or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.
  • the thickness of the second base electrode layer 50B located on the second end surface LS2 in the length direction L is preferably, for example, approximately 3 ⁇ m or more and 200 ⁇ m or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.
  • the thickness of the first base electrode layer 50A provided in this portion is preferably, for example, approximately 3 ⁇ m or more and 25 ⁇ m or less at the center in the length direction L and width direction W of the first base electrode layer 50A provided in this portion.
  • the thickness of the first base electrode layer 50A provided in this portion, corresponding to the width direction W is preferably, for example, approximately 3 ⁇ m or more and 25 ⁇ m or less, at the center of the first base electrode layer 50A provided in this portion in the length direction L and stacking direction T.
  • the thickness of the second base electrode layer 50B provided in this portion is preferably, for example, approximately 3 ⁇ m or more and 25 ⁇ m or less, at the center in the length direction L and width direction W of the second base electrode layer 50B provided in this portion.
  • the thickness of the second base electrode layer 50B provided in this portion is preferably, for example, approximately 3 ⁇ m or more and 25 ⁇ m or less, at the center in the length direction L and stacking direction T of the second base electrode layer 50B provided in this portion.
  • the first base electrode layer 50A and the second base electrode layer 50B may be thin film layers. Thin film layers are layers on which metal particles are deposited.
  • first base electrode layer 50A and the second base electrode layer 50B are formed as thin film layers, they are preferably formed by a thin film formation method such as sputtering or vapor deposition.
  • a thin film formation method such as sputtering or vapor deposition.
  • the first base electrode layer 50A may be composed of a first thin film layer formed by a sputtered electrode.
  • the second base electrode layer 50B may be composed of a second thin film layer formed by a sputtered electrode.
  • the sputtered electrode When forming the base electrode layer using a sputtered electrode, it is preferable to form the sputtered electrode directly on a portion of at least one of the first main surface TS1 and the second main surface TS2 of the laminate 10.
  • the first thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 facing the first side surface WS1.
  • the second thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 facing the second side surface WS2.
  • the thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10.
  • the thin film layer may be a single layer, or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni-Cr alloy and a layer of Ni-Cu alloy.
  • the first plating layer 60A is arranged to cover the first base electrode layer 50A.
  • the second plating layer 60B is arranged to cover the second base electrode layer 50B.
  • the first plating layer 60A and the second plating layer 60B may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc.
  • the first plating layer 60A and the second plating layer 60B may each be formed from multiple layers.
  • the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.
  • the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.
  • the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.
  • the Ni plating layer prevents the first and second base electrode layers 50A and 50B from being eroded by solder when the multilayer ceramic capacitor 1 is mounted.
  • the Sn plating layer also improves the wettability of the solder when the multilayer ceramic capacitor 1 is mounted, thereby facilitating mounting of the multilayer ceramic capacitor 1. It is preferable that the thickness of each of the first Ni plating layer 61A, first Sn plating layer 62A, second Ni plating layer 61B, and second Sn plating layer 62B be 2 ⁇ m or more and 10 ⁇ m or less.
  • the external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin.
  • the conductive resin layer may be arranged so as to cover the baked layer.
  • the conductive resin layer is arranged between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B).
  • the conductive resin layer may completely cover the baked layer, or may cover only a portion of the baked layer.
  • Conductive resin layers containing thermosetting resins are more flexible than conductive layers made of, for example, plating films or baked conductive pastes. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock due to thermal cycling, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.
  • the metal that makes up the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these.
  • the conductive particles preferably contain Ag.
  • the conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, because Ag is a noble metal, it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as conductive particles.
  • the conductive particles may also be metal powder with an Ag coating on the surface.
  • the metal powder is preferably a powder of Cu, Ni, Sn, Bi, or an alloy of these. In order to maintain the properties of Ag while making the base metal less expensive, it is preferable to use Ag-coated metal powder.
  • the conductive particles may be Cu or Ni that has been treated to prevent oxidation. Furthermore, the conductive particles may be metal powder whose surface is coated with Sn, Ni, or Cu. When using metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder of these.
  • the shape of the conductive particles is not particularly limited. Conductive particles having a spherical or flat shape can be used, but it is preferable to use a mixture of spherical metal powder and flat metal powder.
  • the conductive particles contained in the conductive resin layer primarily play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, when multiple conductive particles come into contact with each other, an electrical path is formed within the conductive resin layer.
  • the resin constituting the conductive resin layer may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin.
  • epoxy resin which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.
  • the resin of the conductive resin layer contains a curing agent in addition to the thermosetting resin.
  • the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.
  • the conductive resin layer may be formed from multiple layers.
  • the thickness of the thickest part of the conductive resin layer is preferably 10 ⁇ m or more and 150 ⁇ m or less.
  • the first plating layer 60A and second plating layer 60B described below may be disposed directly on the laminate 10 without providing the first base electrode layer 50A and second base electrode layer 50B.
  • the multilayer ceramic capacitor 1 may be configured to include plating layers that are directly and electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such cases, the plating layers may be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.
  • the plating layer be multiple layers.
  • the lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals.
  • the lower plating layer is more preferably formed using Ni, which has solder barrier properties.
  • the upper plating layer is more preferably formed using Sn or Au, which have good solder wettability.
  • the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni
  • the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni.
  • the upper plating layer may be formed as needed, and the external electrode 40 may be composed of only the lower plating layer.
  • the upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.
  • each plating layer which is placed without a base electrode layer, is preferably 2 ⁇ m or more and 10 ⁇ m or less. It is preferable that the plating layer does not contain glass.
  • the metal content per unit volume of the plating layer is preferably 99% by volume or more.
  • the thickness of the base electrode layer can be reduced. Therefore, the dimension of the multilayer ceramic capacitor 1 in the height direction T can be reduced by the amount of the reduced thickness of the base electrode layer, thereby making it possible to reduce the height of the multilayer ceramic capacitor 1.
  • the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 can be increased by the amount of the reduced thickness of the base electrode layer, thereby improving the thickness of the element body. In this way, by forming the plating layer directly on the laminate 10, the design freedom of the multilayer ceramic capacitor can be improved.
  • the L dimension is preferably 0.2 mm or more and 6 mm or less.
  • the T dimension is preferably 0.05 mm or more and 5 mm or less.
  • W dimension is preferably 0.1 mm or more and 5 mm or less.
  • the inventors of the present application have discovered that in order to increase capacitance without increasing the size of the multilayer ceramic capacitor, it is desirable to appropriately set the dimensions and coverage of each component included in the multilayer ceramic capacitor.
  • the internal electrode layer 30 contains, in addition to the metal material, hollow portions where no metal material is present. The percentage of the internal electrode layer 30 occupied by the metal material will be described as coverage. Coverage is also referred to as the coverage rate of the internal electrode layer 30 relative to the dielectric layer 20.
  • the hollow portions where no metal material is present may contain ceramic components such as dielectrics or glass components such as silica. Alternatively, the hollow portions where no metal material is present may be voids. This embodiment will be described in detail below using Figures 1 to 7.
  • the inner layer portion 11 has a first main surface side inner layer portion 112, a second main surface side inner layer portion 113, and a central inner layer portion 111 disposed between the first main surface side inner layer portion and the second main surface side inner layer portion.
  • Figures 2A to 3 are schematic diagrams, and for ease of explanation, only a small number of internal electrode layers 30 are shown.
  • the first main surface side inner layer portion 112 is the portion of the inner layer portion 11 on the first main surface TS1 side.
  • the first main surface side inner layer portion 112 is, for example, the portion of the inner layer portion 11 on the first main surface TS1 side, and is a portion that includes at least the fifth internal electrode layer 30 from the internal electrode layer 30 closest to the first main surface TS1.
  • the first main surface side inner layer portion 112 is, for example, 25% of the inner layer portion 11 on the first main surface TS1 side in the stacking direction.
  • the second main surface side inner layer portion 113 is the portion of the inner layer portion 11 on the second main surface TS2 side.
  • the second main surface side inner layer portion 113 is, for example, the portion of the inner layer portion 11 on the second main surface TS2 side, and is a portion that includes at least the fifth internal electrode layer 30 from the internal electrode layer 30 closest to the second main surface TS2.
  • the second main surface side inner layer portion 113 is, for example, 25% of the inner layer portion 11 on the second main surface TS2 side in the stacking direction.
  • the central inner layer portion 111 is the portion of the inner layer portion 11 that is located at the center of the stacking direction T of the laminate 10.
  • the central inner layer portion 111 is, for example, a portion that includes at least the internal electrode layer 30 arranged in the central region of the laminate in the stacking direction T.
  • the thicknesses of the central inner layer portion 111, the first main surface side internal layer portion 112, and the second main surface side internal layer portion 113 in the stacking direction T each vary along the length direction L in accordance with the shape of the internal electrode layer 30.
  • the series capacitor forming portion 11E of the inner layer portion 11 has a first side region 112E, a second side region 113E, and a central region 111E.
  • the first side surface side region 112E is the portion of the series capacitor forming portion 11E on the first side surface WS1 side.
  • the first side surface side region 112E is, for example, 25% of the series capacitor forming portion 11E on the first side surface WS1 side in the width direction W.
  • the first side surface side region 112E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and part of the central inner layer portion 111.
  • the second side surface region 113E is the portion of the series capacitor forming portion 11E on the second side surface WS2 side.
  • the second side surface region 113E is, for example, 25% of the series capacitor forming portion 11E on the second side surface WS2 side in the width direction W.
  • the second side surface region 113E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and part of the central inner layer portion 111.
  • the central region 111E is disposed between the first side region 112E and the second side region 113E.
  • the central region 111E is a portion of the series capacitor forming portion 11E in the width direction W that includes the central region in the width direction W.
  • the central region 111E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and part of the central inner layer portion 111.
  • the first opposing portion EA of the first internal electrode layer 31 has a first region EA1 and a second region EA2.
  • the first region EA1 is the region of the first opposing portion EA on the first end face LS1 side.
  • the second region EA2 is the region of the first opposing portion EA on the second end face LS2 side.
  • the second region EA2 has higher coverage than the first region EA1.
  • the second region EA2 is thicker in the stacking direction T than the first region EA1, and is positioned more toward the outside of the laminate 10 than the first region EA1.
  • the second region EA2 of the first internal electrode layer 31 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the first region EA1.
  • the second region EA2 of the first internal electrode layer 31 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the first region EA1.
  • the second region EA2 may be arranged biased toward the outside of the laminate 10 relative to the first region EA1.
  • the second opposing portion EB of the second internal electrode layer 32 has a third region EB1 and a fourth region EB2.
  • the third region EB1 is the region of the second opposing portion EB on the second end face LS2 side.
  • the fourth region EB2 is the region of the second opposing portion EB on the first end face LS1 side.
  • the fourth region EB2 has a higher coverage than the third region EB1.
  • the fourth region EB2 is thicker in the stacking direction T than the third region EB1, and is positioned more toward the outside of the laminate 10 than the third region EB1.
  • the fourth region EB2 of the second internal electrode layer 32 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the third region EB1. Also, in this embodiment, in the second main surface side inner layer portion 113, the fourth region EB2 of the second internal electrode layer 32 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the third region EB1. Note that in at least either the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, the fourth region EB2 may be arranged biased toward the outside of the laminate 10 relative to the third region EB1.
  • the first electrode layer side facing portion ECA of the intermediate electrode layer 33 has a fifth region ECA1 and a sixth region ECA2.
  • the fifth region ECA1 is the region of the first electrode layer side facing portion ECA on the first end face LS1 side.
  • the sixth region ECA2 is the region of the first electrode layer side facing portion ECA on the second end face LS2 side.
  • the sixth region ECA2 has a higher coverage than the fifth region ECA1. Also, as shown in FIG. 2C, the sixth region ECA2 is thicker in the stacking direction T than the fifth region ECA1, and is positioned closer to the outside of the laminate 10 than the fifth region ECA1.
  • the sixth region ECA2 of the intermediate electrode layer 33 is positioned closer to the first main surface TS1 side of the laminate 10 than the fifth region ECA1 of the intermediate electrode layer 33. Furthermore, in this embodiment, in the second main surface side inner layer portion 113, the sixth region ECA2 of the intermediate electrode layer 33 is positioned closer to the second main surface TS2 side of the laminate 10 than the fifth region ECA1 of the intermediate electrode layer 33.
  • the second electrode layer side facing portion ECB of the intermediate electrode layer 33 has a seventh region ECB1 and an eighth region ECB2.
  • the seventh region ECB1 is the region of the second electrode layer side facing portion ECB on the second end face LS2 side.
  • the eighth region ECB2 is the region of the second electrode layer side facing portion ECB on the first end face LS1 side.
  • the eighth region ECB2 has a higher coverage than the seventh region ECB1. Also, as shown in FIG. 2C, the eighth region ECB2 is thicker in the stacking direction T than the seventh region ECB1, and is positioned more toward the outside of the stack 10 than the seventh region ECB1.
  • the eighth region ECB2 of the intermediate electrode layer 33 is positioned closer to the first principal surface TS1 side of the laminate 10 than the seventh region ECB1 of the intermediate electrode layer 33. Furthermore, in this embodiment, in the second principal surface side inner layer portion 113, the eighth region ECB2 of the intermediate electrode layer 33 is positioned closer to the second principal surface TS2 side of the laminate 10 than the seventh region ECB1 of the intermediate electrode layer 33.
  • the coverage of at least a portion of the intermediate electrode layer 33 is higher than the coverage of the area on the first end face LS1 side of the first opposing portion EA of the first internal electrode layer 31, and is also higher than the coverage of the area on the second end face LS2 side of the second opposing portion EB of the second internal electrode layer 32.
  • the sixth region ECA2 of the intermediate electrode layer 33 has a higher coverage than the first region EA1 of the first internal electrode layer 31. Also, as shown in FIG. 2C, the sixth region ECA2 of the intermediate electrode layer 33 is thicker in the stacking direction T than the first region EA1 of the first internal electrode layer 31.
  • the eighth region ECB2 of the intermediate electrode layer 33 has a higher coverage than the third region EB1 of the second internal electrode layer 32. Also, as shown in FIG. 2C, the eighth region ECB2 of the intermediate electrode layer 33 is thicker in the stacking direction T than the third region EB1 of the second internal electrode layer 32.
  • the coverage of the second region EA2 of the first opposing portion EA of the first internal electrode layer 31 is higher than the coverage of the fifth region ECA1 of the first electrode layer side opposing portion ECA of the intermediate electrode layer 33.
  • the second region EA2 of the first opposing portion EA of the first internal electrode layer 31 is thicker in the stacking direction T than the fifth region ECA1 of the first electrode layer side opposing portion ECA of the intermediate electrode layer 33.
  • the coverage of the fourth region EB2 of the second opposing portion EB of the second internal electrode layer 32 is higher than the coverage of the seventh region ECB1 of the second electrode layer side opposing portion ECB of the intermediate electrode layer 33.
  • the fourth region EB2 of the second opposing portion EB of the second internal electrode layer 32 is thicker in the stacking direction T than the seventh region ECB1 of the second electrode layer side opposing portion ECB of the intermediate electrode layer 33.
  • high coverage areas are arranged as high coverage portions with higher coverage, such as the second area EA2, fourth area EB2, sixth area ECA2, and eighth area ECB2 described above.
  • the thickness of the internal electrode layers 30 in the second region EA2 of the first internal electrode layer 31, the fourth region EB2 of the second internal electrode layer 32, the sixth region ECA2 of the intermediate electrode layer 33, and the eighth region ECB2 of the intermediate electrode layer 33 to be increased, thereby improving coverage and increasing capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing. It is preferable that the thickness of the connecting portion E0 of the intermediate electrode layer 33 be the same as the thickness of the sixth region ECA2 and the eighth region ECB2 of the intermediate electrode layer 33. This allows the capacitances CAP1 and CAP2 to be connected in series with higher reliability. It also facilitates manufacturing. However, this is not limited to this.
  • the second region EA2 is preferably approximately parallel to a plane perpendicular to the stacking direction T.
  • the first region EA1 and the second region EA2 preferably have portions that are approximately parallel to each other. More preferably, the first region EA1 and the second region EA2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the fourth region EB2 is preferably approximately parallel to a plane perpendicular to the stacking direction T.
  • the third region EB1 and the fourth region EB2 preferably have portions that are approximately parallel to each other. More preferably, the third region EB1 and the fourth region EB2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the sixth region ECA2 is preferably approximately parallel to a plane perpendicular to the stacking direction T.
  • the fifth region ECA1 and the sixth region ECA2 preferably have portions that are approximately parallel to each other. More preferably, the fifth region ECA1 and the sixth region ECA2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the sixth region ECA2, the first region EA1, and the second region EA2 have portions that are approximately parallel to one another. More preferably, the sixth region ECA2, the first region EA1, and the second region EA2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the eighth region ECB2 is preferably approximately parallel to a plane perpendicular to the stacking direction T.
  • the seventh region ECB1 and the eighth region ECB2 preferably have portions that are approximately parallel to each other. More preferably, the seventh region ECB1 and the eighth region ECB2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the eighth region ECB2, the third region EB1, and the fourth region EB2 have portions that are approximately parallel to one another. More preferably, the eighth region ECB2, the third region EB1, and the fourth region EB2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the fifth region ECA1, the sixth region ECA2, the seventh region ECB1, and the eighth region ECB2 have portions that are approximately parallel to one another. More preferably, the fifth region ECA1, the sixth region ECA2, the seventh region ECB1, and the eighth region ECB2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.
  • the distance Le0 from the end of the second region EA2 on the first end face LS1 side to the end of the fourth region EB2 on the second end face LS2 side is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the distance Le0 from the end of the sixth region ECA2 on the first end face LS1 side to the end of the eighth region ECB2 on the second end face LS2 side is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the distance Le0 from the end of the second region EA2 on the first end face LS1 side to the end of the fourth region EB2 on the second end face LS2 side and the distance Le0 from the end of the sixth region ECA2 on the first end face LS1 side to the end of the eighth region ECB2 on the second end face LS2 side are approximately equal, but this is not limited to this.
  • the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 are arranged within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the ends of the second region EA2 and the sixth region ECA2 on the first end face LS1 side are located closer to the second end face LS2 than the end 40AE of the first external electrode 40A on the stack center side, which is located on the first principal surface TS1 and the second principal surface TS2.
  • the ends of the fourth region EB2 and the eighth region ECB2 on the second end face LS2 side are located closer to the first end face LS1 than the end 40BE of the second external electrode 40B on the stack center side, which is located on the first principal surface TS1 and the second principal surface TS2.
  • the ends of the first region EA1 and the fifth region ECA1 on the first end face LS1 side are located closer to the first end face LS1 than the end 40AE of the first external electrode 40A on the stack center side, which is located on the first principal surface TS1 and the second principal surface TS2.
  • the ends of the third region EB1 and the seventh region ECB1 on the second end face LS2 side are located closer to the second end face LS2 than the end 40BE of the second external electrode 40B on the stack center side, which is located on the first principal surface TS1 and the second principal surface TS2.
  • the thickness of the second region EA2 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first region EA1 in the stacking direction T.
  • the thickness of the second region EA2 is preferably 101% to 111% of the thickness of the first region EA1.
  • the thickness of the second region EA2 may be 101% to 110% of the thickness of the first region EA1, and is more preferably 102% to 110%.
  • the thickness of the second region EA2 is even more preferably 103% to 110% of the thickness of the first region EA1.
  • the thickness of the fourth region EB2 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the third region EB1 in the stacking direction T.
  • the thickness of the fourth region EB2 is preferably 101% to 111% of the thickness of the third region EB1.
  • the thickness of the fourth region EB2 may be 101% to 110% of the thickness of the third region EB1, and is more preferably 102% to 110%.
  • the thickness of the fourth region EB2 is even more preferably 103% to 110% of the thickness of the third region EB1.
  • the thickness of the sixth region ECA2 of the intermediate electrode layer 33 in the stacking direction T is greater than the thickness of the fifth region ECA1 in the stacking direction T.
  • the thickness of the sixth region ECA2 be 101% or more and 111% or less of the thickness of the fifth region ECA1.
  • the thickness of the sixth region ECA2 may be 101% or more and 110% or less of the thickness of the fifth region ECA1, and it is more preferable that the thickness of the sixth region ECA2 be 102% or more and 110% or less.
  • the thickness of the sixth region ECA2 be 103% or more and 110% or less of the thickness of the fifth region ECA1.
  • the thickness of the eighth region ECB2 of the intermediate electrode layer 33 in the stacking direction T is greater than the thickness of the seventh region ECB1 in the stacking direction T.
  • the thickness of the eighth region ECB2 is preferably 101% or more and 111% or less of the thickness of the seventh region ECB1.
  • the thickness of the eighth region ECB2 may be 101% or more and 110% or less of the thickness of the seventh region ECB1, and is more preferably 102% or more and 110% or less.
  • the thickness of the eighth region ECB2 is even more preferably 103% or more and 110% or less of the thickness of the seventh region ECB1.
  • the thicknesses of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 are thicker than the thicknesses of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1. It is preferable that the thicknesses of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 be 101% or more and 111% or less of the thicknesses of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1.
  • the thicknesses of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 may be 101% or more and 110% or less of the thicknesses of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1, and are more preferably 102% or more and 110% or less.
  • the thicknesses of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 are 103% or more and 110% or less of the thicknesses of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1.
  • the thickness of the second region EA2 of the first opposing portion EA of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first lead portion D1.
  • the thickness of the second region EA2 be 101% or more and 111% or less of the thickness of the first lead portion D1.
  • the thickness of the second region EA2 may be 101% or more and 110% or less of the thickness of the first lead portion D1, and it is more preferable that the thickness be 102% or more and 110% or less.
  • the thickness of the second region EA2 be 103% or more and 110% or less of the thickness of the first lead portion D1.
  • the thickness in the stacking direction T of the fourth region EB2 of the second opposing portion EB of the second internal electrode layer 32 is greater than the thickness of the second lead portion D2.
  • the thickness of the fourth region EB2 be 101% or more and 111% or less of the thickness of the second lead portion D2.
  • the thickness of the fourth region EB2 may be 101% or more and 110% or less of the thickness of the second lead portion D2, and it is more preferable that the thickness be 102% or more and 110% or less.
  • the thickness of the fourth region EB2 be 103% or more and 110% or less of the thickness of the second lead portion D2.
  • the second area EA2 has higher coverage than the first area EA1.
  • the difference between the coverage of the second area EA2 and the coverage of the first area EA1 is 2 percentage points or more. It is also preferable that the difference between the coverage of the second area EA2 and the coverage of the first area EA1 is 2 percentage points or more and 11 percentage points or less.
  • the difference between the coverage of the second area EA2 and the coverage of the first area EA1 be between 3 and 11 percentage points, in order to expect even greater effectiveness. It is even more preferable that the difference between the coverage of the second area EA2 and the coverage of the first area EA1 be between 4 and 11 percentage points.
  • the fourth region EB2 has a higher coverage than the third region EB1.
  • the difference between the coverage of the fourth region EB2 and the coverage of the third region EB1 be 2 percentage points or more. It is also preferable that the difference between the coverage of the fourth region EB2 and the coverage of the third region EB1 be 2 percentage points or more and 11 percentage points or less.
  • the difference between the coverage of the fourth region EB2 and the coverage of the third region EB1 be between 3 and 11 percentage points, inclusive, as this is expected to produce a greater effect. It is even more preferable that the difference between the coverage of the fourth region EB2 and the coverage of the third region EB1 be between 4 and 11 percentage points, inclusive.
  • the sixth area ECA2 has a higher coverage than the fifth area ECA1.
  • the difference between the coverage of the sixth region ECA2 and the coverage of the fifth region ECA1 is 2 percentage points or more. It is also preferable that the difference between the coverage of the sixth region ECA2 and the coverage of the fifth region ECA1 is 2 percentage points or more and 11 percentage points or less.
  • the difference between the coverage of the sixth region ECA2 and the coverage of the fifth region ECA1 be between 3 and 11 percentage points, in order to achieve even greater effectiveness. It is even more preferable that the difference between the coverage of the sixth region ECA2 and the coverage of the fifth region ECA1 be between 4 and 11 percentage points.
  • the eighth region ECB2 has a higher coverage than the seventh region ECB1.
  • the difference between the coverage of the eighth region ECB2 and the coverage of the seventh region ECB1 is 2 percentage points or more. It is also preferable that the difference between the coverage of the eighth region ECB2 and the coverage of the seventh region ECB1 is 2 percentage points or more and 11 percentage points or less.
  • the difference between the coverage of the eighth region ECB2 and the coverage of the seventh region ECB1 be between 3 and 11 percentage points, inclusive, as this is expected to produce even greater results. It is even more preferable that the difference between the coverage of the eighth region ECB2 and the coverage of the seventh region ECB1 be between 4 and 11 percentage points, inclusive.
  • the coverage of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 is higher than the coverage of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1. It is preferable that the coverage of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 be 2 percentage points or more higher than the coverage of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1.
  • the difference between the coverage of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 and the coverage of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1 be 2 percentage points or more and 11 percentage points or less. It is even more preferable that the difference between the coverage of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 and the coverage of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1 be 3 percentage points or more and 11 percentage points or less, which is expected to produce even greater effects.
  • the difference between the coverage of the second region EA2, the fourth region EB2, the sixth region ECA2, and the eighth region ECB2 and the coverage of the first region EA1, the third region EB1, the fifth region ECA1, and the seventh region ECB1 be 4 percentage points or more and 11 percentage points or less.
  • the multiple internal electrode layers 30 further have inclined portions.
  • the first opposing portion EA of the first internal electrode layer 31 has a first inclined portion FA1 connecting the first region EA1 and the second region EA2.
  • the second opposing portion EB of the second internal electrode layer 32 has a second inclined portion FB1 connecting the third region EB1 and the fourth region EB2.
  • the first electrode layer side facing portion ECA of the intermediate electrode layer 33 has a third inclined portion FCA1 connecting the fifth region ECA1 and the sixth region ECA2, as shown in Figures 2B and 2C.
  • the second electrode layer side facing portion ECB of the intermediate electrode layer 33 has a fourth inclined portion FCB1 connecting the seventh region ECB1 and the eighth region ECB2, as shown in Figure 2B.
  • the distance Le3 in the longitudinal direction L of the first inclined portion FA1 and the distance Le4 in the longitudinal direction L of the second inclined portion FB1 are shorter than the distance Le0 from the end of the second region EA2 on the first end face LS1 side in the longitudinal direction L to the end of the fourth region EB2 on the second end face LS2 side in the longitudinal direction L. Furthermore, the distance Le3 in the longitudinal direction L of the third inclined portion FCA1 and the distance Le4 in the longitudinal direction L of the fourth inclined portion FCB1 are shorter than the distance Le0 from the end of the sixth region ECA2 on the first end face LS1 side in the longitudinal direction L to the end of the eighth region ECB2 on the second end face LS2 side in the longitudinal direction L.
  • the distance Le1 in the longitudinal direction L of the first region EA1 and the distance Le2 in the longitudinal direction L of the third region EB1 may be shorter than the distance Le0 from the end of the second region EA2 on the first end face LS1 side in the longitudinal direction L to the end of the fourth region EB2 on the second end face LS2 side in the longitudinal direction L.
  • the distance Le1 in the longitudinal direction L of the fifth region ECA1 and the distance Le2 in the longitudinal direction L of the seventh region ECB1 may be shorter than the distance Le0 from the end of the sixth region ECA2 on the first end face LS1 side in the longitudinal direction L to the end of the eighth region ECB2 on the second end face LS2 side in the longitudinal direction L.
  • the ratio of the area of the second region EA2 to the area of the first opposing portion EA is preferably 30% to 80% and may be 30% to 60%.
  • the ratio of the area of the fourth region EB2 to the area of the second opposing portion EB is preferably 30% to 80% and may be 30% to 60%.
  • the ratio of the area of the sixth region ECA2 to the area of the first electrode layer side facing portion ECA is preferably 30% to 80% and may be 30% to 60%.
  • the ratio of the area of the eighth region ECB2 to the area of the second electrode layer side facing portion ECB is preferably 30% to 80% and may be 30% to 60%.
  • the distance Le3 in the longitudinal direction L between the first inclined portion FA1 and the third inclined portion FCA1 and the distance Le4 in the longitudinal direction L between the second inclined portion FB1 and the fourth inclined portion FCB1 be approximately equal.
  • the second region EA2, the fourth region EB2, the sixth region ECA2, and the eighth region ECB2 are arranged within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B in the longitudinal direction L, and that the first inclined portion FA1, the second inclined portion FB1, the third inclined portion FCA1, and the fourth inclined portion FCB1 are also arranged.
  • the sum of the distance Le0 from the end of the second region EA2 on the first end face LS1 side in the length direction L to the end of the fourth region EB2 on the second end face LS2 side in the length direction L, or from the end of the sixth region ECA2 on the first end face LS1 side in the length direction L to the end of the eighth region ECB2 on the second end face LS2 side in the length direction L, the distance Le3 in the length direction L of the first inclined portion FA1 or the third inclined portion FCA1, and the distance Le4 in the length direction L of the second inclined portion FB1 or the fourth inclined portion FCB1 ( Le0 + Le3 + Le4) is preferably shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. However, this is not limited to this.
  • the inclination angle ⁇ of the first inclined portion FA1 relative to the second region EA2 be 1° or greater.
  • the inclination angle ⁇ of the first inclined portion FA1 relative to the second region EA2 may be 1° or greater and 12° or less. More preferably, the inclination angle ⁇ of the first inclined portion FA1 relative to the second region EA2 may be 2° or greater and 10° or less.
  • the inclination angle ⁇ of the second inclined portion FB1 relative to the fourth region EB2 be 1° or greater.
  • the inclination angle ⁇ of the second inclined portion FB1 relative to the fourth region EB2 may be 1° or greater and 12° or less. More preferably, the inclination angle ⁇ of the second inclined portion FB1 relative to the fourth region EB2 may be 2° or greater and 10° or less.
  • the inclination angle ⁇ of the third inclined portion FCA1 relative to the sixth region ECA2 be 1° or greater.
  • the inclination angle ⁇ of the third inclined portion FCA1 relative to the sixth region ECA2 may be 1° or greater and 12° or less. More preferably, the inclination angle ⁇ of the third inclined portion FCA1 relative to the sixth region ECA2 may be 2° or greater and 10° or less.
  • the inclination angle ⁇ of the fourth inclined portion FCB1 relative to the eighth region ECB2 be 1° or greater.
  • the inclination angle ⁇ of the fourth inclined portion FCB1 relative to the eighth region ECB2 may be 1° or greater and 12° or less. More preferably, the inclination angle ⁇ of the fourth inclined portion FCB1 relative to the eighth region ECB2 may be 2° or greater and 10° or less.
  • Figure 2C shows the inclination angle ⁇ of the second inclined portion FB1 relative to the fourth region EB2 in the second internal electrode layer 32, and the inclination angle ⁇ of the fourth inclined portion FCB1 relative to the eighth region ECB2 in the intermediate electrode layer 33, as representative examples of the inclination angles ⁇ described above.
  • the inclination angle ⁇ within the above-mentioned range, it becomes easy to set the relationship between the thicknesses of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 and the thicknesses of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1 within the range of this embodiment. Furthermore, by setting the inclination angle ⁇ within the above-mentioned range, it becomes easy to set the relationship between the maximum distance T0 at the center of the exposed portion of the laminate 10 (described below) and the maximum distance T1 in the covered portion of the laminate (described below) within the range of this embodiment.
  • the thickness of the first inclined portion FA1 gradually decreases toward the first end surface LS1. Also, as shown in Figures 2A to 2C, the thickness of the second inclined portion FB1 gradually decreases toward the second end surface LS2.
  • the thickness of the third inclined portion FCA1 gradually decreases toward the first end surface LS1. Furthermore, as shown in Figures 2A to 2C, the thickness of the fourth inclined portion FCB1 gradually decreases toward the second end surface LS2.
  • the step distance ls1 in the stacking direction T between the first region EA1 and the second region EA2 caused by the first inclined portion FA1 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls1 in the stacking direction T between the first region EA1 and the second region EA2 caused by the first inclined portion FA1 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls2 in the stacking direction T between the third region EB1 and the fourth region EB2 caused by the second inclined portion FB1 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls2 in the stacking direction T between the third region EB1 and the fourth region EB2 caused by the second inclined portion FB1 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls3 in the stacking direction T between the fifth region ECA1 and the sixth region ECA2 caused by the third inclined portion FCA1 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls3 in the stacking direction T between the fifth region ECA1 and the sixth region ECA2 caused by the third inclined portion FCA1 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls4 in the stacking direction T between the seventh region ECB1 and the eighth region ECB2 caused by the fourth inclined portion FCB1 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the step distance ls4 in the stacking direction T between the seventh region ECB1 and the eighth region ECB2 caused by the fourth inclined portion FCB1 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the thickness Te of the internal electrode layer 30 in the stacking direction T is the thickness of the internal electrode layer 30 in the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 in the stacking direction T.
  • the thickness Tc of the dielectric layer 20 in the stacking direction T is the thickness of the dielectric layer 20 arranged between the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 in the stacking direction T.
  • the thickness of the internal electrode layers 30 in the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 can be increased by taking advantage of the steps created by the inclined portions, thereby sufficiently increasing coverage, thereby further increasing capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • the step distance ls1 in the stacking direction T between the first region EA1 and the second region EA2 caused by the first inclined portion FA1 may be 1.6 ⁇ m or more, or may be 1.6 ⁇ m or more and 16 ⁇ m or less. For example, it may be 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the step distance ls2 in the stacking direction T between the third region EB1 and the fourth region EB2 caused by the second inclined portion FB1 may be 1.6 ⁇ m or more, or may be 1.6 ⁇ m or more and 16 ⁇ m or less. For example, it may be 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the step distance ls3 in the stacking direction T between the fifth region ECA1 and the sixth region ECA2 caused by the third inclined portion FCA1 may be 1.6 ⁇ m or more, or may be 1.6 ⁇ m or more and 16 ⁇ m or less. For example, it may be 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the step distance ls4 in the stacking direction T between the seventh region ECB1 and the eighth region ECB2 caused by the fourth inclined portion FCB1 may be 1.6 ⁇ m or more, or may be 1.6 ⁇ m or more and 16 ⁇ m or less. For example, it may be 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the first internal electrode layer 31 further has a fifth inclined portion FA2 located in the first lead portion D1.
  • the fifth inclined portion FA2 is preferably located closer to the first end face LS1 than the end of the intermediate electrode layer 33 on the first end face LS1 side in the longitudinal direction L.
  • the second internal electrode layer 32 further has a sixth inclined portion FB2 located in the second lead portion D2.
  • the sixth inclined portion FB2 is preferably located closer to the second end face LS2 than the end of the intermediate electrode layer 33 on the second end face LS2 side in the longitudinal direction L.
  • Moisture from plating solutions and other sources can penetrate through the interface between the laminate 10 and the external electrode layers.
  • the distance of the penetration path through this interface to the end of the internal electrode layer 30 can be increased. This allows for increased capacitance and moisture resistance without increasing the size of the multilayer ceramic capacitor 1.
  • the end of the internal electrode layer 30 can be positioned closer to the center of the height of the laminate 10, where the thickness of the external electrode 40 in the length direction L typically tends to be greater. This makes it possible to increase capacitance and ensure moisture resistance without increasing the size of the multilayer ceramic capacitor 1.
  • the distance from the end of the internal electrode layer 30 to the opposing portion of the internal electrode layer 30 can be increased. This increases the distance of the path for moisture to penetrate to the opposing portion of the internal electrode layer 30. Therefore, it is possible to increase capacitance and ensure moisture resistance without increasing the size of the multilayer ceramic capacitor 1.
  • the inclination angle ⁇ of the first inclined portion FA1 is smaller than the inclination angle ⁇ 2 of the fifth inclined portion FA2.
  • the inclination angle ⁇ 2 of the fifth inclined portion FA2 is larger than the inclination angle ⁇ of the first inclined portion FA1.
  • the inclination angle ⁇ 2 of the fifth inclined portion FA2 relative to the first region EA1 or the second region EA2 may be, for example, 10° or more, or 15° or more.
  • the inclination angle ⁇ of the third inclined portion FCA1 is smaller than the inclination angle ⁇ 2 of the fifth inclined portion FA2.
  • the inclination angle ⁇ 2 of the fifth inclined portion FA2 is larger than the inclination angle ⁇ of the third inclined portion FCA1.
  • the inclination angle ⁇ of the second inclined portion FB1 is smaller than the inclination angle ⁇ 2 of the sixth inclined portion FB2.
  • the inclination angle ⁇ 2 of the sixth inclined portion FB2 is larger than the inclination angle ⁇ of the second inclined portion FB1.
  • the inclination angle ⁇ 2 of the sixth inclined portion FB2 relative to the third region EB1 or the fourth region EB2 may be, for example, 10° or more, or 15° or more.
  • the inclination angle ⁇ of the fourth inclined portion FCB1 is smaller than the inclination angle ⁇ 2 of the sixth inclined portion FB2.
  • the inclination angle ⁇ 2 of the sixth inclined portion FB2 is larger than the inclination angle ⁇ of the third inclined portion FCA1 and the fourth inclined portion FCB1.
  • Figure 2C shows the inclination angle ⁇ 2 of the sixth inclined portion FB2 relative to the third region EB1 in the second internal electrode layer 32 as a representative of the inclination angle ⁇ 2 described above.
  • the laminate 10 has an exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 covered by the first external electrode, and a second covered portion C2 covered by the second external electrode 40B.
  • the distance L1 in the length direction L of the exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B corresponds to the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the exposed portion Ep according to this embodiment has a first recess DE1 on the first main surface TS1 side and a second recess DE2 on the second main surface TS2 side.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep is longer than the maximum distance T1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1. Also, in this embodiment, the maximum distance T0 in the stacking direction T of the exposed portion Ep is longer than the maximum distance T1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covering portion C2. Note that in this embodiment, the maximum distance T0 in the stacking direction T of the exposed portion Ep is the maximum distance in the stacking direction T of the exposed portion Ep of the laminate 10.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep is preferably 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1.
  • the distance in the stacking direction T connecting the first planar portion PA1 and the third planar portion PB1 described below is the above-mentioned maximum distance T1.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep is preferably 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covering portion C2.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covering portion C2.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covering portion C2.
  • the distance in the stacking direction T connecting the second planar portion PA2 and the fourth planar portion PB2 described below is the above-mentioned maximum distance T1.
  • the maximum distance T0 in the stacking direction T of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first external electrode 40A. Furthermore, the maximum distance T0 in the stacking direction T of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second external electrode 40B.
  • the ratio between the thickness in the stacking direction T of the second region EA2 of the first internal electrode layer 31 and the thickness in the stacking direction T of the first region EA1 may be set to be greater than the ratio between the maximum distance T0 in the stacking direction T of the exposed portion Ep of the laminate 10 and the maximum distance T1 in the stacking direction T of the first covered portion C1 of the laminate 10.
  • the ratio between the thickness in the stacking direction T of the fourth region EB2 of the second internal electrode layer 32 and the thickness in the stacking direction T of the third region EB1 may be set to be greater than the ratio between the maximum distance T0 in the stacking direction T of the exposed portion Ep of the laminate 10 and the maximum distance T1 in the stacking direction T of the second covered portion C2 of the laminate 10.
  • the first principal surface TS1 has a first covered surface C1sA covered by the first external electrode 40A, a second covered surface C2sA covered by the second external electrode 40B, and a first raised surface EpsA exposed from the first external electrode 40A and the second external electrode 40B and raised toward the center in the longitudinal direction L.
  • the first raised surface EpsA has a first flat surface FPA1, a second flat surface FPA2, a first recess DE1 as a recess, a first inclined surface FC1, and a second inclined surface FC2.
  • the first recess DE1 is a recessed portion formed in the center of the first raised surface EpsA in the length direction L and extending in the width direction W.
  • the first flat surface FPA1 is a surface perpendicular to the stacking direction T and is formed on the first end surface LS1 side of the first recess DE1.
  • the second flat surface FPA2 is a surface perpendicular to the stacking direction T and is formed on the second end surface LS2 side of the first recess DE1.
  • the first inclined surface FC1 connects the first flat surface FPA1 and the first coated surface C1sA.
  • the second inclined surface FC2 connects the second flat surface FPA2 and the second coated surface C2sA.
  • a first flat portion PA1 is formed on the first coated surface C1sA toward the center of the laminate, and a first inclined surface FC1 connects the first flat surface FPA1 and the first flat portion PA1.
  • a second flat portion PA2 is formed on the second coated surface C2sA toward the center of the laminate, and a second inclined surface FC2 connects the second flat surface FPA2 and the second flat portion PA2.
  • the first main surface TS1 of this embodiment has a first planar portion PA1 on the first end surface LS1 side, a second planar portion PA2 on the second end surface LS2 side, a first flat surface FPA1 arranged between the first planar portion PA1 and the first recess DE1 and protruding from the first planar portion PA1, a second flat surface FPA2 arranged between the second planar portion PA2 and the first recess DE1 and protruding from the second planar portion PA2, a first inclined surface FC1 connecting the first flat surface FPA1 and the first planar portion PA1, a second inclined surface FC2 connecting the second flat surface FPA2 and the second planar portion PA2, and a first recess DE1 formed to extend in the width direction W between the first flat surface FPA1 and the second flat surface FPA2.
  • the second principal surface TS2 has a third covered surface C1sB covered by the first external electrode 40A, a fourth covered surface C2sB covered by the second external electrode 40B, and a second raised surface EpsB exposed from the first external electrode 40A and the second external electrode 40B and raised toward the center in the longitudinal direction L.
  • the second raised surface EpsB has a third flat surface FPB1, a fourth flat surface FPB2, a second recess DE2 as a recess, a third inclined surface FC3, and a fourth inclined surface FC4.
  • the second recess DE2 is a recessed portion formed in the center of the second raised surface EpsB in the length direction L and extending in the width direction W.
  • the third flat surface FPB1 is a surface perpendicular to the stacking direction T and is formed on the first end face LS1 side of the second recess DE2.
  • the fourth flat surface FPB2 is a surface perpendicular to the stacking direction T and is formed on the second end face LS2 side of the second recess DE2.
  • the third inclined surface FC3 connects the third flat surface FPB1 and the third coated surface C1sB.
  • the fourth inclined surface FC4 connects the fourth flat surface FPB2 and the fourth coated surface C2sB.
  • a third flat portion PB1 is formed on the third coated surface C1sB toward the center of the laminate, and a third inclined surface FC3 connects the third flat surface FPB1 and the third flat portion PB1.
  • a fourth flat portion PB2 is formed on the fourth coated surface C2sB toward the center of the laminate, and a fourth inclined surface FC4 connects the fourth flat surface FPB2 and the fourth flat portion PB2.
  • the second main surface TS2 of this embodiment has a third flat surface PB1 on the first end surface LS1 side, a fourth flat surface PB2 on the second end surface LS2 side, a third flat surface FPB1 disposed between the third flat surface PB1 and the second recess DE2 and protruding from the third flat surface PB1, a fourth flat surface FPB2 disposed between the fourth flat surface PB2 and the second recess DE2 and protruding from the fourth flat surface PB2, a third inclined surface FC3 connecting the third flat surface FPB1 and the third flat surface PB1, a fourth inclined surface FC4 connecting the fourth flat surface FPB2 and the fourth flat surface PB2, and a second recess DE2 formed to extend in the width direction W between the third flat surface FPB1 and the fourth flat surface FPB2.
  • the distance Lt1 in the longitudinal direction L of the first inclined surface FC1 and the distance Lt2 in the longitudinal direction L of the second inclined surface FC2 are shorter than the distance Lt0 in the longitudinal direction L from the end of the first flat surface FPA1 on the first end face LS1 side to the end of the second flat surface FPA2 on the second end face LS2 side.
  • the distance Lt1 in the longitudinal direction L of the third inclined surface FC3 and the distance Lt2 in the longitudinal direction L of the fourth inclined surface FC4 are shorter than the distance Lt0 in the longitudinal direction L from the end of the third flat surface FPB1 on the first end face LS1 side to the end of the fourth flat surface FPB2 on the second end face LS2 side.
  • the distance Lt0 from the end of the first flat surface FPA1 on the first end surface LS1 side to the end of the second flat surface FPA2 on the second end surface LS2 side is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. Furthermore, in the length direction L, the distance Lt0 from the end of the third flat surface FPB1 on the first end surface LS1 side to the end of the fourth flat surface FPB2 on the second end surface LS2 side is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the distance Lt0 in the length direction L from the end of the first flat surface FPA1 on the first end face LS1 side to the end of the second flat surface FPA2 on the second end face LS2 side is located within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the distance Lt0 in the longitudinal direction L from the end of the third flat surface FPB1 on the first end face LS1 side to the end of the fourth flat surface FPB2 on the second end face LS2 side is located within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B.
  • the end 40AE of the first external electrode 40A may be located on the first inclined surface FC1 and the third inclined surface FC3, or on the first flat surface PA1 and the third flat surface PB1 closer to the first end face LS1 than the first inclined surface FC1 and the third inclined surface FC3.
  • the end 40BE of the second external electrode 40B may be located on the second inclined surface FC2 and the fourth inclined surface FC4, or on the second flat surface PA2 and the fourth flat surface PB2 closer to the second end face LS2 than the second inclined surface FC2 and the fourth inclined surface FC4.
  • the end 40AE of the first external electrode 40A is located near the boundary between the first inclined surface FC1 and the first flat surface portion PA1, and near the boundary between the third inclined surface FC3 and the third flat surface portion PB1.
  • the end 40BE of the second external electrode 40B is located near the boundary between the second inclined surface FC2 and the second flat surface portion PA2, and near the boundary between the fourth inclined surface FC4 and the fourth flat surface portion PB2.
  • the inclination angle ⁇ of the first inclined surface FC1 relative to the first flat surface FPA1 is 1° or greater.
  • the inclination angle ⁇ of the first inclined surface FC1 relative to the first flat surface FPA1 may be 1° or greater and 10° or less. More preferably, the inclination angle ⁇ of the first inclined surface FC1 relative to the first flat surface FPA1 may be 2° or greater and 5° or less.
  • the inclination angle ⁇ of the second inclined surface FC2 relative to the second flat surface FPA2 be 1° or greater.
  • the inclination angle ⁇ of the second inclined surface FC2 relative to the second flat surface FPA2 may be 1° or greater and 10° or less. More preferably, the inclination angle ⁇ of the second inclined surface FC2 relative to the second flat surface FPA2 may be 2° or greater and 5° or less.
  • the inclination angle ⁇ of the third inclined surface FC3 relative to the third flat surface FPB1 be 1° or greater.
  • the inclination angle ⁇ of the third inclined surface FC3 relative to the third flat surface FPB1 may be 1° or greater and 10° or less. More preferably, the inclination angle ⁇ of the third inclined surface FC3 relative to the third flat surface FPB1 may be 2° or greater and 5° or less.
  • the inclination angle ⁇ of the fourth inclined surface FC4 relative to the fourth flat surface FPB2 be 1° or greater.
  • the inclination angle ⁇ of the fourth inclined surface FC4 relative to the fourth flat surface FPB2 may be 1° or greater and 10° or less. More preferably, the inclination angle ⁇ of the fourth inclined surface FC4 relative to the fourth flat surface FPB2 may be 2° or greater and 5° or less.
  • Figure 2C shows the inclination angle ⁇ of the third inclined surface FC3 relative to the third flat surface FPB1 on the second main surface TS2, and the inclination angle ⁇ of the fourth inclined surface FC4 relative to the fourth flat surface FPB2 on the second main surface TS2, as representative examples of the inclination angles ⁇ described above.
  • inclination angle ⁇ to 1° or more, and preferably 2° or more, it is possible to ensure an area for increasing the thickness of the internal electrode layers 30 in the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2.
  • the above-mentioned inclination angle ⁇ is 10° or less, and preferably 5° or less, it is possible to prevent the surface of the laminate 10 from expanding too much in the stacking direction T and protruding outward beyond the surface of the external electrode 40. More specifically, by setting the inclination angle ⁇ within the above-mentioned range, it becomes easy to set the relationship between the thicknesses of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 and the thicknesses of the first region EA1, second region EA2, third region EB1, and fourth region EB2 within the range of this embodiment.
  • first flat surface FPA1 is approximately parallel to a plane perpendicular to the stacking direction T. It is preferable that the first flat surface FPA1 is approximately parallel to the first and second flat portions PA1 and PA2. More preferably, the first flat surface FPA1 is approximately parallel to the plane perpendicular to the stacking direction T.
  • the second flat surface FPA2 is preferably approximately parallel to a plane perpendicular to the stacking direction T.
  • the second flat surface FPA2 is preferably approximately parallel to the first and second flat portions PA1 and PA2. More preferably, the second flat surface FPA2 is approximately parallel to the plane perpendicular to the stacking direction T.
  • the third flat surface FPB1 is approximately parallel to a plane perpendicular to the stacking direction T. It is preferable that the third flat surface FPB1 is approximately parallel to the third planar portion PB1 and the fourth planar portion PB2. More preferably, the third flat surface FPB1 is approximately parallel to the plane perpendicular to the stacking direction T.
  • the fourth flat surface FPB2 is approximately parallel to a plane perpendicular to the stacking direction T. It is preferable that the fourth flat surface FPB2 is approximately parallel to the third flat portion PB1 and the fourth flat portion PB2. More preferably, the fourth flat surface FPB2 is approximately parallel to the plane perpendicular to the stacking direction T.
  • the step distance tf in the stacking direction T between the first flat surface FPA1 formed by the first inclined surface FC1 and the first flat portion PA1, i.e., the protrusion height tf of the first flat surface FPA1 formed by the first inclined surface FC1 (the bulge dimension on one side of the laminate), is preferably smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1.
  • the step distance tf in the stacking direction T between the second flat surface FPA2 formed by the second inclined surface FC2 and the second flat portion PA2, i.e., the protrusion height tf of the second flat surface FPA2 formed by the second inclined surface FC2 (the bulge dimension on one side of the laminate), is preferably smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1.
  • the step distance tf in the stacking direction T between the third flat surface FPB1 formed by the third inclined surface FC3 and the third flat portion PB1, i.e., the protrusion height tf of the third flat surface FPB1 formed by the third inclined surface FC3 (the bulge dimension on one side of the laminate), is preferably smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2.
  • the step distance tf in the stacking direction T between the fourth flat surface FPB2 formed by the fourth inclined surface FC4 and the fourth flat portion PB2, i.e., the protrusion height tf of the fourth flat surface FPB2 formed by the fourth inclined surface FC4 (the bulge dimension on one side of the laminate), is preferably smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2.
  • the protrusion height tf of the first flat surface FPA1 formed by the first inclined surface FC1 is preferably 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the protrusion height tf of the first flat surface FPA1 formed by the first inclined surface FC1 may also be 2.9 ⁇ m or more and 12.6 ⁇ m or less.
  • the protrusion height tf of the second flat surface FPA2 formed by the second inclined surface FC2 is preferably 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the protrusion height tf of the second flat surface FPA2 formed by the second inclined surface FC2 may also be 2.9 ⁇ m or more and 12.6 ⁇ m or less.
  • the protrusion height tf of the third flat surface FPB1 formed by the third inclined surface FC3 is preferably 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the protrusion height tf of the third flat surface FPB1 formed by the third inclined surface FC3 may also be 2.9 ⁇ m or more and 12.6 ⁇ m or less.
  • the protrusion height tf of the fourth flat surface FPB2 formed by the fourth inclined surface FC4 is preferably 2.9 ⁇ m or more and 14.8 ⁇ m or less.
  • the protrusion height tf of the fourth flat surface FPB2 formed by the fourth inclined surface FC4 may also be 2.9 ⁇ m or more and 12.6 ⁇ m or less.
  • the protrusion height tf of the first flat surface FPA1 formed by the first inclined surface FC1 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height tf of the first flat surface FPA1 formed by the first inclined surface FC1 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the protrusion height tf of the second flat surface FPA2 formed by the second inclined surface FC2 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height tf of the second flat surface FPA2 formed by the second inclined surface FC2 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the protrusion height tf of the third flat surface FPB1 formed by the third inclined surface FC3 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height tf of the third flat surface FPB1 formed by the third inclined surface FC3 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the protrusion height tf of the fourth flat surface FPB2 formed by the fourth inclined surface FC4 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height tf of the fourth flat surface FPB2 formed by the fourth inclined surface FC4 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.
  • the thickness t01 in the stacking direction T in the first flat surface FPA1 region of the first principal surface side outer layer portion 12 is smaller than the thickness t11 in the stacking direction T in the first coated surface C1sA region of the first principal surface side outer layer portion 12 and the thickness t21 in the stacking direction T in the second coated surface C2sA region of the first principal surface side outer layer portion 12.
  • the thickness t01 in the stacking direction T in the second flat surface FPA2 region of the first principal surface side outer layer portion 12 is smaller than the thickness t11 in the stacking direction T in the first coated surface C1sA region of the first principal surface side outer layer portion 12 and the thickness t21 in the stacking direction T in the second coated surface C2sA region of the first principal surface side outer layer portion 12.
  • the thickness t02 in the stacking direction T in the third flat surface FPB1 region of the second principal surface side outer layer portion 13 is smaller than the thickness t12 in the stacking direction T in the first coated surface C1sA region of the second principal surface side outer layer portion 13 and the thickness t22 in the stacking direction T in the second coated surface C2sA region of the second principal surface side outer layer portion 13.
  • the thickness t02 in the stacking direction T in the fourth flat surface FPB2 region of the second principal surface side outer layer portion 13 is smaller than the thickness t12 in the stacking direction T in the first coated surface C1sA region of the second principal surface side outer layer portion 13 and the thickness t22 in the stacking direction T in the second coated surface C2sA region of the second principal surface side outer layer portion 13.
  • the crack can be prevented from reaching the internal electrode.
  • flat surfaces as part of the surface of the laminate 10 are arranged in a raised manner on both the first main surface TS1 and the second main surface TS2.
  • a flat surface as part of the surface of the laminate 10 may be arranged in a raised manner on either the first main surface TS1 or the second main surface TS2.
  • the first flat surface FPA1, the second flat surface FPA2, the third flat surface FPB1, and the fourth flat surface FPB2 have flat surfaces, but they may also be gently rounded surfaces overall.
  • the thickness in the length direction L of the first external electrode 40A at the center in the stacking direction T is thicker than the thickness in the length direction L on the first main surface TS1 side in the stacking direction T of the first external electrode 40A and the thickness in the length direction L on the second main surface TS2 side in the stacking direction T of the first external electrode 40A.
  • the thickness in the length direction L of the first external electrode 40A at the center in the width direction W of the first external electrode 40A is thicker than the thickness in the length direction L on the first side surface WS1 side in the width direction W of the first external electrode 40A and the thickness in the length direction L on the second side surface WS2 side in the width direction W of the first external electrode 40A.
  • the thickness in the length direction L of the second external electrode 40B at the center in the stacking direction T is thicker than the thickness in the length direction L of the second external electrode 40B on the first main surface TS1 side in the stacking direction T and the thickness in the length direction L of the second external electrode 40B on the second main surface TS2 side in the stacking direction T.
  • the thickness in the length direction L of the second external electrode 40B at the center in the width direction W is thicker than the thickness in the length direction L of the second external electrode 40B on the first side surface WS1 side in the width direction W and the thickness in the length direction L of the second external electrode 40B on the second side surface WS2 side in the width direction W.
  • the first internal electrode layer 31 of this embodiment preferably has the above-mentioned second region EA2, which has higher coverage and is thicker than the first region EA1, in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111.
  • the first internal electrode layer 31 may also have the above-mentioned second region EA2, which has higher coverage and is thicker than the first region EA1, in at least one portion of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113. This also achieves the effect of increasing capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • the second internal electrode layer 32 of this embodiment preferably has the above-mentioned fourth region EB2, which has higher coverage and is thicker than the third region EB1, in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111.
  • the second internal electrode layer 32 may also have the above-mentioned fourth region EB2, which has higher coverage and is thicker than the third region EB1, in at least one portion of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113. This also achieves the effect of increasing capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • the intermediate electrode layer 33 of this embodiment preferably has the sixth region ECA2 and eighth region ECB2, which have higher coverage and are thicker than the fifth region ECA1 and seventh region ECB1, in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111.
  • the second internal electrode layer 32 may have the sixth region ECA2 and eighth region ECB2, which have higher coverage and are thicker than the fifth region ECA1 and seventh region ECB1, in at least either the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113. This also has the effect of increasing capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • first inclined portion FA1, the second inclined portion FB1, the third inclined portion FCA1, the fourth inclined portion FCB1, the fifth inclined portion FA2, and the sixth inclined portion FB2 are arranged in the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113.
  • first inclined portion FA1, the second inclined portion FB1, the third inclined portion FCA1, the fourth inclined portion FCB1, the fifth inclined portion FA2, and the sixth inclined portion FB2 may also be arranged in at least one portion of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113.
  • the first internal electrode layer 31 of this embodiment preferably has the above-mentioned second region EA2, which has higher coverage and a greater thickness than the first region EA1, in the first side region 112E, the second side region 113E, and the central region 111E.
  • the present disclosure is not limited to this, by having the above-mentioned second region EA2, which has higher coverage and is thicker than the first region EA1, in the first side region 112E and the second side region 113E in addition to the central region 111E, it is possible to ensure the area of the second region EA2 with higher coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • at least the central region 111E may have the above-mentioned second region EA2, which has higher coverage and is thicker than the first region EA1.
  • the second internal electrode layer 32 of this embodiment preferably has the above-mentioned fourth region EB2, which has higher coverage and a greater thickness than the third region EB1, in the first side region 112E, the second side region 113E, and the central region 111E.
  • the present disclosure is not limited to this, by having the above-mentioned fourth region EB2, which has higher coverage and is thicker than the third region EB1, in the first side region 112E and the second side region 113E in addition to the central region 111E, it is possible to ensure the area of the fourth region EB2 with higher coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • at least the central region 111E may have the above-mentioned fourth region EB2, which has higher coverage and is thicker than the third region EB1.
  • the intermediate electrode layer 33 of this embodiment preferably has the sixth region ECA2 and eighth region ECB2, which have higher coverage and are thicker than the fifth region ECA1 and seventh region ECB1, in the first side region 112E, the second side region 113E, and the central region 111E.
  • the present disclosure is not limited to this, by providing the sixth region ECA2 and eighth region ECB2, which have higher coverage and are thicker than the fifth region ECA1 and seventh region ECB1, in the first side region 112E and second side region 113E in addition to the central region 111E, the area of the sixth region ECA2 and eighth region ECB2, which have higher coverage, can be secured, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.
  • at least the central region 111E may have the sixth region ECA2 and eighth region ECB2, which have higher coverage and are thicker than the fifth region ECA1 and seventh region ECB1.
  • the end of the intermediate electrode layer 33 on the first end face LS1 side is located closer to the first end face LS1 than the end face 40AE of the first external electrode 40A.
  • the end of the intermediate electrode layer 33 on the second end face LS2 side is located closer to the second end face LS2 than the end face 40BE of the second external electrode 40B.
  • the first electrode layer side facing portion ECA of the intermediate electrode layer 33 does not have the fifth region ECA1 but has only the sixth region ECA2, and the second electrode layer side facing portion ECB of the intermediate electrode layer 33 does not have the seventh region ECB1 but has only the eighth region ECB2.
  • the first electrode layer side facing portion ECA, second electrode layer side facing portion ECB, and connecting portion E0 of the intermediate electrode layer 33 may have the same thickness.
  • the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to expose the LT cross section where the series capacitor forming portion 11E of the laminate 10 is exposed. If necessary, the exposed cross section at the observation position is etched to remove the internal electrode layer 30 that has been stretched by polishing. Of the exposed cross section, measurement points M1 to M8, described below, are observed using an SEM (scanning electron microscope). Note that, for example, if only the first main surface side inner layer portion 112 has the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2, which have high coverage and a large thickness, measurement points M1 to M4 are observed using an SEM.
  • Measurement points are set in areas with high coverage and thick thickness, and areas with low coverage and thin thickness.
  • the measurement value is the average value for each area. Since the multilayer ceramic capacitor 1 according to this embodiment has a double structure, measurement points M1 to M8, described below, are set, but it is preferable to set measurement points according to the structure of the multilayer ceramic capacitor.
  • Measurement points M1 to M4 are set in the first main surface side inner layer portion 112.
  • Measurement point M1 is a portion of the first main surface side inner layer portion 112 that includes the first region EA1 of the first internal electrode layer 31 and the fifth region ECA1 of the intermediate electrode layer 33.
  • Measurement point M2 is a portion of the first main surface side inner layer portion 112 that includes the second region EA2 of the first internal electrode layer 31 and the sixth region ECA2 of the intermediate electrode layer 33.
  • Measurement point M3 is a portion of the first main surface side inner layer portion 112 that includes the fourth region EB2 of the second internal electrode layer 32 and the eighth region ECB2 of the intermediate electrode layer 33.
  • Measurement point M4 is a portion of the first main surface side inner layer portion 112 that includes the third region EB1 of the second internal electrode layer 32 and the seventh region ECB1 of the intermediate electrode layer 33.
  • Measurement points M5 to M8 are set in the second main surface side inner layer portion 113.
  • Measurement point M5 is a portion of the second main surface side inner layer portion 113 that includes the first region EA1 of the first internal electrode layer 31 and the fifth region ECA1 of the intermediate electrode layer 33.
  • Measurement point M6 is a portion of the second main surface side inner layer portion 113 that includes the second region EA2 of the first internal electrode layer 31 and the sixth region ECA2 of the intermediate electrode layer 33.
  • Measurement point M7 is a portion of the second main surface side inner layer portion 113 that includes the fourth region EB2 of the second internal electrode layer 32 and the eighth region ECB2 of the intermediate electrode layer 33.
  • Measurement point M8 is a portion of the second main surface side inner layer portion 113 that includes the third region EB1 of the second internal electrode layer 32 and the seventh region ECB1 of the intermediate electrode layer 33.
  • Measurement points M1 and M5 are set in the length direction L at the center position of the distance Le1 shown in FIG. 2C.
  • Measurement points M2 and M6 are set in the length direction L at the center position of the second region EA2 of the first internal electrode layer 31 shown in FIG. 2C.
  • Measurement points M3 and M7 are set in the length direction L at the center position of the fourth region EB2 of the second internal electrode layer 32 shown in FIG. 2C.
  • Measurement points M4 and M8 are set in the length direction L at the center position of the distance Le2 shown in FIG. 2C.
  • Measurement points M2, M3, M6, and M7 are set in areas with high coverage and high thickness, while measurement points M1, M4, M5, and M8 are set in areas with low coverage and low thickness.
  • FIG. 5 is a diagram illustrating an example of a magnified SEM image of the cross section of the exposed internal layer at the measurement point.
  • the pitch S can be set to approximately 5 to 10 times the thickness of the internal electrode layers 30 to be measured. For example, when measuring an internal electrode with a thickness of approximately 0.5 ⁇ m, the pitch S should be set to 2.5 ⁇ m.
  • the thickness d1 on line La, the thickness d2 on line Lb, the thickness d3 on line Lc, the thickness d4 on line Ld, and the thickness d5 on line Le are measured. Then, for each of the measurement points on the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113, the thickness of each of the five internal electrode layers 30 is measured using the above method, and the average value is taken as the thickness of the internal electrode layers 30 in this embodiment.
  • the thickness of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 which are regions with high coverage and large thickness
  • the thickness is measured at 25 points (5 locations x 5 layers) at measurement points M2, M3, M6, and M7, respectively, and the average value of a total of 100 points is used as the thickness of the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2 in this embodiment.
  • the thickness of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1 which are regions with low coverage and thin thickness
  • the thickness is measured at 25 points (5 locations x 5 layers) at each of measurement points M1, M4, M5, and M8, and the average value of a total of 100 points is used as the thickness of the first region EA1, third region EB1, fifth region ECA1, and seventh region ECB1 in this embodiment.
  • the thickness of the dielectric layer 20 is also measured in the same manner as the internal electrode layer 30.
  • the thickness D1 on the line La, the thickness D2 on the line Lb, the thickness D3 on the line Lc, the thickness D4 on the line Ld, and the thickness D5 on the line Le are measured.
  • the thickness of each of the four dielectric layers 20 is measured using the above method at each measurement point in the first main surface side inner layer portion 112 and each measurement point in the second main surface side inner layer portion 113, and the average value is taken as the thickness of the dielectric layer 20 of this embodiment.
  • the thickness of the dielectric layer 20 can be measured for each of the regions corresponding to the second region EA2, fourth region EB2, sixth region ECA2, and eighth region ECB2, the regions corresponding to the first region EA1 and fifth region ECA1, and the regions corresponding to the third region EB1 and seventh region ECB1.
  • measurements can be performed at eight measurement points M1 to M8 at three locations: the center position in the width direction W of the first side region 112E, the center position in the width direction W of the central region 111E, and the center position in the width direction W of the second side region 113E.
  • ⁇ Coverage measurement method> A description will now be given of a method for measuring coverage as the coverage rate of the internal electrode layers 30 relative to the dielectric layers 20. Note that the measurement of coverage in this measurement method is also referred to as measurement of line coverage.
  • the line coverage of the exposed LT cross section is measured using an optical microscope.
  • the measurement points for measuring line coverage are the same as those for measurement points M1 to M8 described above. However, the magnification for observing each measurement point is 1000x.
  • the internal electrode layer 30 has regions where conductive components are present and regions where conductive components are not present, such as hollow portions.
  • Line coverage is calculated as the ratio of the length in the length direction L of the region occupied by the conductive components that actually constitute the internal electrode layer 30 to the length in the length direction L of the internal electrode layer 30 in an optical microscope image without taking into account the presence or absence of conductive components, i.e., the ratio of the length in the length direction L of the internal electrode layer 30 excluding the region where conductive components are not present to the length in the length direction L of the internal electrode layer 30 without taking into account the presence or absence of conductive components.
  • the coverage of the internal electrode layer 30 is then measured for each measurement point on the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113, and the average value is taken as the coverage of the internal electrode layer 30 in this embodiment.
  • the coverage of the internal electrode layer 30 is measured at measurement points M2, M3, M6, and M7, respectively, and the average value is used as the coverage of the second region EA2, the fourth region EB2, the sixth region ECA2, and the eighth region ECB2 in this embodiment.
  • the coverage of the internal electrode layer 30 is measured at measurement points M1, M4, M5, and M8, respectively, and the average value is used as the coverage of the first region EA1, the third region EB1, the fifth region ECA1, and the seventh region ECB1 in this embodiment.
  • a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described.
  • the method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements.
  • a suitable manufacturing method includes the following steps. Each step will be described in detail below.
  • a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared.
  • the dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent.
  • the binder and solvent may be known.
  • a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing. This results in the preparation of a dielectric sheet on which the pattern for the first internal electrode layer 31 and the pattern for the second internal electrode layer 32 are formed, and a dielectric sheet on which the pattern for the intermediate electrode layer 33 is formed. Note that the printing method is not limited to screen printing, etc.
  • Figure 6 is a schematic diagram showing the cross section of the dielectric sheet when conductive paste P1 is printed.
  • Figure 7 is a schematic diagram showing the cross section of the dielectric sheet when conductive paste P2 is printed on the dielectric sheet of Figure 6.
  • the dielectric sheet on which the pattern of the internal electrode layer 30 is printed is composed of a ceramic green sheet G and conductive paste P1 and conductive paste P2 placed on the ceramic green sheet G.
  • the conductive paste P1 and conductive paste P2 are formed by the hollow portions of the screen S1 and the hollow portions of the screen S2.
  • a conductive paste P1 is placed on a ceramic green sheet G using a screen S1 having a hollow portion formed in a pattern corresponding to the outer shape of the intermediate electrode layer 33, for example.
  • a screen S2 having hollow portions formed in a pattern corresponding to the sixth region ECA2, the eighth region ECB2, and the connecting portion E0 is used to screen-print conductive paste P2 onto the conductive paste P1.
  • the portions corresponding to the sixth region ECA2 and the eighth region ECB2 become thicker than the other regions by the amount of conductive paste P2 screen-printed.
  • the conductive paste P1 and conductive paste P2 shown in Figure 7 are the portions that will become the intermediate electrode layer 33 of the multilayer ceramic capacitor. In this way, a dielectric sheet on which the conductive paste P33 is formed is prepared.
  • a screen with hollow portions formed in a pattern corresponding to the second region EA2 and fourth region EB2 is used to screen-print the conductive paste corresponding to the second region EA2 and fourth region EB2 onto the conductive paste corresponding to the first internal electrode layer 31 and second internal electrode layer 32.
  • the portions corresponding to the second region EA2 and fourth region EB2 are thicker than the other regions by the amount of conductive paste P2 screen-printed. In this way, a dielectric sheet on which conductive pastes P31 and P32 are formed is prepared.
  • dielectric sheets G1 on which conductive pastes P31 and P32, which will become the first internal electrode layer 31 and the second internal electrode layer 32, are arranged, and dielectric sheets G2, on which conductive paste P33, which will become the intermediate electrode layer 33, are arranged, are sequentially laminated alternately.
  • portion C in FIG. 8 is cut out in a subsequent process to form a single laminated chip.
  • a dielectric paste may be placed between the conductive pastes P31 and P32 to prevent the formation of the first recess DE1 and second recess DE2.
  • a predetermined number of dielectric sheets, on which the pattern of the internal electrode layer 30 is not printed, are laminated on the surface of portion P11, which will become the inner layer portion 11, to form portion P13, which will become the second main surface outer layer portion 13 on the second main surface TS2 side. This completes the laminated sheet.
  • the laminated sheets are pressed vertically using a means such as an isostatic press to create a laminated block.
  • the laminated block is cut to a specified size to produce laminated chips.
  • the corners and ridges of the laminated chips may be rounded by barrel polishing or other methods.
  • the laminated chip is fired to produce the laminate 10.
  • the firing temperature depends on the materials of the dielectric layers 20 and internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.
  • Conductive paste is applied to both end surfaces of the laminate 10 to form the base electrode layer.
  • conductive paste is also applied to the first principal surface TS1 and second principal surface TS2 and the first side surface WS1 and second side surface WS2 of the laminate 10.
  • the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lt0 in the length direction L from the end of the second region EA2 on the first end face LS1 side to the end of the fourth region EB2 on the second end face LS2 side in the length direction L, or the distance Lt0 in the length direction L from the end of the sixth region ECA2 on the first end face LS1 side to the end of the eighth region ECB2 on the second end face LS2 side in the length direction L.
  • the first main surface TS1 or the second main surface TS2 of the laminate 10 has a first flat surface FPA1, a second flat surface FPA2, a third flat surface FPB1, a fourth flat surface FPB2, a first recess DE1, and a second recess DE2, which correspond to the positions of the second region EA2, the fourth region EB2, the sixth region ECA2, and the eighth region ECB2. Also formed around these are a first inclined surface FC1, a second inclined surface FC2, a third inclined surface FC3, and a fourth inclined surface FC4. Furthermore, a first flat surface PA1, a second flat surface PA2, a third flat surface PB1, and a fourth flat surface PB2 are formed closer to the end surface than each inclined surface.
  • conductive paste is applied to the first flat surface PA1, second flat surface PA2, third flat surface PB1, and fourth flat surface PB2, which are closer to the end surface than each inclined surface.
  • the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lt0 in the length direction L from the end of the second region EA2 on the first end surface LS1 side to the end of the fourth region EB2 on the second end surface LS2 side, or the distance Lt0 in the length direction L from the end of the sixth region ECA2 on the first end surface LS1 side to the end of the eighth region ECB2 on the second end surface LS2 side.
  • conductive paste may also be applied to portions of the end surface sides of the first inclined surface FC1, second inclined surface FC2, third inclined surface FC3, and fourth inclined surface FC4.
  • the base electrode layer can also be removed after the baking process for adjustment.
  • the base electrode layer is a baked layer.
  • a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping.
  • a baking process is then performed to form the base electrode layer.
  • the baking temperature at this time is preferably 700°C or higher and 900°C or lower.
  • the fired layer When firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the fired layer by firing a material to which a ceramic material has been added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material to be added.
  • the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 10 with the fired layer formed.
  • a plating layer is formed on the surface of the base electrode layer.
  • a first plating layer 60A is formed on the surface of the first base electrode layer 50A.
  • a second plating layer 60B is formed on the surface of the second base electrode layer 50B.
  • a Ni plating layer and a Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process.
  • electroless plating has the disadvantage of requiring pretreatment using a catalyst or other means to improve the plating deposition rate, which makes the process more complicated. Therefore, electrolytic plating is usually preferred.
  • the Ni plating layer and Sn plating layer are formed sequentially, for example, by barrel plating.
  • the conductive resin layer When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be disposed so as to cover the baked layer.
  • a conductive resin paste containing a thermosetting resin and a metal component is applied to the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer.
  • the atmosphere during this heat treatment is preferably an N2 atmosphere.
  • the oxygen concentration is preferably 100 ppm or less.
  • the multilayer ceramic capacitor 1 is manufactured through this manufacturing process.
  • the multilayer ceramic capacitor 1 according to the second embodiment is not limited to the configuration shown in Figures 1 to 4B.
  • the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor with a triple structure as shown in Figure 9, and the effects of the present disclosure can be obtained.
  • FIG. 9 is a diagram illustrating the general configuration of a triple-layer laminate according to the second embodiment, and corresponds to Figure 2A in the first embodiment.
  • Figure 10 is a schematic diagram showing a portion of a laminate sheet in which a portion that will become the first main surface side outer layer portion and a portion that will become the second main surface side outer layer portion are formed above and below a portion that will become the inner layer portion in the second embodiment.
  • the multilayer ceramic capacitor 1 according to the first embodiment has a first recess DE1 formed as a recess at approximately the center in the length direction L on the first main surface TS1, and a second recess DE2 formed as a recess at approximately the center in the length direction L on the second main surface TS2.
  • the multilayer ceramic capacitor 1 according to the second embodiment has two first recesses DE1 formed on the first main surface TS1 and two second recesses DE2 formed on the second main surface TS2.
  • the multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and an intermediate electrode layer 33.
  • the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332.
  • the first intermediate electrode layer 331 has a first electrode layer side facing portion EC1A, a first intermediate electrode layer facing portion EC1B, and a first connecting portion E10.
  • the first electrode layer side facing portion EC1A is an area facing the first internal electrode layer 31 arranged adjacently in the stacking direction T, and is located inside the laminate 10.
  • the first intermediate electrode layer facing portion EC1B is an area facing the second intermediate electrode layer 332 arranged adjacently in the stacking direction T, and is located inside the laminate 10.
  • the first connecting portion E10 is a portion that connects the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B, and is located between the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B.
  • the second intermediate electrode layer 332 has a second electrode layer side facing portion EC2A, a second intermediate electrode layer facing portion EC2B, and a second connecting portion E20.
  • the second electrode layer side facing portion EC2A faces the second internal electrode layer 32 arranged adjacently in the stacking direction T.
  • the second intermediate electrode layer facing portion EC2B faces the first intermediate electrode layer 331 arranged adjacently in the stacking direction T.
  • the second connecting portion E20 connects the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B, and is arranged between the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B.
  • the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the longitudinal direction L.
  • the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the longitudinal direction L.
  • the first internal electrode layer 31 and the second intermediate electrode layer 332, and the second internal electrode layer 32 and the first intermediate electrode layer 331 are stacked alternately with the dielectric layer 20 interposed therebetween.
  • the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion).
  • the second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer, thereby forming a capacitance CAP2 (second capacitor portion).
  • the first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B face each other via the dielectric layer 20, thereby forming a capacitance CAP3 (third capacitor portion).
  • the first connecting portion E10 connects the capacitances CAP1 and CAP3 in series.
  • the second connecting portion E20 connects the capacitances CAP2 and CAP3 in series.
  • the multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called triplet series structure, in which three series-connected capacitor portions are formed.
  • the shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion EC1A, the first intermediate electrode layer side opposing portion EC1B, the second electrode layer side opposing portion EC2A, and the second intermediate electrode layer side opposing portion EC2B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.
  • the shapes of the first lead-out portion D1 and the second lead-out portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.
  • the laminate 10 has a series capacitor forming portion 11E.
  • the series capacitor forming portion 11E includes a portion where the first opposing portion EA of the first internal electrode layer 31 faces the first electrode layer side opposing portion EC1A of the intermediate electrode layer 33 (portion forming capacitance CAP1), a portion where the second opposing portion EB of the second internal electrode layer 32 faces the second electrode layer side opposing portion EC2A of the intermediate electrode layer 33 (portion forming capacitance CAP2), a portion where the first intermediate electrode layer opposing portion EC1B of the intermediate electrode layer 33 faces the second intermediate electrode layer opposing portion EC2B (portion forming capacitance CAP3), a portion connecting capacitances CAP1 and CAP3 in series, and a portion connecting capacitances CAP2 and CAP3 in series.
  • the series capacitor forming portion 11E is configured as part of the inner layer portion 11.
  • the portion forming capacitance CAP1 first capacitor portion
  • the portion forming capacitance CAP2 second capacitor portion
  • the portion forming capacitance CAP3 third capacitor portion
  • effective capacitor portions are also referred to as effective capacitor portions.
  • the series capacitor forming portion 11E of the laminate 10 has a first series connection region and a second series connection region.
  • the first series connection region is a portion including the dielectric layer 20 and the first coupling portion E10, located between the portion forming the capacitance CAP1 and the portion forming the capacitance CAP3.
  • the second series connection region is a portion including the dielectric layer 20 and the second coupling portion E20, located between the portion forming the capacitance CAP2 and the portion forming the capacitance CAP3.
  • the first series connection region is a collection of portions of the multiple dielectric layers 20 that overlap with the first coupling portion E10 when viewed from the stacking direction T, and multiple first coupling portions E10.
  • the second series connection region is a collection of portions of the multiple dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T, and multiple second coupling portions E20.
  • the external electrode 40 has a first external electrode 40A arranged on the first end surface LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end surface LS2 side of the laminate 10.
  • the first connecting portion E10 connects the capacitances CAP1 and CAP3 in series.
  • the second connecting portion E20 connects the capacitances CAP2 and CAP3 in series.
  • the multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the form of the internal electrode layers 30 inside the laminate 10. Specifically, while the multilayer ceramic capacitor 1 of the first embodiment has a double internal electrode layer 30, the multilayer ceramic capacitor 1 of the second embodiment has a triple internal electrode layer 30, and the form of the internal electrode layers 30 inside the laminate 10 differs from that of the first embodiment.
  • the thickness of the internal electrode layers is increased by the manufacturing method described above.
  • the internal electrode layers 30 in areas with high coverage are thicker than the internal electrode layers 30 in areas with low coverage.
  • an inclined portion in which the thickness changes gradually is formed between the internal electrode layers 30 in the high coverage region and the internal electrode layers 30 in the low coverage region. Furthermore, in the high coverage region, a raised surface is formed on the first main surface TS1 and the second main surface TS2. Furthermore, an inclined surface is formed between the raised surface in the high coverage region and the flat portion in the other region. Furthermore, as in the multilayer ceramic capacitor 1 according to the first embodiment, if there is a gap between two internal electrode layers 30 aligned in the length direction L at the center of the length direction L in the high coverage region, a recess may be formed in the raised surface at a position corresponding to the gap in the length direction L.
  • the same configuration as that of the first embodiment, which is formed by increasing the thickness of the internal electrode layers using the manufacturing method described above in order to improve coverage, may be omitted.
  • the first opposing portion EA of the first internal electrode layer 31 has a first region EA1 and a second region EA2.
  • the second opposing portion EB of the second internal electrode layer 32 has a third region EB1 and a fourth region EB2.
  • the first electrode layer side facing portion EC1A of the first intermediate electrode layer 331 has a fifth region EC1A1 and a sixth region EC1A2.
  • the fifth region EC1A1 is the region of the first electrode layer side facing portion EC1A on the first end face LS1 side.
  • the sixth region EC1A2 is the region of the first electrode layer side facing portion EC1A on the second end face LS2 side.
  • the second electrode layer side facing portion EC2A of the second intermediate electrode layer 332 has a seventh region EC2A1 and an eighth region EC2A2.
  • the seventh region EC2A1 is the region of the second electrode layer side facing portion EC2A on the second end face LS2 side.
  • the eighth region EC2A2 is the region of the second electrode layer side facing portion EC2A on the first end face LS1 side.
  • the coverage of the first intermediate electrode layer opposing portion EC1B and the coverage of the second intermediate electrode layer opposing portion EC2B are higher than the coverage of the area on the first end face LS1 side of the first opposing portion EA and the coverage of the area on the second end face LS2 side of the second opposing portion EB.
  • the coverage of the first intermediate electrode layer facing portion EC1B and the coverage of the second intermediate electrode layer facing portion EC2B are higher than the coverage of the area on the first end face LS1 side of the first electrode layer side facing portion EC1A and the coverage of the area on the second end face LS2 side of the second electrode layer side facing portion EC2A.
  • the thickness of the internal electrode layer 30 in the second region EA2, fourth region EB2, sixth region EC1A2, first intermediate electrode layer opposing portion EC1B, eighth region EC2A2, and second intermediate electrode layer opposing portion EC2B to be increased, improving coverage and increasing capacitance while preventing the size of the multilayer ceramic capacitor 1 from increasing. It is preferable that the thickness of the first connecting portion E10 of the first intermediate electrode layer 331 be the same as the thickness of the sixth region EC1A2 of the first electrode layer side opposing portion EC1A and the first intermediate electrode layer opposing portion EC1B.
  • the thickness of the second connecting portion E20 of the second intermediate electrode layer 332 be the same as the thickness of the eighth region EC2A2 of the second electrode layer side opposing portion EC2A and the second intermediate electrode layer opposing portion EC2B. This allows the capacitances CAP1, CAP2, and CAP3 to be connected in series with higher reliability. It also facilitates manufacturing. However, this is not limited to this.
  • the multiple internal electrode layers 30 further have inclined portions.
  • the first internal electrode layer 31 has a first inclined portion FA1 connecting the first region EA1 and the second region EA2.
  • the second internal electrode layer 32 has a second inclined portion FB1 connecting the third region EB1 and the fourth region EB2.
  • the first intermediate electrode layer 331 has a third inclined portion FCA1 connecting the fifth region EC1A1 and the sixth region EC1A2.
  • the second intermediate electrode layer 332 has a fourth inclined portion FCB1 connecting the seventh region EC2A1 and the eighth region EC2A2.
  • the first internal electrode layer 31 further has a fifth inclined portion FA2 located in the first lead portion D1.
  • the fifth inclined portion FA2 is preferably located closer to the first end face LS1 than the end of the first intermediate electrode layer 331 on the first end face LS1 side in the longitudinal direction L.
  • the second internal electrode layer 32 further has a sixth inclined portion FB2 located in the second lead portion D2.
  • the sixth inclined portion FB2 is preferably located closer to the second end face LS2 than the end of the second intermediate electrode layer 332 on the second end face LS2 side in the longitudinal direction L.
  • FIG. 9 it has a first raised surface EpsA that is exposed from the first external electrode 40A and the second external electrode 40B and that raises toward the center in the longitudinal direction L.
  • the first raised surface EpsA has a first flat surface FPA1 and two first recesses DE1.
  • the first recesses DE1 are concave portions formed to extend in the width direction W.
  • the two first recesses DE1 are formed at positions on the first flat surface FPA1 in the length direction L that correspond to the gaps between the first internal electrode layer 31 and the second internal electrode layer 32.
  • the first flat surface FPA1 is a surface perpendicular to the stacking direction T and is located approximately in the center of the length direction L of the first main surface TS1.
  • the second principal surface TS2 has a second raised surface EpsB that is exposed from the first external electrode 40A and the second external electrode 40B and that raises toward the center in the longitudinal direction L.
  • the second raised surface EpsB has a third flat surface FPB1 and two second recesses DE2.
  • the second recesses DE2 are concave portions formed to extend in the width direction W.
  • the two second recesses DE2 are formed at positions on the third flat surface FPB1 in the length direction L that correspond to the gaps between the first internal electrode layer 31 and the second internal electrode layer 32.
  • the measurement method for various parameters will be described below. As mentioned above, the description of the same configuration as in the first embodiment may be omitted.
  • the multilayer ceramic capacitor 1 according to the second embodiment has a triplet structure, unlike the first embodiment. Therefore, the measurement points in the measurement method according to the second embodiment are different from those in the first embodiment. The measurement points according to this embodiment will be described below.
  • Measurement points are set in areas with high coverage and high thickness, and areas with low coverage and low thickness.
  • the measurement value is the average value for each area.
  • measurement points MB1 to MB10 described below, are set.
  • Measurement points MB1 to MB5 are set in the first main surface side inner layer portion 112.
  • Measurement point MB1 is a portion of the first main surface side inner layer portion 112 that includes the first region EA1 of the first internal electrode layer 31 and the fifth region EC1A1 of the first intermediate electrode layer 331.
  • Measurement point MB2 is a portion of the first main surface side inner layer portion 112 that includes the second region EA2 of the first internal electrode layer 31 and the sixth region EC1A2 of the first intermediate electrode layer 331.
  • Measurement point MB3 is a portion of the first main surface side inner layer portion 112 that includes the first intermediate electrode layer facing portion EC1B of the first intermediate electrode layer 331 and the second intermediate electrode layer facing portion EC2B of the second intermediate electrode layer 332.
  • Measurement point MB4 is a portion of the first main surface side inner layer portion 112 that includes the fourth region EB2 of the second internal electrode layer 32 and the eighth region EC2A2 of the second intermediate electrode layer 332.
  • Measurement point MB5 is a portion of the first main surface side inner layer portion 112 that includes the third region EB1 of the second internal electrode layer 32 and the seventh region EC2A1 of the second intermediate electrode layer 332.
  • Measurement points MB6 to MB10 are set in the second main surface side inner layer portion 113.
  • Measurement point MB6 is a portion of the second main surface side inner layer portion 113 that includes the first region EA1 of the first internal electrode layer 31 and the fifth region EC1A1 of the first intermediate electrode layer 331.
  • Measurement point MB7 is a portion of the second main surface side inner layer portion 113 that includes the second region EA2 of the first internal electrode layer 31 and the sixth region EC1A2 of the first intermediate electrode layer 331.
  • Measurement point MB8 is a portion of the second main surface side inner layer portion 113 that includes the first intermediate electrode layer facing portion EC1B of the first intermediate electrode layer 331 and the second intermediate electrode layer facing portion EC2B of the second intermediate electrode layer 332.
  • Measurement point MB9 is a portion of the second main surface side inner layer portion 113 that includes the fourth region EB2 of the second internal electrode layer 32 and the eighth region EC2A2 of the second intermediate electrode layer 332.
  • Measurement point MB10 is a portion of the second main surface side inner layer portion 113 that includes the third region EB1 of the second internal electrode layer 32 and the seventh region EC2A1 of the second intermediate electrode layer 332.
  • Measurement points MB1 and MB6 are set in the length direction L at the center position of the distance Le1 shown in FIG. 9.
  • Measurement points MB2 and MB7 are set in the length direction L at the center position of the second region EA2 of the first internal electrode layer 31 shown in FIG. 9.
  • Measurement points MB3 and MB8 are set in the length direction L at the center position of the distance Le0 shown in FIG. 9.
  • Measurement points MB4 and M9 are set in the length direction L at the center position of the fourth region EB2 of the second internal electrode layer 32 shown in FIG. 9.
  • Measurement points M5 and M10 are set in the length direction L at the center position of the distance Le2 shown in FIG. 9.
  • the multilayer ceramic capacitor 1 of the second embodiment may be manufactured by any method as long as it satisfies the above-mentioned requirements.
  • a suitable manufacturing method includes the following steps. Each step will be described in detail below.
  • the laminate sheet is made by stacking dielectric sheets.
  • the method for creating a dielectric sheet as shown in Figures 6 and 7 is the same as in the first embodiment, so explanation will be omitted.
  • dielectric sheets G1 on which conductive pastes P31 and P332, which will become the first internal electrode layer 31 and the second intermediate electrode layer 332, are arranged, and dielectric sheets G2, on which conductive pastes P331 and P32, which will become the first intermediate electrode layer 331 and the second internal electrode layer 32, are arranged, are sequentially laminated alternately.
  • portion C in FIG. 8 is cut out in a subsequent process to form a single laminated chip.
  • a predetermined number of dielectric sheets, on which the pattern of the internal electrode layer 30 is not printed, are laminated on the surface of portion P11, which will become the inner layer portion 11, to form portion P13, which will become the second main surface outer layer portion 13 on the second main surface TS2 side. This completes the laminated sheet.
  • conductive paste P2 is applied to the portions that will become the second region EA2 of the first internal electrode layer 31, the fourth region EB2 of the second internal electrode layer 32, the sixth region EC1A2 of the first intermediate electrode layer 331, the eighth region EC2A2 of the second intermediate electrode layer 332, the first intermediate electrode layer opposing portion EC1B, and the second intermediate electrode layer opposing portion EC2B.
  • the second region EA2 of the first internal electrode layer 31, the fourth region EB2 of the second internal electrode layer 32, the sixth region EC1A2 of the first intermediate electrode layer 331, the eighth region EC2A2 of the second intermediate electrode layer 332, the first intermediate electrode layer opposing portion EC1B, and the second intermediate electrode layer opposing portion EC2B become thicker, resulting in high coverage portions.
  • high coverage regions are also arranged in the first internal electrode layer 31 and the second internal electrode layer 32 as shown in Fig. 9, but the present invention is not limited to this configuration.
  • high coverage regions may be arranged only in the intermediate electrode layer 33 as shown in Fig. 11, and high coverage regions may not be arranged in the first internal electrode layer 31 and the second internal electrode layer 32.
  • FIG. 11 is a schematic diagram illustrating the range of the high coverage portion of the triple-structure laminate according to the third embodiment.
  • Figure 12 is a schematic diagram showing a portion of a laminate sheet in which a portion that will become the first main surface side outer layer portion and a portion that will become the second main surface side outer layer portion are formed above and below a portion that will become the inner layer portion in the third embodiment.
  • the multilayer ceramic capacitor 1 of this embodiment differs from the second embodiment in the configuration of the internal electrode layers inside the laminate 10. Specifically, in the triple-structure multilayer ceramic capacitor 1 of the second embodiment, high coverage portions were set in the first internal electrode layer 31, the second internal electrode layer 32, the first intermediate electrode layer 331, and the second intermediate electrode layer 332. However, in the triple-structure multilayer ceramic capacitor 1 of the third embodiment, as shown in FIG. 11, high coverage portions are not set in the first internal electrode layer 31 and the second internal electrode layer 32, but are set in the first intermediate electrode layer 331 and the second intermediate electrode layer 332.
  • the method for measuring various parameters in the third embodiment is basically the same as that in the above-described embodiments.
  • the measurement points in the measurement method in the third embodiment are the same as those in the second embodiment, except for MB2, MB4, MB7, and MB9.
  • a method for manufacturing the multilayer ceramic capacitor 1 of the third embodiment will be described. As mentioned above, the description of the same configuration as in the first embodiment may be omitted.
  • the multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.
  • portion P12 screen-printed dielectric sheets such as those shown in FIG. 7 are sequentially laminated on the surface of portion P12, which will become the first main surface side outer layer portion 12, to form portion P11, which will become the inner layer portion 11.
  • dielectric sheets G1 on which conductive pastes P31 and P332, which will become the first internal electrode layer 31 and the second intermediate electrode layer 332, are arranged, and dielectric sheets G2, on which conductive paste P32, which will become the first intermediate electrode layer 331 and the second internal electrode layer 32, are arranged, are sequentially laminated alternately.
  • portion C in FIG. 12 is cut out in a subsequent process to form a single laminated chip.
  • the conductive paste P2 is applied only to the portion that will become the intermediate electrode layer 33, and as shown in Figure 11, only the intermediate electrode layer 33 is thick, creating a high coverage portion.
  • the multilayer ceramic capacitor 1 according to the fourth embodiment is not limited to the configuration shown in Figures 1 to 4B.
  • the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a four-layer structure as shown in Figure 13.
  • FIG. 13 is a schematic diagram illustrating the range of the high coverage portion of the four-layer structure laminate 10 according to the fourth embodiment.
  • Figure 14 is a schematic diagram showing a portion of a laminate sheet in which a portion that will become the first main surface side outer layer portion 12 and a portion that will become the second main surface side outer layer portion 13 are formed above and below a portion that will become the inner layer portion 11 in the fourth embodiment.
  • the multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layers 30 inside the laminate 10 and the external electrodes 40. Specifically, while the multilayer ceramic capacitor 1 of the first embodiment has a two-layer internal electrode layer 30, the multilayer ceramic capacitor 1 of the fourth embodiment has a four-layer internal electrode layer 30, and the configuration of the internal electrode layers 30 inside the laminate 10 differs from that of the first embodiment.
  • the multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and an intermediate electrode layer 33.
  • the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333.
  • the first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A that faces the first internal electrode layer 31 arranged adjacently in the stacking direction T, a first intermediate electrode layer opposing portion EC1B that faces the third intermediate electrode layer 333 arranged adjacently in the stacking direction T, and a first connecting portion E10.
  • the second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A that faces the second internal electrode layer 32 arranged adjacently in the stacking direction T, a second intermediate electrode layer opposing portion EC2B that faces the third intermediate electrode layer 333 arranged adjacently in the stacking direction T, and a second connecting portion E20.
  • the third intermediate electrode layer 333 has a third intermediate electrode layer facing portion EC3A facing the first intermediate electrode layer 331 arranged adjacently in the stacking direction T, a fourth intermediate electrode layer facing portion EC3B facing the second intermediate electrode layer 332 arranged adjacently in the stacking direction T, and a third connecting portion E30.
  • the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the longitudinal direction L.
  • the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the longitudinal direction L.
  • the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32, and the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are stacked alternately with the dielectric layer 20 interposed therebetween.
  • the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion).
  • the second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion).
  • the first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A face each other via the dielectric layer 20, thereby forming a capacitance CAP3 (third capacitor portion).
  • the second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B face each other via the dielectric layer 20, thereby forming a capacitance CAP4 (fourth capacitor portion).
  • the first connecting portion E10 connects the capacitances CAP1 and CAP3 in series.
  • the second connecting portion E20 connects the capacitances CAP2 and CAP4 in series.
  • the third coupling portion E30 connects the capacitances CAP3 and CAP4 in series.
  • the multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called four-series structure, in which four capacitor sections are connected in series.
  • the shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion EC1A, the first intermediate electrode layer side opposing portion EC1B, the second electrode layer side opposing portion EC2A, the second intermediate electrode layer side opposing portion EC2B, the third intermediate electrode layer side opposing portion EC3A, and the fourth intermediate electrode layer opposing portion EC3B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.
  • the shapes of the first lead-out portion D1 and the second lead-out portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.
  • the laminate 10 has a series capacitor forming portion 11E.
  • the series capacitor forming portion 11E includes: a portion where the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion EC1A of the intermediate electrode layer 33 face each other (portion forming capacitance CAP1); a portion where the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion EC2A of the intermediate electrode layer 33 face each other (portion forming capacitance CAP2); a portion where the first intermediate electrode layer opposing portion EC1B of the intermediate electrode layer 33 and the third intermediate electrode layer opposing portion EC3A face each other (portion forming capacitance CAP3); a portion where the second intermediate electrode layer opposing portion EC2B of the intermediate electrode layer 33 and the fourth intermediate electrode layer opposing portion EC3B face each other (portion forming capacitance CAP4); a portion connecting the capacitances CAP1 and CAP3 in series; a portion connecting the capacitances
  • the series capacitor forming portion 11E is configured as part of the inner layer portion 11.
  • the portion forming capacitance CAP1 first capacitor portion
  • the portion forming capacitance CAP2 second capacitor portion
  • the portion forming capacitance CAP3 third capacitor portion
  • the portion forming capacitance CAP4 fourth capacitor portion
  • the series capacitor forming portion 11E of the laminate 10 has a first series connection region, a second series connection region, and a third series connection region.
  • the first series connection region is a portion including the dielectric layer 20 and the first coupling portion E10, located between the portion forming the capacitance CAP1 and the portion forming the capacitance CAP3.
  • the second series connection region is a portion including the dielectric layer 20 and the second coupling portion E20, located between the portion forming the capacitance CAP2 and the portion forming the capacitance CAP4.
  • the third series connection region is a portion including the dielectric layer 20 and the third coupling portion E30, located between the portion forming the capacitance CAP3 and the portion forming the capacitance CAP4.
  • the first series connection region is an assembly of a plurality of first connecting portions E10 and portions of the plurality of dielectric layers 20 that overlap with the first connecting portion E10 when viewed from the stacking direction T.
  • the second series connection region is an assembly of a plurality of second connecting portions E20 and portions of the plurality of dielectric layers 20 that overlap with the second connecting portion E20 when viewed from the stacking direction T.
  • the third series connection region is an assembly of a plurality of third connecting portions E30 and portions of the plurality of dielectric layers 20 that overlap with the third connecting portion E30 when viewed from the stacking direction T.
  • the external electrode 40 has a first external electrode 40A arranged on the first end surface LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end surface LS2 side of the laminate 10.
  • the first connecting portion E10 connects capacitances CAP1 and CAP3 in series.
  • the second connecting portion E20 connects capacitances CAP2 and CAP4 in series.
  • the third connecting portion E30 connects capacitances CAP3 and CAP4 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.
  • the multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the form of the internal electrode layers 30 inside the laminate 10.
  • the multilayer ceramic capacitor 1 of the first embodiment has a two-layer structure for the internal electrode layers 30
  • the multilayer ceramic capacitor 1 of the fourth embodiment has a four-layer structure for the internal electrode layers 30 inside the laminate 10, and the form of the internal electrode layers 30 inside the laminate 10 differs from the first embodiment.
  • the multilayer ceramic capacitor 1 according to the first embodiment and the multilayer ceramic capacitor 1 according to the fourth embodiment have similar structures due to increased coverage, as described below. Therefore, in describing the multilayer ceramic capacitor 1 according to this embodiment, for the sake of convenience, the same structure as that of the first embodiment, which is formed by increasing the thickness of the internal electrode layers using the manufacturing method described above in order to increase coverage, may be omitted.
  • the coverage of the first intermediate electrode layer facing portion EC1B, the coverage of the second intermediate electrode layer facing portion EC2B, the coverage of the third intermediate electrode layer facing portion EC3A, and the coverage of the fourth intermediate electrode layer facing portion EC3B are higher than the coverage of the first facing portion EA on the first end face LS1 side and the coverage of the second facing portion EB on the second end face LS2 side.
  • the coverage of the first intermediate electrode layer facing portion EC1B, the coverage of the second intermediate electrode layer facing portion EC2B, the coverage of the third intermediate electrode layer facing portion EC3A, and the coverage of the fourth intermediate electrode layer facing portion EC3B are higher than the coverage of the first end face LS1 side of the first electrode layer side facing portion EC1A and the coverage of the second end face LS2 side of the second electrode layer side facing portion EC2A.
  • the coverage of the third intermediate electrode layer 333 is higher than the coverage of the first internal electrode layer 31 on the first end face LS1 side and the coverage of the second internal electrode layer 32 on the second end face LS2 side.
  • the method for measuring various parameters in the fourth embodiment is basically the same as that in the above-described embodiments.
  • the measurement points in the measurement method according to the fourth embodiment are set in a region where the coverage is high and the thickness is large, and in a region where the coverage is low and the thickness is small.
  • a method for manufacturing the multilayer ceramic capacitor 1 of the fourth embodiment will be described. As mentioned above, the description of the same configuration as in the first embodiment may be omitted.
  • the multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.
  • portion P12 screen-printed dielectric sheets such as those shown in FIG. 7 are sequentially laminated on the surface of portion P12, which will become the first main surface side outer layer portion 12, to form portion P11, which will become the inner layer portion 11.
  • dielectric sheet G1 on which conductive pastes P31, P32, and P333, which will become the first internal electrode layer 31, second internal electrode layer 32, and third intermediate electrode layer 333, are arranged, and dielectric sheet G2, on which conductive pastes P331 and P332, which will become the first intermediate electrode layer 331 and second intermediate electrode layer 332, are arranged, are sequentially laminated alternately. Note that portion C in FIG. 14 is cut out in a subsequent process to form a single laminated chip.
  • conductive paste P2 is applied to the portions that will become the first internal electrode layer 31, second internal electrode layer 32, and intermediate electrode layer 33, and as shown in FIG. 13, portions of the first internal electrode layer 31, second internal electrode layer 32, and intermediate electrode layer 33 become thicker, creating high coverage portions.
  • high coverage regions are also arranged in the first internal electrode layer 31 and the second internal electrode layer 32 as shown in Fig. 13, but the present invention is not limited to this configuration.
  • high coverage regions may be arranged only in the intermediate electrode layer 33 as shown in Fig. 15, and high coverage regions may not be arranged in the first internal electrode layer 31 and the second internal electrode layer 32.
  • FIG. 15 is a schematic diagram illustrating the range of the high coverage portion of a four-layer structure laminate according to the fifth embodiment.
  • Figure 16 is a schematic diagram showing a portion of a laminate sheet in which portions that will become the first main surface side outer layer portion and the second main surface side outer layer portion are formed above and below a portion that will become the inner layer portion in the fifth embodiment.
  • the multilayer ceramic capacitor 1 of this embodiment differs from the fourth embodiment in the configuration of the internal electrode layers inside the laminate 10. Specifically, in the four-element multilayer ceramic capacitor 1 of the fourth embodiment, high coverage portions were set in parts of the first internal electrode layer 31, parts of the second internal electrode layer 32, parts of the first intermediate electrode layer 331, parts of the second intermediate electrode layer 332, and the third intermediate electrode layer 333. However, in the four-element multilayer ceramic capacitor 1 of the fifth embodiment, as shown in FIG. 15, high coverage portions are not set in the first internal electrode layer 31 and the second internal electrode layer 32, but are set in parts of the first intermediate electrode layer 331, parts of the second intermediate electrode layer 332, and the third intermediate electrode layer 333.
  • the method for measuring various parameters in the fifth embodiment is basically the same as that in the above-described embodiments.
  • the measurement points in the measurement method according to the fifth embodiment are set in a region where the coverage is high and the thickness is large, and in a region where the coverage is low and the thickness is small.
  • a method for manufacturing the multilayer ceramic capacitor 1 of the fifth embodiment will be described. As mentioned above, the description of the same configuration as in the first embodiment may be omitted.
  • the multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.
  • portion P12 screen-printed dielectric sheets such as those shown in FIG. 7 are sequentially laminated on the surface of portion P12, which will become the first main surface side outer layer portion 12, to form portion P11, which will become the inner layer portion 11.
  • dielectric sheet G1 on which conductive pastes P31, P32, and P333, which will become the first internal electrode layer 31, second internal electrode layer 32, and third intermediate electrode layer 333, are arranged, and dielectric sheet G2, on which conductive pastes P331 and P332, which will become the first intermediate electrode layer 331 and second intermediate electrode layer 332, are arranged, are sequentially laminated alternately. Note that portion C in FIG. 16 is cut out in a subsequent process to form a single laminated chip.
  • the conductive paste P2 is applied only to the portion that will become the intermediate electrode layer 33, and as shown in Figure 15, only a portion of the intermediate electrode layer 33 becomes thicker, creating a high coverage portion.
  • the multilayer ceramic capacitor 1 has the following advantages.
  • a space exists between the surface of the laminate and an imaginary plane connecting the surfaces of the first external electrode and the second external electrode. This space is always present as long as the external electrodes have a side thickness, but it does not contribute to capacitance density.
  • One possible method for improving capacitance is to increase the coverage of the internal electrode layers, thereby increasing the net effective surface area.
  • improving coverage requires increasing the thickness of the internal electrode layers. Therefore, in order to design a laminate with the same dimensions in the stacking direction T, it was necessary to reduce the number of internal electrode layers by the amount of thickness increase. As a result, the effect of improving capacitance by increasing the thickness of the internal electrode layers is negated by the reduction in the number of internal electrode layers.
  • This disclosure makes it possible to provide a multilayer ceramic capacitor that can increase capacitance without increasing the size of the multilayer ceramic capacitor 1, even in a series-structure multilayer ceramic capacitor with high voltage resistance specifications, by effectively utilizing the space between the virtual plane connecting the surfaces of the first external electrode and the second external electrode and the surface of the laminate.
  • the multilayer ceramic capacitor 1 of this embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, and including a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first side surface WS1 and a second side surface WS2 facing in the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in the length direction L perpendicular to the stacking direction T and the width direction W;
  • the multilayer ceramic capacitor 1 has a first external electrode 40A arranged on a first end face LS1 and a second external electrode 40B arranged on a second end face LS2, and the plurality of internal electrode layers 30 include a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33, and the first internal electrode layer 31 has a first lead portion D1, one end of which is led out to the first end face LS1 and connected to the first external electrode
  • the coverage of at least a portion of the intermediate electrode layer 33 is higher than the coverage of the area on the first end face LS1 side of the first opposing portion EA of the first internal electrode layer 31, and higher than the coverage of the area on the second end face LS2 side of the second opposing portion EB of the second internal electrode layer 32.
  • the intermediate electrode layer 33 has a first electrode layer side opposing portion ECA that faces the first internal electrode layer 31 arranged adjacently in the stacking direction T, and a second electrode layer side opposing portion ECB that faces the second internal electrode layer 32 arranged adjacently in the stacking direction T, and the first opposing portion EA of the first internal electrode layer 31 faces the intermediate electrode layer 33 as an internal electrode layer arranged adjacently in the stacking direction T, and the second opposing portion EB of the second internal electrode layer 32 faces the intermediate electrode layer as an internal electrode layer arranged adjacently in the stacking direction T.
  • the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1.
  • the coverage of the area on the second end face LS2 side of the first electrode layer side opposing portion ECA is higher than the coverage of the area on the first end face LS1 side of the first opposing portion EA
  • the coverage of the area on the first end face LS1 side of the second electrode layer side opposing portion ECB is higher than the coverage of the area on the second end face LS2 side of the second opposing portion EB.
  • the coverage of the area on the second end face LS2 side of the first electrode layer side opposing portion ECA is higher than the coverage of the area on the first end face LS1 side of the first electrode layer side opposing portion ECA
  • the coverage of the area on the first end face LS1 side of the second electrode layer side opposing portion ECB is higher than the coverage of the area on the second end face side of the second electrode layer side opposing portion ECB.
  • the coverage of the area on the second end face LS2 side of the first opposing portion EA is higher than the coverage of the area on the first end face LS1 side of the first opposing portion EA
  • the coverage of the area on the first end face LS1 side of the second opposing portion EB is higher than the coverage of the area on the second end face LS2 side of the second opposing portion EB.
  • the coverage of the area on the second end face LS2 side of the first opposing portion EA is higher than the coverage of the area on the first end face LS1 side of the first electrode layer side opposing portion ECA
  • the coverage of the area on the first end face LS1 side of the second opposing portion EB is higher than the coverage of the area on the second end face LS2 side of the first electrode layer side opposing portion ECA.
  • the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332.
  • the first intermediate electrode layer 331 has a first electrode layer-side facing portion EC1A facing the first internal electrode layer 31 arranged adjacently in the stacking direction T, and a first intermediate electrode layer-side facing portion EC1B facing the second intermediate electrode layer 332 arranged adjacently in the stacking direction T.
  • the second intermediate electrode layer 332 has a second electrode layer-side facing portion EC2A facing the second internal electrode layer 32 arranged adjacently in the stacking direction T, and a second intermediate electrode layer-side facing portion EC2B facing the first intermediate electrode layer 331 arranged adjacently in the stacking direction T.
  • the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1.
  • the coverage of the first intermediate electrode layer opposing portion EC1B and the coverage of the second intermediate electrode layer opposing portion EC2B are higher than the coverage of the area on the first end face LS1 side of the first opposing portion EA and the coverage of the area on the second end face LS2 side of the second opposing portion EB.
  • the coverage of the first intermediate electrode layer facing portion EC1B and the coverage of the second intermediate electrode layer facing portion EC2B are higher than the coverage of the area on the first end face LS1 side of the first electrode layer side facing portion EC1A and the coverage of the area on the second end face LS2 side of the second electrode layer side facing portion EC2A.
  • the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333.
  • the first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A that faces the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and a first intermediate electrode layer side opposing portion EC1B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T.
  • the second intermediate electrode layer 332 has a first electrode layer side opposing portion EC1A that faces the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and a first intermediate electrode layer side opposing portion EC1B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T.
  • It has a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacently in the stacking direction T, and a second intermediate electrode layer opposing portion EC2B opposing the third intermediate electrode layer 333 arranged adjacently in the stacking direction T, and the third intermediate electrode layer 333 has a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 arranged adjacently in the stacking direction T, and a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 arranged adjacently in the stacking direction T.
  • the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1.
  • the coverage of the first intermediate electrode layer opposing portion EC1B, the coverage of the second intermediate electrode layer opposing portion EC2B, the coverage of the third intermediate electrode layer opposing portion EC3A, and the coverage of the fourth intermediate electrode layer opposing portion EC3B are higher than the coverage of the first opposing portion EA and the coverage of the second opposing portion EB.
  • the coverage of the first intermediate electrode layer facing portion EC1B, the coverage of the second intermediate electrode layer facing portion EC2B, the coverage of the third intermediate electrode layer facing portion EC3A, and the coverage of the fourth intermediate electrode layer facing portion EC3B are higher than the coverage of the first electrode layer side facing portion EC1A and the coverage of the second electrode layer side facing portion EC2A.
  • the coverage of the third intermediate electrode layer 333 is higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32.
  • the portion of the first opposing portion EA on the second end face LS2 side is defined as the second region EA2
  • the portion of the second opposing portion EB on the first end face LS1 side is defined as the fourth region EB2
  • the end of the second region EA2 on the first end face LS1 side is located closer to the second end face LS2 than the end of the first external electrode 40A on the second end face LS2 side
  • the end of the fourth region EB2 on the second end face LS2 side is located closer to the first end face LS1 than the end of the second external electrode 40B on the first end face LS1 side.
  • the laminate 10 has exposed portions Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 covered by the first external electrode 40A, and a second covered portion C2 covered by the second external electrode 40B, and the maximum distance T0 in the stacking direction T of the exposed portions Ep is longer than the maximum distance T1 in the stacking direction T connecting the surfaces of the first and second main surfaces TS1 and TS2 of the first and second covered portions C1 and C2, and is shorter than the maximum distance T2 in the stacking direction T connecting the surfaces of the first and second main surfaces TS1 and TS2 of the first and second external electrodes 40A and 40B.
  • the first principal surface TS1 has a first covered surface C1sA covered by the first external electrode 40A, a second covered surface C2sA covered by the second external electrode, and a first raised surface EpsA exposed from the first external electrode 40A and the second external electrode 40B and raised toward the center in the longitudinal direction L.
  • the first raised surface EpsA has a first recess DE1 extending in the width direction.
  • the multilayer ceramic capacitor 1 of this embodiment includes a laminate 10 that includes a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, and includes a first main surface TS1 and a second main surface TS2 that face the stacking direction T, a first side surface WS1 and a second side surface WS2 that face the width direction W that is perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face the length direction L that is perpendicular to the stacking direction T and the width direction W, a first external electrode 40A arranged on the first end surface LS1, and a second external electrode 40B arranged on the second end surface LS2, and the plurality of internal electrode layers 30 are
  • the first internal electrode layer 31 has a first lead portion D1, one end of which is drawn to the first end surface LS1 and connected to the first external electrode 40A, and a first opposing portion EA, which is connected to the first lead portion D1 and faces the intermediate electrode
  • the second internal electrode layer 32 has a second lead portion D2, one end of which is drawn to the second end surface LS2 and connected to the second external electrode 40B, and a second opposing portion EB, which is connected to the second lead portion D2 and faces the intermediate electrode layer 33 arranged adjacent to the first internal electrode layer 31 in the stacking direction T.
  • the capacitor includes a first electrode layer side opposing portion ECA that is not connected to either the external electrode 40A or the second external electrode 40B and that faces the first internal electrode layer 31 that is arranged adjacent to the external electrode 40A in the stacking direction T, and a second electrode layer side opposing portion ECB that faces the second internal electrode layer 32 that is arranged adjacent to the external electrode 40A in the stacking direction T, the first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32 forming a series-connected capacitor element, the first opposing portion EA having a first region EA1 that is an area on the first end face LS1 side, and a second region EA2 that is an area on the second end face LS2 side and has a higher coverage than the coverage of the first region EA1, and the second opposing portion EB has a second
  • the first electrode layer side facing portion ECA has a fifth region ECA1 on the first end face LS1 side and a sixth region ECA2 on the second end face LS2 side which has a
  • the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1.
  • the present invention is not limited to the configuration of the above embodiment, and can be modified and applied as appropriate within the scope of the present invention without changing the gist of the invention. Furthermore, a combination of two or more of the individual desirable configurations described in the above embodiment also constitutes the present invention.

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  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
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PCT/JP2024/009640 2024-03-12 2024-03-12 積層セラミックコンデンサ Pending WO2025191704A1 (ja)

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PCT/JP2024/009640 WO2025191704A1 (ja) 2024-03-12 2024-03-12 積層セラミックコンデンサ
EP24929676.5A EP4685832A1 (en) 2024-03-12 2024-03-12 Multilayer ceramic capacitor
CN202480029716.6A CN121039766A (zh) 2024-03-12 2024-03-12 层叠陶瓷电容器
KR1020257037929A KR20250168680A (ko) 2024-03-12 2024-03-12 적층 세라믹 콘덴서
JP2025512144A JP7816637B2 (ja) 2024-03-12 2024-03-12 積層セラミックコンデンサ
US19/347,927 US20260031273A1 (en) 2024-03-12 2025-10-02 Multilayer ceramic capacitor

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JPWO2025191704A1 (https=) 2025-09-18
EP4685832A1 (en) 2026-01-28

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