Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

• This disclosure relates to a semiconductor device.
• Patent Document 1 There is a known pixel ADC type imaging device that performs analog-to-digital conversion (hereafter, AD conversion) at each pixel (see, for example, Patent Document 1).
• a time code transfer section is arranged in the column direction of the pixel array section, and a time code is transferred from the time code transfer section to each pixel, and the time code is held as an AD conversion value when the pixel signal matches the reference signal.
• this disclosure provides a semiconductor device capable of transferring data in two or more directions.
• a circuit configuration including: a plurality of first data transfer groups, each of which includes a plurality of first flip-flops that transfer data in a first direction and is arranged in a second direction intersecting the first direction; a plurality of second data transfer groups arranged in the first direction, each group including a plurality of second flip-flops for transferring data in the second direction; A switching controller that individually switches and controls connection destinations of output terminals of the first flip-flops and the second flip-flops in each of the first data transfer groups and the second data transfer groups.
• a propagation order of the clock signal input to the first flip-flops and a propagation order of the data input to the first flip-flops are opposite to each other;
• a propagation order of the clock signal input to the second flip-flops and a propagation order of the data input to the second flip-flops may be opposite to each other.
• Each of the plurality of arithmetic units may perform an arithmetic process based on an output signal of the corresponding first flip-flop or the corresponding second flip-flop.
• the plurality of computing elements may perform at least one of the four arithmetic operations or analog-to-digital conversion.
• Each of the plurality of arithmetic units may input the calculation result to the first flip-flop or the second flip-flop in the next stage of the first data transfer group or the second data transfer group that is the same as the first flip-flop or the second flip-flop that output the output signal.
• Each of the plurality of arithmetic units may input the calculation result to the first flip-flop or the second flip-flop of either the first data transfer group or the second data transfer group that is different from the first flip-flop or the second flip-flop that output the output signal.
• the switching controller may individually control switching between transferring the calculation results of the multiple arithmetic units in the first direction by the multiple first data transfer groups, and transferring the calculation results of the multiple arithmetic units in the second direction by the multiple second data transfer groups.
• the device may also include a plurality of switches that switch the output signal paths of the plurality of first flip-flops and the plurality of second flip-flops in each of the plurality of first data transfer groups and the plurality of second data transfer groups in accordance with switching control by the switching controller.
• the multiple switches may be connected between the input nodes of the multiple first flip-flops and the output nodes of the multiple arithmetic units, and may also be connected between the input nodes of the multiple second flip-flops and the output nodes of the multiple arithmetic units.
• the switching controller may input operation results of the plurality of arithmetic units to the plurality of first flip-flops or the plurality of second flip-flops via the plurality of first output buffers or the plurality of second output buffers.
• the first data transfer groups, the second data transfer groups, and the computing units may be arranged in one semiconductor layer, or may be divided and arranged in multiple semiconductor layers.
• the plurality of first data transfer groups and the plurality of second data transfer groups may transfer data including at least one of the opcodes, operands, the time code of the operation, the identification information of the next input operation, or the operation end information of the plurality of operation units.
• the plurality of first data transfer groups transfer data in parallel to one end in the first direction;
• the plurality of second data transfer groups may transfer data in parallel up to one end in the second direction.
• the data transferred to a first end in the first direction by a portion of the first data transfer groups among the plurality of first data transfer groups is transferred in a direction opposite to the first direction by a portion of the first data transfer groups among the plurality of first data transfer groups other than the portion of the first data transfer groups to a second end;
• the plurality of second data transfer groups may transfer data in parallel up to one end in the second direction.
• the plurality of first data transfer groups transfer data in parallel to one end in the first direction;
• Data transferred to a first end in the second direction in a portion of the plurality of second data transfer groups may be transferred to a second end in a direction opposite to the second direction in a portion of the plurality of second data transfer groups other than the portion of the plurality of second data transfer groups.
• the data transferred to a first end in the first direction by a portion of the first data transfer groups among the plurality of first data transfer groups is transferred in a direction opposite to the first direction by a portion of the first data transfer groups among the plurality of first data transfer groups other than the portion of the first data transfer groups to a second end;
• Data transferred to a third end in the second direction in a portion of the plurality of second data transfer groups may be transferred to a fourth end in a direction opposite to the second direction in a portion of the plurality of second data transfer groups other than the portion of the plurality of second data transfer groups.
• the plurality of first data transfer groups may alternate between data transfer in the first direction and data transfer in the opposite direction to the first direction in the order of the second direction.
• the plurality of second data transfer groups may alternate between data transfer in the second direction and data transfer in the opposite direction to the first direction in the order of the first direction.
• Each of the first flip-flops and the second flip-flops may output a signal of the same logic as the input signal from an output node when the clock signal is a first logic, and may set the output node to high impedance when the clock signal is a second logic.
• Each of the first flip-flops and the second flip-flops may take in the input signal when the clock signal is at the second logic, and then output a signal of the same logic as the input signal taken in from the output node when the clock signal transitions to the first logic.
• FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device 1 according to an embodiment.
• 11 is a circuit diagram showing a connection configuration of a plurality of first flip-flops in a first data transfer group;
• FIG. 13 is a diagram showing the state of each transistor of a dynamic FF when a clock signal is low.
• FIG. 2 is a diagram showing the state of each transistor of a dynamic FF when a clock signal is high.
• FIG. 11 is a block diagram showing a schematic configuration of a semiconductor device according to a modified example of the embodiment.
• FIG. 2 is a diagram showing an example of a plurality of switches provided for each computing unit;
• FIG. 13 is a diagram showing an example in which a total of nine arithmetic units are arranged, three in the first direction and three in the second direction.
• FIG. 4 is a diagram showing a normal output order of calculation results.
• FIG. 13 is a diagram showing a transposed output order of operation results.
• FIG. 5 is a block diagram of a semiconductor device according to a modification of FIG. 4 .
• FIG. 2 is a diagram showing an arrangement of a plurality of arithmetic units. 13 is a diagram showing an example in which the operation results of a plurality of operation units are read out row by row in a plurality of first data transfer groups 2.
• FIG. FIG. 2 is a diagram showing storage areas of a frame memory; FIG.
• 13 is a diagram showing an example of reading out a calculation result from a frame memory.
• 5 is a block diagram showing a more detailed configuration of a plurality of first data transfer groups and a plurality of second data transfer groups shown in FIG. 4 .
• 11 is a diagram showing an example in which a plurality of first data transfer groups transfer data in a first direction, and a plurality of second data transfer groups transfer data in a second direction.
• 13 is a diagram showing an example in which the data transfer directions are reversed between odd-numbered rows and even-numbered rows among a plurality of first data transfer groups.
• 13 is a diagram showing an example in which the data transfer directions are reversed between odd-numbered columns and even-numbered columns in a plurality of second data transfer groups.
• FIG. 13A and 13B are diagrams showing an example in which the data transfer directions of odd-numbered rows and even-numbered rows among a plurality of first data transfer groups are reversed to each other, and the data transfer directions of odd-numbered columns and even-numbered columns among a plurality of second data transfer groups are reversed to each other;
• 1 is a schematic perspective view of a semiconductor device having a stacked structure according to an embodiment of the present invention
• FIG. 2 is a block diagram of a first semiconductor substrate.
• FIG. 4 is a block diagram of a second semiconductor substrate.
• FIG. 17 is a block diagram of a second semiconductor substrate according to a modification of FIG. 16 .
• FIG. 2 is a block diagram showing a first example of the internal configuration of a computing unit.
• FIG. 13 is a block diagram showing a second example of the internal configuration of the arithmetic unit when the semiconductor device is a pixel ADC type imaging device.
• FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system.
• FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.
• FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device 1 according to one embodiment.
• the semiconductor device 1 in FIG. 1 is a device disposed on one or more semiconductor substrates (not shown).
• the semiconductor device 1 in FIG. 1 includes a plurality of first data transfer groups 2, a plurality of second data transfer groups 3, and a controller (switching controller) 4.
• the multiple first data transfer groups 2 are arranged in a second direction (e.g., vertical direction) Y that intersects with a first direction (e.g., horizontal direction) X.
• Each of the multiple first data transfer groups 2 has multiple first flip-flops 5 that transfer data in the first direction X.
• the multiple first flip-flops 5 are connected in series. The number of first flip-flops 5 connected in series is arbitrary.
• a low data generator 6 is connected to the data input terminal D of the first flip-flop 5 in the first stage in each of the multiple first data transfer groups 2.
• the low data generator 6 generates data to be input to the data input terminal D of the first flip-flop 5 in the first stage in each first data transfer group 2.
• a low output circuit 7 is connected to the data output terminal Q of the first flip-flop 5 in the last stage in each first data transfer group 2.
• the low output circuit 7 is a circuit that outputs data output from the data output terminal Q of the first flip-flop 5 in the last stage in each first data transfer group 2 to the outside of the semiconductor device 1.
• a memory (a frame memory as a more specific example) may be connected to the low output circuit 7 to store the data output from the data output terminal Q of the first flip-flop 5 in the last stage inside the semiconductor device 1.
• the multiple second data transfer groups 3 are arranged in the first direction X. Each of the multiple second data transfer groups 3 has multiple second flip-flops 8 that transfer data in the second direction Y. The multiple second flip-flops 8 are connected in series. The number of second flip-flops 8 connected in series is arbitrary.
• a column data generator 9 is connected to the data input terminal D of the first flip-flop 5 in the first stage in each second data transfer group 3.
• a column output circuit 10 is connected to the data output terminal Q of the second flip-flop 8 in the last stage in each second data transfer group 3.
• the column output circuit 10 is a circuit that outputs data output from the data output terminal Q of the second flip-flop 8 in the last stage in each second data transfer group 3 to the outside of the semiconductor device 1.
• a memory may be connected to the column output circuit 10 to store the data output from the data output terminal Q of the second flip-flop 8 in the last stage inside the semiconductor device 1.
• the row data generator 6 and the column data generator 9 are controlled by the controller 4.
• the controller 4 also individually switches and controls the connection destinations of the output terminals of the multiple first flip-flops 5 and the multiple second flip-flops 8 in each of the multiple first data transfer groups 2 and the multiple second data transfer groups 3.
• the semiconductor device 1 can arbitrarily combine a plurality of first data transfer groups 2 and a plurality of second data transfer groups 3, and can switch the data transfer direction to the first direction X or the second direction Y as necessary. Therefore, data can be transferred in any direction, not just the first direction X or the second direction Y.
• FIG. 2 is a circuit diagram showing the connection of the multiple first flip-flops 5 in the first data transfer group 2.
• the connection of the multiple second flip-flops 8 in the second data transfer group 3 is also represented by a circuit diagram similar to that of FIG. 2, so below we will explain the connection of the multiple first flip-flops 5 and omit a detailed explanation of the connection of the multiple second flip-flops 8.
• each first flip-flop 5 is connected to the data input terminal D of the first flip-flop 5 of the next stage.
• the clock terminal of each first flip-flop 5 receives the clock signal CLK output from the corresponding clock buffer 11.
• the multiple clock buffers 11 corresponding to the multiple first flip-flops 5 are connected in series, and the first stage clock buffer 11 is provided corresponding to the last stage first flip-flop 5, and the last stage clock buffer 11 is provided corresponding to the first stage first flip-flop 5. That is, the clock signal CLK is input to the clock terminal of the last stage first flip-flop 5 at the earliest timing, and the clock signal CLK is input to the clock terminal of the first stage first flip-flop 5 at the latest timing.
• the propagation order of the clock signal CLK input to the multiple first flip-flops 5 and the propagation order of the data input to the multiple first flip-flops 5 are opposite to each other.
• the propagation order of the clock signal CLK input to the multiple second flip-flops 8 and the propagation order of the data input to the multiple second flip-flops 8 are opposite to each other.
• each first flip-flop 5 and each second flip-flop 8 can take in the input data with the clock signal CLK while ensuring sufficient setup and hold times for the input data. This prevents input data from being taken in incorrectly, and stabilizes the operation of the first flip-flops 5 and the second flip-flops 8.
• the first flip-flop 5 and the second flip-flop 8 in this embodiment may be dynamic flip-flops (hereinafter, dynamic FFs) having a TSPC (True Single Phase Clock).
• dynamic FFs dynamic flip-flops having a TSPC (True Single Phase Clock).
• FIGS. 3A and 3B are diagrams showing the circuit configuration of a dynamic FF and the state of each transistor.
• a dynamic FF having the circuit configuration of FIG. 3A and FIG. 3B can be applied to the first flip-flop 5 and the second flip-flop 8.
• Figure 3A shows the on/off state of each transistor when the clock signal CLK is low
• Figure 3B shows the on/off state of each transistor when the clock signal CLK is high.
• the dynamic FF in Figures 3A and 3B has a PMOS transistor Q1 and an NMOS transistor Q2 connected between a power supply voltage node and a ground node, PMOS transistors Q3, Q4 and an NMOS transistor Q5 cascode-connected between the power supply voltage node and the ground node, a PMOS transistor Q6 and an NMOS transistor Q7, Q8 cascode-connected between the power supply voltage node and the ground node, and a PMOS transistor Q9 and an NMOS transistor Q10, Q11 cascode-connected between the power supply voltage node and the ground node.
• the gates of transistors Q1 and Q2 are connected to data input terminal D.
• the drains of transistors Q1 and Q2 are connected to the gates of transistors Q3 and Q5.
• a clock signal CLK is input to the gate of transistor Q4.
• a clock signal CLK is input to the gates of transistors Q6 and Q8.
• a gate of transistor Q7 is connected to the drains of transistors Q4 and Q5.
• the gates of transistors Q9 and Q11 are connected to the drains of transistors Q6 and Q7.
• a clock signal CLK is input to the gate of transistor Q10.
• the drains of transistors Q9 and Q10 are connected to data output terminal Q.
• transistor Q4 When the clock signal CLK is at a low level, transistor Q4 is turned on.
• the inverted data of the input data input to data input terminal D is input to the gates of transistors Q3 and Q5, and because transistor Q4 is on, the drains of transistors Q4 and Q5 (the gate of transistor Q7) have the same logic as the input data.
• transistor Q6 When the clock signal CLK is at a low level, transistor Q6 is on and transistor Q8 is off, so the drains of transistors Q6 and Q7 are at a high level. As a result, transistor Q9 is off and transistor Q11 is on. Also, because the clock signal CLK is at a low level, transistor Q10 is off.
• the input data input to the data input terminal is taken into the dynamic FF, and the drains of transistors Q4 and Q5 have a logic level according to the input data.
• transistors Q9 and Q10 are both off, the data output terminals connected to the drains of transistors Q9 and Q10 become high impedance.
• transistor Q4 When the clock signal CLK goes high, as shown in Figure 3B, transistor Q4 is off, transistor Q6 is off, transistor Q8 is on, and transistor Q10 is on.
• the drains of transistors Q4 and Q5 have the same logic as the input data, and the drains of transistors Q6 and Q7 have the inverted logic of the input data, so the data output terminals connected to the drains of transistors Q9 and Q10 have the same logic as the input data.
• each of the first flip-flops 5 and the second flip-flops 8 outputs a signal of the same logic as the input signal from the output node when the clock signal is the first logic, and makes the output node high impedance when the clock signal is the second logic.
• Each of the first flip-flops 5 and the second flip-flops 8 takes in the input signal when the clock signal is the second logic, and then outputs a signal of the same logic as the input signal taken in from the output node when the clock signal transitions to the first logic.
• the semiconductor device 1 includes a plurality of arithmetic units 12, as shown in FIG. 1, for example.
• the plurality of arithmetic units 12 are provided corresponding to at least one of the plurality of first data transfer groups 2 or the plurality of second data transfer groups 3, and are arranged along the first direction X and the second direction Y.
• the plurality of arithmetic units 12 are arranged in a number that is one less than the number of first flip-flops 5 in each first data transfer group 2.
• each first data transfer group 2 has five first flip-flops 5, while four arithmetic units 12 are provided.
• the specific number and location of the calculators 12 are arbitrary and are not necessarily limited to the number and location shown in FIG. 1.
• the calculators 12 perform, for example, arithmetic operations or analog-to-digital conversion (AD conversion) processing.
• the calculators 12 may also perform calculations other than arithmetic operations or AD conversion.
• each arithmetic unit group 12g is associated with each first data transfer group 2.
• An input buffer 13 and an output buffer 14 are arranged between each arithmetic unit 12 and the corresponding first data transfer group 2.
• the enable signal WEN is at a high level
• the input buffer 13 inputs the output data of the corresponding first flip-flop 5 to the arithmetic unit 12.
• the enable signal REN is at a high level
• the output buffer 14 inputs the calculation result of the arithmetic unit 12 to the first flip-flop 5 of the next stage or the corresponding second flip-flop 8.
• each calculator 12 performs a predetermined calculation process based on the output data of the corresponding first flip-flop 5.
• the calculation result of each calculator 12 is transferred to the first data transfer group 2 including the first flip-flop 5, or the second data transfer group 3 including the second flip-flop 8.
• the first data transfer group 2 has a plurality of first flip-flops 5 and a plurality of clock buffers (first clock buffers) 11, and the second data transfer group 3 has a plurality of second flip-flops 8 and a plurality of clock buffers (second clock buffers) 11.
• first clock buffers first clock buffers
• second clock buffers second clock buffers
• first flip-flops 5 and the second flip-flops 8 may be provided with enable terminals, and the signal input to the enable terminals may be used to switch whether data is transferred in the first direction X or the second direction Y.
• the first arithmetic unit group 12g corresponds to the first data transfer group 2, and an input buffer 13 and an output buffer 14 are connected between each arithmetic unit 12 and the corresponding first flip-flop 5.
• the first arithmetic unit group 12g may correspond to the second data transfer group 3, and an input buffer 13 and an output buffer 14 may be connected between each arithmetic unit 12 and the corresponding second flip-flop 8.
• each of the multiple arithmetic units 12 inputs the calculation result to the first flip-flop 5 or second flip-flop 8 in the next stage of the first data transfer group 2 or second data transfer group 3 that is the same as the first flip-flop 5 or second flip-flop 8 that output the output signal.
• each of the multiple arithmetic units 12 inputs the calculation result to the first flip-flop 5 or second flip-flop 8 in either the first data transfer group 2 or the second data transfer group 3 that is different from the first flip-flop 5 or second flip-flop 8 that output the output signal.
• the controller 4 individually switches and controls whether the calculation results of the multiple calculators 12 are transferred in the first direction X by the multiple first data transfer groups 2, or whether the calculation results of the multiple calculators 12 are transferred in the second direction Y by the multiple second data transfer groups 3.
• FIG. 4 is a block diagram showing a schematic configuration of a semiconductor device 1 according to a modified example of this embodiment.
• the semiconductor device 1 according to the modified example corresponds a computing unit group 12g having a plurality of computing units 12 arranged in a first direction X to two first data transfer groups 2 adjacent to each other in a second direction Y, and an input buffer 13 and an output buffer 14 are connected between each computing unit 12 and the corresponding first flip-flop 5 of each first data transfer group 2.
• an input buffer 13 and an output buffer 14 are disposed between each arithmetic unit 12 and the two first data transfer groups 2, respectively.
• the enable signals input to the enable terminals of these input buffers 13 and output buffers 14 can be controlled individually, so that the output data of the first flip-flop 5 of one of the two first data transfer groups 2 is taken into the arithmetic unit 12 for arithmetic processing, and the result of this arithmetic processing is output from one of the two output buffers 14 and transferred to the first data transfer group 2 or the second data transfer group 3.
• the semiconductor device 1 can output the results of calculations by the multiple arithmetic units 12 in the order in which the multiple arithmetic units 12 are arranged, using multiple first data transfer groups 2, or in the order in which the arrangement of the multiple arithmetic units 12 is transposed, using multiple first data transfer groups 2 and multiple second data transfer groups 3. In this way, switching the order in which the results of calculations by the multiple arithmetic units 12 are output can be easily achieved by providing multiple switches for each arithmetic unit 12.
• FIG. 5 is a diagram showing an example of the functions of multiple switches SW1, SW2 provided for each arithmetic unit 12.
• the semiconductor device 1 includes, for each arithmetic unit 12, a first switch SW1 arranged between the corresponding arithmetic unit 12 and the first data transfer group 2, and a second switch SW2 arranged between the corresponding arithmetic unit 12 and the second data transfer group 3.
• the first switch SW1 and the second switch SW2 are exclusively switched on and off, with one closed and the other open. For example, when the first switch SW1 is closed, the calculation result of the calculator 12 is transferred in the first direction X via the first data transfer group 2. When the second switch SW2 is closed, the calculation result of the calculator 12 is transferred in the second direction Y via the second data transfer group 3.
• the first switch SW1 and the second switch SW2 in FIG. 5 can be configured using the input buffer 13 and the output buffer 14 in FIG. 1, etc.
• the multiple output buffers 14 include multiple first output buffers that output the calculation results of the multiple arithmetic units 12 in a first direction X or a second direction Y, and multiple second output buffers that output the calculation results of the multiple arithmetic units 12 in the opposite direction to the first direction X or the second direction Y.
• the controller 4 inputs the calculation results of the multiple arithmetic units 12 to the multiple first output buffers or multiple second output buffers via the multiple first output buffers or multiple second output buffers.
• FIG. 6A is a diagram showing an example in which a total of nine arithmetic units 12 are arranged, three in the first direction X (e.g., row direction) and three in the second direction Y (e.g., column direction).
• the calculation results of the nine arithmetic units 12 are normally transferred and output in sequence in the first direction X, as shown in FIG. 6B.
• the first switch SW1 in FIG. 5 is closed and the second switch SW2 is opened.
• FIG. 6A is a diagram showing an example in which a total of nine arithmetic units 12 are arranged, three in the first direction X (e.g., row direction) and three in the second direction Y (e.g., column direction).
• the calculation results of the nine arithmetic units 12 are normally transferred and output in sequence in the first direction X, as shown in FIG. 6B.
• the first switch SW1 in FIG. 5 is closed and the second switch SW2 is opened.
• the calculation results a11, a12, and a13 of the first row are output in sequence, then the calculation results a21, a22, and a23 of the second row are output in sequence, and finally the calculation results a31, a32, and a33 of the third row are output in sequence.
• the first switch SW1 in Fig. 5 is opened and the second switch SW2 is closed.
• the calculation results a11, a21, and a31 in the first column are output in order
• the calculation results a12, a22, and a32 in the second column are output in order
• the calculation results a13, a23, and a33 in the third column are output in order.
• FIG. 5 an example is described in which a first switch SW1 and a second switch SW2 are provided for each calculator 12 to switch the transfer order, but instead of providing a first switch SW1 and a second switch SW2 for each calculator 12, the calculation results of the multiple calculators 12 transferred for each first data transfer group 2 may be stored in a frame memory, and after the calculation results of the multiple calculators 12 transferred in the multiple first data transfer groups 2 are stored in the frame memory, the order in which the calculation results are read out from the frame memory may be switched to select whether the calculation results are output row by row or column by column.
• FIG. 7 is a block diagram of a semiconductor device 1 according to a modified example of FIG. 4.
• the semiconductor device 1 in FIG. 7 includes a frame memory 15 connected to the row output circuit 7, and an output order switching circuit 16.
• the frame memory 15 sequentially stores the calculation results for each row transferred in each of the multiple first data transfer groups 2.
• the output order switching circuit 16 selects either row-by-row or column-by-column the results of the calculations of the multiple calculators 12 stored in the frame memory 15 and sequentially reads them out.
• the frame memory 15 and the output order switching circuit 16 may be connected to the column output circuit 10.
• FIG. 8A is a diagram showing the arrangement of multiple arithmetic units 12. Similar to FIG. 6A, FIG. 8A shows an example in which a total of nine arithmetic units 12 are arranged, three in the first direction X (e.g., row direction) and three in the second direction Y (e.g., column direction). These nine arithmetic units 12 output calculation results a11, a12, a13, a21, a22, a23, a31, a32, and a33.
• first direction X e.g., row direction
• Y e.g., column direction
• FIG. 8B is a diagram showing an example in which the calculation results of multiple calculators 12 are read out row by row in multiple first data transfer groups 2.
• the calculation results a11, a12, and a13 of the calculators 12 in the (1)th row of FIG. 8A are read out, then the calculation results a21, a22, and a23 in the (2)th row are read out, and finally the calculation results a31, a32, and a33 in the (3)th row are read out.
• FIG. 8C is a diagram showing the storage area of the frame memory 15.
• the frame memory 15 stores the calculation results of each calculator 12, which are read out row by row, in order column by column. More specifically, the frame memory 15 stores the calculation results a11, a21, and a31 of the (4)th column ((4)-1, (4)-2, and (4)-3 in FIG. 8C), then stores the calculation results a12, a22, and a32 of the (5)th column ((5)-1, (5)-2, and (5)-3 in FIG. 8C), and finally stores the calculation results a13, a23, and a33 of the (6)th column ((6)-1, (6)-2, and (6)-3 in FIG. 8C).
• FIG. 8D is a diagram showing an example of reading out the calculation results from the frame memory 15. By reading out the calculation results in an order different from the order in which they were stored in the frame memory 15, it is possible to read out the calculation results with rows and columns swapped.
• the rows and columns are swapped and stored, so that when the frame memory 15 is read in address order, the rows and columns can be swapped and read.
• FIG. 9 is a block diagram showing a more detailed configuration of the multiple first data transfer groups 2 and the multiple second data transfer groups 3 shown in FIG. 4.
• each of the first data transfer groups 2 has a plurality of first flip-flops 5 connected in series in a first direction X (e.g., row direction) and a plurality of first clock buffers 11a connected in the opposite direction to the transfer order of the first flip-flops 5.
• first direction X e.g., row direction
• first clock buffers 11a connected in the opposite direction to the transfer order of the first flip-flops 5.
• Each of the multiple second data transfer groups 3 has multiple second flip-flops 8 connected in series in the second direction Y (e.g., the column direction) and multiple second clock buffers 11b connected in the opposite direction to the transfer order of the multiple second flip-flops 8.
• the data output terminals of the first flip-flops 5 except for the final stage are connected to a calculator 12 via an input buffer 13 and an output buffer 14.
• Two sets of input buffers 13 and output buffers 14, one above the other in the column direction, are connected to each calculator 12.
• the upper input buffer 13 inputs the output signal of the corresponding first flip-flop 5 of the upper first data transfer group 2 to the calculator 12 when the enable signal REN_U is, for example, at a high level.
• the upper output buffer 14 outputs the calculation result of the calculator 12 to the upper first data transfer group 2 when the enable signal WEN_U is, for example, at a high level.
• the lower input buffer 13 inputs the output signal of the corresponding first flip-flop 5 of the lower first data transfer group 2 to the calculator 12 when the enable signal REN_D is, for example, at a high level.
• the lower output buffer 14 outputs the calculation result of the calculator 12 to the lower first data transfer group 2 when the enable signal WEN_D is, for example, at a high level.
• the calculation result of each calculator 12 is input to the data input terminal of the corresponding first flip-flop 5 in the first data transfer group 2 and the data input terminal of the corresponding second flip-flop 8 in the second data transfer group 3 via the output buffer 14.
• the clock signal CLK is propagated by the first clock buffers 11a that supply the clock signal CLK to the first flip-flops 5
• the calculation result of each calculator 12 is transferred in the first direction X via the first data transfer group 2.
• the clock signal CLK is propagated by the second clock buffers 11b that supply the clock signal CLK to the second flip-flops 8
• the calculation result of each calculator 12 is transferred in the second direction Y via the second data transfer group 3.
• the transfer direction of the calculation results of the multiple arithmetic units 12 can be switched depending on whether the clock signal CLK is propagated through the multiple first clock buffers 11a or the multiple second clock buffers 11b.
• the multiple first data transfer groups 2 do not necessarily need to transfer data in the same direction, and some of the first data transfer groups 2 may transfer data in the opposite direction to the other first data transfer groups 2.
• the multiple second data transfer groups 3 do not necessarily need to transfer data in the same direction, and some of the second data transfer groups 3 may transfer data in the opposite direction to the other second data transfer groups 3.
• FIGS. 10 to 13 are diagrams showing typical variations in the data transfer direction of multiple first data transfer groups 2 and multiple second data transfer groups 3.
• the arrows in FIG. 10 to FIG. 13 indicate the data transfer direction.
• FIG. 10 shows an example in which multiple first data transfer groups 2 all transfer data in a first direction X, and multiple second data transfer groups 3 all transfer data in a second direction Y.
• multiple first data transfer groups 2 transfer data in parallel up to one end in the first direction X.
• Multiple second data transfer groups 3 transfer data in parallel up to one end in the second direction Y.
• FIG. 11 shows an example in which the data transfer directions of the odd-numbered and even-numbered rows of the multiple first data transfer groups 2 are reversed.
• the multiple second data transfer groups 3 all transfer data in the second direction YY.
• data transferred to a first end in the first direction X by some of the multiple first data transfer groups 2 is transferred to a second end in the opposite direction to the first direction X by the remaining first data transfer groups 2 of the multiple first data transfer groups 2.
• the multiple second data transfer groups 3 transfer data in parallel to one end in the second direction Y.
• FIG. 12 shows an example in which the data transfer directions of the odd-numbered columns and the even-numbered columns of the multiple second data transfer groups 3 are reversed. All of the multiple first data transfer groups 2 transfer data in the first direction X. In FIG. 12, the multiple first data transfer groups 2 transfer data in parallel to one end of the first direction X. Data transferred to the first end in the second direction Y by some of the multiple second data transfer groups 3 is transferred in the opposite direction of the second direction Y to the second end by the remaining second data transfer groups 3 of the multiple second data transfer groups 3.
• FIG. 13 shows an example in which the data transfer directions are reversed between odd-numbered rows and even-numbered rows among the multiple first data transfer groups 2, and the data transfer directions are reversed between odd-numbered columns and even-numbered columns among the multiple second data transfer groups 3.
• data transferred to a first end in the first direction X by some of the multiple first data transfer groups 2 is transferred to a second end in the opposite direction to the first direction X by other first data transfer groups 2 among the multiple first data transfer groups 2
• the data transferred to the third end in the second direction Y by some of the multiple second data transfer groups 3 is transferred in the opposite direction of the second direction Y to the fourth end by other second data transfer groups 3 than the part of the multiple second data transfer groups 3.
• the multiple first data transfer groups 2 alternate between data transfer in the first direction X and data transfer in the opposite direction to the first direction X in the order of the arrangement in the second direction Y.
• the multiple second data transfer groups 3 alternate between data transfer in the second direction Y and data transfer in the opposite direction to the first direction X in the order of the arrangement in the first direction X.
• the semiconductor device 1 according to the present embodiment can be disposed on one semiconductor substrate, or can have a stacked structure in which two or more semiconductor substrates are stacked.
• FIG. 14 is a schematic perspective view of a semiconductor device 1 having a stacked structure according to this embodiment.
• FIG. 14 shows an example in which the semiconductor device 1 is constructed by stacking two semiconductor substrates 21 and 22.
• a plurality of arithmetic units 12, a plurality of first data transfer groups 2, a row data generator 6, and a row output circuit 7 are arranged on the first semiconductor substrate 21.
• a plurality of arithmetic units 12, a plurality of second data transfer groups 3, a column data generator 9, and a column output circuit 10 are arranged on the second semiconductor substrate 22.
• Signal transmission between the first semiconductor substrate 21 and the second semiconductor substrate 22 is performed, for example, by CCC (Copper-Copper Connection), vias, or bumps. Either the first semiconductor substrate 21 or the second semiconductor substrate 22 may be placed on top.
• CCC Copper-Copper Connection
• vias vias
• bumps Either the first semiconductor substrate 21 or the second semiconductor substrate 22 may be placed on top.
• FIG. 15 is a block diagram of the first semiconductor substrate 21, and FIG. 16 is a block diagram of the second semiconductor substrate 22.
• a first semiconductor substrate 21 has a plurality of first data transfer groups 2 arranged in the second direction Y and a plurality of arithmetic unit groups 12g arranged in the first direction X.
• Each of the first data transfer groups 2 has a plurality of first flip-flops 5 connected in series in the first direction X.
• a plurality of second data transfer groups 3 arranged in the first direction X and a plurality of arithmetic unit groups 12g arranged in the first direction X are arranged on the second semiconductor substrate 22.
• Each of the plurality of second data transfer groups 3 has a plurality of second flip-flops 8 connected in series in the second direction Y.
• the multiple computing units 12 on the first semiconductor substrate 21 and the multiple computing units 12 on the second semiconductor substrate 22 may be arranged so as not to overlap when viewed in a plan view, or may be arranged so as to overlap.
• FIG. 16 shows an example in which the calculation result of each calculator 12 is input to the data input terminal of the second flip-flop 8 in the next stage of the second data transfer group 3, which is the same as the second flip-flop 8 that inputs data to each calculator 12.
• the calculation result of each calculator 12 may be input to the data input terminal of any second flip-flop 8 in a second data transfer group 3 different from the second data transfer group 3, which is the same as the second flip-flop 8 that inputs data to each calculator 12.
• FIG. 17 is a block diagram of a second semiconductor substrate 22 according to a modified example of FIG. 16.
• the calculation result of the arithmetic unit 12 is input to the data input terminal of the corresponding second flip-flop 8 in a second data transfer group 3 different from the second data transfer group 3 including the second flip-flop 8 that input the data to the arithmetic unit 12.
• the calculation result of the calculator 12 may be input to the corresponding first flip-flop 5 or second flip-flop 8 of a first data transfer group 2 or second data transfer group 3 different from the first data transfer group 2 or second data transfer group 3 that input data to the calculator 12.
• Each arithmetic unit 12 can perform various arithmetic processing, and the content of the arithmetic processing to be performed may be switched depending on the time and situation.
• the multiple first data transfer groups 2 and the multiple second data transfer groups 3 transfer data including at least one of the opcodes of the multiple arithmetic units 12, the operands, the time code of the operation, the identification information of the arithmetic unit 12 to be input next, or the operation end information.
• FIG. 18 is a block diagram showing a first example of the internal configuration of the arithmetic unit 12.
• the arithmetic unit 12 shown in FIG. 18 has an internal configuration similar to that of a processor, and has an input/output control unit 23, a register group 24, multiple arithmetic units (ALUs: Arithmetic Logic Units) 25, and a program counter 26.
• the register group 24 includes a general-purpose register, an instruction register, an index register, etc.
• FIG. 19 is a block diagram showing a second example of the internal configuration of the calculator 12 when the semiconductor device 1 is an imaging device using a pixel ADC method.
• the calculator 12 has at least one pixel unit 27 having an ADC, at least one memory unit 28, and an input/output control unit 29.
• the semiconductor device 1 includes a plurality of first data transfer groups 2 each of which transfers data in a first direction X, and a plurality of second data transfer groups 3 each of which transfers data in a second direction Y, and individually switches and controls the connection destinations of the output terminals of the plurality of first flip-flops 5 and the plurality of second flip-flops 8.
• This makes it possible to switch the data transfer direction as necessary. For example, it is possible to easily transpose and output the results of calculations performed in the row direction using the plurality of arithmetic units 12 in the column direction.
• the technology disclosed herein can be applied to a variety of products.
• the technology disclosed herein may be realized as a device mounted on any type of moving object, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, construction machinery, agricultural machinery (tractor), etc.
• FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology disclosed herein can be applied.
• the vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010.
• the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside vehicle information detection unit 7400, an inside vehicle information detection unit 7500, and an integrated control unit 7600.
• the communication network 7010 connecting these multiple control units may be, for example, an in-vehicle communication network conforming to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay (registered trademark).
• CAN Controller Area Network
• LIN Local Interconnect Network
• LAN Local Area Network
• FlexRay registered trademark
• Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various devices to be controlled.
• Each control unit includes a network I/F for communicating with other control units via a communication network 7010, and a communication I/F for communicating with devices or sensors inside and outside the vehicle by wired or wireless communication.
• the functional configuration of the integrated control unit 7600 includes a microcomputer 7610, a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I/F 7660, an audio/image output unit 7670, an in-vehicle network I/F 7680, and a storage unit 7690.
• Other control units also include a microcomputer, a communication I/F, a storage unit, and the like.
• the drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs.
• the drive system control unit 7100 functions as a control device for a drive force generating device for generating a drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
• the drive system control unit 7100 may also function as a control device such as an ABS (Antilock Brake System) or ESC (Electronic Stability Control).
• the drive system control unit 7100 is connected to a vehicle state detection unit 7110.
• the vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the rotation speed of the wheels, etc.
• the drive system control unit 7100 performs arithmetic processing using the signal input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.
• the body system control unit 7200 controls the operation of various devices installed in the vehicle body according to various programs.
• the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
• radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 7200.
• the body system control unit 7200 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
• the battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, according to various programs. For example, information such as the battery temperature, battery output voltage, or remaining capacity of the battery is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs calculations using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.
• the outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000.
• the imaging unit 7410 and the outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400.
• the imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras.
• the outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc., around the vehicle equipped with the vehicle control system 7000.
• the environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the level of sunlight, and a snow sensor that detects snowfall.
• the surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device.
• the imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.
• FIG. 21 shows an example of the installation positions of the imaging unit 7410 and the outside vehicle information detection unit 7420.
• the imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 7900.
• the imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900.
• the imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900.
• the imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900.
• the imaging unit 7918, which is installed on the top of the windshield inside the vehicle is primarily used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
• FIG. 21 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916.
• Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose
• imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors
• imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door.
• image data captured by the imaging units 7910, 7912, 7914, and 7916 are superimposed to obtain an overhead image of the vehicle 7900.
• External information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and upper part of the windshield inside the vehicle 7900 may be, for example, ultrasonic sensors or radar devices.
• External information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and upper part of the windshield inside the vehicle 7900 may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are primarily used to detect preceding vehicles, pedestrians, obstacles, etc.
• the outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle, and receives the captured image data.
• the outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 transmits ultrasonic waves or electromagnetic waves, and receives information on the received reflected waves.
• the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface, based on the received information.
• the outside-vehicle information detection unit 7400 may perform environmental recognition processing for recognizing rainfall, fog, road surface conditions, etc., based on the received information.
• the outside-vehicle information detection unit 7400 may calculate the distance to an object outside the vehicle based on the received information.
• the outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, cars, obstacles, signs, or characters on the road surface based on the received image data.
• the outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by synthesizing image data captured by different imaging units 7410.
• the outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different imaging units 7410.
• the in-vehicle information detection unit 7500 detects information inside the vehicle.
• the in-vehicle information detection unit 7500 is connected to, for example, a driver state detection unit 7510 that detects the state of the driver.
• the driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound inside the vehicle.
• the biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or a driver gripping the steering wheel.
• the in-vehicle information detection unit 7500 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off.
• the in-vehicle information detection unit 7500 may perform processing such as noise canceling on the collected sound signal.
• the integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs.
• the input unit 7800 is connected to the integrated control unit 7600.
• the input unit 7800 is realized by a device that can be operated by the passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input by a microphone may be input to the integrated control unit 7600.
• the input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a PDA (Personal Digital Assistant) that supports the operation of the vehicle control system 7000.
• PDA Personal Digital Assistant
• the input unit 7800 may be, for example, a camera, in which case the passenger can input information by gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800 and outputs the signal to the integrated control unit 7600. The passenger or the like operates the input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.
• the memory unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc.
• the memory unit 7690 may also be realized by a magnetic memory device such as a HDD (Hard Disc Drive), a semiconductor memory device, an optical memory device, or a magneto-optical memory device, etc.
• the general-purpose communication I/F 7620 is a general-purpose communication I/F that mediates communication between various devices present in the external environment 7750.
• the general-purpose communication I/F 7620 may implement cellular communication protocols such as GSM (registered trademark) (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution) or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also called Wi-Fi (registered trademark)) and Bluetooth (registered trademark).
• GSM Global System of Mobile communications
• WiMAX registered trademark
• LTE registered trademark
• LTE-A Long Term Evolution
• Bluetooth registered trademark
• the general-purpose communication I/F 7620 may connect to devices (e.g., application servers or control servers) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point.
• the general-purpose communication I/F 7620 may connect to a terminal located near the vehicle (e.g., a driver's, pedestrian's, or store's terminal, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.
• P2P Peer To Peer
• the dedicated communication I/F 7630 is a communication I/F that supports a communication protocol developed for use in vehicles.
• the dedicated communication I/F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or a cellular communication protocol, which is a combination of the lower layer IEEE 802.11p and the higher layer IEEE 1609.
• the dedicated communication I/F 7630 typically performs V2X communication, which is a concept that includes one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.
• the positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle.
• GNSS Global Navigation Satellite System
• GPS Global Positioning System
• the positioning unit 7640 may determine the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.
• the beacon receiver 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations installed on the road, and acquires information such as the current location, congestion, road closures, and travel time.
• the functions of the beacon receiver 7650 may be included in the dedicated communication I/F 7630 described above.
• the in-vehicle device I/F 7660 is a communication interface that mediates the connection between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle.
• the in-vehicle device I/F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB).
• the in-vehicle device I/F 7660 may also establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-definition Link) via a connection terminal (and a cable, if necessary) not shown.
• USB Universal Serial Bus
• HDMI High-Definition Multimedia Interface
• MHL Mobile High-definition Link
• the in-vehicle device 7760 may include, for example, at least one of a mobile device or wearable device owned by a passenger, or an information device carried into or attached to the vehicle.
• the in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination.
• the in-vehicle device I/F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.
• the in-vehicle network I/F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010.
• the in-vehicle network I/F 7680 transmits and receives signals in accordance with a specific protocol supported by the communication network 7010.
• the microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired through at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I/F 7660, and the in-vehicle network I/F 7680.
• the microcomputer 7610 may calculate the control target value of the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output a control command to the drive system control unit 7100.
• the microcomputer 7610 may perform cooperative control for the purpose of realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.
• ADAS Advanced Driver Assistance System
• the microcomputer 7610 may control the driving force generating device, steering mechanism, braking device, etc. based on the acquired information about the surroundings of the vehicle, thereby performing cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
• the microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people based on information acquired via at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle equipment I/F 7660, and the in-vehicle network I/F 7680, and may create local map information including information about the surroundings of the vehicle's current position.
• the microcomputer 7610 may also predict dangers such as vehicle collisions, the approach of pedestrians, or entry into closed roads based on the acquired information, and generate warning signals.
• the warning signals may be, for example, signals for generating warning sounds or turning on warning lights.
• the audio/image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information.
• an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices.
• the display unit 7720 may include, for example, at least one of an on-board display and a head-up display.
• the display unit 7720 may have an AR (Augmented Reality) display function.
• the output device may be other devices such as headphones, wearable devices such as glasses-type displays worn by the occupants, projectors, or lamps other than these devices.
• the display device visually displays the results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, graphs, etc. Also, if the output device is an audio output device, the audio output device converts an audio signal consisting of reproduced voice data or acoustic data, etc., into an analog signal and outputs it audibly.
• At least two control units connected via the communication network 7010 may be integrated into one control unit.
• each control unit may be composed of multiple control units.
• the vehicle control system 7000 may include another control unit not shown.
• some or all of the functions performed by any control unit may be provided by another control unit.
• a predetermined calculation process may be performed by any control unit.
• a sensor or device connected to any control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.
• the semiconductor device 1 according to this embodiment described using FIG. 1 etc. can be applied to the integrated control unit 7600 of the application example shown in FIG. 20.
• the components of the semiconductor device 1 described using FIG. 1 etc. may be realized in a module (e.g., an integrated circuit module configured on a single die) for the integrated control unit 7600 shown in FIG. 20.
• the semiconductor device 1 described using FIG. 1 etc. may be realized by multiple control units of the vehicle control system 7000 shown in FIG. 20.
• This technology can be configured as follows:
• a plurality of arithmetic units are provided corresponding to at least one of the plurality of first data transfer groups or the plurality of second data transfer groups and are arranged along the first direction and the second direction; each of the plurality of arithmetic units performs an arithmetic process based on an output signal of the corresponding first flip-flop or the corresponding second flip-flop;
• the plurality of arithmetic units perform at least one of four arithmetic operations or analog-to-digital conversion.
• Each of the plurality of arithmetic units inputs an operation result to the first flip-flop or the second flip-flop in the next stage of the first data transfer group or the second data transfer group that is the same as the first flip-flop or the second flip-flop that outputs the output signal.
• Each of the plurality of arithmetic units inputs an operation result to the first flip-flop or the second flip-flop in either the first data transfer group or the second data transfer group, the first flip-flop or the second flip-flop being different from the first flip-flop or the second flip-flop that outputs the output signal.
• the switching controller individually controls switching between transferring the operation results of the plurality of arithmetic units in the first direction by the plurality of first data transfer groups and transferring the operation results of the plurality of arithmetic units in the second direction by the plurality of second data transfer groups.
• the semiconductor device according to any one of (3) to (6).
• the digital signal processing device includes a plurality of switches that switch output signal paths of the first flip-flops and the second flip-flops in each of the first data transfer groups and the second data transfer groups in accordance with switching control by the switching controller.
• the plurality of switches are connected between input nodes of the plurality of first flip-flops and output nodes of the plurality of arithmetic units, and are connected between input nodes of the plurality of second flip-flops and output nodes of the plurality of arithmetic units.
• a plurality of first output buffers that output operation results of the plurality of arithmetic units in the first direction or the second direction; a plurality of second output buffers that output the operation results of the plurality of arithmetic units in a direction opposite to the first direction or the second direction; the switching controller inputs operation results of the plurality of arithmetic units to the plurality of first flip-flops or the plurality of second flip-flops via the plurality of first output buffers or the plurality of second output buffers;
• the semiconductor device according to any one of (3) to (9).
• the plurality of first data transfer groups, the plurality of second data transfer groups, and the plurality of arithmetic units are arranged in one semiconductor layer, or are divided and arranged in a plurality of semiconductor layers.
• (12) The plurality of first data transfer groups and the plurality of second data transfer groups transfer data including at least one of opcodes, operands, time codes of operations performed, identification information of a next input operation unit, or operation end information of the plurality of operation units.
• the plurality of first data transfer groups transfer data in parallel to one end in the first direction; the plurality of second data transfer groups transfer data in parallel to one end in the second direction; The semiconductor device according to any one of (1) to (12).
• Data transferred to a first end in the first direction in a portion of the plurality of first data transfer groups is transferred to a second end in a direction opposite to the first direction in a portion of the plurality of first data transfer groups other than the portion of the plurality of first data transfer groups; the plurality of second data transfer groups transfer data in parallel to one end in the second direction;
• the semiconductor device according to any one of (1) to (12).
• the plurality of first data transfer groups transfer data in parallel to one end in the first direction; the data transferred to a first end in the second direction by a portion of the second data transfer groups among the plurality of second data transfer groups is transferred in a direction opposite to the second direction by a portion of the second data transfer groups among the plurality of second data transfer groups other than the portion of the second data transfer groups to a second end;
• the semiconductor device according to any one of (1) to (12).
• Data transferred to a first end in the first direction in a portion of the plurality of first data transfer groups is transferred to a second end in a direction opposite to the first direction in a portion of the plurality of first data transfer groups other than the portion of the plurality of first data transfer groups; the data transferred to a third end in the second direction by a portion of the second data transfer groups among the plurality of second data transfer groups is transferred in a direction opposite to the second direction by a portion of the second data transfer groups among the plurality of second data transfer groups other than the portion of the second data transfer groups to a fourth end.
• the semiconductor device according to any one of (1) to (12).
• the plurality of first data transfer groups alternately transfer data in the first direction and data in a direction opposite to the first direction in an order of arrangement in the second direction.
• the plurality of second data transfer groups alternately transfer data in the second direction and data in a direction opposite to the first direction in the order of the first direction.
• Each of the first flip-flops and the second flip-flops outputs a signal having the same logic as an input signal from an output node when a clock signal has a first logic, and sets the output node to a high impedance state when the clock signal has a second logic.
• Each of the first flip-flops and the second flip-flops takes in the input signal when the clock signal is at the second logic level, and outputs a signal having the same logic level as the input signal taken in from the output node when the clock signal subsequently transitions to the first logic level.
• 1 semiconductor device 2 first data transfer group, 3 second data transfer group, 4 controller, 5 first output buffer, 5 first flip-flop, 6 row data generator, 7 row output circuit, 8 second output buffer, 8 second flip-flop, 9 column data generator, 10 column output circuit, 11 clock buffer, 11a first clock buffer, 11b second clock buffer, 12 arithmetic unit, 12g arithmetic unit group, 13 input buffer, 14 output buffer, 15 frame memory, 16 output order switching circuit, 21 first semiconductor substrate, 22 second semiconductor substrate, 23 input/output control unit, 24 register group, 25 arithmetic unit, 26 program counter, 27 pixel unit, 28 memory unit, 29 input/output control unit

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