Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
  • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
  • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
  • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/10—Junction-based devices
  • H10N60/12—Josephson-effect devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/20—Permanent superconducting devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N60/00—Superconducting devices
  • H10N60/80—Constructional details
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10378—Interposers

Definitions

• the present disclosure relates to structures, quantum processors, quantum computers, and methods for manufacturing structures.
• Patent Document 1 semiconductor devices and methods for manufacturing semiconductor devices using silicon through-hole electrode technology are known (see, for example, Patent Document 1 and Non-Patent Document 1).
• the structure of the present disclosure includes a substrate having a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; A wire passes through the through hole and electrically connects a first conductive portion located on the first surface and a second conductive portion located on the second surface.
• the quantum processor of the present disclosure has the above structure.
• the quantum computer disclosed herein includes the quantum processor described above.
• the method for producing a structure of the present disclosure includes a preparation step of preparing a substrate precursor and a metal wire; a manufacturing step of forming a through hole in the substrate precursor to manufacture a substrate; and an insertion step of inserting the metal wire into the through hole.
• FIG. 2 is a plan view illustrating an example of a structure according to an embodiment of the present disclosure.
• 2 is a cross-sectional view taken along the line II-II in FIG. 1.
• 4A to 4C are cross-sectional views showing examples of the shape of a through hole in a substrate.
• 4A to 4C are cross-sectional views showing examples of the shape of a through hole in a substrate.
• 4A to 4C are cross-sectional views showing examples of the shape of a through hole in a substrate.
• FIG. 11 is a cross-sectional view showing an example of a wire passing through a through hole.
• FIG. 11 is a cross-sectional view showing an example of a wire passing through a through hole.
• FIG. 1 is a cross-sectional view illustrating an example of a quantum processor according to an embodiment of the present disclosure.
• FIG. 9 is a plan view showing an example of a superconducting quantum bit circuit included in the quantum processor of FIG. 8.
• FIG. 10 is a perspective view showing an example of a Josephson junction device included in the superconducting quantum bit circuit of FIG. 9 .
• FIG. 1 is a block diagram illustrating an example of a quantum computer according to an embodiment of the present disclosure.
• 1A to 1C are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 1A to 1C are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 1A to 1C are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 1A to 1C are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 1A to 1C are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 1A to 1C are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 11A to 11C are diagrams illustrating another example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 11A to 11C are diagrams illustrating another example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 11A to 11C are diagrams illustrating another example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 11A to 11C are diagrams illustrating another example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• 11A to 11C are diagrams illustrating another example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• FIG. 13 is a plan view illustrating an example of a structure according to another embodiment of the present disclosure.
• 24 is a cross-sectional view taken along the line XXIV-XXIV in FIG. 23.
• FIG. 11 is a cross-sectional view showing another example of a structure according to another embodiment of the present disclosure.
• FIG. 11 is a cross-sectional view showing another example of a structure according to another embodiment of the present disclosure.
• TSV Through Silicon Via
• a copper plating layer is generally formed on the inner surface of a via formed in a silicon chip, and the electrodes arranged on the front and back surfaces of the silicon chip are electrically connected to each other through the copper plating layer.
• FIG. 1 is a plan view showing an example of a structure according to an embodiment of the present disclosure
• FIG. 2 is a cross-sectional view taken along the cutting line II-II in FIG. 1.
• FIGS. 3 to 5 are cross-sectional views showing an example of the shape of a through hole in a substrate
• FIGS. 6 and 7 are cross-sectional views showing an example of a wire passing through a through hole.
• the first conductive portion, second conductive portion, and wire are omitted from FIGS. 3 to 5.
• the structure 1 of this embodiment is a structure for mounting an electric circuit.
• the electric circuit may be a superconducting circuit such as a superconducting quantum bit circuit.
• the structure 1 includes a substrate 2, a first conductive portion 4a, a second conductive portion 4b, and a wire 5.
• first conductive portion 4a and the second conductive portion 4b are not to be distinguished from each other, they may be referred to as conductive portions 4a and 4b.
• the following describes a case where the structure 1 has one conductive structure composed of conductive portions 4a and 4b and a wire 5, but the structure 1 may have multiple conductive structures composed of conductive portions 4a and 4b and a wire 5.
• the substrate 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a.
• a superconducting circuit such as a superconducting quantum bit circuit may be mounted on the first surface 2a.
• the substrate 2 may be, for example, polygonal, circular, elliptical, or other shape. Polygonal shapes include triangular, rectangular, pentagonal, hexagonal, etc.
• the substrate 2 may have a thickness of about 100 ⁇ m to 500 ⁇ m, or may have a thickness of about 300 ⁇ m.
• the substrate 2 is made of single crystal sapphire (Al 2 O 3 ).
• the material constituting the substrate 2 is not limited to single crystal sapphire, and may be single crystal silicon (Si) or a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, or a glass ceramic sintered body.
• the substrate 2 has a through hole 3 that penetrates from the first surface 2a to the second surface 2b.
• the through hole 3 has a first opening 3a on the first surface 2a and a second opening 3b on the second surface 2b.
• openings 3a and 3b when there is no need to distinguish between the first opening 3a and the second opening 3b, they may be referred to as openings 3a and 3b.
• the first opening 3a and the second opening 3b may be, for example, circular, elliptical, or other shapes in plan view. In the following description, the first opening 3a and the second opening 3b are assumed to be circular in plan view.
• the opening diameter da of the first opening 3a and the opening diameter db of the second opening 3b may be the same or different. If the first opening 3a and the second opening 3b are not circular, the opening diameter da of the first opening 3a may be the circle-equivalent diameter of the first opening 3a, and the opening diameter db of the second opening 3b may be the circle-equivalent diameter of the second opening 3b.
• the through hole 3 may be configured such that the opening shape when viewed in a cross section parallel to the first surface 2a is similar to the planar shapes of the first opening 3a and the second opening 3b. As shown in FIG. 3, the through hole 3 may be configured such that the opening diameter (also called the inner diameter) d when viewed in a cross section parallel to the first surface 2a is constant in the thickness direction (Z-axis direction) of the substrate 2.
• the opening diameter d of the through hole 3 does not have to be constant in the thickness direction of the substrate 2.
• the through hole 3 may be configured so that the opening diameter d gradually increases or decreases.
• FIG. 4 shows an example in which the opening diameter d of the through hole 3 gradually decreases from the first opening 3a to the second opening 3b, but the opening diameter d of the through hole 3 may also gradually increase from the first opening 3a to the second opening 3b.
• the through hole 3 may have a narrowed portion 3c located between the first opening 3a and the second opening 3b, as shown in FIG. 5.
• the narrowed portion 3c is the portion where the opening diameter d in the through hole 3 is smallest, and the opening diameter dc of the narrowed portion 3c is smaller than the opening diameters da and db.
• the narrowed portion 3c may be located at a position where the depth from the first surface 2a is about 0.3T to 0.7T, or may be located at a position where the depth is about 0.5T.
• the opening diameter dc of the narrowed portion 3c may be about 0.5 to 0.9 times the opening diameter da of the first opening 3a, and about 0.5 to 0.9 times the opening diameter db of the second opening 3b.
• the through hole 3 may have an aspect ratio of about 3 to 10, or about 5 to 7.
• the aspect ratio may be the thickness T of the substrate 2 divided by the maximum opening diameter d of the through hole 3.
• the first conductive portion 4a is located on the first surface 2a
• the second conductive portion 4b is located on the second surface 2b.
• the conductive portions 4a and 4b may be, for example, circular, elliptical, or other shapes. In the following description, the plan view shape of the conductive portions 4a and 4b is assumed to be circular.
• the conductive portions 4a and 4b may have a thickness of, for example, about 1 ⁇ m to 50 ⁇ m, about 1 ⁇ m to 10 ⁇ m, or about 4 ⁇ m to 6 ⁇ m.
• the conductive parts 4a and 4b may be superconductors.
• the conductive parts 4a and 4b may be made of a superconducting material such as aluminum (Al), tantalum (Ta), niobium (Nb), tin (Sn), indium (In), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride (TiN), niobium nitride (NbN), or niobium titanium (NbTi).
• a superconducting material such as aluminum (Al), tantalum (Ta), niobium (Nb), tin (Sn), indium (In), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride (TiN), niobium nitride (NbN), or niobium titanium (NbTi).
• the first conductive portion 4a may block the first opening 3a as shown in FIG. 2.
• the first conductive portion 4a may have a diameter that is more than 1 time and not more than about 2 times the opening diameter da of the first opening 3a in a plan view.
• the second conductive portion 4b may block the second opening 3b as shown in FIG. 2.
• the second conductive portion 4b may have a diameter that is more than 1 time and not more than about 2 times the opening diameter db of the second opening 3b in a plan view.
• the conductive portions 4a and 4b may be formed using a film formation method such as physical vapor deposition (PVD), printing, plating, or ALD.
• PVD physical vapor deposition
• ALD ALD
• At least one of the first conductive portion 4a and the second conductive portion 4b may form part of a superconducting circuit mounted on the structure 1.
• the superconducting circuit is a superconducting quantum bit circuit including a Josephson junction element
• the first conductive portion 4a may form part of the Josephson junction element.
• the wire 5 passes through the through hole 3 and connects the first conductive portion 4a and the second conductive portion 4b.
• the wire 5 may have a cross-sectional shape such as a circular shape, an elliptical shape, or another shape. In the following description, the cross-sectional shape of the wire 5 is assumed to be circular.
• the wire 5 may have a diameter ⁇ that is approximately the same as the minimum opening diameter of the through hole 3, or may have a diameter ⁇ that is equal to or smaller than the minimum opening diameter of the through hole 3.
• the wire 5 may have a diameter ⁇ of, for example, about 30 ⁇ m to 70 ⁇ m, or may have a diameter ⁇ of about 50 ⁇ m.
• the wire 5 may be located in the through hole 3, with one end connected to the first conductive portion 4a and the other end connected to the second conductive portion 4b.
• the wire 5 and the conductive portions 4a and 4b may be joined using a joining method such as a joining method using at least one of heat and pressure, ultrasonic joining, laser welding, etc.
• the end of the wire 5 extending from the first opening 3a may be connected to the first conductive portion 4a.
• the second conductive portion 4b does not block the second opening 3b
• the end of the wire 5 extending from the second opening 3b may be connected to the second conductive portion 4b.
• the wire 5 and the conductive portions 4a and 4b may be joined using a joining method using at least one of heat and pressure, ultrasonic joining, laser welding, or the like.
• the wire 5 may be a superconductor.
• the wire 5 may be made of a superconducting material such as aluminum, tantalum, niobium, tin, titanium, indium, rhenium, palladium, etc.
• At least a portion of the outer peripheral surface 5a of the wire 5 may be fixed to the inner peripheral surface 3d of the through hole 3. At least a portion of the outer peripheral surface 5a may be fixed to the inner peripheral surface 3d by being thermocompressed to the inner peripheral surface 3d.
• the wire 5 may have at least a portion of its outer surface 5a in contact with the inner surface 3d of the through hole 3 and be fixed to the inner surface 3d by friction. As shown in FIG. 6, the wire 5 may be bent or curved within the through hole 3 and be fixed to the inner surface 3d by friction. As shown in FIG. 7, the wire 5 may have at least a portion of its outer surface 5a in contact with the narrowed portion 3c and be fixed to the narrowed portion 3c by friction.
• the structure 1 can be equipped with electronic circuits such as IC chips and LSIs.
• the structure 1 is configured such that the first conductive portion 4a and the second conductive portion 4b are connected by wires 5 passing through the through holes 3, so that the structure 1 equipped with electronic circuits can be three-dimensionally mounted on a wiring board, thereby enabling high integration of electronic devices.
• the structure 1 does not connect the first conductive portion 4a and the second conductive portion 4b with a plating layer formed by an ALD method or the like on the inner surface 3d of the through hole 3, and therefore can improve mass productivity. Furthermore, the structure 1 can suppress poor connection between the first conductive portion 4a and the second conductive portion 4b due to poor formation of the plating layer, thereby improving the reliability of the electrical device.
• the structure 1 can be applied to superconducting devices because the conductive parts 4a, 4b and the wire 5 are superconductors.
• the quantum processor can be highly integrated by three-dimensionally mounting the structure 1 equipped with a superconducting circuit such as a quantum bit circuit on a wiring board. As a result, the quantum processor can be made multi-bit.
• the first conductive part 4a and the second conductive part 4b can be well connected by the wire 5, improving the reliability of the superconducting device.
• the structure 1 has a substrate 2 made of single crystal sapphire with a low dielectric tangent, so that the dielectric loss is small, and as a result, the coherence time of the quantum bit circuit can be extended. Furthermore, the noise generated in the quantum bit circuit can be reduced, making it possible to perform quantum error correction efficiently. Therefore, the operation of the quantum processor can be stabilized.
• FIG. 8 is a cross-sectional view showing an example of a quantum processor according to an embodiment of the present disclosure
• FIG. 9 is a plan view showing an example of a superconducting quantum bit circuit included in the quantum processor of FIG. 8
• FIG. 10 is a perspective view showing an example of a Josephson junction element included in the superconducting quantum bit circuit of FIG. 9.
• the quantum processor 30 of this embodiment includes a quantum chip 31, an interposer 39, and a wiring substrate 42.
• the quantum chip 31, the interposer 39, and the wiring substrate 42 may be stacked in this order as shown in FIG. 8.
• the quantum processor 30 may include a support substrate 45 as shown in FIG. 8.
• the quantum chip 31, the interposer 39, and the wiring substrate 42 may be located on the support substrate 45.
• the quantum chip 31 includes a structure 1 and a quantum bit circuit 32.
• the quantum bit circuit 32 is mounted on the structure 1.
• the quantum bit circuit 32 may include a quantum bit 33, a readout resonator 34, an inter-quantum bit coupling capacitor 35, and a detection electrode 46, as shown in FIG. 9, for example.
• the quantum bit 33, the readout resonator 34, and the inter-quantum bit coupling capacitor 35 may be mounted on the first surface 2a of the substrate 2.
• the quantum bit 33 may be configured to include, for example, a central electrode 36, an annular electrode 37 surrounding the central electrode 36, and a Josephson junction element 38 connecting the central electrode 36 and the annular electrode 37.
• the central electrode 36 and the annular electrode 37 may be configured to include a superconducting material such as aluminum, tantalum, niobium, tin, indium, rhenium, palladium, titanium, titanium nitride, niobium nitride, niobium titanium, or the like.
• the central electrode 36 may include a first conductive portion 4a.
• the Josephson junction element 38 has a structure in which an insulating thin film 38a is sandwiched between superconductors 38b and 38c, as shown in FIG. 10, for example.
• the insulating thin film 38a may be configured to include an oxide having insulating properties such as aluminum, tantalum, titanium, or the like, and the superconductors 38b and 38c may be configured to include, for example, aluminum, tantalum, titanium, or the like.
• the quantum bit 33 can essentially form a two-level system, and can hold, for example, a quantum state (coherence state) that is composed of a ground state and a first excited state.
• the quantum bit 33 is not limited to the concentric quantum bit shown in FIG. 9.
• the quantum bit 33 may be configured to include, for example, a cross-shaped electrode, an adjacent electrode located adjacent to the cross-shaped electrode, and a Josephson junction element that connects the cross-shaped electrode and the adjacent electrode.
• the readout resonator 34 is electromagnetically coupled to the quantum bit 33.
• the readout resonator 34 is configured to read out the quantum state held in the quantum bit 33.
• the state of the quantum bit 33 read out by the readout resonator 34 may be taken out of the quantum bit circuit 32 as a detection signal via the detection electrode 46.
• the detection signal may be taken out of the quantum bit circuit 32 via the detection electrode 46 and a conductive structure formed of the conductive parts 4a, 4b and the wire 5.
• the readout resonator 34 is not limited to the meandering resonator shown in FIG. 9.
• the readout resonator 34 may be, for example, a linear resonator or a U-shaped resonator.
• the inter-qubit coupling capacitor 35 couples adjacent quantum bits 33 to each other.
• the quantum bit circuit 32 may include a relaxation suppression filter resonator (not shown) that suppresses relaxation of the quantum bit 33.
• a relaxation suppression filter resonator (not shown) that suppresses relaxation of the quantum bit 33.
• the quantum state of the quantum bit 33 can be prevented from being damaged by thermal noise, electromagnetic noise, etc., so the coherence time of the quantum bit circuit 32 can be extended.
• the quantum chip 31 may include a control circuit (not shown) for controlling the quantum bits 33.
• the control circuit may be disposed on the second surface 2b of the substrate 2.
• the control circuit may be connected to the first conductive portion 4a via the second conductive portion 4b and the wire 5.
• the control circuit may be disposed on or inside the surface of the interposer 39, or on or inside the surface of the wiring board 42.
• the interposer 39 may be made of, for example, single crystal silicon, a ceramic material, or the like.
• the ceramic material used for the interposer 39 may be, for example, an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, or the like.
• the interposer 39 may be made of low-temperature co-fired ceramics (LTCC) and may have wiring conductors inside for controlling the quantum bit 33 circuit.
• LTCC low-temperature co-fired ceramics
• the interposer 39 has a third surface 39a and a fourth surface 39b opposite the third surface 39a.
• the interposer 39 is positioned such that the third surface 39a faces the second surface 2b of the substrate 2.
• the interposer 39 has a through hole 40 penetrating from the third surface 39a to the fourth surface 39b.
• the interposer 39 has a wire 41 located in the through hole 40.
• the upper end of the wire 41 may be connected to the second conductive portion 4b of the structure 1.
• the interposer 39 may have a third conductive portion (not shown) that closes the upper end opening of the through hole 40, and the upper end of the wire 41 may be connected to the second conductive portion 4b via the third conductive portion.
• the interposer 39 may have a fourth conductive portion (not shown) that closes the lower end opening of the through hole 40, and the lower end of the wire 41 may be connected to the fourth conductive portion.
• the fourth conductive portion may be connected to wiring conductors 43, 44 of the wiring board 42.
• the wire 41, the third conductive portion, and the fourth conductive portion may be superconductors.
• the wire 41 may be made of a superconducting material such as aluminum, tantalum, niobium, tin, titanium, indium, rhenium, palladium, etc.
• the third conductive portion and the fourth conductive portion may be made of a superconducting material such as aluminum, tantalum, niobium, tin, indium, rhenium, palladium, titanium, titanium nitride, niobium nitride, niobium titanium, etc.
• the wiring board 42 may be composed of, for example, a printed wiring board, a ceramic wiring board, an organic wiring board, etc.
• the wiring conductors 43, 44 are located inside the wiring board 42.
• the wiring conductors 43, 44 may include a wiring conductor 43 composed of a superconducting material, and a wiring conductor 44 composed of a normal conducting material.
• the superconducting material used for the wiring conductor 43 may be, for example, aluminum, tantalum, niobium, tin, indium, rhenium, palladium, titanium, titanium nitride, niobium nitride, niobium titanium, etc.
• the normal conducting material used for the wiring conductor 44 may be, for example, copper (Cu), silver (Ag), etc.
• the support substrate 45 may be made of a metal material such as copper (Cu) or titanium.
• the quantum chip 31, the interposer 39, and the wiring substrate 42 may be disposed in the freezing space of the refrigerator via the support substrate 45.
• the quantum processor 30 includes a structure 1 that allows for easy three-dimensional mounting of the quantum chip 31 on the interposer 39 and wiring board 42, making it possible to achieve high integration and multi-bit capacity for the quantum processor 30.
• the quantum processor 30 includes a substrate 2 made of single crystal sapphire with a low dielectric tangent, making it possible to lengthen the coherence time of the quantum bit circuit 32 and reduce noise generated in the quantum bit circuit 32. Therefore, the quantum processor 30 can operate stably.
• FIG. 11 is a block diagram showing a quantum computer according to an embodiment of the present disclosure.
• the quantum computer 50 of this embodiment includes a quantum processor 30.
• the quantum computer 50 may include a refrigerator 51, microwave amplifiers 52 and 53, a circulator 54, a cryogenic noise filter 55, a coaxial cable connector 56, a microwave input/output device 57, and a control computer 58.
• the refrigerator 51 has a refrigeration space 51a.
• the quantum processor 30, microwave amplifiers 52 and 53, a circulator 54, a cryogenic noise filter 55, and a coaxial cable connector 56 are located inside the refrigeration space 51a.
• the microwave input/output device 57 and a control computer 58 are located outside the refrigeration space 51a.
• the refrigerator 51 cools the refrigeration space 51a to a temperature lower than (or lower than) the transition temperature of the superconducting material constituting the quantum processor 30.
• the transition temperature is a phase transition temperature between a normal conducting phase and a superconducting phase.
• the refrigerator 51 may be configured as a dilution refrigerator.
• the dilution refrigerator is a refrigerator that utilizes the heat of dilution generated when liquid 4He is diluted with liquid 3He .
• the quantum processor 30 may be located in a region of the refrigeration space 51a that is particularly low temperature (e.g., about 10 mK). This makes it possible to suppress thermal noise generated in the quantum processor 30, thereby lengthening the coherence time in the quantum processor 30 and enabling the quantum processor 30 to operate stably.
• the refrigerator 51 may include a vacuum pump that reduces the pressure in the refrigeration space 51a. By reducing the pressure in the refrigeration space 51a, temperature changes around the quantum processor 30 can be reduced, thereby stabilizing the operation of the quantum processor 30.
• the control computer 58 generates a control signal for controlling the quantum processor 30, and the control signal is supplied to the quantum processor 30 via the microwave input/output device 57, the coaxial cable connector 56, and the cryogenic noise filter 55.
• the quantum processor 30 executes quantum calculations based on the control signal supplied from the control computer 58. The calculation results are output to the control computer 58 via the microwave controller and the microwave input/output device 57.
• the quantum computer 50 is highly integrated (i.e., compact) because the quantum processor 30 includes the structure 1. Therefore, even if the volume of the freezing space 51a of the refrigerator 51 is limited, it is easy to place the quantum processor 30 in an area of the freezing space 51a that is particularly cold. As a result, the operation of the quantum processor 30 can be stabilized. Furthermore, the quantum computer 50 is configured such that the quantum processor 30 includes the structure 1, so the operation of the quantum processor 30 can be stabilized.
• Figures 12 to 17 are diagrams illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• the manufacturing method of the structure of this example includes a preparation step, a fabrication step, and an insertion step.
• the manufacturing method of this example may include a formation step that is performed after the insertion step.
• the preparation process is a process of preparing a substrate precursor 6 (see Figure 12) that will become the substrate 2 and a metal wire 7 that will become the wire 5.
• the substrate precursor 6 has a first main surface 6a corresponding to the first surface 2a and a second main surface 6b corresponding to the second surface 2b.
• the substrate precursor 6 may be made of single crystal sapphire, single crystal silicon, or a ceramic material.
• the ceramic material may be, for example, an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, or the like.
• the metal wire 7 may be made of a superconducting material, for example, aluminum, tantalum, niobium, tin, titanium, indium, rhenium, palladium, or the like.
• the manufacturing process is a process of forming a through hole (hereinafter referred to as through hole 3) in the substrate precursor 6 and manufacturing the substrate 2, as shown in FIG. 13.
• the through hole 3 penetrates the substrate precursor 6 from the first main surface 6a to the second main surface 6b.
• the through hole 3 can be formed by laser processing in which the substrate precursor 6 is irradiated with laser light.
• the laser processing can be performed using, for example, a Fiber laser, a YAG laser, or the like.
• the laser light irradiated to the substrate precursor 6 may have a power of about 1 W to 100 W, or may have a power of about 1 W to 10 W, and may have a frequency of about 1 KHz to 100 KHz.
• the laser light may be irradiated from the first main surface 6a side or from the second main surface 6b side.
• the laser light can be irradiated from the first main surface 6a side or the second main surface 6b side to form a through hole 3 with a relatively small difference between the entrance diameter and the exit diameter.
• the difference between the entrance diameter and the exit diameter may be 10% or less of the thickness of the substrate precursor 6.
• the opening diameter d of the through hole 3 becomes approximately constant, and the contact area between the inner surface 3d of the through hole 3 and the metal wire 7 increases, making it possible to fix the metal wire 7 well to the inner surface 3d.
• the distance between adjacent through holes 3 may be equal to or greater than the thickness of the substrate precursor 6. In this case, it becomes easier to form multiple through holes 3 while minimizing damage to the substrate precursor 6.
• the laser light may be applied from the first main surface 6a side and the second main surface 6b side.
• the laser light is applied from the first main surface 6a side to form a recess on the first main surface 6a side with a depth of about half the thickness of the substrate precursor 6, and then the laser light is applied from the second main surface 6b side to form a hole that communicates with the recess on the first main surface 6a side, thereby forming the through hole 3.
• the laser light from the first main surface 6a side and the second main surface 6b side, even if the thickness of the substrate precursor 6 is thick (for example, about 300 ⁇ m or more), it is possible to form the through hole 3 with a small change in the opening diameter d in the thickness direction of the substrate 2.
• the contact area between the inner circumferential surface 3d of the through hole 3 and the metal wire 7 increases, so that the metal wire 7 can be fixed well to the inner circumferential surface 3d.
• the irradiation can be stopped immediately after a hole communicating with the recess on the first main surface 6a side is formed, thereby easily forming a through hole 3 (see FIG. 5) having a narrowed portion 3c.
• "immediately after a hole communicating with the recess on the first main surface 6a side is formed” refers to a predetermined time after the hole formed from the second main surface 6b side communicates with the recess on the first main surface 6a side.
• the predetermined time may be set appropriately depending on the position where the narrowed portion 3c is to be formed, the power and frequency of the laser light, etc.
• laser light is irradiated from the first main surface 6a side and then from the second main surface 6b side, but this is not limited thereto, and laser light may be irradiated from the second main surface 6b side and then from the first main surface 6a side.
• the method of forming the through-hole 3 is not limited to laser processing.
• the through-hole 3 may be formed using an etching technique such as reactive ion etching (RIE).
• RIE reactive ion etching
• the insertion process is a process of inserting a metal wire 7 into a through hole 3 of a substrate 2, as shown in FIG. 14. Inserting the metal wire 7 into the through hole 3 may mean inserting one end of the metal wire 7 from one opening of the through hole 3 and extending the one end from the other opening of the through hole 3, or inserting one end of the metal wire 7 from one opening of the through hole 3 and allowing the one end to reach the other opening of the through hole 3.
• the metal wire 7 may be manually inserted into the through hole 3 using a camera capable of capturing an image of the opening of the through hole 3 on the side where the metal wire 7 is inserted, or the metal wire 7 may be inserted into the through hole 3 using a wire bonding device used in the manufacture of semiconductor devices, etc.
• the insertion process may include fixing at least a portion of the outer peripheral surface 7a of the metal wire 7 to the inner peripheral surface 3d of the through hole 3. This allows the production of a substrate 2 in which a wire 5 is fixed to the inner peripheral surface 3d of the through hole 3.
• the insertion process may include, after fixing at least a portion of the outer peripheral surface 7a of the metal wire 7 to the inner peripheral surface 3d of the through hole 3, cutting off the portions of the metal wire 7 that extend out from the openings 3a and 3b.
• a sacrificial layer 9 may be placed on the second surface 2b of the substrate 2, and the metal wire 7 may be inserted into the through hole 3 from the first opening 3a.
• the metal wire 7 does not extend from the second opening 3b, it is possible to omit cutting off the portion of the metal wire 7 that extends from the second opening 3b. As a result, the mass productivity of the structure 1 can be improved.
• At least a part of the outer peripheral surface 7a may be thermocompressed to the inner peripheral surface 3d.
• the substrate 2 with the metal wire 7 inserted through the through hole 3 may be heated to a temperature at which the metal wire 7 can be plastically deformed.
• the substrate 2 with the metal wire 7 inserted through the through hole 3 may be heated to a temperature at which the metal wire 7 can be plastically deformed.
• the metal wire 7 does not have to be thermocompressed to the inner circumferential surface 3d of the through hole 3.
• a sacrificial layer 9 that blocks the second opening 3b is disposed on the second surface 2b, and the metal wire 7 is strongly inserted into the through hole 3 from the first opening 3a, so that the metal wire 7 is bent or curved in the through hole 3 and contacts the inner circumferential surface 3d, and is fixed to the inner circumferential surface 3d by friction, as in the wire 5 shown in FIG. 6.
• the surface on which the sacrificial layer 9 is disposed may be the first surface 2a.
• the metal wire 7 can be formed like the wire 5 shown in FIG.
• a wire 5 having a diameter ⁇ equal to or larger than the opening diameter dc can be inserted into the through hole 3 to form a metal wire 7 that contacts the narrowed portion 3c and is fixed to the narrowed portion 3c by friction, as in the wire 5 shown in FIG. 7.
• the metal wire 7 can be easily inserted into the through hole 3 by inserting the metal wire 7 from the first opening 3a into the through hole 3.
• the mass productivity of the structure 1 can be improved.
• the opening diameter da of the first opening 3a is smaller than the opening diameter db of the second opening 3b, the metal wire 7 can be easily inserted into the through hole 3 by inserting the metal wire 7 from the second opening 3b into the through hole 3.
• multiple substrates 2 may be arranged so that their through holes 3 overlap in a plan view, and one metal wire 7 may be inserted into the multiple through holes 3.
• the insertion process can be performed efficiently, improving the mass productivity of the structure 1.
• the forming process is a process of forming conductive portions 4a, 4b and connecting the conductive portions 4a, 4b to the metal wire 7, as shown in FIG. 17.
• the first conductive portion 4a is formed on the first surface 2a of the substrate 2
• the second conductive portion 4b is formed on the second surface 2b of the substrate 2.
• the first conductive portion 4a may be formed so as to block the first opening 3a
• the second conductive portion 4b may be formed so as to block the second opening 3b.
• the conductive parts 4a and 4b may be made of a superconducting material such as aluminum, tantalum, niobium, tin, indium, rhenium, palladium, titanium, titanium nitride, niobium nitride, or niobium titanium.
• the conductive parts 4a and 4b can be formed using a film formation method such as a printing method, a plating method, a PVD method, or an ALD method.
• the conductive portions 4a and 4b can be joined to the metal wire 7 using a joining method such as a joining method using at least one of heat and pressure, ultrasonic joining, laser welding, etc.
• Figures 18 to 22 are diagrams illustrating another example of a method for manufacturing a structure according to an embodiment of the present disclosure.
• the manufacturing method of the structure of this example includes a preparation process, a fabrication process, a formation process (also called a first formation process), and an insertion process.
• the manufacturing method of this example may include a second formation process that is performed after the insertion process.
• a case where the substrate 2 has one through hole 3 is described, but the same applies when the substrate 2 has multiple through holes 3.
• the preparation process and fabrication process are similar to the preparation process and fabrication process described above, respectively, and therefore detailed description will be omitted.
• the preparation process is a process of preparing a substrate precursor 6 (see FIG. 18) that will become the substrate 2, and a metal wire 8 that will become the wire 5.
• the metal wire 8 has a length that is the same as or approximately the same as the thickness T of the substrate 2.
• the preparation process may include cutting a metal wire that is longer than the thickness T of the substrate 2, to produce a metal wire 8 that has a length that is the same as or approximately the same as the thickness T.
• the manufacturing process is a process of forming a through hole (hereinafter referred to as through hole 3) in a substrate precursor 6 and manufacturing a substrate 2, as shown in FIG. 19.
• the first forming step is a step of forming a conductive portion (first conductive portion 4a or second conductive portion 4b) in one opening (first opening 3a or second opening 3b) of the through hole 3, as shown in FIG. 20.
• first conductive portion 4a may be formed in the first opening 3a of the through hole 3.
• the second conductive portion 4b may close the second opening 3b.
• the second conductive portion 4b is formed using a film formation method such as a printing method, a plating method, or a PVD method. This makes it possible to form the second conductive portion 4b that closes the second opening 3b even if there is no metal wire 7 in the second opening 3b.
• the conductive portion may be formed in the opening 3a or 3b, whichever has the smaller diameter. This allows the conductive portion to be formed satisfactorily even if the metal wire 8 is not positioned in the through hole 3.
• the insertion process is a process in which the metal wire 8 is inserted from the other opening (first opening 3a) of the through hole 3 and connected to the conductive portion (second conductive portion 4b).
• an electronic component mounting device used in the manufacture of semiconductor devices and the like may be used to position the metal wire 8 in the through hole 3. This allows the metal wire 8 to be positioned in the through hole 3 quickly and efficiently.
• the metal wire 8 may be placed in the through hole 3 from the first opening 3a, and one end of the metal wire 8 may be connected to the second conductive portion 4b.
• the one end of the metal wire 8 may be joined to the second conductive portion 4b using a joining method that uses at least one of heat and pressure, ultrasonic joining, laser welding, or the like.
• at least a portion of the outer peripheral surface 8a of the metal wire 8 may or may not be fixed to the inner peripheral surface 3d.
• at least a portion of the outer peripheral surface 8a may be thermocompressed to the inner peripheral surface 3d.
• the outer peripheral surface 8a does not need to be thermocompressed to the inner peripheral surface 3d.
• the metal wire 8 By strongly inserting the metal wire 8 from the first opening 3a into the through hole 3, it is possible to form a metal wire 8 that is bent or curved within the through hole 3 and contacts the inner peripheral surface 3d, as shown in FIG. 6, and is fixed to the inner peripheral surface 3d by friction.
• the through hole 3 has a narrowed portion 3c, it is possible to form a metal wire 8 that is bent or curved within the through hole 3 and contacts the narrowed portion 3c, as shown in FIG. 7, and is fixed to the narrowed portion 3c by friction, as shown in FIG. 7.
• the metal wire 8 can be easily positioned in the through hole 3 by inserting the metal wire 8 from the first opening 3a into the through hole 3.
• the mass productivity of the structure 1 can be improved.
• the metal wire 8 can be easily positioned in the through hole 3 by inserting the metal wire 8 from the second opening 3b into the through hole 3.
• the second formation process is a process of forming a conductive portion (first conductive portion 4a) in the other opening (first opening 3a) of the through hole 3, as shown in FIG. 22, and connecting the first conductive portion 4a to the metal wire 8 located inside the through hole 3.
• the first conductive portion 4a may close the first opening 3a.
• the first conductive portion 4a can be formed using a film formation method such as a printing method, a plating method, or a PVD method.
• the first conductive portion 4a and the metal wire 8 can be joined using a joining method using at least one of heat and pressure, ultrasonic joining, laser welding, or the like.
• the method for manufacturing a structure according to an embodiment of the present disclosure allows for efficient manufacturing of structure 1.
• FIG. 23 is a plan view showing an example of a structure according to another embodiment of the present disclosure
• FIG. 24 is a cross-sectional view taken along the cutting line XXIV-XXIV in FIG. 23
• FIGS. 25 and 26 are cross-sectional views showing another example of a structure according to another embodiment of the present disclosure.
• the first conductive portion, the second conductive portion, and the insulating layer are omitted, and the wires and conductors are hatched.
• the cross-sectional views shown in FIGS. 25 and 26 correspond to the cross-sectional view shown in FIG. 24.
• the structure of this embodiment differs from the structure of the above embodiment in that it has an insulator and a conductor, but is otherwise similar in configuration. Therefore, the same reference symbols as those in the structure of the above embodiment are used for similar configurations, and detailed descriptions are omitted.
• the structure 1A of this embodiment includes a substrate 2, a first conductive portion 4a, a second conductive portion 4b, a wire 5, an insulator 10, and a conductor 11.
• the insulator 10 is located in the through hole 3 of the substrate 2 and covers the outer peripheral surface 5a of the wire 5.
• the insulator 10 may completely cover the outer peripheral surface 5a of the wire 5, or may partially cover the outer peripheral surface 5a of the wire 5.
• the insulator 10 may be a hollow columnar shape.
• the insulator 10 has an inner peripheral surface 10a facing the outer peripheral surface 5a of the wire 5, and an outer peripheral surface 10b opposite to the inner peripheral surface 10a.
• the insulator 10 may have a thickness of, for example, about 3 ⁇ m to 10 ⁇ m (1/2 the difference between the outer diameter and the inner diameter), or may have a thickness of about 5 ⁇ m.
• the insulator 10 may be made of, for example, silicon (Si), silica (SiO 2 ), alumina (Al 2 O 3 ), or the like.
• the conductor 11 is located in the through hole 3 of the substrate 2 and covers the outer peripheral surface 10b of the insulator 10.
• the conductor 11 may completely cover the outer peripheral surface 10b of the insulator 10, or may partially cover the outer peripheral surface 10b of the insulator 10.
• the conductor 11 may be hollow and cylindrical.
• the conductor 11 has an inner peripheral surface 11a facing the outer peripheral surface 10b of the insulator 10, and an outer peripheral surface 11b opposite the inner peripheral surface 11a. At least a portion of the outer peripheral surface 11b of the conductor 11 may be fixed to the inner peripheral surface 3d of the through hole 3.
• the conductor 11 may have a thickness of, for example, about 1 ⁇ m to 5 ⁇ m (half the difference between the outer diameter and the inner diameter), or may have a thickness of about 3 ⁇ m.
• the conductor 11 may be made of a superconducting material such as aluminum, tantalum, niobium, tin, titanium, indium, rhenium, or palladium, or may be made of a normal conducting material such as copper or silver.
• the conductor 11 may be made of nonmagnetic ferrite.
• the wire 5, the insulator 10, and the conductor 11 constitute a coaxial through electrode 12.
• the wire 5 is the internal conductor of the coaxial through electrode 12, and the conductor 11 is the external conductor of the coaxial through electrode 12.
• the conductor 11 may be connected to a ground potential.
• the wire 5 and the conductor 11 may or may not be concentric.
• the conductive parts 4a, 4b are electrically connected to the wire 5 and electrically insulated from the conductor 11.
• the structure 1A may be configured such that the diameter d4 of the conductive parts 4a, 4b is less than the inner diameter d11 of the conductor 11, and the centroids of the conductive parts 4a, 4b and the centroid of the wire 5 coincide or nearly coincide with each other in a plan view.
• the conductor 11 can function as a shielding material that prevents electromagnetic waves generated inside and outside the quantum computer 50 from undesirably penetrating the wire 5 or leaking from the wire 5. Therefore, according to the structure 1A, even when the quantum processor 30 is highly integrated, the noise generated in the quantum bit circuit 32 can be reduced. As a result, quantum error correction can be performed efficiently, and the operation of the quantum processor 30 can be stabilized.
• the structure 1A may include an insulating layer 13.
• the insulating layer 13 is located between the conductive parts 4a, 4b and the conductor 11, and electrically insulates the conductive parts 4a, 4b from the conductor 11.
• the insulating layer 13 may be located between the conductive parts 4a, 4b and the substrate 2, or between the conductive parts 4a, 4b and the insulator 10, as long as it does not impede the electrical connection between the conductive parts 4a, 4b and the wire 5.
• the insulating layer 13 may be made of, for example, silicon, silica, alumina, or the like.
• the 25 can also electrically connect the conductive parts 4a, 4b and the wire 5, and electrically insulate the conductive parts 4a, 4b from the conductor 11.
• the quantum processor 30 is highly integrated, the noise generated in the quantum bit circuit 32 can be reduced.
• quantum error correction can be efficiently performed, and the operation of the quantum processor 30 can be stabilized.
• the structure 1A may be configured such that the upper end surface of the conductor 11 is located below the upper end surface of the wire 5, and the lower end surface of the conductor 11 is located above the lower end surface of the wire 5.
• the coaxial through electrode 12 may have a notch 11c in which the conductor 11 is cut out from the first surface 2a side, and a notch 11d in which the conductor 11 is cut out from the second surface 2b side.
• the structure 1A shown in FIG. 26 can also electrically connect the conductive parts 4a and 4b to the wire 5 and electrically insulate the conductive parts 4a and 4b from the conductor 11. As a result, even if the quantum processor 30 is highly integrated, the noise generated in the quantum bit circuit 32 can be reduced. In addition, quantum error correction can be efficiently performed, and the operation of the quantum processor 30 can be stabilized.
• Structure 1A can be manufactured by a manufacturing method similar to that of structure 1.
• steps similar to those of the method for manufacturing structure 1 reference will be made to the drawings showing the steps of the method for manufacturing structure 1, and detailed explanations will be omitted.
• the manufacturing method of this example includes a preparation step, a fabrication step, and an insertion step.
• the manufacturing method of this example may include a formation step that is performed after the insertion step.
• the preparation process is a process of preparing a substrate precursor 6 (see FIG. 12) and a coaxial cable that will become a coaxial through electrode 12.
• the coaxial cable can be prepared by forming an insulator layer on the outer peripheral surface 7a of a metal wire 7 (see FIG. 14) and forming a conductor layer on the outer peripheral surface of the insulator layer opposite to the inner peripheral surface facing the metal wire 7.
• the insulator layer becomes the insulator 10 of the coaxial through electrode 12.
• the insulator layer may be made of, for example, silicon, silica, alumina, or the like.
• the insulator layer can be formed using a thin film formation method such as a plating method or a sputtering method.
• the plating method may be an immersion plating method.
• the conductor layer becomes the conductor 11 of the coaxial through electrode 12.
• the conductor layer may be made of a superconducting material such as aluminum, tantalum, niobium, tin, titanium, indium, rhenium, palladium, or the like, or may be made of a normal conducting material such as copper or silver.
• the conductive material layer may be made of non-magnetic ferrite.
• the conductive layer can be formed using a thin film formation method such as plating or sputtering. The plating method may be immersion plating.
• the manufacturing process involves forming through holes 3 in a substrate precursor 6 to produce a substrate 2 (see Figure 13).
• the insertion process is a process of inserting a coaxial cable into the through hole 3 of the substrate 2 (see FIG. 14).
• the insertion process may include fixing at least a part of the outer peripheral surface of the conductive layer to the inner peripheral surface 3d of the through hole 3.
• the at least a part may be thermocompressed to the inner peripheral surface 3d, or may be fixed to the inner peripheral surface 3d by friction (see FIGS. 6 and 7).
• the insertion process may include, after fixing at least a part of the coaxial cable to the inner peripheral surface 3d of the through hole 3, cutting off the portions of the coaxial cable extending from the openings 3a and 3b.
• the coaxial cable may be inserted manually through the through hole 3, or the coaxial cable may be inserted through the through hole 3 using a wire bonding device.
• a sacrificial layer 9 that blocks the second opening 3b may be disposed on the second surface 2b of the substrate 2, and the coaxial cable may be inserted from the first opening 3a into the through hole 3 (see FIG. 15).
• a coaxial cable that is bent or curved within the through hole 3 and contacts the inner peripheral surface 3d, and is fixed to the inner peripheral surface 3d by friction can be easily formed (see FIG. 6).
• multiple substrates 2 may be disposed such that their through holes 3 overlap in a plan view, and one coaxial cable may be inserted into multiple through holes 3 (see FIG. 16). In this case, the insertion process can be performed efficiently, and the mass productivity of the structure 1A can be improved.
• the forming process is a process of forming the conductive parts 4a, 4b and connecting the conductive parts 4a, 4b to the metal wire 7 (see FIG. 17).
• the conductive parts 4a, 4b are connected to the metal wire 7 without electrically connecting the conductive parts 4a, 4b to the conductor layer.
• the conductive parts 4a, 4b (see FIG. 24) having a diameter d4 less than the inner diameter d11 of the conductor 11 may be formed so that the centroids of the conductive parts 4a, 4b and the centroid of the wire 5 coincide or approximately coincide with each other in a plan view.
• an insulating layer 13 before forming the conductive parts 4a, 4b, an insulating layer 13 (see FIG.
• a notch (notch 11c, 11d shown in FIG. 26) may be formed in the coaxial cable.
• the insulating layer 13 may be formed using a thin film forming method such as a plating method or a sputtering method.
• the notch in the coaxial cable may be formed before the coaxial cable is inserted into the through hole 3.
• the structure 1A can be manufactured by the above manufacturing method.
• a coaxial cable manufactured separately from the substrate 2 is inserted into the through hole 3 to manufacture the coaxial through electrode 12.
• the coaxial cable can be manufactured continuously, for example, by forming an insulating layer on the outer surface 7a of the metal wire 7 while unwinding the metal wire 7 wound around a bobbin or the like, and then forming a conductive layer on the outer surface of the insulating layer. Therefore, according to the manufacturing method of this example, the coaxial through electrode 12 can be manufactured in a short time and at low cost compared to the case where a coaxial through electrode is manufactured in the through hole 3 using a deep reactive ion etching (Deep-RIE) method, an ALD method, or the like. As a result, the mass productivity of the structure 1A can be improved.
• Deep-RIE deep reactive ion etching
• the manufacturing method of this example includes a preparation process, a fabrication process, a formation process (also called a first formation process), and an insertion process.
• the manufacturing method of this example may include a second formation process that is performed after the insertion process.
• the preparation process is a process of preparing a substrate precursor 6 and a coaxial cable.
• the coaxial cable is composed of a metal wire 8 (see FIG. 21), an insulating layer, and a conductive layer, and has a length equal to or approximately equal to the thickness T of the substrate 2.
• the preparation process may include cutting a coaxial cable that is longer than the thickness T of the substrate 2, and producing a coaxial cable having a length equal to or approximately equal to the thickness T.
• the preparation process may include forming a notch portion (notch portions 11c and 11d shown in FIG. 26) in the coaxial cable.
• the manufacturing process involves forming through holes 3 in a substrate precursor 6 to produce a substrate 2 (see Figure 13).
• the first formation process is a process of forming a second conductive portion 4b that closes the second opening 3b of the through hole 3 (see FIG. 20).
• the first formation process may include forming an insulating layer 13 that electrically insulates the second conductive portion 4b from the conductor layer of the coaxial cable.
• the insertion process is a process in which the coaxial cable is inserted through the first opening 3a of the through hole 3 and the metal wire 8 of the coaxial cable is connected to the second conductive portion 4b.
• the coaxial cable may be placed in the through hole 3 using an electronic component mounting device. This allows the coaxial cable to be placed in the through hole 3 quickly and efficiently.
• the insertion step may include fixing at least a portion of the outer circumferential surface of the conductive layer to the inner circumferential surface 3d of the through hole 3.
• the at least a portion may be heat-pressed to the inner circumferential surface 3d, or the coaxial cable may be fixed to the inner circumferential surface 3d by friction (see Figures 6 and 7).
• the second formation process is a process of forming a first conductive portion 4a in the first opening 3a of the through hole 3 and connecting the first conductive portion 4a to the metal wire 8 (see FIG. 17).
• the first conductive portion 4a is connected to the metal wire 8 without electrically connecting the first conductive portion 4a to the conductor layer.
• the second formation process may include forming an insulating layer 13 that electrically insulates the first conductive portion 4a from the conductor layer of the coaxial cable.
• the coaxial cable can be placed in the through hole 3 quickly and efficiently by using an electronic component mounting device. As a result, the mass productivity of the structure 1A can be improved.
• electrical continuity between electrodes can be easily achieved by TSVs.
• the structure of the present disclosure can be applied to superconducting devices such as quantum processors, and the structure of the present disclosure can easily achieve high integration and multi-bit quantum processors.
• This disclosure can be implemented in the following configurations (1) to (12).
• a substrate having a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; a wire passing through the through hole and electrically connecting a first conductive portion located on the first surface and a second conductive portion located on the second surface.
• a quantum processor having a structure described in any one of the above configurations (1) to (6).
• an insulating layer is formed on an outer peripheral surface of the metal wire, and a conductor layer is formed on a surface of the insulating layer opposite to a surface facing the metal wire,

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