WO2024203120A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024203120A1
WO2024203120A1 PCT/JP2024/008808 JP2024008808W WO2024203120A1 WO 2024203120 A1 WO2024203120 A1 WO 2024203120A1 JP 2024008808 W JP2024008808 W JP 2024008808W WO 2024203120 A1 WO2024203120 A1 WO 2024203120A1
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WIPO (PCT)
Prior art keywords
electrode
region
flr
film
trench
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Ceased
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PCT/JP2024/008808
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English (en)
French (fr)
Japanese (ja)
Inventor
信敬 大井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202480020670.1A priority Critical patent/CN120937526A/zh
Priority to JP2025510173A priority patent/JPWO2024203120A1/ja
Publication of WO2024203120A1 publication Critical patent/WO2024203120A1/ja
Priority to US19/337,946 priority patent/US20260020294A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • This disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a semiconductor device that includes an active region and an edge termination region surrounding the active region. An IGBT and a free wheel diode are formed in the active region. In the edge termination region, a plurality of guard rings (field limiting rings (FLR)) and field plate electrodes (FLR electrodes) are formed on the plurality of guard rings and electrically connected to the corresponding guard rings.
  • FLR field limiting rings
  • FLR electrodes field plate electrodes
  • the objective of this disclosure is to provide a semiconductor device that can increase the breakdown voltage at corners where curved portions of the FLR exist in the outer peripheral region.
  • One embodiment of the present disclosure provides a semiconductor device including a chip having a first main surface that is rectangular in plan view and a second main surface on the opposite side thereof, an active region provided on the first main surface and in which an element structure is formed, a peripheral region outside the active region, the peripheral region being provided on the outer periphery of the first main surface and having four corners, a first conductivity type drift region formed inside the chip, and a plurality of second conductivity type field limiting rings (hereinafter referred to as "FLRs”) formed in the peripheral region on the surface layer of the first main surface so as to surround the active region, each of the FLRs having an FLR curved portion that is curved in plan view at the four corners, each of the FLRs having a straight line portion that is linear in plan view between the four corners, and each of the FLR curved portions having a double diffusion structure including an inner first diffusion region and an outer second diffusion region having a lower second conductivity type impurity concentration than the first diffusion region.
  • FLRs second conductivity type field
  • This configuration can increase the breakdown voltage at corners where curved portions of the FLR exist in the outer peripheral region.
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment.
  • FIG. 2 is a plan view showing the layout of the first main surface.
  • FIG. 3 is an enlarged plan view showing the active region and the peripheral region.
  • FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG.
  • FIG. 5 is a cross-sectional view taken along line V-V shown in FIG.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is an enlarged plan view showing the active and boundary regions.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG.
  • FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG.
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment.
  • FIG. 2 is a plan view showing the layout of the first main surface.
  • FIG. 3 is an enlarged plan view showing the active region and the peripheral region.
  • FIG. 10A is a cross-sectional view taken along the line XA-XA shown in FIG. 10B is a cross-sectional view taken along line XB-XB shown in FIG.
  • FIG. 10C is a cross-sectional view showing a modified example of the FLR curve portion, and corresponds to the cross-sectional view of FIG. 10B.
  • FIG. 11 is an enlarged plan view showing the pad area.
  • FIG. 12 is an enlarged plan view showing the gate resistor structure shown in FIG.
  • FIG. 13 is an enlarged plan view showing an inner part of the gate resistor structure shown in FIG.
  • FIG. 14 is an enlarged plan view showing one end of the gate resistor structure shown in FIG.
  • FIG. 15 is an enlarged plan view showing the other end of the gate resistor structure shown in FIG.
  • FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. 13.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 13.
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG.
  • FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 15.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 12.
  • FIG. 23 is a plan view showing the layout of the resistance film, the gate electrode film, and the gate wiring film.
  • FIG. 24 is an electrical circuit diagram showing a gate resistor structure, a gate terminal electrode, and a gate wiring electrode.
  • FIG. 25 is a schematic plan view for explaining a modified example of the FLR, the FLR electrode, and the FLR connecting electrode, and is a schematic plan view mainly showing the structure of the second corner portion of the outer circumferential region.
  • Figure 26 is a schematic cross-sectional view taken along line XXVI-XXVI shown in Figure 25.
  • FIG. 27 is a schematic plan view for explaining a modification of the FLR curve portion in FIG. 25. In FIG. FIG. FIG.
  • FIG. 28 is a schematic plan view for explaining another modified example of the FLR, the FLR electrode, and the FLR connecting electrode, and is a schematic plan view mainly showing the structure of the second corner portion of the outer circumferential region.
  • FIG. 29 is a schematic plan view for explaining a modification of the FLR curve portion of FIG.
  • FIG. 30A is a schematic plan view showing a structure of a first corner portion in still another modified example of an FLR, an FLR electrode, and an FLR connecting electrode.
  • FIG. 30B is a schematic plan view showing the structure of a second corner portion in the same modified example as FIG. 30A.
  • FIG. 30C is a schematic plan view showing the structure of a third corner portion in the same modified example as FIG. 30A.
  • FIG. 30D is a schematic plan view showing the structure of a fourth corner portion in the same modified example as FIG. 30A.
  • FIG. 31 is a schematic cross-sectional view taken along line XXXI-XXXI shown in FIG. 30B.
  • FIG. 32 is a schematic plan view for explaining a modification of the FLR curve portion of FIG. 30B.
  • this phrase includes a numerical value (shape) equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the phrases “first,” “second,” “third,” etc. are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.
  • FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment.
  • FIG. 2 is a plan view showing the layout of a first main surface 3.
  • FIG. 3 is an enlarged plan view showing an active region 6 and a peripheral region 9.
  • FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. 3.
  • FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. 3.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 3.
  • FIG. 7 is an enlarged plan view showing the active region 6 and the boundary region 8.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7.
  • FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7.
  • FIG. 10A is a cross-sectional view taken along line XA-XA shown in FIG. 1.
  • FIG. 10B is a cross-sectional view taken along line XB-XB shown in FIG. 1.
  • the semiconductor device 1A is an IGBT semiconductor device equipped with an IGBT (Insulated Gate Bipolar Transistor). With reference to Figures 1 to 10B, the semiconductor device 1A includes a chip 2 having a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 may be referred to as a "semiconductor chip.” In this embodiment, the chip 2 has a single-layer structure made of a silicon single crystal substrate (semiconductor substrate).
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").
  • the normal direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 has a quadrangular shape when viewed in a plan view.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the semiconductor device 1A includes a plurality of active regions 6 spaced apart on the first main surface 3.
  • the plurality of active regions 6 include a first active region 6A and a second active region 6B.
  • the first active region 6A is provided in an area on the first side surface 5A side of a line that crosses the center of the first main surface 3 in the first direction X.
  • the second active region 6B is provided in an area on the second side surface 5B side of a line that crosses the center of the first main surface 3 in the first direction X.
  • each active region 6 is formed in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar shape of each active region 6 is arbitrary.
  • the element structure includes an IGBT structure Tr (transistor structure).
  • the element structure may include a transistor other than an IGBT.
  • the element structure may include an IGBT structure and a free wheel diode (FWD) structure connected in inverse parallel to the IGBT structure.
  • the semiconductor device 1A includes an inactive region 7 provided in a region outside the multiple active regions 6 on the first main surface 3.
  • the inactive region 7 includes a boundary region 8 and a peripheral region 9.
  • the boundary region 8 is provided in a band shape extending in the first direction X in the region between the first active region 6A and the second active region 6B. In this embodiment, the boundary region 8 is located on a straight line that crosses the center of the first main surface 3 in the first direction X.
  • the boundary region 8 includes a pad region 10 having a relatively large width in the second direction Y, and a street region 11 having a width in the second direction Y that is smaller than the width of the pad region 10.
  • the pad region 10 may be referred to as a "first boundary region” or a "wide region”.
  • the street region 11 may be referred to as a "second boundary region", a "line region” or a "narrow region”.
  • the pad region 10 is provided in an area on one side in the first direction X (the third side surface 5C side). In this embodiment, the pad region 10 is located on a straight line that crosses the center of the first main surface 3 in the first direction X in a plan view, and is provided in a rectangular shape near the center of the third side surface 5C.
  • the street region 11 is provided in an area on the other side in the first direction X (the fourth side surface 5D side) of the pad region 10. In this embodiment, the street region 11 is pulled out in a strip shape from the pad region 10 toward the fourth side surface 5D side, and is located on a straight line that crosses the center of the first main surface 3 in the first direction X.
  • the peripheral region 9 is provided on the periphery of the chip 2 so as to collectively surround the multiple active regions 6.
  • the peripheral region 9 is provided in a ring shape (a square ring shape in this embodiment) extending along the periphery (first to fourth side faces 5A to 5D) of the chip 2.
  • the peripheral region 9 is connected to the pad region 10 on one side (the third side face 5C side) of the first main surface 3, and is connected to the street region 11 on the other side (the fourth side face 5D side) of the first main surface 3.
  • the outer peripheral region 9 has four corners 201, 202, 203, and 204.
  • Corner 201 is a corner sandwiched between the first side 5A and the third side 5C in a plan view (hereinafter referred to as "first corner 201").
  • Corner 202 is a corner sandwiched between the first side 5A and the fourth side 5D in a plan view (hereinafter referred to as "second corner 202").
  • Corner portion 203 is a corner portion sandwiched between fourth side surface 5D and second side surface 5B in plan view (hereinafter referred to as “third corner portion 203").
  • Corner portion 204 is a corner portion sandwiched between second side surface 5B and third side surface 5C in plan view (hereinafter referred to as "fourth corner portion 204").
  • the semiconductor device 1A includes an n-type (first conductivity type) drift region 12 formed inside the chip 2.
  • the drift region 12 is formed throughout the entire inside of the chip 2.
  • the chip 2 is made of an n-type semiconductor substrate (n-type semiconductor chip), and the drift region 12 is formed by utilizing the n-type chip 2.
  • the semiconductor device 1A includes an n-type buffer region 13 formed in a surface layer of the second main surface 4.
  • the buffer region 13 is formed in a layer extending along the second main surface 4 over the entire area of the second main surface 4.
  • the buffer region 13 has a higher n-type impurity concentration than the drift region 12.
  • the presence or absence of the buffer region 13 is optional, and a configuration without the buffer region 13 may be adopted.
  • the semiconductor device 1A includes a p-type (second conductivity type) collector region 14 formed in a surface layer portion of the second main surface 4.
  • the collector region 14 is formed in a surface layer portion on the second main surface 4 side of the buffer region 13.
  • the collector region 14 is formed in a layer shape extending along the second main surface 4 over the entire area of the second main surface 4.
  • the collector region 14 is exposed from the second main surface 4 and parts of the first to fourth side surfaces 5A to 5D.
  • the semiconductor device 1A includes a plurality of trench isolation structures 15 formed on the first main surface 3 so as to partition a plurality of active regions 6.
  • a gate potential is applied to the plurality of trench isolation structures 15.
  • the trench isolation structures 15 may also be referred to as “trench gate isolation structures” or “trench gate connection structures.”
  • the plurality of trench isolation structures 15 include a first trench isolation structure 15A on the first active region 6A side and a second trench isolation structure 15B on the second active region 6B side.
  • the first trench isolation structure 15A surrounds the first active region 6A and separates the first active region 6A from the boundary region 8 and the outer peripheral region 9.
  • the first trench isolation structure 15A is formed in a polygonal ring shape having four sides parallel to the periphery of the chip 2 in a plan view.
  • the first trench isolation structure 15A has a bent portion that separates the pad region 10 and street region 11 of the boundary region 8 in a plan view.
  • the second trench isolation structure 15B surrounds the second active region 6B and separates the second active region 6B from the boundary region 8 and the outer peripheral region 9.
  • the second trench isolation structure 15B is formed in a polygonal ring shape having four sides parallel to the periphery of the chip 2 in a plan view.
  • the second trench isolation structure 15B has a bent portion that separates the pad region 10 and street region 11 of the boundary region 8 in a plan view.
  • the trench isolation structure 15 preferably has a width less than the width of the street region 11.
  • the width of the trench isolation structure 15 is the width in a direction perpendicular to the direction in which the trench isolation structure 15 extends.
  • the width of the trench isolation structure 15 may be 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the width of the trench isolation structure 15 is preferably 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the width of the trench isolation structure 15 is preferably 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the trench isolation structure 15 may have a depth of 1 ⁇ m or more and 20 ⁇ m or less.
  • the depth of the trench isolation structure 15 is preferably 4 ⁇ m or more and 10 ⁇ m or less.
  • the trench isolation structure 15 includes an isolation trench 16, an isolation insulating film 17, and an isolation buried electrode 18.
  • the isolation trench 16 is formed in the first main surface 3 and defines the wall surface of the trench isolation structure 15.
  • the isolation insulating film 17 covers the wall surface of the isolation trench 16 in a film-like manner.
  • the isolation insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.
  • the isolation insulating film 17 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the isolation insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.
  • the isolation buried electrode 18 is buried in the isolation trench 16 with the isolation insulating film 17 in between.
  • the isolation buried electrode 18 may include conductive polysilicon. A gate potential is applied to the isolation buried electrode 18.
  • the semiconductor device 1A includes an IGBT structure Tr (transistor structure) formed in each active region 6.
  • the IGBT structure Tr is not formed in the inactive region 7. Since the configuration on the second active region 6B side (the configuration of the IGBT structure Tr) is substantially the same as the configuration on the first active region 6A side (the configuration of the IGBT structure Tr), the configuration on the first active region 6A side will be described below.
  • the configuration on the second active region 6B side is linearly symmetrical to the configuration on the first active region 6A side across the boundary region 8.
  • the description of the structure on the second active region 6B side is omitted, as the description of the structure on the first active region 6A side applies.
  • the n-type impurity concentration of drift region 12 gradually decreases from the surface of drift region 12 on the first main surface 3 side toward the surface of drift region 12 on the second main surface 4 side.
  • the n-type impurity concentration of drift region 12 is preferably, for example, not less than 1.0 ⁇ 10 13 cm ⁇ 3 and not more than 1.0 ⁇ 10 15 cm ⁇ 3 .
  • the semiconductor device 1A includes a p-type channel region 20 formed in the surface layer of the first main surface 3 in the first active region 6A.
  • the channel region 20 may be referred to as a "body region” or a "base region”.
  • the channel region 20 is formed in the surface layer of the drift region 12 on the first main surface 3 side.
  • the channel region 20 extends in a layered manner along the first main surface 3 and is connected to the inner peripheral wall of the trench isolation structure 15.
  • the channel region 20 is formed shallower than the trench isolation structure 15 and has a bottom located on the first main surface 3 side of the bottom wall of the trench isolation structure 15. It is preferable that the bottom of the channel region 20 is located on the first main surface 3 side of the intermediate depth range of the trench isolation structure 15.
  • the thickness of the channel region 20 may be about 1 ⁇ m.
  • the semiconductor device 1A includes a plurality of first trench structures 21 formed on the first main surface 3 in the first active region 6A.
  • a gate potential is applied to the plurality of first trench structures 21.
  • the first trench structures 21 may be referred to as "trench gate structures.”
  • the plurality of first trench structures 21 penetrate the channel region 20 to reach the drift region 12.
  • the plurality of first trench structures 21 are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of first trench structures 21 are arranged in a stripe shape extending in the second direction Y.
  • Each first trench structure 21 has one end on the boundary region 8 side and the other end on the outer periphery region 9 side in the longitudinal direction (second direction Y).
  • One end and the other end of the multiple first trench structures 21 are mechanically and electrically connected to the trench isolation structure 15.
  • the multiple first trench structures 21, together with the trench isolation structure 15, form a ladder-shaped trench structure.
  • the connection portion between the first trench structure 21 and the trench isolation structure 15 may be considered as part of the trench isolation structure 15 and/or part of the first trench structure 21.
  • the spacing between the multiple first trench structures 21 is preferably less than the width of the street region 11.
  • the width of the first trench structure 21 is preferably less than the width of the street region 11.
  • the width of the first trench structure 21 is the width in a direction perpendicular to the direction in which the first trench structure 21 extends.
  • the width of the first trench structure 21 may be 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the width of the first trench structure 21 is preferably 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the width of the first trench structure 21 is 0.4 ⁇ m or more and 0.7 ⁇ m or less. It is preferable that the width of the first trench structure 21 is approximately equal to the width of the trench isolation structure 15.
  • the first trench structure 21 may have a depth of 1 ⁇ m or more and 20 ⁇ m or less. It is preferable that the depth of the first trench structure 21 is 4 ⁇ m or more and 10 ⁇ m or less. It is preferable that the depth of the first trench structure 21 is approximately equal to the depth of the trench isolation structure 15.
  • the first trench structure 21 includes a first trench 22, a first insulating film 23, and a first buried electrode 24.
  • the first trench 22 is formed in the first main surface 3 and defines the wall surface of the first trench structure 21.
  • the first trench 22 communicates with the isolation trench 16 at both ends in the second direction Y.
  • the sidewall of the first trench 22 communicates with the sidewall of the isolation trench 16, and the bottom wall of the first trench 22 communicates with the bottom wall of the isolation trench 16.
  • the first insulating film 23 covers the wall surface of the first trench 22 in a film-like manner.
  • the first insulating film 23 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. It is preferable that the first insulating film 23 has a single-layer structure consisting of a single insulating film.
  • the first insulating film 23 includes a silicon oxide film made of an oxide of the chip 2.
  • the first insulating film 23 is made of the same insulating film as the isolation insulating film 17.
  • the first insulating film 23 is connected to the isolation insulating film 17 at the communicating portion between the isolation trench 16 and the first trench 22.
  • the first buried electrode 24 is buried in the first trench 22 with the first insulating film 23 sandwiched therebetween.
  • the first buried electrode 24 may contain conductive polysilicon.
  • a gate potential is applied to the first buried electrode 24.
  • the first buried electrode 24 is mechanically and electrically connected to the isolated buried electrode 18 at the communicating portion between the isolation trench 16 and the first trench 22.
  • the semiconductor device 1A includes a plurality of second trench structures 25 formed in the regions between adjacent first trench structures 21 in the first main surface 3 of the first active region 6A.
  • the second trench structures 25 may be referred to as "emitter trench structures.”
  • Each second trench structure 25 is formed at a distance from the plurality of first trench structures 21 in the first direction X in a plan view, and is formed in a square ring shape extending in the second direction Y.
  • the width of the second trench structure 25 is preferably less than the width of the street region 11.
  • the width of the second trench structure 25 is the width in a direction perpendicular to the direction in which the second trench structure 25 extends.
  • the width of the second trench structure 25 may be 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the width of the second trench structure 25 is preferably 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the width of the second trench structure 25 is particularly preferably 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the width of the second trench structure 25 is preferably approximately equal to the width of the first trench structure 21.
  • the second trench structure 25 may have a depth of 1 ⁇ m or more and 20 ⁇ m or less.
  • the depth of the second trench structure 25 is preferably 4 ⁇ m or more and 10 ⁇ m or less.
  • the depth of the second trench structure 25 is preferably approximately equal to the depth of the first trench structure 21.
  • the second trench structure 25 includes a second trench 26, a second insulating film 27, and a second buried electrode 28.
  • the second trench 26 is formed in the first main surface 3 and defines the wall surface of the second trench structure 25.
  • the second insulating film 27 covers the wall surface of the second trench 26 in a film-like manner.
  • the second insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. It is preferable that the second insulating film 27 has a single-layer structure made of a single insulating film. It is particularly preferable that the second insulating film 27 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the second insulating film 27 is made of the same insulating film as the first insulating film 23.
  • the second buried electrode 28 is buried in the second trench 26 with the second insulating film 27 sandwiched therebetween.
  • the second buried electrode 28 may include conductive polysilicon.
  • An emitter potential is applied to the second buried electrode 28.
  • the semiconductor device 1A includes a plurality of n-type emitter regions 29 formed in a surface layer portion of the channel region 20 in the first active region 6A.
  • the plurality of emitter regions 29 each have a higher n-type impurity concentration than the drift region 12.
  • the plurality of emitter regions 29 are formed on both sides of the plurality of first trench structures 21, respectively.
  • the n-type impurity concentration of the emitter regions 29 is preferably, for example, not less than 1.0 ⁇ 10 19 cm ⁇ 3 and not more than 1.0 ⁇ 10 21 cm ⁇ 3 .
  • the multiple emitter regions 29 are each formed in a band shape extending along the multiple first trench structures 21 in a planar view.
  • the multiple emitter regions 29 may be formed at intervals along the multiple first trench structures 21 in a planar view.
  • the multiple emitter regions 29 are formed in the region between the first trench structure 21 and the second trench structure 25 so as to be connected to the first trench structure 21 and the second trench structure 25. It is preferable that the emitter regions 29 are not formed in the region between the trench isolation structure 15 and the outermost second trench structure 25.
  • the semiconductor device 1A includes a plurality of contact holes 30 formed in the first main surface 3 so as to expose the emitter region 29 in the first active region 6A.
  • the plurality of contact holes 30 are formed on both sides of the plurality of first trench structures 21 at intervals from the plurality of first trench structures 21.
  • the plurality of contact holes 30 may each be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.
  • the multiple contact holes 30 penetrate the emitter region 29 so as to reach the channel region 20.
  • the multiple contact holes 30 may be spaced away from the bottom of the emitter region 29 toward the first main surface 3 so as not to reach the channel region 20.
  • the multiple contact holes 30 are each formed in a band shape extending along the multiple first trench structures 21 in a plan view. In terms of the longitudinal direction (second direction Y), the multiple contact holes 30 are preferably shorter than the multiple first trench structures 21. It is particularly preferable that the multiple contact holes 30 are shorter than the multiple second trench structures 25.
  • the semiconductor device 1A includes a plurality of p-type channel contact regions 31 formed in a region different from the plurality of emitter regions 29 in the surface layer portion of the channel region 20 of the first active region 6A.
  • the plurality of channel contact regions 31 have a higher p-type impurity concentration than the channel region 20.
  • the plurality of channel contact regions 31 are each formed in a band shape extending along the corresponding contact hole 30 in a plan view.
  • the bottoms of the plurality of channel contact regions 31 are each formed in a region between the bottom wall of the corresponding contact hole 30 and the bottom of the channel region 20.
  • the p-type impurity concentration of the channel region 20 is preferably, for example, not less than 1.0 ⁇ 10 16 cm ⁇ 3 and not more than 1.0 ⁇ 10 18 cm ⁇ 3
  • the p-type impurity concentration of the channel contact region 31 is preferably, for example, not less than 1.0 ⁇ 10 18 cm ⁇ 3 and not more than 1.0 ⁇ 10 20 cm ⁇ 3 .
  • the semiconductor device 1A includes a plurality of p-type floating regions 32 formed in regions surrounded by a plurality of second trench structures 25 in the surface layer portion of the first main surface 3 of the first active region 6A.
  • the plurality of floating regions 32 are formed in an electrically floating state.
  • an emitter potential may be applied to the plurality of floating regions 32.
  • the plurality of floating regions 32 have a higher p-type impurity concentration than the channel region 20.
  • Each floating region 32 extends in a layer shape along the first main surface 3 and is connected to the inner peripheral wall of each second trench structure 25. It is preferable that each floating region 32 is formed deeper than the middle part of the depth range of the second trench structure 25. In this embodiment, each floating region 32 is formed deeper than the second trench structure 25 and has a portion that covers the bottom wall of the second trench structure 25.
  • the first active region 6A includes, as an IGBT structure Tr, a channel region 20, a plurality of first trench structures 21, a plurality of second trench structures 25, a plurality of emitter regions 29, a plurality of contact holes 30, a plurality of channel contact regions 31, and a plurality of floating regions 32.
  • the second active region 6B includes, as an IGBT structure Tr, a channel region 20, a plurality of first trench structures 21, a plurality of second trench structures 25, a plurality of emitter regions 29, a plurality of contact holes 30, a plurality of channel contact regions 31, and a plurality of floating regions 32.
  • the semiconductor device 1A includes a p-type boundary well region 40 formed in the surface layer of the first main surface 3 in the boundary region 8.
  • the boundary well region 40 has a higher p-type impurity concentration than the channel region 20.
  • the boundary well region 40 may have a lower p-type impurity concentration than the channel region 20.
  • the boundary well region 40 is formed in a band shape extending in the first direction X along the boundary region 8 in a plan view.
  • the boundary well region 40 is formed in a layer shape extending along the first main surface 3 in the region sandwiched between the first trench isolation structure 15A and the second trench isolation structure 15B, and is exposed from the first main surface 3.
  • the boundary well region 40 is formed in the region sandwiched between the multiple first trench structures 21 on the first active region 6A side and the multiple first trench structures 21 on the second active region 6B side.
  • the boundary well region 40 includes a first boundary well region 40A formed in the pad region 10, and a second boundary well region 40B formed in the street region 11.
  • the first boundary well region 40A has a relatively large region width in the second direction Y.
  • the first boundary well region 40A is formed in a polygonal shape (a square shape in this embodiment) in a plan view. It is preferable that the first boundary well region 40A is formed over the entire pad region 10.
  • the second boundary well region 40B has a width in the second direction Y that is smaller than the width of the first boundary well region 40A, and is pulled out in a strip from the first boundary well region 40A toward the street region 11.
  • the second boundary well region 40B is located on a straight line that crosses the center of the first main surface 3 in the first direction X.
  • the second boundary well region 40B extends in a strip so as to be located on one side (the third side surface 5C side) and the other side (the fourth side surface 5D side) of the straight line that crosses the center of the first main surface 3 in the second direction Y.
  • the boundary well region 40 is preferably formed deeper than the channel region 20. It is particularly preferable that the boundary well region 40 is formed deeper than the multiple trench isolation structures 15 (multiple first trench structures 21). In this embodiment, the boundary well region 40 has a width in the second direction Y that is greater than the width of the boundary region 8, and is pulled out from the boundary region 8 into the multiple active regions 6.
  • the boundary well region 40 is connected to a plurality of trench isolation structures 15 adjacent to each other in the second direction Y.
  • the boundary well region 40 has a portion that covers the bottom walls of the plurality of trench isolation structures 15.
  • the boundary well region 40 has a portion that crosses the plurality of trench isolation structures 15 and covers the bottom walls of the plurality of first trench structures 21.
  • the boundary well region 40 covers the sidewalls of the trench isolation structure 15 and the sidewalls of the trench structures in the active regions 6, and is connected to each channel region 20 in the surface portion of the first main surface 3.
  • the depth of the boundary well region 40 may be 1 ⁇ m or more and 20 ⁇ m or less.
  • the depth of the boundary well region 40 is preferably 5 ⁇ m or more and 10 ⁇ m or less.
  • the semiconductor device 1A includes a p-type peripheral well region 41 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the peripheral well region 41 has a higher p-type impurity concentration than the channel region 20.
  • the peripheral well region 41 may have a lower p-type impurity concentration than the channel region 20. It is preferable that the p-type impurity concentration of the peripheral well region 41 is approximately equal to the p-type impurity concentration of the boundary well region 40.
  • the peripheral well region 41 is formed in a layer extending along the first main surface 3 and is exposed from the first main surface 3.
  • the peripheral well region 41 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the peripheral well region 41 is formed in a band shape extending along the multiple active regions 6 in a planar view.
  • the peripheral well region 41 is formed in a ring shape (a square ring shape in this embodiment) that collectively surrounds the multiple active regions 6 in a planar view.
  • the peripheral well region 41 is preferably formed deeper than the channel region 20. It is particularly preferable that the peripheral well region 41 is formed deeper than the multiple trench isolation structures 15 (multiple first trench structures 21). The peripheral well region 41 preferably has a depth approximately equal to that of the boundary well region 40.
  • the peripheral well region 41 is connected to the multiple trench isolation structures 15.
  • the peripheral well region 41 has a portion that covers the bottom walls of the multiple trench isolation structures 15.
  • the peripheral well region 41 is pulled out from the peripheral region 9 into the multiple active regions 6.
  • the peripheral well region 41 has a portion that crosses the multiple trench isolation structures 15 and covers the bottom walls of the multiple first trench structures 21.
  • the peripheral well region 41 covers the sidewalls of the trench isolation structure 15 and the sidewalls of the multiple first trench structures 21 in each active region 6, and is connected to multiple channel regions 20 in the surface portion of the first main surface 3.
  • the peripheral well region 41 is connected to the boundary well region 40 at the connection portion of the boundary region 8 and the peripheral region 9. In other words, the peripheral well region 41, together with the boundary well region 40, defines multiple active regions 6.
  • semiconductor device 1A includes a plurality of p-type field limiting rings (FLR: Field Limiting Ring) 42 formed on the surface layer of first main surface 3 in peripheral region 9.
  • field limiting rings will be referred to as FLR42.
  • FLR42 are provided to reduce the concentration of an electric field at the outer end of the PN junction of semiconductor device 1A.
  • FLR42 may also be referred to as a "guard ring.”
  • the number of FLRs 42 is arbitrary and may be 2 to 20 (typically 3 to 10). In this embodiment, four FLRs 42 are provided. The multiple FLRs 42 are formed in an electrically floating state.
  • the multiple FLRs 42 are formed in a region between the periphery of the chip 2 and the peripheral well region 41, spaced apart from the periphery of the chip 2 and the peripheral well region 41.
  • the multiple FLRs 42 are formed in a band shape extending along the peripheral well region 41 in a plan view.
  • the multiple FLRs 42 are formed in a ring shape (square ring shape) surrounding the peripheral well region 41 in a plan view.
  • Each of the multiple FLRs 42 has a width smaller than the width of the peripheral well region 41.
  • the multiple FLRs 42 are preferably formed deeper than the channel region 20.
  • the multiple FLRs 42 may be formed at a depth approximately equal to that of the peripheral well region 41.
  • the multiple FLRs 42 may be formed shallower than the peripheral well region 41.
  • the multiple FLRs 2 may be formed at a constant depth.
  • Each FLR 42 has FLR curved portions 42A whose planar shape is an arc at the four corners 201-204. At each corner 201-204, the inner edges 42Aa and outer edges 42Ab of all FLR curved portions 42A may have the same center of curvature.
  • Each FLR 42 has FLR straight portions 42B whose planar shape is a straight line between the four corners 201-204.
  • Each FLR curve portion 42A has a double diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 having a lower p-type impurity concentration than the first diffusion region 301.
  • each FLR curved portion 42A is the inner edge of the first diffusion region 301 of that FLR curved portion 42A.
  • the outer edge 42Ab of each FLR curved portion 42A is the outer edge of the second diffusion region 302 of that FLR curved portion 42A.
  • a boundary line between the first diffusion region 301 and the second diffusion region 302 (hereinafter referred to as the "diffusion region boundary line BL") is formed in the middle of the width between the inner edge 42Aa and the outer edge 42Ab of the FLR curved portion 42A.
  • the diffusion region boundary line BL constitutes the outer edge of the first diffusion region 301 and the inner edge of the second diffusion region 302.
  • Each FLR straight portion 42B has a single diffusion structure consisting of only a diffusion region having the same second conductivity type impurity concentration as the first diffusion region 301.
  • the spacing between the multiple FLR straight line portions 42B is constant between the four corner portions 201-204, and the widths of the multiple FLR straight line portions 42B are the same. Furthermore, the spacing between the multiple FLR curved portions 42A is constant between the four corner portions 201-204, and the widths of the multiple FLR curved portions 42A are the same. Furthermore, the widths of the first diffusion regions 301 of the multiple FLR curved portions 42A are the same between the four corner portions 201-204, and the widths of the second diffusion regions 302 of the multiple FLR curved portions 42A are the same. Furthermore, the width of the first diffusion region 301 of each FLR curved portion 42A is the same as the width of each FLR straight line portion 42B.
  • the inner edge 42Aa and the outer edge 42Ab of all the FLR curved portions 42A have the same center of curvature in each of the corners 201-204.
  • the centers of curvature of the inner edge 42Aa and the outer edge BL of the first diffusion region 301 and the inner edge BL and the outer edge 42Ab of the second diffusion region 302 in each of the FLR curved portions 42A are located on a dividing line, which is a straight line that divides the apex angle of the corner in half.
  • the spacing between the multiple FLR straight line portions 42B does not have to be constant between the four corner portions 201-204. Furthermore, the widths of the multiple FLR straight line portions 42B may differ between the four corner portions 201-204. Furthermore, the spacing between the multiple FLR curved portions 42A does not have to be constant between the four corner portions 201-204. Furthermore, the widths of the multiple FLR curved portions 42A may differ between the four corner portions 201-204. Furthermore, the widths of the first diffusion regions 301 of the multiple FLR curved portions 42A may differ between the multiple FLR curved portions 42A. Furthermore, the widths of the second diffusion regions 302 of the multiple FLR curved portions 42A may differ between the multiple FLR curved portions 42A.
  • the inner edges 42Aa and outer edges 42Ab of all of the FLR curved portions 42A do not have to have the same center of curvature. Furthermore, in each of the corners 201-204, the centers of curvature of the inner edges 42Aa and outer edges BL of the first diffusion region 301 and the inner edges BL and outer edges 42Ab of the second diffusion region 302 in each of the FLR curved portions 42A do not have to be located on a dividing line that is a straight line that divides the apex angle of the corner in half.
  • the width of the second diffusion region 302 in each FLR curve portion 42A is narrower than the width of the first diffusion region 301.
  • the width of the second diffusion region 302 in each FLR curve portion 42A may be wider than the width of the first diffusion region 301.
  • the width of the second diffusion region 302 in each FLR curve portion 42A may be the same as the width of the first diffusion region 301.
  • the depth of the second diffusion region 302 in each FLR curve portion 42A is the same as the depth of the first diffusion region 301.
  • the depth of the second diffusion region 302 in each FLR curve portion 42A may be different from the depth of the first diffusion region 301.
  • the depth of the second diffusion region 302 in each FLR curve portion 42A may be deeper than the depth of the first diffusion region 301.
  • the FLR 42 is formed linearly in a planar view in the area between the corners 201-204, whereas the FLR 42 is formed curvedly in a planar view in the area between the corners 201-204. For this reason, electric field concentration is more likely to occur in the corners 201-204 where the FLR curved portion 42A exists, compared to the area between the corners where the FLR straight portion 42B exists in the outer peripheral region 9. As a result, the breakdown voltage (BV) of the corners 201-204 in the outer peripheral region 9 is lower than the area between the corners in the outer peripheral region 9.
  • the multiple FLR curve portions 42A of each corner portion 201-204 have a double diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 having a lower p-type impurity concentration than the first diffusion region 301. This makes it possible to smooth the equipotential surface at each corner portion 201-204, thereby mitigating electric field concentration at each corner portion 201-204. This makes it possible to increase the breakdown voltage of the corner portions 201-204.
  • the semiconductor device 1A includes a channel stop region 43 formed in the surface layer of the first main surface 3 at a distance from the multiple FLRs 42 toward the periphery of the chip 2 in the peripheral region 9.
  • the channel stop region 43 has a higher n-type impurity concentration than the drift region 12.
  • Such a channel stop region 43 can be formed simultaneously with the emitter region 29, for example, in the process of forming the emitter region 29.
  • the channel stop region 43 is formed in a band shape extending along the periphery of the chip 2 in a plan view.
  • the channel stop region 43 is formed in a ring shape (quadratic ring shape) surrounding the multiple FLRs 42 in a plan view.
  • the channel stop region 43 may be exposed from the first to fourth side faces 5A to 5D.
  • the channel stop region 43 is formed in an electrically floating state.
  • the semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3.
  • the main surface insulating film 45 selectively covers the first main surface 3 in the active region 6, the boundary region 8, and the peripheral region 9.
  • the main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.
  • the main surface insulating film 45 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 45 is made of the same insulating film as the first insulating film 23 (isolation insulating film 17). The main surface insulating film 45 covers the first main surface 3 so as to expose the trench isolation structure 15, the first trench structure 21, and the second trench structure 25.
  • the main surface insulating film 45 is connected to the isolation insulating film 17, the first insulating film 23, and the second insulating film 27, and exposes the isolation buried electrode 18, the first buried electrode 24, and the second buried electrode 28.
  • the main surface insulating film 45 selectively covers the boundary well region 40, the peripheral well region 41, the FLR 42, and the channel stop region 43 in the boundary region 8 and the peripheral region 9.
  • the semiconductor device 1A includes a plurality of emitter electrode films 47 arranged on the first main surface 3 so as to cover the plurality of second trench structures 25 in the active region 6.
  • the plurality of emitter electrode films 47 are arranged on the main surface insulating film 45.
  • the plurality of emitter electrode films 47 may include conductive polysilicon.
  • the multiple emitter electrode films 47 cover both ends of the multiple second trench structures 25 in the second direction Y.
  • the multiple emitter electrode films 47 are formed in strips extending in the second direction Y in the region between the corresponding second trench structures 25 and trench isolation structures 15.
  • the multiple emitter electrode films 47 are formed at intervals from the trench isolation structures 15 toward the second trench structures 25.
  • the multiple emitter electrode films 47 face the channel region 20 with the main surface insulating film 45 in between.
  • the multiple emitter electrode films 47 are each formed integrally with the second buried electrodes 28 of the multiple second trench structures 25.
  • the multiple emitter electrode films 47 are each made up of a portion of the second buried electrode 28 that is pulled out in a film-like form onto the first main surface 3 (main surface insulating film 45).
  • the multiple emitter electrode films 47 may also be formed separately from the second buried electrodes 28.
  • FIG. 11 is an enlarged plan view showing the pad region 10.
  • FIG. 12 is an enlarged plan view showing the gate resistance structure 50 shown in FIG. 11.
  • FIG. 13 is an enlarged plan view showing the inner part of the gate resistance structure 50 shown in FIG. 12.
  • FIG. 14 is an enlarged plan view showing one end of the gate resistance structure 50 shown in FIG. 12.
  • FIG. 15 is an enlarged plan view showing the other end of the gate resistance structure 50 shown in FIG. 12.
  • FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 13.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 13.
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 13.
  • FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 13.
  • FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 14.
  • FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 15.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 12.
  • FIG. 23 is a plan view showing the layout of the resistance film 60, gate electrode film 64, and gate wiring film 65.
  • FIG. 24 is an electrical circuit diagram showing the gate resistance structure 50, gate terminal electrode 90, and gate wiring electrode 93.
  • the semiconductor device 1A includes a gate resistance structure 50 formed in the pad region 10.
  • the gate resistance structure 50 constitutes a gate resistance RG for the gate of the IGBT (first trench structure 21 of the IGBT structure Tr).
  • the gate resistance structure 50 includes a plurality of trench resistance structures 51 formed on the first main surface 3 in the pad region 10. A gate potential is applied to the plurality of trench resistance structures 51, but the plurality of trench resistance structures 51 do not contribute to channel control.
  • the multiple gate resistance structures 50 constitute a first trench group 52 and a second trench group 53.
  • the first trench group 52 includes multiple first trench resistance structures 51A that constitute part of the multiple trench resistance structures 51, and is provided on one side in the second direction Y (the first side surface 5A side).
  • the number of first trench resistance structures 51A is arbitrary and is adjusted based on the resistance value to be achieved.
  • the first trench group 52 may include 2 to 100 first trench resistance structures 51A.
  • the number of first trench resistance structures 51A is preferably 50 or less.
  • the number of first trench resistance structures 51A may be 25 or less.
  • the number of first trench resistance structures 51A is preferably 5 or more.
  • the gate resistance structure 50 may include a single first trench resistance structure 51A instead of the first trench group 52.
  • the first trench group 52 is provided in a region on one side (first side surface 5A) in the second direction Y with respect to a straight line that crosses the center of the first main surface 3 in the first direction X.
  • the first trench group 52 is preferably arranged in the pad region 10 so as to be biased toward the active region 6 (street region 11) rather than the peripheral region 9.
  • the first trench group 52 is arranged at intervals from the center of the pad region 10 toward the active region 6 (street region 11).
  • the multiple first trench resistance structures 51A are formed on the first main surface 3 at intervals from the multiple trench isolation structures 15 (multiple first trench structures 21).
  • the multiple first trench resistance structures 51A are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the multiple first trench resistance structures 51A are arranged in a stripe shape extending in the second direction Y.
  • the multiple first trench resistance structures 51A have one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).
  • the multiple first trench resistance structures 51A are formed at intervals from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3 so as to be located within the boundary well region 40 (first boundary well region 40A), and face the drift region 12 across a portion of the boundary well region 40. In other words, the multiple first trench resistance structures 51A do not penetrate the boundary well region 40 (first boundary well region 40A).
  • the spacing between the multiple first trench resistance structures 51A is preferably less than the width of the street region 11.
  • the spacing between the multiple first trench resistance structures 51A is preferably approximately equal to the spacing between the first trench structure 21 and the second trench structure 25.
  • the spacing between the multiple first trench resistance structures 51A may be smaller than the spacing between the first trench structure 21 and the second trench structure 25.
  • the spacing between the multiple first trench resistance structures 51A may be larger than the spacing between the first trench structure 21 and the second trench structure 25.
  • the width of the first trench resistance structure 51A is preferably less than the width of the street region 11.
  • the width of the first trench resistance structure 51A is the width in a direction perpendicular to the direction in which the first trench resistance structure 51A extends.
  • the width of the first trench resistance structure 51A may be 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the width of the first trench resistance structure 51A is preferably 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the width of the first trench resistance structure 51A is 0.4 ⁇ m or more and 0.7 ⁇ m or less. It is preferable that the width of the first trench resistance structure 51A is approximately equal to the width of the first trench structure 21.
  • the first trench resistance structure 51A may have a depth of 1 ⁇ m or more and 20 ⁇ m or less. It is preferable that the depth of the first trench resistance structure 51A is 4 ⁇ m or more and 10 ⁇ m or less. It is preferable that the depth of the first trench resistance structure 51A is approximately equal to the depth of the first trench structure 21.
  • the second trench group 53 includes a plurality of second trench resistance structures 51B that form part of the plurality of trench resistance structures 51, and are spaced apart from the first trench group 52 on the other side in the second direction Y (the second side surface 5B side).
  • the number of second trench resistance structures 51B is arbitrary and is adjusted based on the resistance value to be achieved. For example, when a resistance value approximately equal to the resistance value on the first trench group 52 side is to be realized, the second trench group 53 may include the same number of second trench resistance structures 51B as the number of first trench resistance structures 51A.
  • the second trench group 53 may include a number of second trench resistance structures 51B different from the number of first trench resistance structures 51A.
  • the number of second trench resistance structures 51B may be less than the number of first trench resistance structures 51A.
  • the number of second trench resistance structures 51B may be greater than the number of first trench resistance structures 51A.
  • the second trench group 53 may include 2 to 100 second trench resistance structures 51B.
  • the number of second trench resistance structures 51B is preferably 50 or less.
  • the number of second trench resistance structures 51B may be 25 or less.
  • the number of second trench resistance structures 51B is preferably 5 or more.
  • the semiconductor device 1A may include a single second trench resistance structure 51B instead of the second trench group 53.
  • the second trench group 53 is provided in a region on the other side (second side surface 5B) in the second direction Y with respect to a straight line that crosses the center of the first main surface 3 in the first direction X.
  • the second trench group 53 faces the first trench group 52 in the second direction Y.
  • the second trench group 53 is preferably arranged so as to be biased toward the active region 6 side (street region 11 side) rather than the outer periphery region 9 in the pad region 10.
  • the second trench group 53 is arranged at intervals from the center of the pad region 10 toward the active region 6 side (street region 11 side).
  • the second trench resistance structures 51B are formed on the first main surface 3 at intervals from the trench isolation structures 15 (the first trench structures 21).
  • the second trench resistance structures 51B are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y.
  • the multiple second trench resistance structures 51B are arranged in a stripe pattern extending in the second direction Y.
  • the multiple second trench resistance structures 51B each face the multiple first trench resistance structures 51A in a one-to-one correspondence in the second direction Y.
  • the multiple second trench resistance structures 51B are each arranged in the same straight line as the multiple first trench resistance structures 51A.
  • the multiple second trench resistance structures 51B each have one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).
  • the second trench resistance structures 51B are formed at intervals from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3 so as to be located within the boundary well region 40 (first boundary well region 40A), and face the drift region 12 across a portion of the boundary well region 40. In other words, the second trench resistance structures 51B do not penetrate the boundary well region 40 (first boundary well region 40A).
  • the spacing between the multiple second trench resistance structures 51B is preferably less than the width of the street region 11.
  • the spacing between the multiple second trench resistance structures 51B is preferably approximately equal to the spacing between adjacent first trench structures 21 and second trench structures 25.
  • the spacing between the multiple second trench resistance structures 51B may be smaller than the spacing between the first trench structures 21 and second trench structures 25.
  • the spacing between the multiple second trench resistance structures 51B may be larger than the spacing between the first trench structures 21 and second trench structures 25.
  • the spacing between the multiple second trench resistance structures 51B may be smaller than the spacing between the multiple first trench resistance structures 51A.
  • the spacing between the multiple second trench resistance structures 51B may be larger than the spacing between the multiple first trench resistance structures 51A. It is preferable that the spacing between the multiple second trench resistance structures 51B is approximately equal to the spacing between the multiple first trench resistance structures 51A.
  • the width of the second trench resistance structure 51B is preferably less than the width of the street region 11.
  • the width of the second trench resistance structure 51B is the width in a direction perpendicular to the direction in which the second trench resistance structure 51B extends.
  • the width of the second trench resistance structure 51B may be 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the width of the second trench resistance structure 51B is preferably 0.3 ⁇ m or more and 1 ⁇ m or less. It is particularly preferable that the width of the second trench resistance structure 51B is 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the width of the second trench resistance structure 51B is preferably approximately equal to the width of the first trench resistance structure 51A.
  • the second trench resistance structure 51B has a length in the second direction Y that is approximately equal to the length of the first trench resistance structure 51A.
  • the second trench resistance structure 51B may be longer than the first trench resistance structure 51A in the second direction Y.
  • the second trench resistance structure 51B may be shorter than the first trench resistance structure 51A in the second direction Y. The length of the first trench resistance structure 51A and the length of the second trench resistance structure 51B are adjusted according to the resistance value to be achieved.
  • the second trench resistance structure 51B may have a depth of 1 ⁇ m or more and 20 ⁇ m or less.
  • the depth of the second trench resistance structure 51B is preferably 4 ⁇ m or more and 10 ⁇ m or less.
  • the depth of the second trench resistance structure 51B is preferably approximately equal to the depth of the first trench resistance structure 51A (first trench structure 21).
  • the trench resistance structure 51 includes a resistive trench 54, a resistive insulating film 55, and a resistive buried electrode 56.
  • the resistive trench 54 is formed in the first main surface 3, and defines the wall surface of the trench resistance structure 51.
  • the resistive insulating film 55 covers the wall surface of the resistive trench 54 in the form of a film.
  • the resistive insulating film 55 is connected to the main surface insulating film 45 on the first main surface 3.
  • the resistive insulating film 55 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. It is preferable that the resistive insulating film 55 has a single-layer structure made of a single insulating film. It is particularly preferable that the resistive insulating film 55 includes a silicon oxide film made of an oxide of the chip 2.
  • the resistor-buried electrode 56 is buried in the resistor trench 54 with a resistor insulating film 55 sandwiched therebetween.
  • the resistor-buried electrode 56 may contain conductive polysilicon. A gate potential is applied to the resistor-buried electrode 56.
  • the gate resistor structure 50 includes a space region 57 defined in the pad region 10 between the first trench group 52 and the second trench group 53.
  • the space region 57 is formed by a flat portion of the first main surface 3 in the region between the other ends of the multiple first trench resistor structures 51A and one ends of the multiple second trench resistor structures 51B.
  • the space region 57 is partitioned into a rectangular shape in a plan view.
  • the space region 57 exposes the boundary well region 40 from the first main surface 3.
  • the space region 57 is formed on a straight line that crosses the center of the first main surface 3 in the first direction X in a plan view, and faces the street region 11 in the first direction X.
  • the space region 57 has a space width along the second direction Y.
  • the space width is larger than the width in the first direction X of the first trench resistance structure 51A (second trench resistance structure 51B).
  • the space width is larger than the distance between two first trench resistance structures 51A (second trench resistance structures 51B) adjacent to each other in the first direction X.
  • the space width is preferably larger than the width in the first direction X of the first trench group 52 (second trench group 53).
  • the space width may be smaller than the width in the first direction X of the first trench group 52 (second trench group 53).
  • the space width is preferably smaller than the length in the second direction Y of the first trench group 52 (second trench group 53).
  • the space width may be approximately equal to the width in the second direction Y of the street region 11.
  • the space width may be larger than the width in the second direction Y of the street region 11.
  • the space width may be smaller than the width in the second direction Y of the street region 11.
  • the gate resistor structure 50 includes a resistive film 60 arranged on the first main surface 3 so as to cover the multiple trench resistor structures 51 in the pad region 10. Specifically, the resistive film 60 is arranged on the main surface insulating film 45.
  • the resistive film 60 includes at least one of a conductive polysilicon film and an alloy film.
  • the alloy film may include alloy crystals composed of metallic elements and non-metallic elements.
  • the alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.
  • the resistive film 60 includes conductive polysilicon.
  • the thickness of the resistive film 60 is adjusted as appropriate depending on the resistance value to be achieved. It is preferable that the thickness of the resistive film 60 is equal to or less than the depth of the first trench resistance structure 51A (second trench resistance structure 51B). It is particularly preferable that the thickness of the resistive film 60 is less than the depth of the first trench resistance structure 51A (second trench resistance structure 51B).
  • the thickness of the resistive film 60 is preferably 0.5 times or more the width of the first trench resistance structure 51A (second trench resistance structure 51B).
  • the thickness of the resistive film 60 may be 0.05 ⁇ m or more and 2.5 ⁇ m or less.
  • the thickness of the resistive film 60 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the thickness of the resistive film 60 may be 0.1 nm or more and 100 nm or less.
  • the resistive film 60 is formed in a band shape extending in the second direction Y, and has a first end 60A on one side in the second direction Y (the first side surface 5A side) and a second end 60B on the other side in the second direction Y (the second side surface 5B side).
  • the resistive film 60 has a width in the first direction X that is greater than the width in the first direction X of the first trench group 52 (second trench group 53).
  • the width of the resistive film 60 may be less than the space width. Of course, the width of the resistive film 60 may be greater than or equal to the space width. It is preferable that the resistive film 60 has a uniform width in the first direction X.
  • the resistive film 60 has a portion located on one side (first side surface 5A side) and a portion located on the other side (second side surface 5B side) in the second direction Y with respect to a line that crosses the center of the first main surface 3 in the first direction X.
  • the resistive film 60 faces the first active region 6A, the second active region 6B, and the street region 11 in the first direction X.
  • the resistive film 60 faces the multiple trench isolation structures 15, the multiple first trench structures 21, and the multiple second trench structures 25 in the first direction X.
  • the resistive film 60 has a first covering portion 61 covering the space region 57, a second covering portion 62 covering the first trench group 52, and a third covering portion 63 covering the second trench group 53.
  • the first covering portion 61 is a portion that covers the first main surface 3 in the area outside the first trench group 52 (plurality of first trench resistance structures 51A) and the second trench group 53 (plurality of second trench resistance structures 51B).
  • the first covering portion 61 is located in the middle between the first end portion 60A and the second end portion 60B, and faces the boundary well region 40 across the main surface insulating film 45 in the thickness direction.
  • the second covering portion 62 forms the first end 60A of the resistive film 60 and covers all of the first trench resistance structures 51A.
  • the second covering portion 62 forms the first end 60A on the outer side (the peripheral edge side of the pad region 10) of one end of the multiple first trench resistance structures 51A.
  • the first end 60A faces the first covering portion 61 across the first trench group 52 in a plan view.
  • the second covering portion 62 is connected to the resistor-embedded electrodes 56 of the multiple first trench resistance structures 51A and faces the boundary well region 40 across the main surface insulating film 45 in the thickness direction.
  • the third covering portion 63 forms the second end portion 60B of the resistive film 60 and covers all the second trench resistance structures 51B.
  • the third covering portion 63 forms the second end portion 60B on the outer side (the peripheral side of the pad region 10) of the other ends of the multiple second trench resistance structures 51B.
  • the second end portion 60B faces the first covering portion 61 across the second trench group 53 in a plan view.
  • the third covering portion 63 is connected to the resistor-embedded electrodes 56 of the multiple second trench resistance structures 51B and faces the boundary well region 40 across the main surface insulating film 45 in the thickness direction.
  • the resistive film 60 is formed integrally with the resistor-buried electrodes 56 of the multiple first trench resistor structures 51A in the second covering portion 62, and is formed integrally with the resistor-buried electrodes 56 of the multiple second trench resistor structures 51B in the third covering portion 63.
  • the resistive film 60 is formed by a portion of the resistor-buried electrode 56 that is extended in the form of a film onto the first main surface 3 (main surface insulating film 45).
  • the resistive film 60 may be formed separately from the resistor-buried electrode 56.
  • the semiconductor device 1A includes a gate electrode film 64 disposed on the first main surface 3 so as to be adjacent to the resistive film 60. Specifically, the gate electrode film 64 is disposed on the main surface insulating film 45.
  • the gate electrode film 64 includes at least one of a conductive polysilicon film and an alloy film.
  • the alloy film may include alloy crystals composed of a metallic element and a non-metallic element.
  • the alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.
  • the gate electrode film 64 is preferably formed of the same resistive material as the resistive film 60. In this embodiment, the gate electrode film 64 includes conductive polysilicon. The gate electrode film 64 preferably has a thickness approximately equal to that of the resistive film 60.
  • the gate electrode film 64 is disposed on the main surface insulating film 45 at a distance from the resistive film 60 toward the inner side of the pad region 10 (the third side surface 5C side), and is physically separated from the resistive film 60.
  • the gate electrode film 64 is formed at a distance from the multiple trench isolation structures 15 toward the inner side of the pad region 10 in a plan view.
  • the gate electrode film 64 faces the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45.
  • the gate electrode film 64 is formed in a polygonal shape (a quadrangular shape in this embodiment) in a plan view. In this embodiment, the gate electrode film 64 is formed in a rectangular shape extending in the second direction Y along the resistive film 60.
  • the semiconductor device 1A includes a gate wiring film 65 arranged on the first main surface 3 adjacent to the resistive film 60 so as to face the gate electrode film 64 with the resistive film 60 in between.
  • the gate wiring film 65 is arranged on the main surface insulating film 45.
  • the gate wiring film 65 includes at least one of a conductive polysilicon film and an alloy film.
  • the alloy film may include alloy crystals composed of a metallic element and a non-metallic element.
  • the alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.
  • the gate wiring film 65 is preferably formed of the same resistive material as the resistive film 60. In this embodiment, the gate wiring film 65 includes conductive polysilicon. The gate wiring film 65 preferably has a thickness approximately equal to that of the resistive film 60.
  • the gate wiring film 65 is disposed on the main surface insulating film 45 at a distance from the gate electrode film 64, and is physically separated from the gate electrode film 64.
  • the gate wiring film 65 has a first connection portion connected to the first end 60A of the resistive film 60, and a second connection portion connected to the second end 60B of the resistive film 60.
  • the gate wiring film 65 is electrically connected to the multiple trench resistance structures 51 via the resistive film 60. Specifically, the gate wiring film 65 is electrically connected to the multiple first trench resistance structures 51A between the first covering portion 61 and the second covering portion 62 of the resistive film 60, and is electrically connected to the multiple second trench resistance structures 51B between the first covering portion 61 and the third covering portion 63 of the resistive film 60.
  • the gate wiring film 65 includes a first lower wiring portion 66, a second lower wiring portion 67, and a third lower wiring portion 68.
  • the first lower wiring portion 66 is routed to the pad region 10. Specifically, the first lower wiring portion 66 surrounds the resistive film 60 and the gate electrode film 64 in the pad region 10 from multiple directions (three directions in this embodiment).
  • the first lower wiring portion 66 includes a first lower line portion 69 and multiple second lower line portions 70A, 70B.
  • the first lower line portion 69 is arranged on the street region 11 side of the resistive film 60 in the pad region 10.
  • the first lower line portion 69 is arranged on the first main surface 3 adjacent to the resistive film 60 so as to face the gate electrode film 64 across the resistive film 60 in a plan view.
  • the first lower line portion 69 faces the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45 in the thickness direction.
  • the first lower line portion 69 is formed in a band shape extending in the second direction Y along the resistive film 60.
  • the first lower line portion 69 has a length in the second direction Y that is greater than the length of the resistive film 60 and the length of the gate electrode film 64.
  • the first lower line portion 69 has one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).
  • the multiple second lower line portions 70A, 70B include a second lower line portion 70A on one side and a second lower line portion 70B on the other side.
  • the second lower line portion 70A is arranged in a region on one side (first side surface 5A side) of the resistive film 60 and the gate electrode film 64 in the pad region 10 in the second direction Y with respect to the resistive film 60 and the gate electrode film 64.
  • the second lower line portion 70B is arranged in a region on the other side (second side surface 5B side) of the resistive film 60 and the gate electrode film 64 in the pad region 10 in the second direction Y with respect to the resistive film 60 and the gate electrode film 64.
  • the second lower line portion 70A is formed in a band shape extending in the first direction X, and has one end connected to one end of the first lower line portion 69, and the other end located on the peripheral side (third side surface 5C side) of the chip 2.
  • the second lower line portion 70A is further connected to the first end 60A of the resistive film 60, and is formed at a distance from the gate electrode film 64.
  • the second lower line portion 70A constitutes a first connection portion for the first end 60A.
  • the second lower line portion 70A faces the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45 in the thickness direction.
  • the second lower line portion 70B is formed in a band shape extending in the first direction X, and has one end connected to the other end of the first lower line portion 69, and the other end located on the peripheral side of the chip 2 (the third side surface 5C side).
  • the other side second lower line portion 70B is further connected to the second end 60B of the resistive film 60, and is formed at a distance from the gate electrode film 64.
  • the second lower line portion 70B constitutes a second connection portion for the first end portion 60A.
  • the other second lower line portion 70B faces the one second lower line portion 70A across the gate electrode film 64.
  • the other second lower line portion 70B faces the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45 in the thickness direction.
  • the second lower wiring portion 67 is routed to the street region 11. Specifically, the second lower wiring portion 67 is pulled out from the first lower wiring portion 66 to the street region 11. More specifically, the second lower wiring portion 67 is pulled out from the inner portion (the center portion in this embodiment) of the first lower line portion 69 to the street region 11, and is formed in a band shape extending in the first direction X.
  • the second lower wiring portion 67 crosses the center of the chip 2.
  • the second lower wiring portion 67 extends in a band shape so as to be located in an area on one side (the third side surface 5C side) and an area on the other side (the fourth side surface 5D side) of the first direction X with respect to a straight line that crosses the center of the first main surface 3 in the second direction Y.
  • the second lower wiring portion 67 has one end connected to the first lower line portion 69 (the first lower wiring portion 66) on one side of the first direction X, and the other end on the other side of the first direction X.
  • the second lower wiring portion 67 faces the boundary well region 40 (second boundary well region 40B) across the main surface insulating film 45 in the thickness direction.
  • the second lower wiring portion 67 has a width greater than the width of the street region 11 in the second direction Y, and is drawn out from the street region 11 to the multiple active regions 6.
  • the second lower wiring portion 67 covers the multiple trench isolation structures 15 in the multiple active regions 6.
  • the second lower wiring portion 67 also covers the ends of the first trench structures 21 in the active regions 6. As a result, the second lower wiring portion 67 is electrically connected to the isolated buried electrodes 18 and the first buried electrodes 24, and transmits the gate potential to the isolated buried electrodes 18 and the first buried electrodes 24.
  • the second lower wiring portion 67 is formed integrally with the multiple isolated buried electrodes 18 and the multiple first buried electrodes 24.
  • the second lower wiring portion 67 is composed of a portion of the multiple isolated buried electrodes 18 and a portion of the multiple first buried electrodes 24 that are pulled out in a film-like form onto the first main surface 3 (main surface insulating film 45).
  • the second lower wiring portion 67 may be formed separately from the multiple isolated buried electrodes 18 and the multiple first buried electrodes 24.
  • the third lower wiring portion 68 is routed to the outer peripheral region 9. Specifically, the third lower wiring portion 68 is pulled out from the first lower wiring portion 66 to the outer peripheral region 9. More specifically, the third lower wiring portion 68 is pulled out from the other ends of the multiple second lower line portions 70A, 70B to one side (first side surface 5A side) and the other side (second side surface 5B side) of the outer peripheral region 9, and is formed in a band shape extending along the outer peripheral region 9.
  • the third lower wiring portion 68 sandwiches multiple active regions 6.
  • the third lower wiring portion 68 extends along the periphery (first side surfaces 5A-5D) of the chip 2 so as to surround the multiple active regions 6 in a planar view, and is connected to the other end of the second lower wiring portion 67.
  • the third lower wiring portion 68, together with the second lower wiring portion 67 surrounds the multiple active regions 6.
  • the third lower wiring portion 68 faces the inner portion of the peripheral well region 41 across the main surface insulating film 45. Specifically, the third lower wiring portion 68 faces the inner portion of the peripheral well region 41 at a distance inward from the inner and outer edges of the peripheral well region 41 in a plan view.
  • the third lower wiring portion 68 has a plurality of lead-out portions 68a that are led out from the peripheral region 9 to the plurality of active regions 6 in the portion extending along the first side surface 5A.
  • the plurality of lead-out portions 68a cover the first trench isolation structure 15A on the first active region 6A side, and cover the second trench isolation structure 15B on the second active region 6B side.
  • the multiple drawers 68a cover the ends of the multiple first trench structures 21.
  • the third lower wiring portion 68 is electrically connected to the multiple isolated buried electrodes 18 and the multiple first buried electrodes 24 in the first active region 6A, and transmits the gate potential to the multiple isolated buried electrodes 18 and the multiple first buried electrodes 24.
  • a single pull-out portion 68a may be formed that extends in a strip along the first trench isolation structure 15A.
  • a single pull-out portion 68a may be formed that extends in a strip along the second trench isolation structure 15B.
  • the third lower wiring portion 68 is formed integrally with the multiple isolated buried electrodes 18 and the multiple first buried electrodes 24.
  • the third lower wiring portion 68 is composed of a portion of the multiple isolated buried electrodes 18 and a portion of the multiple first buried electrodes 24 that are pulled out in a film-like manner onto the first main surface 3 (main surface insulating film 45).
  • the third lower wiring portion 68 may be formed separately from the multiple isolated buried electrodes 18 and the multiple first buried electrodes 24.
  • the semiconductor device 1A includes a first slit 71 defined in a region between the resistive film 60 and the gate electrode film 64.
  • the first slit 71 is formed in a band shape extending in the second direction Y in a plan view, and defines the first to third covering portions 61 to 63 of the resistive film 60.
  • the first slit 71 exposes the main surface insulating film 45.
  • the first slit 71 is formed outward from the multiple trench resistance structures 51 in a plan view, and faces the boundary well region 40 (first boundary well region 40A) in the thickness direction. In other words, the first slit 71 does not face the trench resistance structures 51 in the thickness direction.
  • the first slit 71 has a first length in the second direction Y.
  • the first slit 71 is formed narrower than the gate electrode film 64 in the first direction X.
  • the first slit 71 is preferably formed narrower than the resistive film 60 in the first direction X.
  • the first slit 71 is preferably formed narrower than the first trench group 52 in the first direction X.
  • the first slit 71 is preferably formed wider than the trench resistive structure 51 in the first direction X.
  • the width of the first slit 71 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the first slit 71 may be 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 7.5 ⁇ m or less, or 7.5 ⁇ m or more and 10 ⁇ m or less.
  • the width of the first slit 71 is preferably 3 ⁇ m or more and 7 ⁇ m or less.
  • the semiconductor device 1A includes a second slit 72 defined in a region between the resistive film 60 and the gate wiring film 65.
  • the second slit 72 is defined in a region between the resistive film 60 and the first lower line portion 69.
  • the second slit 72 faces the first slit 71 across the resistive film 60.
  • the second slit 72 is formed in a band shape extending in the second direction Y in a plan view, and divides the first to third covering portions 61 to 63 of the resistive film 60.
  • the second slit 72 extends parallel to the first slit 71, and divides the resistive film 60 together with the first slit 71.
  • the second slit 72 exposes the main surface insulating film 45.
  • the second slits 72 are formed outward from the multiple trench resistance structures 51 in a plan view, and face the boundary well region 40 (first boundary well region 40A) in the thickness direction. In other words, the second slits 72 do not face the trench resistance structures 51 in the thickness direction.
  • the second slits 72 face the first slits 71 in a plan view, sandwiching the multiple first trench resistance structures 51A and the multiple second trench resistance structures 51B between them.
  • the second slit 72 has a second length in the second direction Y.
  • the second length may be different from the first length of the first slit 71. It is preferable that the second length is equal to or less than the first length from the viewpoint of properly connecting the resistive film 60 and the gate wiring film 65. In this embodiment, the second length is less than the first length. Of course, the second length may be approximately equal to the first length. Also, the second length may be greater than the first length.
  • the second slit 72 is formed narrower than the gate electrode film 64 in the first direction X.
  • the second slit 72 is preferably formed narrower than the first lower line portion 69 in the first direction X. It is particularly preferable that the second slit 72 is formed narrower than the resistance film 60 in the first direction X.
  • the second slit 72 is preferably formed narrower than the first trench group 52 in the first direction X.
  • the second slit 72 is preferably formed wider than the trench resistance structure 51.
  • the width of the second slit 72 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the second slit 72 may be 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 7.5 ⁇ m or less, or 7.5 ⁇ m or more and 10 ⁇ m or less.
  • the width of the second slit 72 is preferably 3 ⁇ m or more and 7 ⁇ m or less.
  • the width of the second slit 72 may be equal to or greater than the width of the first slit 71.
  • the width of the second slit 72 may be less than the width of the first slit 71.
  • the width of the second slit 72 may be approximately equal to the width of the first slit 71.
  • the semiconductor device 1A includes a plurality of third slits 73 defined in a region between the gate electrode film 64 and the gate wiring film 65.
  • the plurality of third slits 73 are each defined in a region between the gate electrode film 64 and the plurality of second lower line portions 70A, 70B.
  • the multiple third slits 73 are each formed in a band shape extending in the first direction X in a plan view, exposing the main surface insulating film 45.
  • the multiple third slits 73 are connected to the first slits 71, and face each other in the second direction Y with the gate electrode film 64 in between.
  • the multiple third slits 73, together with the first slits 71 partition the gate electrode film 64.
  • the multiple third slits 73, together with the first slits 71 physically and electrically separate the gate electrode film 64 from the gate wiring film 65.
  • the third slit 73 is formed narrower than the gate electrode film 64.
  • the third slit 73 is preferably formed narrower than the second lower line portions 70A, 70B. It is particularly preferable that the third slit 73 is formed narrower than the resistance film 60.
  • the third slit 73 is preferably formed narrower than the first trench group 52 (second trench group 53).
  • the third slit 73 is preferably formed wider than the trench resistance structure 51.
  • the width of the third slit 73 may be 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the third slit 73 may be 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 7.5 ⁇ m or less, or 7.5 ⁇ m or more and 10 ⁇ m or less.
  • the width of the third slit 73 is preferably 3 ⁇ m or more and 7 ⁇ m or less.
  • the width of the third slit 73 may be equal to or greater than the width of the first slit 71.
  • the width of the third slit 73 may be less than the width of the first slit 71.
  • the width of the third slit 73 may be approximately equal to the width of the first slit 71.
  • the semiconductor device 1A includes an interlayer insulating film 74 that covers the main surface insulating film 45.
  • the interlayer insulating film 74 is thicker than the main surface insulating film 45.
  • the interlayer insulating film 74 may have a single-layer structure made of a single insulating film, or a layered structure including multiple insulating films.
  • the interlayer insulating film 74 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.
  • the interlayer insulating film 74 may have a layered structure including multiple silicon oxide films.
  • the interlayer insulating film 74 may include at least one of an NSG (Non-doped Silicate Glass) film, a PSG (Phosphor Silicate Glass) film, and a BPSG (Boron Phosphor Silicate Glass) film, which are examples of silicon oxide films.
  • the NSG film, PSG film, and BPSG film may be layered in any order.
  • the interlayer insulating film 74 covers the main surface insulating film 45 in the active region 6, the boundary region 8, and the peripheral region 9.
  • the interlayer insulating film 74 covers the multiple trench isolation structures 15, the multiple first trench structures 21, and the multiple second trench structures 25 in the active region 6.
  • the interlayer insulating film 74 covers the trench resistor structures 51 (resistance buried electrodes 56), resistor film 60, gate electrode film 64, and gate wiring film 65 in the pad region 10.
  • the interlayer insulating film 74 covers the boundary well region 40 (first boundary well region 40A) in the pad region 10 with the main surface insulating film 45 in between.
  • the interlayer insulating film 74 selectively covers the peripheral well region 41, FLR 42, and channel stop region 43 with the main surface insulating film 45 in between.
  • the stacked film of the main surface insulating film 45 and the interlayer insulating film 74 is an example of an "insulating film" in this disclosure.
  • the interlayer insulating film 74 enters the first slit 71 from above the resistive film 60 and the gate electrode film 64, and has a portion that covers the main surface insulating film 45 within the first slit 71.
  • the interlayer insulating film 74 faces the boundary well region 40 (first boundary well region 40A) in the thickness direction within the first slit 71, sandwiching the main surface insulating film 45 therebetween.
  • the interlayer insulating film 74 electrically insulates the resistive film 60 and the gate electrode film 64 within the first slit 71.
  • the interlayer insulating film 74 enters the second slit 72 from above the resistive film 60 and the gate wiring film 65 (first lower line portion 69), and has a portion that covers the main surface insulating film 45 within the second slit 72.
  • the interlayer insulating film 74 faces the boundary well region 40 (first boundary well region 40A) in the thickness direction within the second slit 72, sandwiching the main surface insulating film 45 therebetween.
  • the interlayer insulating film 74 electrically insulates the resistive film 60 and the gate wiring film 65 (first lower line portion 69) within the second slit 72.
  • the interlayer insulating film 74 enters the third slits 73 from above the gate electrode film 64 and the gate wiring film 65 (second lower line portions 70A, 70B), and has a portion that covers the main surface insulating film 45 within the third slits 73.
  • the interlayer insulating film 74 faces the boundary well region 40 (first boundary well region 40A) in the thickness direction within the third slits 73, sandwiching the main surface insulating film 45 therebetween.
  • the interlayer insulating film 74 electrically insulates the gate electrode film 64 and the gate wiring film 65 within the multiple third slits 73.
  • the interlayer insulating film 74 has an insulating main surface 75 extending along the first main surface 3 (main surface insulating film 45).
  • the insulating main surface 75 has a first recess portion 76, a second recess portion 77, and multiple third recess portions 78 in the pad region 10 (see Figures 16 to 22).
  • the first recess portion 76 is formed in a portion that covers the first slit 71.
  • the first recess portion 76 is recessed toward the first slit 71, and is formed in a band shape extending in the second direction Y along the first slit 71 in a plan view.
  • the second recess portion 77 is formed in a portion covering the second slit 72.
  • the second recess portion 77 is recessed toward the second slit 72, and is formed in a band shape extending in the second direction Y along the second slit 72 in a plan view.
  • the multiple third recess portions 78 are each formed in a portion covering the multiple third slits 73.
  • the multiple third recess portions 78 are each recessed toward the corresponding third slit 73, and are each formed in a band shape extending in the first direction X along the corresponding third slit 73 in a plan view.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) first resistor connection electrodes 81 embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60.
  • the first resistor connection electrode 81 may be referred to as a "first resistor via electrode.”
  • the first resistor connection electrode 81 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the first resistor connection electrode 81 has a layered structure including a Ti film and a W film.
  • the multiple first resistor connection electrodes 81 are connected to the first covering portion 61 of the resistive film 60. That is, the multiple first resistor connection electrodes 81 are connected to a portion of the resistive film 60 that covers the area outside the multiple trench resistance structures 51. Specifically, the multiple first resistor connection electrodes 81 are connected to a portion of the resistive film 60 that covers the space region 57 between the first trench group 52 (multiple first trench resistance structures 51A) and the second trench group 53 (multiple second trench resistance structures 51B).
  • the multiple first resistor connection electrodes 81 are formed in a region spaced apart from the multiple trench resistor structures 51 in the second direction Y in a planar view, and do not face the multiple trench resistor structures 51 in the first direction X.
  • the multiple first resistor connection electrodes 81 are each formed in a band shape extending in the first direction X in a planar view, and are arranged at intervals in the second direction Y.
  • the multiple first resistor connection electrodes 81 are arranged in a stripe shape extending in the first direction X in a planar view.
  • the multiple first resistor connection electrodes 81 extend in a direction intersecting (orthogonal in this embodiment) the extension direction of the resistive film 60 (multiple trench resistor structures 51). In other words, the multiple first resistor connection electrodes 81 intersect (orthogonal) with the current direction of the resistive film 60. This allows the current to be appropriately spread from the multiple first resistor connection electrodes 81 to the resistive film 60. In other words, current constriction caused by the layout of the multiple first resistor connection electrodes 81 is suppressed, and undesired fluctuations (increases) in the resistance value caused by the current constriction are suppressed.
  • the multiple first resistor connection electrodes 81 face only the flat portion of the first main surface 3 across the resistive film 60, and do not face the trench resistor structure 51 across the resistive film 60.
  • the multiple first resistor connection electrodes 81 face the boundary well region 40 (first boundary well region 40A) across the resistive film 60 and the main surface insulating film 45.
  • the multiple first resistor connection electrodes 81 are formed in a region sandwiched between the first slit 71 and the second slit 72 and spaced apart from the first slit 71 and the second slit 72 in a plan view.
  • the multiple first resistor connection electrodes 81 are formed narrower than the resistive film 60 in the first direction X.
  • the multiple first resistor connection electrodes 81 face one or more first trench resistor structures 51A on one side in the second direction Y (first side surface 5A side), and face one or more second trench resistor structures 51B on the other side in the second direction Y (second side surface 5B side).
  • the multiple first resistor connection electrodes 81 only need to face at least two of the multiple first trench resistance structures 51A in the second direction Y, and do not need to face all of the first trench resistance structures 51A. In this embodiment, the multiple first resistor connection electrodes 81 face some of the multiple first trench resistance structures 51A in the second direction Y. Of course, the multiple first resistor connection electrodes 81 may face all of the first trench resistance structures 51A in the second direction Y.
  • the multiple first resistor connection electrodes 81 only need to face at least two of the multiple second trench resistance structures 51B in the second direction Y, and do not need to face all of the first trench resistance structures 51A. In this embodiment, the multiple first resistor connection electrodes 81 face some of the multiple second trench resistance structures 51B in the second direction Y. Of course, the multiple first resistor connection electrodes 81 may face all of the second trench resistance structures 51B in the second direction Y.
  • the multiple first resistor connection electrodes 81 have a first connection area S1 with respect to the resistive film 60.
  • the first connection area S1 is defined by the total planar area of the multiple first resistor connection electrodes 81.
  • the first connection area S1 is defined by the planar area of the single first resistor connection electrode 81.
  • the first connection area S1 is adjusted according to the first current I1 flowing through the first resistor connection electrode 81 (see FIG. 12).
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) second resistor connection electrodes 82 embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 at a location different from the first resistor connection electrode 81.
  • the second resistor connection electrode 82 may be referred to as a "second resistor via electrode.”
  • the second resistor connection electrode 82 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the second resistor connection electrode 82 has a layered structure including a Ti film and a W film.
  • the multiple second resistor connection electrodes 82 are connected to the second covering portion 62 of the resistive film 60.
  • the multiple second resistor connection electrodes 82 are embedded in the portion of the resistive film 60 that covers the first trench group 52 (the multiple first trench resistor structures 51A).
  • the multiple second resistor connection electrodes 82 form a first gate resistor R1 between the multiple first resistor connection electrodes 81.
  • the first gate resistor R1 is composed of the resistive film 60 and the multiple first trench resistor structures 51A in the region between the multiple first resistor connection electrodes 81 and the multiple second resistor connection electrodes 82.
  • the resistance value of the first gate resistor R1 is adjusted by the distance between the multiple first resistor connection electrodes 81 and the multiple second resistor connection electrodes 82.
  • the multiple second resistor connection electrodes 82 are formed in a region facing the multiple first trench resistor structures 51A in the first direction X in a planar view.
  • the multiple second resistor connection electrodes 82 extend in a direction different from the first resistor connection electrodes 81 in a planar view.
  • the multiple second resistor connection electrodes 82 are each formed in a band shape extending in the second direction Y in a planar view, and are arranged at intervals in the first direction X.
  • the multiple second resistor connection electrodes 82 are arranged in a stripe shape extending in the second direction Y in a planar view.
  • the second resistor connection electrodes 82 are each disposed in a region between adjacent first trench resistance structures 51A at a distance from the first trench resistance structures 51A in a plan view. In other words, the second resistor connection electrodes 82 are arranged alternately with the first trench resistance structures 51A in the first direction X.
  • the multiple second resistor connection electrodes 82 face only the flat portion of the first main surface 3 across the resistive film 60, and do not face the trench resistor structure 51 across the resistive film 60.
  • the multiple second resistor connection electrodes 82 face the boundary well region 40 (first boundary well region 40A) across the resistive film 60 and the main surface insulating film 45.
  • the second resistor connection electrodes 82 only need to be arranged in a portion of the region between the first trench resistance structures 51A, and do not necessarily need to be arranged in the entire region between the first trench resistance structures 51A.
  • the second resistor connection electrodes 82 only need to be arranged in at least one region located on the active region 6 side of the region between the first trench resistance structures 51A, and do not need to be arranged in at least one region located on the gate electrode film 64 side.
  • At least one of the multiple second resistor connection electrodes 82 faces the multiple first resistor connection electrodes 81 in the second direction Y in a plan view. In this case, it is preferable that at least one of the multiple second resistor connection electrodes 82 located on the gate electrode film 64 side faces the multiple first resistor connection electrodes 81 in the second direction Y.
  • At least one of the multiple second resistor connection electrodes 82 located on the active region 6 side does not have to face the multiple first resistor connection electrodes 81 in the second direction Y.
  • all of the second resistor connection electrodes 82 may be arranged to face the multiple first resistor connection electrodes 81 in the second direction Y.
  • the multiple second resistor connection electrodes 82 have a length in the second direction Y that is less than the length of the multiple first trench resistance structures 51A. It is preferable that the multiple second resistor connection electrodes 82 are arranged in a region on the other end side of the multiple first trench resistance structures 51A with respect to the longitudinal middle portion of the multiple first trench resistance structures 51A.
  • the length of the multiple second resistor connection electrodes 82 is preferably 1/100 or more and 1/2 or less of the length of the multiple first trench resistor structures 51A.
  • the length of the multiple second resistor connection electrodes 82 may be 1/20 or more and 1/4 or less of the length of the multiple first trench resistor structures 51A.
  • the multiple second resistor connection electrodes 82 have a second connection area S2 with respect to the resistive film 60.
  • the second connection area S2 is defined by the total planar area of the multiple second resistor connection electrodes 82.
  • the second connection area S2 is defined by the planar area of the single second resistor connection electrode 82.
  • the second connection area S2 may be approximately equal to the first connection area S1.
  • the second connection area S2 may be greater than the first connection area S1.
  • the second connection area S2 may be less than the first connection area S1.
  • the second connection area S2 is adjusted according to the current ratio I2/I1 (shunt ratio) of the second current I2 flowing through the second resistor connection electrode 82 to the first current I1 flowing through the first resistor connection electrode 81 (see FIG. 12).
  • the value of the area ratio S2/S1 of the second connection area S2 to the first connection area S1 is set to be equal to or greater than the value of the current ratio I2/I1.
  • the area ratio S2/S1 is set to be equal to or greater than 1.
  • the area ratio S2/S1 is set to be equal to or greater than 1/2.
  • the area ratio S2/S1 is set to 1/4 or more.
  • the current ratio I2/I1 is approximately 1/2
  • the second connection area S2 is 1/2 or more times the first connection area S1. It is preferable that the second connection area S2 is 2 or less times the first connection area S1.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) third resistor connection electrodes 83 embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 at a location different from the first resistor connection electrode 81 and the second resistor connection electrode 82.
  • the third resistor connection electrode 83 may be referred to as a "third resistor via electrode.”
  • the third resistor connection electrode 83 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the third resistor connection electrode 83 has a layered structure including a Ti film and a W film.
  • the multiple third resistor connection electrodes 83 are connected to the third covering portion 63 of the resistive film 60.
  • the multiple third resistor connection electrodes 83 are embedded in the portion of the resistive film 60 that covers the second trench group 53 (the multiple second trench resistor structures 51B).
  • the third resistor connection electrodes 83 form a second gate resistor R2 between the first resistor connection electrodes 81.
  • the second gate resistor R2 is formed by the resistive film 60 and the second trench resistor structures 51B in the region between the first resistor connection electrodes 81 and the third resistor connection electrodes 83.
  • the resistance value of the second gate resistor R2 is adjusted by the distance between the multiple first resistor connection electrodes 81 and the multiple third resistor connection electrodes 83.
  • the resistance value of the second gate resistor R2 is approximately equal to the resistance value of the first gate resistor R1.
  • the distance between the multiple first resistor connection electrodes 81 and the multiple third resistor connection electrodes 83 is approximately equal to the distance between the multiple first resistor connection electrodes 81 and the multiple second resistor connection electrodes 82.
  • the resistance value of the second gate resistor R2 may be different from the resistance value of the first gate resistor R1.
  • the distance between the multiple first resistor connection electrodes 81 and the multiple third resistor connection electrodes 83 may be different from the distance between the multiple first resistor connection electrodes 81 and the multiple second resistor connection electrodes 82.
  • the resistance value of the second gate resistor R2 may be less than the resistance value of the first gate resistor R1.
  • the distance between the multiple first resistor connection electrodes 81 and the multiple third resistor connection electrodes 83 may be set to be less than the distance between the multiple first resistor connection electrodes 81 and the multiple second resistor connection electrodes 82.
  • the resistance value of the second gate resistor R2 may be greater than the resistance value of the first gate resistor R1.
  • the distance between the multiple first resistor connection electrodes 81 and the multiple third resistor connection electrodes 83 may be set to be greater than the distance between the multiple first resistor connection electrodes 81 and the multiple second resistor connection electrodes 82.
  • the multiple third resistor connection electrodes 83 are formed in a region facing the multiple second trench resistor structures 51B in the first direction X in a planar view.
  • the multiple third resistor connection electrodes 83 extend in a direction different from the first resistor connection electrodes 81 in a planar view.
  • the multiple third resistor connection electrodes 83 are each formed in a band shape extending in the second direction Y in a planar view, and are arranged at intervals in the first direction X.
  • the multiple third resistor connection electrodes 83 are arranged in a stripe shape extending in the second direction Y in a planar view.
  • the third resistor connection electrodes 83 are each disposed in a region between adjacent second trench resistance structures 51B at a distance from the second trench resistance structures 51B in a plan view. In other words, the third resistor connection electrodes 83 are arranged alternately with the second trench resistance structures 51B in the first direction X.
  • the multiple third resistor connection electrodes 83 face only the flat portion of the first main surface 3 across the resistive film 60, and do not face the trench resistor structure 51 across the resistive film 60.
  • the multiple third resistor connection electrodes 83 face the boundary well region 40 (first boundary well region 40A) across the resistive film 60 and the main surface insulating film 45.
  • the multiple third resistor connection electrodes 83 only need to be arranged in a portion of the region between the multiple second trench resistance structures 51B, and do not necessarily need to be arranged in the entire region between the multiple second trench resistance structures 51B.
  • the multiple third resistor connection electrodes 83 only need to be arranged in at least one region located on the active region 6 side among the regions between the multiple second trench resistance structures 51B, and do not need to be arranged in at least one region located on the gate electrode film 64 side.
  • At least one of the multiple third resistor connection electrodes 83 faces the multiple first resistor connection electrodes 81 in the second direction Y in a plan view. In this case, it is preferable that at least one of the multiple third resistor connection electrodes 83 located on the gate electrode film 64 side faces the multiple first resistor connection electrodes 81 in the second direction Y.
  • At least one of the multiple third resistor connection electrodes 83 located on the active region 6 side does not have to face the multiple first resistor connection electrodes 81 in the second direction Y.
  • all of the third resistor connection electrodes 83 may be arranged to face the multiple first resistor connection electrodes 81 in the second direction Y.
  • the number of the multiple third resistor connection electrodes 83 is set to be equal to the number of the multiple second resistor connection electrodes 82, and all of the third resistor connection electrodes 83 face all of the second resistor connection electrodes 82 in a one-to-one correspondence in the second direction Y.
  • the number of the third resistor connection electrodes 83 may be greater than the number of the second resistor connection electrodes 82, or may be less than the number of the second resistor connection electrodes 82.
  • the third resistor connection electrodes 83 have a length in the second direction Y that is less than the length of the second trench resistance structures 51B. It is preferable that the third resistor connection electrodes 83 are arranged in a region on the other end side of the second trench resistance structures 51B with respect to the longitudinal middle portion of the second trench resistance structures 51B.
  • the length of the multiple third resistor connection electrodes 83 is preferably 1/100 or more and 1/2 or less of the length of the multiple second trench resistance structures 51B.
  • the length of the multiple third resistor connection electrodes 83 may be 1/20 or more and 1/4 or less of the length of the multiple second trench resistance structures 51B.
  • the length of the third resistor connection electrode 83 may be approximately equal to the length of the second trench resistance structure 51B.
  • the length of the third resistor connection electrode 83 may be greater than the length of the second trench resistance structure 51B.
  • the length of the third resistor connection electrode 83 may be less than the length of the second trench resistance structure 51B.
  • the multiple third resistor connection electrodes 83 have a third connection area S3 with respect to the resistive film 60.
  • the third connection area S3 is defined by the total planar area of the multiple third resistor connection electrodes 83.
  • the third connection area S3 is defined by the planar area of the single third resistor connection electrode 83.
  • the third connection area S3 is adjusted according to the current ratio I3/I1 (shunt ratio) of the third current I3 flowing through the third resistor connection electrode 83 to the first current I1 flowing through the first resistor connection electrode 81 (see FIG. 12).
  • the value of the current ratio I3/I1 of the third connection area S3 to the first connection area S1 is set to be equal to or greater than the value of the current ratio I3/I1.
  • the current ratio I3/I1 is 1, it is preferable that the current ratio I3/I1 is set to be equal to or greater than 1.
  • the current ratio I3/I1 is 1/2, it is preferable that the current ratio I3/I1 is set to be equal to or greater than 1/2.
  • the current ratio I3/I1 is 1/4, it is preferable that the current ratio I3/I1 is set to 1/4 or more.
  • the third connection area S3 is set to 1/2 or more times the first connection area S1. It is preferable that the third connection area S3 is equal to or less than twice the first connection area S1.
  • the third current I3 may be greater than the second current I2 or less than the second current I2.
  • the semiconductor device 1A includes a plurality of gate connection electrodes 84 embedded in the interlayer insulating film 74 so as to be electrically connected to the gate wiring film 65 in the inactive region 7.
  • the gate connection electrodes 84 may be referred to as "gate via electrodes.”
  • the plurality of gate connection electrodes 84 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the plurality of gate connection electrodes 84 has a layered structure including a Ti film and a W film.
  • the multiple gate connection electrodes 84 include at least one (multiple in this embodiment) first gate connection electrode 84A and at least one (multiple in this embodiment) second gate connection electrode 84B.
  • the multiple first gate connection electrodes 84A are embedded in a portion of the interlayer insulating film 74 that covers the second lower wiring portion 67 in the street region 11, and are electrically connected to the second lower wiring portion 67 (see Figures 7 to 9).
  • the multiple first gate connection electrodes 84A are formed at intervals in the second direction Y and in a band shape extending in the first direction X.
  • the multiple second gate connection electrodes 84B are embedded in the portion of the interlayer insulating film 74 that covers the third lower wiring portion 68 in the outer peripheral region 9, and are electrically connected to the third lower wiring portion 68 (see Figures 3 to 6).
  • the multiple second gate connection electrodes 84B are formed at intervals from the inner edge side to the outer edge side of the third lower wiring portion 68, and are formed in a band shape extending along the third lower wiring portion 68.
  • the semiconductor device 1A includes a plurality of first emitter connection electrodes 85 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to a plurality of emitter regions 29 in the active region 6.
  • the first emitter connection electrodes 85 may also be referred to as "first emitter via electrodes.”
  • the multiple first emitter connection electrodes 85 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the multiple first emitter connection electrodes 85 have a layered structure including a Ti film and a W film.
  • the multiple first emitter connection electrodes 85 penetrate the interlayer insulating film 74 and the main surface insulating film 45 and are embedded in the multiple contact holes 30, respectively.
  • the multiple first emitter connection electrodes 85 are each formed in a strip shape extending in the second direction Y along the multiple first trench structures 21 in a plan view. That is, in this embodiment, the multiple first emitter connection electrodes 85 extend in the same direction as the extension direction of the multiple second resistor connection electrodes 82 and the extension direction of the multiple third resistor connection electrodes 83.
  • the multiple first emitter connection electrodes 85 are each electrically connected to the emitter region 29 and the channel contact region 31 in the corresponding contact hole 30.
  • the semiconductor device 1A includes a plurality of second emitter connection electrodes 86 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to a plurality of emitter electrode films 47 in the active region 6.
  • the second emitter connection electrodes 86 may also be referred to as "second emitter via electrodes.”
  • the multiple second emitter connection electrodes 86 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the multiple second emitter connection electrodes 86 have a layered structure including a Ti film and a W film.
  • the multiple second emitter connection electrodes 86 are electrically connected to the second buried electrode 28 via the multiple emitter electrode films 47.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) first well connection electrodes 87 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to the inner edge of the peripheral well region 41.
  • the first well connection electrodes 87 may also be referred to as "first well via electrodes.”
  • the multiple first well connection electrodes 87 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the multiple first well connection electrodes 87 have a layered structure including a Ti film and a W film.
  • the multiple first well connection electrodes 87 are arranged at intervals from the inner edge side to the outer edge side of the peripheral well region 41.
  • the multiple first well connection electrodes 87 are arranged on the inner edge side of the peripheral well region 41 with respect to the widthwise middle portion of the peripheral well region 41, and are electrically connected to a region on the inner edge side of the peripheral well region 41.
  • the multiple first well connection electrodes 87 are arranged in a region between the inner edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65.
  • the multiple first well connection electrodes 87 each extend in a strip shape along the inner edge of the peripheral well region 41.
  • the multiple first well connection electrodes 87 each have multiple segment portions 87a in the portion extending in the first direction X (see FIG. 3).
  • the multiple segment portions 87a are each disposed in the region between the multiple draw-out portions 68a of the gate wiring film 65 (third lower wiring portion 68) at a distance from the multiple draw-out portions 68a.
  • the multiple segment portions 87a are omitted.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) second well connection electrodes 88 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to the outer edge of the peripheral well region 41.
  • the second well connection electrodes 88 may be referred to as "second well via electrodes.”
  • the multiple second well connection electrodes 88 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the multiple second well connection electrodes 88 have a layered structure including a Ti film and a W film.
  • the multiple second well connection electrodes 88 are arranged at intervals from the inner edge side to the outer edge side of the peripheral well region 41.
  • the multiple second well connection electrodes 88 are arranged on the outer edge side of the peripheral well region 41 with respect to the widthwise middle part of the peripheral well region 41, and are electrically connected to the region on the outer edge side of the peripheral well region 41.
  • the multiple second well connection electrodes 88 are arranged in the region between the outer edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65.
  • the multiple second well connection electrodes 88 each extend in a band shape along the outer edge of the peripheral well region 41.
  • the semiconductor device 1A includes a plurality of FLR connection electrodes 89 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to the corresponding FLRs 42.
  • one FLR connection electrode 89 is connected to one FLR 42.
  • multiple FLR connection electrodes 89 may be connected to one FLR 42.
  • the FLR connection electrodes 89 may be referred to as "FLR via electrodes.”
  • the multiple FLR connection electrodes 89 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the multiple FLR connection electrodes 89 have a layered structure including a Ti film and a W film.
  • the multiple FLR connection electrodes 89 are each formed in a band shape extending along the corresponding FLR 42. In this embodiment, the multiple FLR connection electrodes 89 are each formed in a ring shape (square ring shape) extending along the corresponding FLR 42. In this embodiment, the multiple FLR connection electrodes 89 are formed in an electrically floating state.
  • the semiconductor device 1A includes a gate terminal electrode 90 arranged on the first main surface 3 so as to be electrically connected to the gate resistor structure 50 in the pad region 10 (non-active region 7). Specifically, the gate terminal electrode 90 is arranged on the interlayer insulating film 74.
  • the gate terminal electrode 90 may be referred to as a "gate pad” or a "gate pad electrode.”
  • the gate terminal electrode 90 is preferably made of a conductive material different from that of the resistive film 60.
  • the gate terminal electrode 90 is preferably made of a conductive material different from that of the gate electrode film 64.
  • the gate terminal electrode 90 has a lower resistance value than the trench resistance structure 51 and the resistive film 60, and is electrically connected to the trench resistance structure 51 via the resistive film 60.
  • the gate terminal electrode 90 has a lower resistance value than that of the gate electrode film 64.
  • the gate terminal electrode 90 is made of a metal film.
  • the gate terminal electrode 90 may be referred to as a "gate metal terminal.”
  • the gate terminal electrode 90 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the gate terminal electrode 90 may include at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the gate terminal electrode 90 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side.
  • the gate terminal electrode 90 preferably has a thickness greater than the thickness of the resistive film 60 (the thickness of the gate electrode film 64).
  • the thickness of the gate terminal electrode 90 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the gate terminal electrode 90 preferably has a planar area of 1% or more and 30% or less of the planar area of the first main surface 3. It is particularly preferable that the planar area of the gate terminal electrode 90 is 25% or less of the planar area of the first main surface 3.
  • the planar area of the gate terminal electrode 90 may be 10% or less of the planar area of the first main surface 3.
  • the gate terminal electrode 90 is disposed on the interlayer insulating film 74 so as to cover the resistive film 60 and the gate electrode film 64 in the pad region 10.
  • the gate terminal electrode 90 covers the multiple first resistor connection electrodes 81 in the portion covering the resistive film 60, and is electrically connected to the multiple first resistor connection electrodes 81. In other words, the gate terminal electrode 90 is electrically connected to the resistive film 60 (first covering portion 61) via the multiple first resistor connection electrodes 81.
  • the gate terminal electrode 90 includes a first electrode portion 91 and a second electrode portion 92.
  • the first electrode portion 91 has a relatively wide electrode width in the second direction Y.
  • the first electrode portion 91 is a portion that forms the terminal body of the gate terminal electrode 90, and is located in an area outside the first resistor connection electrode 81 in a plan view.
  • the first electrode portion 91 may be referred to as the "terminal body portion.”
  • a bonding wire is connected to the first electrode portion 91. Therefore, the first electrode portion 91 is formed to be wider than the bonding wire joint.
  • the first electrode portion 91 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 (the periphery of the pad region 10) in a plan view.
  • the first electrode portion 91 is disposed in a region facing the gate electrode film 64 with the interlayer insulating film 74 sandwiched therebetween.
  • the first electrode portion 91 preferably covers 50% or more of the area of the gate electrode film 64 in a planar view. It is particularly preferable that the first electrode portion 91 covers 90% or more of the area of the gate electrode film 64 in a planar view. In this embodiment, the first electrode portion 91 has an electrode width wider than the gate electrode film 64 and covers the entire area of the gate electrode film 64.
  • the flatness of the first electrode portion 91 is enhanced by the gate electrode film 64.
  • the first electrode portion 91 may be electrically insulated from the gate electrode film 64 by the interlayer insulating film 74.
  • the first electrode portion 91 may be electrically connected to the gate electrode film 64 via one or more gate connection electrodes 84 embedded in the interlayer insulating film 74.
  • the first electrode portion 91 covers the first slit 71 with the interlayer insulating film 74 in between, and backfills the first recess portion 76 of the interlayer insulating film 74 (insulating main surface 75).
  • a gate terminal electrode 90 first electrode portion 91
  • the gate terminal electrode 90 (first electrode portion 91) covers the entire area of the first slit 71 with the interlayer insulating film 74 sandwiched therebetween.
  • the gate terminal electrode 90 (first electrode portion 91) fills the entire first recess portion 76 of the interlayer insulating film 74 (insulating main surface 75).
  • This configuration provides a layout that avoids the problem of electrode residue in the first recess portion 76.
  • This disclosure does not exclude configurations that include a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess portion 76.
  • the first electrode portion 91 is extended from above the gate electrode film 64 across the first slit 71 onto the resistive film 60 in a plan view.
  • the first electrode portion 91 covers the edge of the resistive film 60 with the interlayer insulating film 74 sandwiched between them.
  • the first electrode portion 91 covers the edge of the resistive film 60 with a gap on the gate electrode film 64 side with respect to a straight line that crosses the center of the resistive film 60 in the second direction Y.
  • the first electrode portion 91 may cover one or more trench resistance structures 51 with the resistive film 60 in between in the portion covering the resistive film 60.
  • the first electrode portion 91 may cover one or more first trench resistance structures 51A with the resistive film 60 in between.
  • the first electrode portion 91 may cover one or more second trench resistance structures 51B with the resistive film 60 in between.
  • the first electrode portion 91 covers one first trench resistance structure 51A and one second trench resistance structure 51B with the resistive film 60 in between.
  • the first electrode portion 91 covers the multiple third slits 73 with the interlayer insulating film 74 in between, and backfills the multiple third recesses 78 in the interlayer insulating film 74 (insulating main surface 75).
  • a gate terminal electrode 90 first electrode portion 91
  • the gate terminal electrode 90 (first electrode portion 91) covers the entire area of the multiple third recess portions 78 with the interlayer insulating film 74 in between.
  • the gate terminal electrode 90 (first electrode portion 91) fills the entire area of the third recess portion 78 of the interlayer insulating film 74 (insulating main surface 75).
  • This configuration provides a layout that avoids the problem of electrode residue in the multiple third recess portions 78.
  • This disclosure does not exclude forms that include a gate terminal electrode 90 (first electrode portion 91) that partially exposes the multiple third recess portions 78.
  • the first electrode portion 91 is extended from above the gate electrode film 64 across the third slits 73 onto the second lower line portions 70A, 70B in a plan view.
  • the first electrode portion 91 covers the edges of the second lower line portions 70A, 70B with the interlayer insulating film 74 in between.
  • the second electrode portion 92 has an electrode width in the second direction Y that is smaller than that of the first electrode portion 91, and is composed of an extension portion that is extended in the first direction X so as to protrude from the first electrode portion 91 toward the multiple first resistor connection electrodes 81.
  • the second electrode portion 92 may be referred to as a "terminal extension portion.” For example, no bonding wire is connected to the second electrode portion 92. Therefore, the second electrode portion 92 is formed to be narrower than the bonding wire joint.
  • the protruding direction of the second electrode portion 92 is the same as the extending direction of the multiple first resistor connection electrodes 81.
  • the second electrode portion 92 is drawn out from the center of the first electrode portion 91 and covers all of the first resistor connection electrodes 81.
  • the second electrode portion 92 is formed at a distance from the first slit 71 toward the second slit 72 in a plan view, and does not intersect with the first slit 71. Furthermore, the second electrode portion 92 is formed at a distance from the second slit 72 toward the first slit 71 in a plan view, and does not intersect with the second slit 72. In other words, the second electrode portion 92 has a width smaller than the width of the resistive film 60 in the first direction X, and is disposed only in the region directly above the resistive film 60.
  • the second electrode portion 92 faces the space region 57 across the main surface insulating film 45, the resistive film 60, and the interlayer insulating film 74. In other words, the second electrode portion 92 faces the flat portion of the first main surface 3 in the thickness direction. The second electrode portion 92 also faces the boundary well region 40 (first boundary well region 40A) in the thickness direction.
  • the second electrode portion 92 has a width in the first direction X that is greater than the width in the first direction X of the trench resistance structure 51.
  • the second electrode portion 92 has a width in the second direction Y that is smaller than the length in the second direction Y of the trench resistance structure 51. It is preferable that the second electrode portion 92 has a width in the second direction Y that is smaller than the space width of the space region 57.
  • the second electrode portion 92 is formed at a distance from the other end portion (first trench group 52) of the multiple first trench resistance structures 51A toward the space region 57. Also, in this embodiment, the second electrode portion 92 is formed at a distance from one end portion (second trench group 53) of the multiple second trench resistance structures 51B toward the space region 57. In other words, the second electrode portion 92 faces only the space region 57 in the thickness direction, and does not face the multiple trench resistance structures 51 in the thickness direction.
  • the second electrode portion 92 may face the other ends (first trench group 52) of the multiple first trench resistance structures 51A in the thickness direction. Also, the second electrode portion 92 may face one ends (second trench group 53) of the multiple second trench resistance structures 51B in the thickness direction. In consideration of the flatness of the second electrode portion 92, it is preferable that the second electrode portion 92 is formed in a region outside the multiple trench resistance structures 51 and spaced apart from the multiple trench resistance structures 51 in a planar view.
  • the semiconductor device 1A includes a gate wiring electrode 93 arranged on the first main surface 3 so as to be electrically connected to the gate resistor structure 50 in the pad region 10 (non-active region 7). Specifically, the gate wiring electrode 93 is arranged on the interlayer insulating film 74. The gate wiring electrode 93 may also be referred to as a "gate finger” or a "gate finger electrode.”
  • the gate wiring electrode 93 is preferably made of a conductive material different from that of the resistive film 60.
  • the gate wiring electrode 93 is preferably made of a conductive material different from that of the gate wiring film 65.
  • the gate wiring electrode 93 has a lower resistance value than the trench resistance structure 51 and the resistive film 60, and is electrically connected to the gate terminal electrode 90 via the trench resistance structure 51 and the resistive film 60.
  • the gate wiring electrode 93 has a lower resistance value than the gate wiring film 65.
  • the gate wiring electrode 93 is made of a metal film.
  • the gate wiring electrode 93 may be referred to as a "gate metal wiring.”
  • the gate wiring electrode 93 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the gate wiring electrode 93 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the gate wiring film 65 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side. In other words, the gate wiring film 65 has the same electrode configuration as the gate terminal electrode 90.
  • the gate wiring electrode 93 preferably has a thickness greater than the thickness of the resistive film 60 (the thickness of the gate wiring film 65).
  • the thickness of the gate wiring electrode 93 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the gate wiring electrode 93 is preferably approximately equal to the thickness of the gate terminal electrode 90.
  • the gate wiring electrode 93 is routed through the area between the active region 6 and the inactive region 7, electrically connected to the first trench structure 21 (trench isolation structure 15) in the active region 6, and electrically connected to the resistive film 60 in the inactive region 7. Specifically, the gate wiring electrode 93 is electrically connected to the first end 60A and the second end 60B of the resistive film 60 via the gate wiring film 65.
  • the gate wiring electrode 93 constitutes a parallel resistance circuit PR including a first gate resistance R1 and a second gate resistance R2 between itself and the gate terminal electrode 90 (see also FIG. 24).
  • the parallel resistance circuit PR constitutes a gate resistance RG interposed between the gate terminal electrode 90 and the gate wiring electrode 93.
  • the parallel resistance circuit PR is also established between the gate electrode film 64 and the gate wiring film 65.
  • the gate wiring electrode 93 includes a first upper wiring portion 94, a second upper wiring portion 95, and a third upper wiring portion 96.
  • the first upper wiring portion 94 is disposed in the pad region 10 so as to surround the gate terminal electrode 90 from multiple directions (three directions in this embodiment), and is disposed on the first lower wiring portion 66 of the gate wiring film 65 with the interlayer insulating film 74 in between.
  • the first upper wiring portion 94 includes a first upper line portion 97 and a plurality of second upper line portions 98A, 98B.
  • the first upper line portion 97 is disposed in a region in the pad region 10 that covers the first lower line portion 69 of the gate wiring film 65 with the interlayer insulating film 74 in between, and is formed in a band shape extending in the second direction Y.
  • the first upper line portion 97 has one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).
  • the first upper line portion 97 covers the second slit 72 with the interlayer insulating film 74 in between, and backfills the second recess portion 77 of the interlayer insulating film 74 (insulating main surface 75).
  • the gate wiring electrode 93 (first upper line portion 97) forms a short circuit with the gate terminal electrode 90 (first electrode portion 91) that does not go through the gate resistor structure 50. Therefore, it is preferable that the gate wiring electrode 93 (first upper line portion 97) covers the entire area of the second slit 72 with the interlayer insulating film 74 in between.
  • the gate wiring electrode 93 (first upper line portion 97) fills the entire second recess portion 77 of the interlayer insulating film 74 (insulating main surface 75).
  • This configuration provides a layout that avoids the problem of electrode residue in the second recess portion 77.
  • This disclosure does not exclude forms that include a gate terminal electrode 90 (first electrode portion 91 and/or second electrode portion 92) that intersects with the second recess portion 77, and a gate wiring electrode 93 (first upper line portion 97) that partially exposes the second recess portion 77.
  • the first upper line portion 97 is drawn out from above the gate wiring film 65 (first lower line portion 69) across the second slit 72 onto the resistive film 60 in a plan view.
  • the first upper line portion 97 covers the edge of the resistive film 60 with the interlayer insulating film 74 in between.
  • the first upper line portion 97 may also cross a straight line that crosses the center of the resistive film 60 in the second direction Y, and cover a portion of the resistive film 60 that is located in the area on the gate electrode film 64 side of the straight line.
  • the first upper line portion 97 is formed at a distance in the first direction X from the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90.
  • the first upper line portion 97 has a recess 97a recessed in the first direction X along the second electrode portion 92 in the portion along the second electrode portion 92 of the gate terminal electrode 90.
  • the first upper line portion 97 includes a first connection region 101 and a second connection region 102.
  • the first connection region 101 is formed in a region on one side (first side surface 5A side) of the recess 97a in the second direction Y, and faces the second electrode portion 92 in the second direction Y.
  • the first connection region 101 covers the second covering portion 62 of the resistive film 60 with the interlayer insulating film 74 in between.
  • the first connection region 101 covers the first trench group 52 (multiple first trench resistance structures 51A) with the interlayer insulating film 74 and the second covering portion 62 of the resistive film 60 in between.
  • the first connection region 101 further covers the multiple second resistor connection electrodes 82 and is electrically connected to the multiple second resistor connection electrodes 82. As a result, the first connection region 101 is electrically connected to the second covering portion 62 of the resistive film 60 and the first trench group 52 (multiple first trench resistor structures 51A) via the multiple second resistor connection electrodes 82.
  • the first connection region 101 only needs to cover one or more first trench resistance structures 51A adjacent to one or more second resistor connection electrodes 82, and does not need to cover all of the first trench resistance structures 51A. Of course, the first connection region 101 may cover all of the first trench resistance structures 51A.
  • the second connection region 102 is formed in a region on the other side (second side surface 5B side) of the recess 97a in the second direction Y, and faces the second electrode portion 92 in the second direction Y.
  • the second connection region 102 covers the third covering portion 63 of the resistive film 60 with the interlayer insulating film 74 in between.
  • the second connection region 102 covers the second trench group 53 (multiple second trench resistance structures 51B) with the interlayer insulating film 74 and the third covering portion 63 of the resistive film 60 in between.
  • the second connection region 102 further covers the multiple third resistor connection electrodes 83 and is electrically connected to the multiple third resistor connection electrodes 83. As a result, the second connection region 102 is electrically connected to the third covering portion 63 of the resistive film 60 and the second trench group 53 (multiple second trench resistor structures 51B) via the multiple third resistor connection electrodes 83.
  • the second connection region 102 only needs to cover one or more second trench resistance structures 51B adjacent to one or more third resistor connection electrodes 83, and does not need to cover all of the second trench resistance structures 51B.
  • the second connection region 102 may cover all of the second trench resistance structures 51B.
  • the facing area of the gate wiring electrode 93 (first upper line portion 97) relative to the resistive film 60 is preferably larger than the facing area of the gate terminal electrode 90 (first electrode portion 91 and second electrode portion 92) relative to the resistive film 60.
  • the facing area of the gate wiring electrode 93 may be smaller than the facing area of the gate terminal electrode 90.
  • the gate wiring electrode 93 (first upper line portion 97) will be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residue.
  • the gate wiring electrode 93 (first upper line portion 97) forms a short circuit together with the gate terminal electrode 90 (first electrode portion 91) that does not go through the gate resistor structure 50.
  • the first upper line portion 97 is formed at a distance from the first recess portion 76 (first slit 71) toward the second recess portion 77 (second slit 72) in a plan view and does not intersect with the first recess portion 76 (first slit 71).
  • the gate terminal electrode 90 (first electrode portion 91) covers the entire area of the first recess portion 76.
  • the first upper line portion 97 faces the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90 in the first direction X in the region above the resistive film 60.
  • This configuration provides a layout that avoids the problem of electrode residue in the first recess portion 76.
  • This disclosure does not exclude a form that includes a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess portion 76, and a first upper line portion 97 that intersects with the first recess portion 76.
  • the first current I1 applied to the gate terminal electrode 90 (second electrode portion 92) is transmitted to the first covering portion 61 of the resistive film 60 via the multiple first resistor connection electrodes 81.
  • the first current I1 transmitted to the first covering portion 61 is divided into a second current I2 on the second covering portion 62 (first trench group 52) side of the resistive film 60, and a third current I3 on the third covering portion 63 (second trench group 53) side of the resistive film 60.
  • the second current I2 is transmitted to the first connection region 101 of the first upper line portion 97 via the plurality of second resistor connection electrodes 82, and the third current I3 is transmitted to the second connection region 102 of the first upper line portion 97 via the plurality of third resistor connection electrodes 83.
  • the gate wiring electrode 93 (first upper line portion 97) constitutes a parallel resistance circuit PR including the first gate resistor R1 and the second gate resistor R2 between the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (second electrode portion 92) (see also FIG. 24).
  • the second upper line portions 98A, 98B include a second upper line portion 98A on one side and a second upper line portion 98B on the other side.
  • the second upper line portion 98A is disposed in a region on one side (first side surface 5A side) of the gate terminal electrode 90 in the second direction Y in the pad region 10.
  • the second upper line portion 98B is disposed in a region on the other side (second side surface 5B side) of the gate terminal electrode 90 in the second direction Y in the pad region 10.
  • the second upper line portion 98A is formed in a band shape extending in the first direction X, and has one end connected to one end of the first upper line portion 97, and the other end located on the peripheral side (third side surface 5C side) of the chip 2.
  • the second upper line portion 98A covers the second lower line portion 70A of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween.
  • the second upper line portion 98A is formed at a distance from the first electrode portion 91 of the gate terminal electrode 90 to one side in the second direction Y.
  • the second upper line portion 98B is formed in a band shape extending in the first direction X, and has one end connected to the other end of the first upper line portion 97, and the other end located on the peripheral side (third side surface 5C side) of the chip 2.
  • the second upper line portion 98B covers the second lower line portion 70B of the gate wiring film 65 with the interlayer insulating film 74 in between.
  • the second upper line portion 98B is formed at a distance from the first electrode portion 91 of the gate terminal electrode 90 on the other side in the second direction Y, and faces the second upper line portion 98A with the first electrode portion 91 in between.
  • the gate wiring electrode 93 (second upper line portions 98A, 98B) forms a short circuit with the gate terminal electrode 90 (first electrode portion 91) that does not go through the gate resistor structure 50. Therefore, it is preferable that the second upper line portions 98A, 98B are disposed at a distance from the first recess portion 76 and do not have a portion that covers the first recess portion 76 (a portion that intersects with the first recess portion 76).
  • This configuration provides a layout that avoids the problem of electrode residue in the first recess 76.
  • the present disclosure does not exclude a configuration that includes a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess 76 and second upper line portions 98A, 98B that intersect with the first recess 76.
  • a gate terminal electrode 90 first electrode portion 91
  • second upper line portions 98A, 98B that intersect with the multiple third recesses 78
  • the second upper line portions 98A, 98B are disposed at a distance from the third recess portions 78 and do not have a portion that covers the third recess portions 78 (a portion that intersects with the third recess portions 78).
  • This configuration provides a layout that avoids the problem of electrode residue in the third recess portions 78.
  • the gate terminal electrode 90 (first electrode portion 91) covers the entire area of the third recess portions 78.
  • the second upper line portions 98A, 98B face the first electrode portion 91 of the gate terminal electrode 90 in the second direction Y in the region above the second lower line portions 70A, 70B.
  • This disclosure does not exclude configurations including a gate terminal electrode 90 (first electrode portion 91) that partially exposes the multiple third recess portions 78, and the second upper line portions 98A, 98B that intersect with the multiple third recess portions 78.
  • the second upper line portions 98A, 98B preferably cover the inner portions of the second lower line portions 70A, 70B with a gap from the periphery of the second lower line portions 70A, 70B in a plan view.
  • the second upper line portions 98A, 98B face only the second lower line portions 70A, 70B across the interlayer insulating film 74, and do not face the main surface insulating film 45 across the interlayer insulating film 74.
  • the second upper wiring portion 95 is pulled out from the first upper wiring portion 94 to the street region 11 and covers the second lower wiring portion 67 of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween. Specifically, the second upper wiring portion 95 is pulled out from the inner portion (the center portion in this embodiment) of the first upper line portion 97 and is formed in a band shape extending in the first direction X.
  • the second upper wiring portion 95 crosses the center of the chip 2.
  • the second upper wiring portion 95 extends in a band shape so as to be located in an area on one side (the third side surface 5C side) and an area on the other side (the fourth side surface 5D side) of the first direction X with respect to a straight line crossing the center of the first main surface 3 in the second direction Y.
  • the second upper wiring portion 95 has one end connected to the first upper wiring portion 94 on one side of the first direction X, and the other end on the other side of the first direction X.
  • the other end of the second upper wiring portion 95 is an open end.
  • the second upper wiring portion 95 covers the multiple first gate connection electrodes 84A and is electrically connected to the second lower wiring portion 67 via the multiple first gate connection electrodes 84A.
  • the second upper wiring portion 95 has a width smaller than the width of the street region 11 in the second direction Y, and is formed at a distance inward from the multiple active regions 6 into the street region 11. In other words, the second upper wiring portion 95 is formed at a distance from the multiple trench isolation structures 15 (multiple first trench structures 21) in a plan view.
  • the third upper wiring portion 96 is pulled out from the first upper wiring portion 94 to the peripheral region 9 and covers the third lower wiring portion 68 of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween. Specifically, the third upper wiring portion 96 is pulled out from the other ends of the multiple second upper line portions 98A, 98B to one side (first side surface 5A side) and the other side (second side surface 5B side) of the peripheral region 9, and is formed in a band shape extending along the peripheral region 9.
  • the third upper wiring portion 96 sandwiches the multiple active regions 6. Specifically, the third upper wiring portion 96 extends along the periphery (first side surfaces 5A-5D) of the chip 2 so as to surround the multiple active regions 6 in a planar view. As a result, the third upper wiring portion 96, together with the second upper wiring portion 95, surrounds the multiple active regions 6. In this embodiment, the third upper wiring portion 96 is formed at a distance from the second upper wiring portion 95. The third upper wiring portion 96 may be connected to the second upper wiring portion 95.
  • the third upper wiring portion 96 covers the multiple second gate connection electrodes 84B and is electrically connected to the third lower wiring portion 68 via the multiple second gate connection electrodes 84B. It is preferable that the third upper wiring portion 96 has a width smaller than the width of the third lower wiring portion 68 in a planar view. It is preferable that the third upper wiring portion 96 covers the inner portion of the third lower wiring portion 68 with a gap from the periphery of the third lower wiring portion 68 in a planar view.
  • the semiconductor device 1A includes an emitter terminal electrode 103 arranged on the first main surface 3 at a distance from the gate terminal electrode 90 and the gate wiring electrode 93 in the active region 6.
  • the emitter terminal electrode 103 is arranged on the interlayer insulating film 74.
  • the emitter terminal electrode 103 may also be referred to as an "emitter pad” or an "emitter pad electrode.”
  • the emitter terminal electrode 103 is preferably made of a conductive material different from that of the resistive film 60.
  • the emitter terminal electrode 103 is preferably made of a conductive material different from that of the emitter electrode film 47.
  • the emitter terminal electrode 103 has a lower resistance value than the trench resistor structure 51 and the resistor film 60.
  • the emitter terminal electrode 103 is made of a metal film.
  • the emitter terminal electrode 103 may be referred to as an "emitter metal terminal.”
  • the emitter terminal electrode 103 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the emitter terminal electrode 103 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the emitter terminal electrode 103 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side.
  • the emitter terminal electrode 103 has the same electrode configuration as the gate terminal electrode 90.
  • the emitter terminal electrode 103 preferably has a thickness greater than the thickness of the resistive film 60 (the thickness of the gate electrode film 64).
  • the thickness of the emitter terminal electrode 103 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the emitter terminal electrode 103 is preferably approximately equal to the thickness of the gate terminal electrode 90.
  • the emitter terminal electrode 103 has a planar area larger than the planar area of the gate terminal electrode 90.
  • the planar area of the emitter terminal electrode 103 is preferably 50% or more and 90% or less of the planar area of the first main surface 3. It is particularly preferable that the planar area of the emitter terminal electrode 103 is 70% or more of the planar area of the first main surface 3.
  • the emitter terminal electrode 103 includes a first emitter terminal electrode 103A and a second emitter terminal electrode 103B.
  • the first emitter terminal electrode 103A is disposed in a region between the second upper wiring portion 95 and the third upper wiring portion 96 on a portion of the interlayer insulating film 74 that covers the first active region 6A.
  • the first emitter terminal electrode 103A is drawn out from the first active region 6A to the peripheral region 9 in a plan view.
  • the first emitter terminal electrode 103A covers the multiple first emitter connection electrodes 85 and multiple second emitter connection electrodes 86 in the first active region 6A, and covers the multiple first well connection electrodes 87 in the peripheral region 9.
  • the first emitter terminal electrode 103A is electrically connected to the multiple second trench structures 25, the multiple emitter regions 29, and the multiple channel contact regions 31 via the multiple first emitter connection electrodes 85 and multiple second emitter connection electrodes 86.
  • the first emitter terminal electrode 103A is electrically connected to the inner edge of the peripheral well region 41 via the multiple first well connection electrodes 87.
  • the second emitter terminal electrode 103B is disposed in the region between the second upper wiring portion 95 and the third upper wiring portion 96 on the portion of the interlayer insulating film 74 that covers the second active region 6B.
  • the second emitter terminal electrode 103B is extended from the second active region 6B to the peripheral region 9 in a plan view.
  • the second emitter terminal electrode 103B covers the multiple first emitter connection electrodes 85 and multiple second emitter connection electrodes 86 in the second active region 6B, and covers the multiple first well connection electrodes 87 in the peripheral region 9.
  • the second emitter terminal electrode 103B is electrically connected to the multiple second trench structures 25, the multiple emitter regions 29, and the multiple channel contact regions 31 via the multiple first emitter connection electrodes 85 and multiple second emitter connection electrodes 86.
  • the second emitter terminal electrode 103B is electrically connected to the inner edge of the peripheral well region 41 via the multiple first well connection electrodes 87.
  • the semiconductor device 1A includes an emitter wiring electrode 104 that is extended from the emitter terminal electrode 103 to a region outside the gate wiring electrode 93 on the interlayer insulating film 74.
  • the emitter wiring electrode 104 may also be referred to as an "emitter finger” or an “emitter finger electrode.”
  • the emitter wiring electrode 104 is preferably made of a conductive material different from that of the resistive film 60.
  • the emitter wiring electrode 104 is preferably made of a conductive material different from that of the emitter electrode film 47.
  • the emitter wiring electrode 104 has a lower resistance value than the trench resistor structure 51 and the resistor film 60.
  • the emitter wiring electrode 104 is made of a metal film.
  • the emitter wiring electrode 104 may be referred to as an "emitter metal wiring.”
  • the emitter wiring electrode 104 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.
  • the emitter wiring electrode 104 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the emitter wiring electrode 104 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side.
  • the emitter wiring electrode 104 has the same electrode configuration as the emitter terminal electrode 103.
  • the emitter wiring electrode 104 preferably has a thickness greater than the thickness of the resistive film 60 (the thickness of the gate electrode film 64).
  • the thickness of the emitter wiring electrode 104 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the emitter wiring electrode 104 is preferably approximately equal to the thickness of the gate terminal electrode 90 (emitter terminal electrode 103).
  • the emitter wiring electrode 104 is connected to both the first emitter terminal electrode 103A and the second emitter terminal electrode 103B, and is extended from the first emitter terminal electrode 103A and the second emitter terminal electrode 103B to an area outside the gate wiring electrode 93 (third upper wiring portion 96).
  • the emitter wiring electrode 104 is formed in a band shape extending along the periphery of the chip 2 so as to surround the gate terminal electrode 90, the gate wiring electrode 93, the first emitter terminal electrode 103A, and the second emitter terminal electrode 103B.
  • the emitter wiring electrode 104 is formed in a ring shape (specifically, a square ring shape) extending along the periphery of the chip 2 (first to fourth side surfaces 5A to 5D), and collectively surrounds the gate terminal electrode 90, the gate wiring electrode 93, the first emitter terminal electrode 103A, and the second emitter terminal electrode 103B.
  • the emitter wiring electrode 104 is routed over a portion of the interlayer insulating film 74 that covers the outer edge of the peripheral well region 41.
  • the emitter wiring electrode 104 covers a plurality of second well connection electrodes 88 and is electrically connected to the outer edge of the peripheral well region 41 via the plurality of second well connection electrodes 88.
  • the semiconductor device 1A includes a plurality of FLR electrodes 105 arranged on the interlayer insulating film 74 in the peripheral region 9.
  • the plurality of FLR electrodes 105 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film and a conductive polysilicon film.
  • the multiple FLR electrodes 105 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the multiple FLR electrodes 105 have a layered structure including a barrier metal film and a main metal film stacked in this order from the chip 2 side.
  • the barrier metal film is made of, for example, a layered film including a Ti film and a TiN film stacked in this order from the chip 2 side.
  • the main metal film is made of, for example, an Al alloy film (an AlCu alloy film in this embodiment).
  • the multiple FLR electrodes 105 are each formed in a band shape extending along the corresponding FLR 42. In this embodiment, the multiple FLR electrodes 105 are each formed in a ring shape (square ring shape) extending along the corresponding FLR 42. In this embodiment, the multiple FLR electrodes 105 are formed in an electrically floating state.
  • Each FLR electrode 105 has an electrode curved portion 105A whose shape in a planar view is an arc at each of the four corners 201-204. At each of the corners 201-204, the inner edge 105Aa and the outer edge 105Ab of all of the electrode curved portions 105A may have the same center of curvature.
  • Each electrode curved portion 105A has an electrode straight portion 105B whose shape in a planar view is straight between the four corners 201-204.
  • the inner edge 105Aa and the outer edge 105Ab of all the electrode curved portions 105A in each of the corners 201-204 have the same center of curvature.
  • the centers of curvature of the inner edge 105Aa and the outer edge 105Ab of each of the electrode curved portions 105A are located on a dividing line, which is a straight line that divides the apex angle of the corner in half.
  • the dividing line which is a straight line that divides the apex angle of the second corner 202 in half, is shown by L0 in FIG. 25, which is used to explain the modified example described below.
  • the inner edges 105Aa and outer edges 105Ab of all of the electrode curved portions 105A do not have to have the same center of curvature.
  • the centers of curvature of the inner edges 105Aa and outer edges 105Ab of each of the electrode curved portions 105A do not have to be located on a dividing line that is a straight line that divides the apex angle of the corner in half.
  • the multiple FLR electrodes 105 face the corresponding FLRs 42. Each FLR electrode 105 collectively covers the corresponding multiple FLR connection electrodes 89. Each FLR electrode 105 is electrically connected to the corresponding FLR 42 via the corresponding multiple FLR connection electrodes 89.
  • the FLR connection electrodes 89 may be formed integrally with the corresponding FLR electrodes 105.
  • the multiple FLR electrodes 105 are formed in an electrically floating state.
  • the semiconductor device 1A includes a channel stop electrode 106 disposed on the interlayer insulating film 74 in the peripheral region 9.
  • the channel stop electrode 106 may be referred to as an "EQR (EQui-potential Ring) electrode.”
  • the channel stop electrode 106 may include at least one of a Ti film, a TiRiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film and a conductive polysilicon film.
  • the channel stop electrode 106 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the channel stop electrode 106 has a layered structure including a barrier metal film and a main metal film, which are layered in this order from the chip 2 side.
  • the barrier metal film is made of, for example, a layered film including a Ti film and a TiN film, which are layered in this order from the chip 2 side.
  • the main metal film is made of, for example, an Al alloy film (an AlCu alloy film in this embodiment).
  • the channel stop electrode 106 is formed in a band shape extending along the periphery of the chip 2.
  • the channel stop electrode 106 is formed in a ring shape (square ring shape) extending along the periphery of the chip 2.
  • the channel stop electrode 106 penetrates from above the interlayer insulating film 74 into the removed portion 46 of the interlayer insulating film 74, and is electrically connected to the channel stop region 43.
  • the channel stop electrode 106 is formed in an electrically floating state.
  • the channel stop region 43 may be formed at a distance inward from the periphery of the chip 2 so as to expose the peripheral portion (channel stop region 43) of the first main surface 3.
  • the semiconductor device 1A includes a collector electrode 107 covering the second main surface 4.
  • the collector electrode 107 is electrically connected to the collector region 14 exposed from the second main surface 4.
  • the collector electrode 107 forms an ohmic contact with the collector region 14.
  • the collector electrode 107 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (the first to fourth side surfaces 5A to 5D).
  • the semiconductor device 1A includes a chip 2, a trench resistor structure 51, a resistive film 60, a gate terminal electrode 90, and a gate wiring electrode 93.
  • the chip 2 has a first main surface 3.
  • the trench resistor structure 51 is formed on the first main surface 3.
  • the resistive film 60 is electrically connected to the trench resistor structure 51 on the first main surface 3.
  • the gate terminal electrode 90 has a lower resistance value than the resistive film 60, and is electrically connected to the trench resistance structure 51 via the resistive film 60 on the first main surface 3.
  • the gate wiring electrode 93 has a lower resistance value than the resistive film 60, and is electrically connected to the gate terminal electrode 90 via the trench resistance structure 51 and the resistive film 60 on the first main surface 3.
  • the gate resistor RG including the trench resistor structure 51 and the resistive film 60 can be interposed between the gate terminal electrode 90 and the gate wiring electrode 93.
  • the trench resistor structure 51 is incorporated into the chip 2 in the region between the gate terminal electrode 90 and the gate wiring electrode 93, so that an increase in the area occupied by the gate resistor RG with respect to the first main surface 3 can be suppressed. Therefore, in a configuration with a gate resistor RG, a semiconductor device 1A having a novel layout that contributes to miniaturization can be provided.
  • the semiconductor device 1A preferably includes a gate electrode film 64 and a gate wiring film 65.
  • the gate electrode film 64 is disposed on the first main surface 3 adjacent to the resistive film 60.
  • the gate wiring film 65 is disposed on the first main surface 3 adjacent to the resistive film 60 so as to face the gate electrode film 64 with the resistive film 60 in between.
  • the gate terminal electrode 90 preferably covers the gate electrode film 64.
  • the gate wiring electrode 93 preferably covers the gate wiring film 65.
  • the resistive film 60 preferably has a first end 60A on one side and a second end 60B on the other side.
  • the gate wiring film 65 preferably has a first connection portion connected to the first end 60A of the resistive film 60, and a second connection portion connected to the second end 60B of the resistive film 60.
  • the gate wiring electrode 93 is preferably electrically connected to the resistive film 60 via the gate wiring film 65.
  • the gate wiring electrode 93 can be electrically connected to the resistive film 60 via the gate wiring film 65, eliminating the need to directly connect the gate wiring electrode 93 to the resistive film 60. This relaxes the design rules for the gate wiring electrode 93, improving the degree of freedom in designing the gate wiring electrode 93.
  • the semiconductor device 1A preferably includes a first slit 71 defined between the resistive film 60 and the gate electrode film 64, and a second slit 72 defined between the resistive film 60 and the gate wiring film 65.
  • the first slit 71 and the second slit 72 can properly separate (define) the resistive film 60 from the gate electrode film 64 and the gate wiring film 65. This can improve the accuracy of the resistance value of the resistive film 60.
  • the gate terminal electrode 90 preferably covers the resistive film 60 and the gate electrode film 64 across the first slit 71 in a planar view.
  • the gate wiring film 65 preferably covers the resistive film 60 and the gate electrode film 64 across the second slit 72 in a planar view.
  • the first slit 71 is preferably formed narrower than the resistive film 60.
  • the second slit 72 is preferably formed narrower than the resistive film 60.
  • the trench resistor structure 51 preferably extends in a strip shape in the second direction Y (one direction) in a planar view.
  • the resistive film 60 preferably extends in a strip shape in the second direction Y (one direction) in a planar view.
  • the first slit 71 preferably extends in a strip shape in the second direction Y (one direction) in a planar view.
  • the second slit 72 preferably extends in a strip shape in the second direction Y (one direction) in a planar view.
  • the first slit 71 may have a first length in the second direction Y (one direction), and the second slit 72 may have a second length in the second direction Y (one direction) that is smaller than the first length.
  • the semiconductor device 1A preferably includes a third slit 73 defined between the gate electrode film 64 and the gate wiring film 65.
  • the third slit 73 can properly separate (define) the gate wiring film 65 from the gate electrode film 64. This can prevent the gate wiring film 65 from forming a short circuit with the gate electrode film 64 that does not go through the resistive film 60.
  • the gate terminal electrode 90 preferably covers the gate electrode film 64 and the gate wiring film 65 across the third slit 73 in a plan view.
  • multiple trench resistance structures 51 are formed at intervals on the first main surface 3.
  • the resistive film 60 covers the multiple trench resistance structures 51.
  • the resistive film 60 preferably has a first covering portion 61 that covers the first main surface 3 outside the trench resistance structure 51, and a second covering portion 62 that covers the trench resistance structure 51.
  • the gate terminal electrode 90 is preferably electrically connected to the resistive film 60 in the portion that covers the first covering portion 61.
  • the gate wiring electrode 93 is preferably electrically connected to the resistive film 60 in the portion that covers the second covering portion 62.
  • the semiconductor device 1A preferably includes an interlayer insulating film 74, a first resistor connection electrode 81, and a second resistor connection electrode 82.
  • the interlayer insulating film 74 covers the resistive film 60.
  • the first resistor connection electrode 81 is embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60.
  • the second resistor connection electrode 82 is embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 at a position different from the first resistor connection electrode 81.
  • the gate terminal electrode 90 is preferably arranged on the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 via the first resistor connection electrode 81.
  • the gate wiring electrode 93 is preferably arranged on the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 via the second resistor connection electrode 82.
  • a gate resistor RG can be formed in the region between the first resistor connection electrode 81 and the second resistor connection electrode 82. The resistance value of the gate resistor RG can be adjusted by adjusting the distance between the first resistor connection electrode 81 and the second resistor connection electrode 82.
  • the second resistor connection electrode 82 may extend in a direction different from that of the first resistor connection electrode 81.
  • the first resistor connection electrode 81 may extend in a first direction X (one direction) in a plan view
  • the second resistor connection electrode 82 may extend in a second direction Y (intersecting direction) that intersects with the first direction X (one direction) in a plan view.
  • the plurality of first resistor connection electrodes 81 are preferably embedded in the interlayer insulating film 74.
  • the plurality of second resistor connection electrodes 82 are preferably embedded in the interlayer insulating film 74.
  • the second connection area S2 of the second resistor connection electrode 82 to the resistive film 60 may be smaller than the first connection area S1 of the first resistor connection electrode 81 to the resistive film 60.
  • the gate terminal electrode 90 preferably has a first electrode portion 91 located outside the first resistor connection electrode 81 in a plan view, and a second electrode portion 92 that protrudes from the first electrode portion 91 toward the first resistor connection electrode 81 and is narrower than the first electrode portion 91.
  • the first electrode portion 91 is preferably formed as a terminal main body portion of the gate terminal electrode 90.
  • the second electrode portion 92 is preferably formed as a terminal pull-out portion pulled out from the terminal main body portion.
  • the first electrode portion 91 ensures an area to which a gate potential is applied
  • the second electrode portion 92 ensures an area that is electrically connected to the resistive film 60.
  • the conductive bonding material can be bonded to the first electrode portion 91. This makes it possible to prevent stress caused by the conductive bonding material from occurring in the resistive film 60 and the trench resistance structure 51. This makes it possible to prevent a deterioration in the electrical characteristics of the gate resistor RG.
  • the semiconductor device 1A preferably includes a p-type boundary well region 40 formed in the surface layer of the first main surface 3.
  • the boundary well region 40 can improve the breakdown voltage.
  • the trench resistance structure 51 is preferably formed at a distance from the bottom of the boundary well region 40 toward the first main surface 3.
  • the boundary well region 40 can suppress electric field concentration on the bottom wall of the trench resistance structure 51. Therefore, the breakdown voltage can be appropriately improved.
  • the semiconductor device 1A preferably includes an active region 6 provided on the first main surface 3, a non-active region 7 provided outside the active region 6 on the first main surface 3, and a first trench structure 21 (trench gate structure) formed in the active region 6.
  • the trench resistance structure 51 is preferably formed in the non-active region 7.
  • the resistance film 60 preferably covers the trench resistance structure 51 in the non-active region 7.
  • the gate terminal electrode 90 is electrically connected to the resistive film 60 in the non-active region 7.
  • the gate wiring electrode 93 is electrically connected to the first trench structure 21 in the active region 6, and is electrically connected to the resistive film 60 in the non-active region 7.
  • FIG. 25 is a schematic plan view for explaining modified examples of the FLR 42, the FLR electrode 105, and the FLR connection electrode 89, and is a schematic plan view mainly showing the structure of the second corner portion 202 of the outer peripheral region 9.
  • FIG. 26 is a schematic cross-sectional view taken along the line XXVI-XXVI shown in FIG. 25.
  • FIG. 25 omits configurations other than the FLR 42 and FLR electrode 105 (peripheral well region 41, channel stop region 43, channel stop electrode 106, etc.). However, FIG. 26 illustrates the channel stop electrode 106 for clarity.
  • each FLR 42 is each formed in an annular shape (square annular shape) in the outer peripheral region 9 so as to surround the active region 6.
  • each FLR 42 has an FLR curved portion 42A in which the inner edge 42Aa and the outer edge 42Ab have a circular arc shape in plan view.
  • each FLR 42 has an FLR straight portion 42B in which the shape in plan view is straight.
  • Each FLR curved portion 42A has a double diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 having a lower p-type impurity concentration than the first diffusion region 301.
  • Each FLR straight portion 42B has a single diffusion structure consisting of only a diffusion region having the same p-type impurity concentration as the first diffusion region 301. The detailed structure of the multiple FLRs 42 will be described later.
  • the multiple FLR electrodes 105 are each formed in a band shape extending along the corresponding FLR 42.
  • the multiple FLR electrodes 105 are each formed in a ring shape (square ring shape) extending along the corresponding FLR 42.
  • the multiple FLR electrodes 105 are formed in an electrically floating state.
  • the multiple FLR electrodes 105 face the corresponding FLRs 42 via a laminated film of the main surface insulating film 45 and the interlayer insulating film 74. In this modified example, the multiple FLR electrodes 105 cover the corresponding FLRs 42.
  • Each FLR electrode 105 has an electrode curved portion 105A whose inner and outer edges have a circular arc shape in plan view at the four corners 201-204.
  • Each FLR electrode 105 has an electrode straight portion 105B whose inner and outer edges have a straight shape in plan view between the four corners 201-204.
  • each electrode curved portion 105A has an inner edge 105Aa and an outer edge 105Ab that have different centers of curvature and different curvatures.
  • the magnitude relationship of the curvature of the inner edge 105Aa and the outer edge 105Ab is opposite between two adjacent electrode curved portions 105A.
  • the center of curvature of the inner edge 105Aa and the center of curvature of the outer edge 105Ab of each electrode curved portion 105A are located at different positions on the dividing line L0, which is a straight line that divides the apex angle of the second corner portion 202 in half, and the radius of curvature of the inner edge 105Aa and the radius of curvature of the outer edge 105Ab are different. Furthermore, the magnitude relationship of the curvature of the inner edge 105Aa and the outer edge 105Ab is opposite between two adjacent electrode curved portions 105A.
  • the center of curvature of the inner edge 105Aa of the innermost electrode curved portion 105A is Q1
  • the center of curvature of the outer edge 105Ab of the electrode curved portion 105A is Q2.
  • the radius of curvature of the inner edge 105Aa is r1
  • the radius of curvature of the outer edge 105Ab is r2 (r2>r1). Therefore, the curvature of the inner edge 105Aa is greater than the curvature of the outer edge 105Ab.
  • the center of curvature of the inner edge 105Aa of the second inner electrode curved portion 105A is Q2, and the center of curvature of the outer edge 105Ab of the electrode curved portion 105A is Q1.
  • the radius of curvature of the inner edge 105Aa is greater than the radius of curvature of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.
  • the center of curvature of the inner edge 105Aa of the third electrode curved portion 105A from the inside is Q1
  • the center of curvature of the outer edge 105Ab of the electrode curved portion 105A is Q2.
  • the radius of curvature of the inner edge 105Aa is smaller than the radius of curvature of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is larger than the curvature of the outer edge 105Ab.
  • the center of curvature of the inner edge 105Aa of the outermost electrode curved portion 105A is Q2, and the center of curvature of the outer edge 105Ab of the electrode curved portion 105A is Q1.
  • the radius of curvature of the inner edge 105Aa is greater than the radius of curvature of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.
  • Each electrode curved portion 105A has a wide region and a narrow region between its inner edge 105Aa and outer edge 105Ab. A part of the wide region in each electrode curved portion 105A is physically and electrically connected to the corresponding FLR 42 via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • the innermost electrode curved portion 105A and the third innermost electrode curved portion 105A have the narrowest width at the center of their length, and the width increases from the center to both ends. Therefore, these electrode curved portions 105A have wide portions 211 at both ends.
  • the second innermost electrode curved portion 105A and the outermost electrode curved portion 105A have the widest width at the center of their length, and the width becomes narrower from the center to both ends. Therefore, these electrode curved portions 105A have a wide portion 211 at the center of their length.
  • the angle in the counterclockwise direction around the center of curvature Q1 with respect to the straight line connecting the center of curvature Q1 and the vertex of the second corner portion 202 is negative, and the angle in the clockwise direction around the center of curvature Q1 is positive.
  • one end of the inner edge 105Aa and one end of the outer edge 105Ab of each electrode curved portion 105A are positioned on a straight line L1 that has a rotation angle of -45 degrees around the center of curvature Q1 with respect to a straight line connecting the center of curvature Q1 and the vertex of the second corner portion 202.
  • the other ends of the inner edge 105Aa and the outer edge 105Ab of each electrode curved portion 105A are located on a straight line L2 that forms an angle of +45 degrees with the center of curvature Q1 as its center with respect to a straight line connecting the center of curvature Q1 and the vertex of the second corner portion 202.
  • the widths of both ends of the innermost electrode curved portion 105A and the third electrode curved portion 105A from the inside are greater than the widths of both ends of the second electrode curved portion 105A from the inside and the outermost electrode curved portion 105A, respectively.
  • the width of the electrode straight portion 105B connected to both ends of each electrode curved portion 105A is equal to the width of both ends of the electrode curved portion 105A.
  • each FLR curved portion 42A has an inner edge 42Aa and an outer edge 42Ab whose centers of curvature are different from each other.
  • the magnitude relationship of the curvature of the inner edge 42Aa and the outer edge 42Ab is opposite between two adjacent FLR curved portions 42A.
  • the center of curvature of the inner edge 42Aa and the center of curvature of the outer edge 42Ab of each FLR curved portion 42A are located at different positions on the dividing line L0, which is a straight line that divides the apex angle of the second corner portion 202 in half, and the radius of curvature of the inner edge 42Aa and the radius of curvature of the outer edge 42Ab are different. Furthermore, the magnitude relationship of the curvature of the inner edge 42Aa and the outer edge 42Ab is opposite between each two adjacent FLR curved portions 42A.
  • the center of curvature of the inner edge 42Aa of the innermost FLR curve portion 42A is Q1
  • the center of curvature of the outer edge 42Ab is Q2.
  • the radius of curvature of the inner edge 42Aa is smaller than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is larger than the curvature of the outer edge 42Ab.
  • the center of curvature of the inner edge 42Aa of the second innermost FLR curved portion 42A is Q2, and the center of curvature of the outer edge 42Ab is Q1.
  • the radius of curvature of the inner edge 42Aa is greater than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.
  • the center of curvature of the inner edge 42Aa of the third innermost FLR curved portion 42A is Q1, and the center of curvature of the outer edge 42Ab is Q2.
  • the radius of curvature of the inner edge 42Aa is smaller than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is larger than the curvature of the outer edge 42Ab.
  • the center of curvature of the inner edge 42Aa of the outermost FLR curved portion 42A is Q2, and the center of curvature of the outer edge 42Ab is Q1.
  • the radius of curvature of the inner edge 42Aa is greater than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.
  • the center of curvature of the inner edge 42Aa of each FLR curved portion 42A coincides with the center of curvature of the inner edge 105Aa of the corresponding electrode curved portion 105A.
  • the center of curvature of the outer edge 42Ab of each FLR curved portion 42A coincides with the center of curvature of the outer edge 105Ab of the corresponding electrode curved portion 105A.
  • each FLR curved portion 42A is set back more inwardly than the inner edge 105Aa of the corresponding electrode curved portion 105A
  • the outer edge 42Ab of each FLR curved portion 42A is set back more inwardly than the outer edge 105Ab of the corresponding electrode curved portion 105A. Therefore, the width of each FLR curved portion 42A at each longitudinal position is narrower than the width of the corresponding electrode curved portion 105A at the corresponding longitudinal position.
  • each FLR curved portion 42A may be located further outward than the inner edge 105Aa of the corresponding electrode curved portion 105A.
  • the outer edge 42Ab of each FLR curved portion 42A may be located further outward than the outer edge 105Ab of the corresponding electrode curved portion 105A.
  • each FLR curved portion 42A may extend outward from the corresponding side edge 105Aa, 105Ab of the corresponding electrode curved portion 105A. Also, both the inner edge 42Aa and the outer edge 42Ab of each FLR curved portion 42A may extend outward from the corresponding side edge 105Aa, 105Ab of the corresponding electrode curved portion 105A.
  • the innermost FLR curved portion 42A and the third innermost FLR curved portion 42A have the narrowest width at the center of their length, and the width increases from the center of their length to both ends. Therefore, these FLR curved portions 42A have wide portions 221 at both ends.
  • the second innermost FLR curved portion 42A and the outermost FLR curved portion 42A have the widest width at the center of their length, and the width becomes narrower from the center of their length to both ends. Therefore, these FLR curved portions 42A have a wide portion 221 at the center of their length.
  • one end of the inner edge 42Aa and one end of the outer edge 42Ab of each FLR curved portion 42A are positioned on a straight line L1.
  • the other ends of the inner edge 42Aa and the outer edge 42Ab of each FLR curve portion 42A are located on a straight line L2.
  • the widths of both ends of the innermost FLR curved portion 42A and the third FLR curved portion 42A from the inside are greater than the widths of both ends of the second FLR curved portion 42A from the inside and the outermost FLR curved portion 42A, respectively.
  • the width of the FLR straight line portion 42B connected to both ends of each FLR curved portion 42A is equal to the width of both ends of that FLR curved portion 42A.
  • the diffusion region boundary line BL in each FLR curved portion 42A has the same center of curvature as the center of curvature of the inner edge 42Aa of the FLR curved portion 42A.
  • the diffusion region boundary line BL in each FLR curved portion 42A may have the same center of curvature as the center of curvature of the outer edge 42Ab of the FLR curved portion 42A.
  • the width of the first diffusion region 301 of the first diffusion region 301 and the second diffusion region 302 of each FLR curve portion 42A is constant in the length direction.
  • the width of the second diffusion region 301 of the first diffusion region 301 and the second diffusion region 302 of each FLR curve portion 42A may be constant in the length direction.
  • planar shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of each FLR curved portion 42A is an arc having the same center of curvature as the center of curvature of the inner edge of the corresponding first electrode curved portion 105A.
  • a portion of the wide portion 211 at both ends is physically and electrically connected to the wide portion 221 at both ends of the corresponding FLR curved portion 42A via the FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • a portion of the center of the length of the wide portion 211 is physically and electrically connected to the center of the length of the wide portion 221 of the corresponding FLR curved portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • the FLR connection electrodes 89 are not formed on the portions (electrode straight portions 105B) of the multiple FLR electrodes 105 other than the electrode curve portions 105A. Note that the FLR connection electrodes 89 may be formed on the electrode straight portions 105B of the multiple FLR electrodes 105. The FLR connection electrodes 89 may be formed integrally with the corresponding FLR electrodes 105 (electrode curve portions 105A).
  • the multiple FLR connection electrodes 89 have a circular shape in a planar view.
  • the multiple FLR connection electrodes 89 may have a polygonal shape such as a square shape in a planar view, or may have an elliptical shape in a planar view.
  • the multiple FLR connection electrodes 89 are formed in an electrically floating state.
  • the FLR 42, FLR electrode 105, and FLR connection electrode 89 in the first corner portion 201 have planar shapes that are symmetrical to their planar shapes in the second corner portion 202 with respect to a straight line that passes through the center of the chip 2 in the first direction X and extends in the second direction Y.
  • the FLR 42, the FLR electrode 105, and the FLR connection electrode 89 at the third corner portion 203 have planar shapes that are symmetrical to their planar shapes at the second corner portion 202 with respect to a straight line that passes through the center of the chip 2 in the second direction Y and extends in the first direction X.
  • the FLR 42, FLR electrode 105, and FLR connection electrode 89 at the fourth corner portion 204 have planar shapes that are symmetrical to their planar shapes at the third corner portion 203 with respect to a straight line that passes through the center of the chip 2 in the first direction X and extends in the second direction Y.
  • each FLR curved portion 42A may have a different shape from the corresponding electrode curved portion 105A.
  • FIG. 27 is a schematic plan view showing the structure of the FLR 42, FLR electrode 108, and FLR connection electrode 89 at the second corner portion 202.
  • the planar shape of the multiple electrode curved portions 105A is the same as the planar shape in FIG. 25.
  • the centers of curvature of the inner edge 42Aa, the outer edge 42Ab, and the diffusion region boundary line BL of the multiple FLR curved portions 42A are the same. Specifically, these centers of curvature are Q2.
  • the electrode curved portions 105A and the FLR curved portions 42A have structures similar to those of the second corner 202.
  • the width of the first diffusion region 301 of each FLR curve portion 42A is constant in the length direction, and the width of the second diffusion region 302 is constant in the length direction.
  • the inner edge 42Aa and the outer edge 42Ab of the innermost and third innermost FLR curved portion 42A have the same center of curvature as the center of curvature of the outer edge 105Ab of the corresponding first electrode curved portion 105A.
  • the inner edge 42Aa and the outer edge 42Ab of the second innermost and outermost FLR curved portion 42A have the same center of curvature as the center of curvature of the inner edge 105Aa of the corresponding first electrode curved portion 105A.
  • the planar shape of the FLR 42, the FLR electrode 105, and the FLR connection electrode 89 in the second corner portion 202 may be as shown in FIG. 28.
  • parts corresponding to those in FIG. 25 are denoted by the same reference numerals as in FIG. 25.
  • each electrode curved portion 105A in FIG. 28 is substantially the same as the structure of the corresponding electrode curved portion 105A in FIG. 25, but the positions of both ends of each electrode curved portion 105A are different from the positions of both ends of the corresponding electrode curved portion 105A in FIG. 25.
  • the angle between the line connecting one end of the inner edge 105Aa of each electrode curved portion 105A and the center of curvature of the inner edge 105Aa and the angle between the line connecting one end of the outer edge 105Ab of each electrode curved portion 105A and the center of curvature of the outer edge 105Ab and the dividing line L0 are set so that the width of one end of each electrode curved portion 105A is a predetermined width W1.
  • the angle between the line connecting the other end of the inner edge 105Aa of each electrode curved portion 105A and the center of curvature of the inner edge 105Aa and the angle between the line connecting the other end of the outer edge 105Ab of each electrode curved portion 105A and the center of curvature of the outer edge 105Ab and the dividing line L0 are set so that the width of the other end of each electrode curved portion 105A is a predetermined width W1.
  • the width of the straight electrode portions 105B connected to both ends of each curved electrode portion 105A is also formed to a predetermined width W1.
  • each FLR curve portion 42A in FIG. 28 is substantially the same as the structure of the corresponding FLR curve portion 42A in FIG. 25, but the positions of both ends of each FLR curve portion 42A are different from the positions of both ends of the corresponding FLR curve portion 42A in FIG. 25.
  • the angle between the line connecting one end of the inner edge 42Aa of each FLR curved portion 42A and the center of curvature of the inner edge 42Aa and the dividing line L0, and the angle between the line connecting one end of the outer edge 42Ab of each FLR curved portion 42A and the center of curvature of the outer edge 42Ab and the dividing line L0 are set so that the width of one end of each FLR curved portion 42A is a predetermined width.
  • the angle between the line connecting the other end of the inner edge 42Aa of each FLR curved portion 42A and the center of curvature of the inner edge 42Aa and the dividing line L0, and the angle between the line connecting the other end of the outer edge 42Ab of each FLR curved portion 42A and the center of curvature of the outer edge 42Ab and the dividing line L0 are set so that the width of the other end of each FLR curved portion 42A is a predetermined width.
  • the width of the FLR straight line portion 42B connected to both ends of each FLR curved portion 42A is equal to the width of the corresponding end of the first diffusion region 301 of that FLR curved portion 42A.
  • the diffusion region boundary line BL of each FLR curved portion 42A has the same center of curvature as the center of curvature of the inner edge 42Aa of the FLR curved portion 42A. Note that the diffusion region boundary line BL of each FLR curved portion 42A may have the same center of curvature as the center of curvature of the outer edge 42Ab of the FLR curved portion 42A.
  • the width of the electrode straight portion 105B of the FLR electrode 105 narrower than the width required to connect the electrode straight portion 105B to the FLR 42 via the FLR connection electrode 89. This makes it possible to narrow the overall width of the multiple FLR electrodes 105, thereby enabling the chip to be made smaller.
  • each FLR curved portion 42A may have a different shape from the corresponding electrode curved portion 105A.
  • FIG. 29 is a schematic plan view showing the structure of the FLR 42, FLR electrode 108, and FLR connection electrode 89 at the second corner portion 202.
  • the planar shape of the multiple electrode curved portions 105A is the same as the planar shape in FIG. 28.
  • the centers of curvature of the inner edge 42Aa, the outer edge 42Ab, and the diffusion region boundary line BL of the multiple FLR curved portions 42A are the same. Specifically, these centers of curvature are Q2.
  • the width of the first diffusion region 301 of each FLR curve portion 42A is constant in the length direction, and the width of the second diffusion region 302 is constant in the length direction.
  • the inner edge 42Aa and the outer edge 42Ab of the innermost and third innermost FLR curved portion 42A have the same center of curvature as the center of curvature of the outer edge 105Ab of the corresponding first electrode curved portion 105A.
  • the inner edge 42Aa and the outer edge 42Ab of the second innermost and outermost FLR curved portion 42A have the same center of curvature as the center of curvature of the inner edge 105Aa of the corresponding first electrode curved portion 105A.
  • the electrode curved portions 105A and the FLR curved portions 42A have structures similar to those of the second corner 202.
  • FIGS. 30A to 30D are schematic plan views for explaining further modified examples of the FLR 42, the FLR electrode 105, and the FLR connection electrode 89, and are schematic plan views mainly showing the structure of the four corner portions 201 to 204 of the peripheral region 9.
  • FIG. 31 is a schematic cross-sectional view taken along line XXXI-XXXI shown in FIG. 30B.
  • configurations other than the FLR 42 and the FLR electrode 105 are omitted in FIG. 30A to 30D.
  • the channel stop electrode 106 is shown in FIG. 31.
  • each FLR 42 is each formed in an annular shape (square annular shape) in the outer peripheral region 9 so as to surround the active region 6.
  • each FLR 42 has an FLR curved portion 42A whose inner edge 42Aa and outer edge 42Ab have a circular arc shape in plan view.
  • each FLR 42 has an FLR straight portion 42B whose shape in plan view is straight.
  • Each FLR curved portion 42A has a double diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 having a lower p-type impurity concentration than the first diffusion region 301.
  • Each FLR straight portion 42B has a single diffusion structure consisting of only a diffusion region having the same p-type impurity concentration as the first diffusion region 301.
  • the multiple FLR electrodes 105 are each formed in a band shape extending along the corresponding FLR 42.
  • the multiple FLR electrodes 105 are each formed in a ring shape (square ring shape) extending along the corresponding FLR 42.
  • the multiple FLR electrodes 105 are formed in an electrically floating state.
  • the multiple FLR electrodes 105 face the corresponding FLRs 42 via a laminated film of the main surface insulating film 45 and the interlayer insulating film 74. In this modified example, the multiple FLR electrodes 105 cover the corresponding FLRs 42.
  • Each FLR electrode 105 has an electrode curved portion 105A at each corner 201-204, the inner and outer edges of which have a circular arc shape in plan view.
  • Each FLR electrode 105 has an electrode straight portion 105B between the four corners 201-204, the inner and outer edges of which have a straight line shape in plan view.
  • the center of curvature of the inner edge 105Aa and the outer edge 105Ab of each electrode curved portion 105A at each corner 201-204 is located on a dividing line L0, which is a straight line that divides the apex angle of the corner 201-204 in half.
  • the multiple electrode straight portions 105B between the corners 201-204 have the same width and the same spacing.
  • the center of curvature of the inner edge 42Aa and the outer edge 42Ab of each FLR curved portion 42A at each corner 201-204 is located on a dividing line L0, which is a straight line that divides the apex angle of the corner 201-204 in half.
  • the multiple FLR straight portions 42B between the corner portions 201-204 have the same width and the same spacing.
  • both side edges of the multiple FLR straight portions 42B between the corner portions 201-204 are set back inward from the corresponding side edges of the corresponding electrode straight portions 105B in a plan view. Therefore, in this embodiment, the width of the FLR straight portions 42B is narrower than the width of the corresponding electrode straight portions 105B.
  • a structure in which the inner edge 105Aa and the outer edge 105Ab of the four electrode curved portions 105A at each corner portion 201-204 have the same center of curvature, and the width and spacing of these electrode curved portions 105A are the same as the width and spacing of the corresponding four electrode straight portions 105B, will be referred to as a basic electrode corner structure.
  • a structure in which the inner edge 42Aa and the outer edge 42Ab of the four FLR curved portions 42A at each corner portion 201, 202, 203, and 204 have the same center of curvature, and the width and spacing of these FLR curved portions 42A are each constant, is referred to as a basic FLR corner structure.
  • the electrode curved portion 105A of the multiple FLR electrodes 105 is physically and electrically connected to the FLR curved portion 42A of the corresponding FLR 42 via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45 at a connection position that is predetermined for each FLR electrode 105.
  • the innermost electrode curve portion 105A of the four electrode curve portions 105A has a structure different from the corresponding electrode curve portion of the basic electrode corner structure.
  • the other three electrode curve portions 105A have the same structure as the corresponding electrode curve portion of the basic electrode corner structure.
  • the center of curvature of the inner edge 105Aa and the outer edge 105Ab of the second, third and outermost electrode curved portions 105A from the inside is Q1.
  • the widths of these electrode curved portions 105A are equal.
  • the widths of these electrode curved portions 105A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 105Aa of the innermost electrode curved portion 105A is Q2, and the center of curvature of the outer edge 105Ab is Q1, and the curvature of the inner edge 105Aa is different from the curvature of the outer edge 105Ab.
  • the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.
  • the radius of curvature of the inner edge 105Aa is larger than the radius of curvature of the outer edge 105Ab.
  • the width of the innermost curved electrode portion 105A varies depending on its position in the longitudinal direction. Specifically, the width of the innermost curved electrode portion 105A is widest at the center of its length and narrows from the center to both ends.
  • the innermost electrode curved portion 105A has a wide portion 211 that is wider than the width of the corresponding electrode curved portion 105A at the three corners 202, 203, and 204 other than the first corner 201.
  • the middle portion of the length of the innermost electrode curved portion 105A is the wide portion 211.
  • the curvature of the inner edge 105Aa of the innermost electrode curved portion 105A is set so that the width of both ends of the electrode curved portion 105A matches the width of the electrode straight portion 105B.
  • the innermost of the four FLR curved portions 42A has a structure different from the corresponding FLR curved portion of the basic FLR corner structure.
  • the other three FLR curved portions 42A have the same structure as the corresponding FLR curved portions of the basic FLR corner structure.
  • the centers of curvature of the inner edge 42Aa and the outer edge 42Ab of the second, third and outermost FLR curved portions 42A from the inside are Q1.
  • the widths of these FLR curved portions 42A are equal.
  • the widths of these FLR curved portions 42A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 42Aa of the innermost FLR curved portion 42A is Q2, and the center of curvature of the outer edge 42Ab is Q1, and the curvature of the inner edge 42Aa is different from the curvature of the outer edge 42Ab.
  • the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.
  • the radius of curvature of the inner edge 42Aa is larger than the radius of curvature of the outer edge 42Ab.
  • the width of the innermost FLR curved portion 42A varies depending on its position in the longitudinal direction. Specifically, the width of the innermost FLR curved portion 42A is widest at the center of its length and narrows from the center to both ends.
  • the innermost FLR curved portion 42A has a wide portion 221 that is larger than the width of the corresponding FLR curved portion 42A at the three corners 202, 203, and 204 other than the first corner 201.
  • the middle portion of the length of the innermost FLR curved portion 42A is the wide portion 221.
  • the width of the first diffusion region 301 of the first diffusion region 301 and the second diffusion region 302 of the innermost FLR curve portion 42A is constant in the length direction.
  • planar shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the innermost FLR curved portion 42A is an arc having the same center of curvature as the center of curvature of the inner edge of the corresponding first electrode curved portion 105A.
  • both side edges of each FLR curved portion 42A are set back further inward from the corresponding side edges of the corresponding electrode curved portion 105A.
  • the width of each longitudinal position of each FLR curved portion 42A is narrower than the width of the corresponding longitudinal position of the corresponding electrode curved portion 105A.
  • a part of the wide portion 211 of the innermost electrode curved portion 105A is physically and electrically connected to the corresponding wide portion 221 of the FLR curved portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • the second electrode curved portion 105A from the inside has a structure different from the corresponding electrode curved portion of the basic electrode corner structure.
  • the other three electrode curved portions 105A have the same structure as the corresponding electrode curved portions of the basic electrode corner structure.
  • the center of curvature of the inner edge 105Aa and the outer edge 105Ab of the innermost electrode curved portion 105A, the third innermost electrode curved portion 105A, and the outermost electrode curved portion 105A is Q3.
  • the widths of these electrode curved portions 105A are equal.
  • the widths of these electrode curved portions 105A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 105Aa of the second inner curved electrode portion 105A is Q4, and the center of curvature of the outer edge 105Ab is Q3, and the curvature of the inner edge 105Aa is different from the curvature of the outer edge 105Ab.
  • the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.
  • the radius of curvature of the inner edge 105Aa is larger than the radius of curvature of the outer edge 105Ab.
  • the width of the second innermost electrode curved portion 105A varies depending on its longitudinal position. Specifically, the width of the second innermost electrode curved portion 105A is widest at the longitudinal center and narrows from the longitudinal center toward both ends.
  • the second innermost electrode curved portion 105A has a wide portion 211 that is wider than the widths of the corresponding electrode curved portions 105A at the three corners 201, 203, and 204 other than the second corner 202.
  • the middle portion of the length of the second innermost electrode curved portion 105A is the wide portion 211.
  • the curvature of the inner edge 105Aa of the second inner curved electrode portion 105A is set so that the width of both ends of the curved electrode portion 105A matches the width of the straight electrode portion 105B.
  • the second FLR curved portion 42A from the inside has a structure different from the corresponding FLR curved portion of the basic FLR corner structure.
  • the other three FLR curved portions 42A have the same structure as the corresponding FLR curved portions of the basic FLR corner structure.
  • the center of curvature of the inner edge 42Aa and the outer edge 42Ab of the innermost FLR curved portion 42A, the third innermost FLR curved portion 42A, and the outermost FLR curved portion 42A is Q3.
  • the widths of these FLR curved portions 42A are equal.
  • the widths of these FLR curved portions 42A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 42Aa of the second innermost FLR curved portion 42A is Q4, and the center of curvature of the outer edge 42Ab is Q3, and the curvature of the inner edge 42Aa is different from the curvature of the outer edge 42Ab.
  • the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.
  • the radius of curvature of the inner edge 42Aa is larger than the radius of curvature of the outer edge 42Ab.
  • the width of the second innermost FLR curved portion 42A varies depending on its longitudinal position. Specifically, the width of the second innermost FLR curved portion 42A is widest at the longitudinal center and narrows from the longitudinal center toward both ends.
  • the second innermost FLR curved portion 42A has a wide portion 221 that is wider than the widths of the corresponding FLR curved portions 42A at the three corners 201, 203, and 204 other than the second corner 202.
  • the intermediate portion of the length of the second innermost FLR curved portion 42A is the wide portion 221.
  • the width of the first diffusion region 301 of the first diffusion region 301 and the second diffusion region 302 of the second innermost FLR curve portion 42A is constant in the length direction.
  • planar shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the second innermost FLR curved portion 42A is an arc having the same center of curvature as the center of curvature of the inner edge of the corresponding first electrode curved portion 105A.
  • both side edges of each FLR curved portion 42A are set back further inward from the corresponding side edges of the corresponding electrode curved portion 105A.
  • the width of each FLR curved portion 42A at each longitudinal position is narrower than the width of the corresponding electrode curved portion 105A at the corresponding longitudinal position.
  • a part of the wide portion 211 of the second innermost electrode curved portion 105A is physically and electrically connected to the corresponding wide portion 221 of the FLR curved portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • the third electrode curved portion 105A from the inside has a structure different from the corresponding electrode curved portion of the basic electrode corner structure.
  • the other three electrode curved portions 105A have the same structure as the corresponding electrode curved portions of the basic electrode corner structure.
  • the center of curvature of the inner edge 105Aa and the outer edge 105Ab of the innermost electrode curved portion 105A, the second innermost electrode curved portion 105A, and the outermost electrode curved portion 105A is Q5.
  • the widths of these electrode curved portions 105A are equal.
  • the widths of these electrode curved portions 105A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 105Aa of the third inner curved electrode portion 105A is Q6, and the center of curvature of the outer edge 105Ab is Q5, and the curvature of the inner edge 105Aa is different from the curvature of the outer edge 105Ab.
  • the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.
  • the radius of curvature of the inner edge 105Aa is larger than the radius of curvature of the outer edge 105Ab.
  • the width of the third innermost electrode curved portion 105A varies depending on its longitudinal position. Specifically, the width of the third innermost electrode curved portion 105A is widest at the longitudinal center and narrows from the longitudinal center toward both ends.
  • the third innermost electrode curved portion 105A has a wide portion 211 that is wider than the widths of the corresponding electrode curved portions 105A at the three corners 201, 202, and 204 other than the third corner 203.
  • the middle portion of the length of the third innermost electrode curved portion 105A is the wide portion 211.
  • the curvature of the inner edge 105Aa of the third inner curved electrode portion 105A is set so that the width of both ends of the curved electrode portion 105A matches the width of the straight electrode portion 105B.
  • the third FLR curve portion 42A from the inside of the four FLR curve portions 42A has a structure different from the corresponding FLR curve portion of the basic FLR corner structure.
  • the other three FLR curve portions 42A have the same structure as the corresponding FLR curve portions of the basic FLR corner structure.
  • the center of curvature of the inner edge 42Aa and the outer edge 42Ab of the innermost FLR curved portion 42A, the second innermost FLR curved portion 42A, and the outermost FLR curved portion 42A is Q5.
  • the widths of these FLR curved portions 42A are equal.
  • the widths of these FLR curved portions 42A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 42Aa of the third innermost FLR curved portion 42A is Q6, and the center of curvature of the outer edge 42Ab is Q5, and the curvature of the inner edge 42Aa is different from the curvature of the outer edge 42Ab.
  • the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.
  • the radius of curvature of the inner edge 42Aa is larger than the radius of curvature of the outer edge 42Ab.
  • the width of the third innermost FLR curved portion 42A varies depending on its longitudinal position. Specifically, the width of the third innermost FLR curved portion 42A is widest at the longitudinal center and narrows from the longitudinal center toward both ends.
  • the third FLR curved portion 42A from the inside has a wide portion 221 that is wider than the widths of the corresponding FLR curved portions 42A of the three corners 201, 202, and 204 other than the third corner 203.
  • the middle portion of the length of the third FLR curved portion 42A from the inside is the wide portion 221.
  • the width of the first diffusion region 301 of the first diffusion region 301 and the second diffusion region 302 of the third innermost FLR curve portion 42A is constant in the length direction.
  • planar shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the third innermost FLR curved portion 42A is an arc having the same center of curvature as the center of curvature of the inner edge of the corresponding first electrode curved portion 105A.
  • both side edges of each FLR curved portion 42A are set back further inward from the corresponding side edges of the corresponding electrode curved portion 105A.
  • the width of each FLR curved portion 42A at each longitudinal position is narrower than the width of the corresponding electrode curved portion 105A at the corresponding longitudinal position.
  • a portion of the wide portion 211 of the third innermost electrode curved portion 105A is physically and electrically connected to the corresponding wide portion 221 of the FLR curved portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • the outermost electrode curve portion 105A of the four electrode curve portions 105A has a structure different from the corresponding electrode curve portion of the basic electrode corner structure.
  • the other three electrode curve portions 105A have the same structure as the corresponding electrode curve portion of the basic electrode corner structure.
  • the center of curvature of the inner edge 105Aa and the outer edge 105Ab of the innermost electrode curved portion 105A and the second and third innermost electrode curved portions 105A is Q7.
  • the widths of these electrode curved portions 105A are equal.
  • the widths of these electrode curved portions 105A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 105Aa of the outermost electrode curved portion 105A is Q8, and the center of curvature of the outer edge 105Ab is Q7, and the curvature of the inner edge 105Aa is different from the curvature of the outer edge 105Ab.
  • the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.
  • the radius of curvature of the inner edge 105Aa is larger than the radius of curvature of the outer edge 105Ab.
  • the width of the outermost electrode curved portion 105A varies depending on its position in the longitudinal direction. Specifically, the width of the outermost electrode curved portion 105A is widest at the center of its length and narrows from the center to both ends.
  • the outermost electrode curved portion 105A has a wide portion 211 that is wider than the width of the corresponding electrode curved portion 105A at the three corners 201, 202, and 203 other than the fourth corner 204.
  • the intermediate portion of the length of the outermost electrode curved portion 105A is the wide portion 211.
  • the curvature of the inner edge 105Aa of the outermost electrode curved portion 105A is set so that the width of both ends of the electrode curved portion 105A matches the width of the electrode straight portion 105B.
  • the outermost FLR curve portion 42A of the four FLR curve portions 42A has a structure different from the corresponding FLR curve portion of the basic FLR corner structure.
  • the other three FLR curve portions 42A have the same structure as the corresponding FLR curve portions of the basic FLR corner structure.
  • the center of curvature of the inner edge 42Aa and the outer edge 42Ab of the innermost FLR curved portion 42A and the second and third FLR curved portions 42A from the inside is Q7.
  • the widths of these FLR curved portions 42A are equal.
  • the widths of these FLR curved portions 42A are constant regardless of their longitudinal positions.
  • the center of curvature of the inner edge 42Aa of the outermost FLR curved portion 42A is Q8, and the center of curvature of the outer edge 42Ab is Q7, and the curvature of the inner edge 42Aa is different from the curvature of the outer edge 42Ab.
  • the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.
  • the radius of curvature of the inner edge 42Aa is larger than the radius of curvature of the outer edge 42Ab.
  • the width of the outermost FLR curved portion 42A varies depending on its position in the longitudinal direction. Specifically, the width of the outermost FLR curved portion 42A is widest at the center of its length and narrows from the center to both ends.
  • the outermost FLR curved portion 42A has a wide portion 221 that is wider than the width of the corresponding FLR curved portion 42A at the three corners 201, 202, and 203 other than the fourth corner 204.
  • the middle portion of the length of the outermost FLR curved portion 42A is the wide portion 221.
  • the width of the first diffusion region 301 of the first diffusion region 301 and the second diffusion region 302 of the outermost FLR curve portion 42A is constant in the length direction.
  • planar shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the outermost FLR curved portion 42A is an arc having the same center of curvature as the center of curvature of the inner edge of the corresponding first electrode curved portion 105A.
  • both side edges of each FLR curved portion 42A are set back further inward from the corresponding side edges of the corresponding electrode curved portion 105A.
  • the width of each FLR curved portion 42A at each longitudinal position is narrower than the width of the corresponding electrode curved portion 105A at the corresponding longitudinal position.
  • a portion of the wide portion 211 of the outermost electrode curved portion 105A is physically and electrically connected to the corresponding wide portion 221 of the FLR curved portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.
  • the multiple FLR connection electrodes 89 have a circular shape in a planar view.
  • the multiple FLR connection electrodes 89 may have a polygonal shape such as a square shape in a planar view, or may have an elliptical shape in a planar view.
  • the multiple FLR connection electrodes 89 are formed in an electrically floating state.
  • each FLR curved portion 42A is the inner edge of the first diffusion region 301 of that FLR curved portion 42A.
  • the outer edge 42Ab of each FLR curved portion 42A is the outer edge of the second diffusion region 302 of that FLR curved portion 42A.
  • a diffusion region boundary line BL is formed in the middle of the width between the inner edge 42Aa and the outer edge 42Ab of the FLR curved portion 42A.
  • the diffusion region boundary line BL of each FLR curved portion 42A has the same center of curvature as the center of curvature of the inner edge 42Aa of the FLR curved portion 42A.
  • the diffusion region boundary line BL of each FLR curved portion 42A may have the same center of curvature as the center of curvature of the outer edge 42Ab of the FLR curved portion 42A.
  • both side edges of the multiple FLR curved portions 42A are set back inward from the corresponding side edges of the corresponding electrode curved portion 105A in a plan view. Therefore, in this embodiment, the width of the FLR curved portion 42A is narrower than the width of the corresponding electrode straight portion 105B.
  • each FLR curved portion 42A may be located further outward than the inner edge 105Aa of the corresponding electrode curved portion 105A.
  • the outer edge 42Ab of each FLR curved portion 42A may be located further outward than the outer edge 105Ab of the corresponding electrode curved portion 105A.
  • each FLR curved portion 42A may extend outward from the inner edge 105Aa of the corresponding electrode curved portion 105A.
  • only the inner edge of each FLR straight portion 42B may extend outward from the inner edge of the corresponding electrode straight portion 105B.
  • each FLR curved portion 42A may extend outward from the outer edge 105Ab of the corresponding electrode curved portion 105A.
  • only the outer edge of each FLR straight portion 42B may extend outward from the outer edge of the corresponding electrode straight portion 105B.
  • Both the inner edge 105Aa and the outer edge 42Ab of the inner edge 42Aa of each FLR curved portion 42A may be located outward of the corresponding side edges 105Aa, 105Ab of the corresponding electrode curved portion 105A.
  • both the inner edge and the outer edge of each FLR straight portion 42B may be located outward of the corresponding outer edge of the corresponding electrode straight portion 105B.
  • the electrode curved portion 105A connected to the FLR 42 via the FLR connection electrode 89 has a smaller curvature of its inner edge 105Aa than the curvature of its outer edge 105Ab, but the curvature of the inner edge 105Aa may be larger than the curvature of the outer edge 105Ab.
  • the width of the electrode curved portion 105A connected to the FLR 42 via the FLR connection electrode 89 increases from the center of its length toward both ends.
  • the electrode curved portion 105A connected to the FLR 42 via the FLR connection electrode 89 may have wide portions 211 at both ends. In that case, a portion of at least one of the wide portions 211 at both ends of the electrode curved portion 105A may be connected to the FLR 42 via the FLR connection electrode 89.
  • the width of the electrode straight portion 105B of the FLR electrode 105 narrower than the width required to connect the electrode straight portion 105B to the FLR 42 via the FLR connection electrode 89. This makes it possible to narrow the overall width of the multiple FLR electrodes 105, thereby enabling the chip to be made smaller.
  • the four pairs of FLRs 42 and their corresponding FLR electrodes 105 satisfy the following first and second conditions.
  • the first condition is that the pair in which the electrode curved portion 105A is connected to the FLR 42 via the FLR connection electrode 89 at each of the four corners 201 to 204 is different for each of the four corners 201 to 204.
  • the second condition is that one electrode curved portion 105A connected to the FLR curved portion 42A via the FLR connection electrode 89 at each corner 201-204 has a wide portion 211 that is wider than the electrode curved portion 105A at the other three corners, and a part of the wide portion 211 is physically and electrically connected to the corresponding FLR 42 via the FLR connection electrode 89.
  • one electrode curved portion 105A connected to the FLR 42 via the FLR connection electrode 89 at each corner portion 201-204 has an inner edge 105Aa and an outer edge 105Ab whose centers of curvature and curvatures are different.
  • the four pairs mentioned above further satisfy a fourth condition that the center of curvature of the inner edge 105Aa and the center of curvature of the outer edge 105Ab of one electrode curved portion 105A connected to the FLR 42 via the FLR connection electrode 89 at each corner 201-204 are located at different positions on the dividing line L0, which is a straight line that divides the apex angle of the corner into 1/2, and the radius of curvature of the inner edge 105Aa is different from the radius of curvature of the outer edge 105Ab.
  • an FLR curved portion 42A to which the electrode curved portion 105A is connected via an FLR connection electrode 89 at each corner portion 201-204 has an inner edge 42Aa and an outer edge 42Ab whose centers of curvature and curvatures are different.
  • the four pairs mentioned above further satisfy the sixth condition that the center of curvature of the inner edge 42Aa and the center of curvature of the outer edge 42Ab of one FLR curved portion 42A to which the electrode curved portion 105A is connected via the FLR connection electrode 89 at each corner portion 201-204 are located at different positions on the dividing line L0, which is a straight line that divides the apex angle of the corner portion in half, and the radius of curvature of the inner edge 42Aa is different from the radius of curvature of the outer edge 42Ab.
  • the semiconductor device 1A may have four pairs of FLRs 42 and FLR electrodes 150 that satisfy the first and second conditions described above. These four pairs may also satisfy the third condition. These four pairs may also satisfy the fourth condition. These four pairs may also satisfy the fifth condition. These four pairs may also satisfy the sixth condition.
  • FIG. 32 is a schematic plan view showing the structure of the FLR 42, FLR electrode 105, and FLR connection electrode 89 in the second corner 202.
  • the planar shape of the multiple electrode curved portions 105A is the same as the planar shape in FIG. 30B.
  • the inner edge 42Aa, the outer edge 42Ab, and the diffusion region boundary line BL of the second innermost FLR curved portion 42A have the same center of curvature. Specifically, in the second corner portion 202, these centers of curvature are Q3.
  • the inner edge 42Aa, outer edge 42Ab, and diffusion region boundary line BL of the FLR curved portion 42A connected to the electrode curved portion 105A via the FLR connection electrode 89 have the same center of curvature as the center of curvature of the corresponding inner edge 105Aa of the electrode curved portion 105A.
  • the inner edge 42Aa, the outer edge 42Ab, and the diffusion region boundary line BL of the FLR curved portion 42A connected to the electrode curved portion 105A via the FLR connection electrode 89 may have the same center of curvature as the center of curvature of the corresponding outer edge 105Ab of the electrode curved portion 105A.
  • the width of the first diffusion region 301 of the FLR curve portion 42A connected to the electrode curve portion 105A via the FLR connection electrode 89 is constant in the length direction
  • the width of the second diffusion region 302 is constant in the length direction.
  • the inner edge 42Aa and outer edge 42Ab of the FLR curved portion 42A connected to the electrode curved portion 105A via the FLR connection electrode 89 have the same center of curvature as the center of curvature of the outer edge 105Ab of the corresponding first electrode curved portion 105A.
  • the present disclosure can also be implemented in other forms.
  • the chip 2 is made of a silicon single crystal substrate.
  • the chip 2 may also be made of a SiC (silicon carbide) single crystal substrate.
  • the n-type semiconductor region may be replaced with a p-type semiconductor region
  • the p-type semiconductor region may be replaced with an n-type semiconductor region.
  • a p-type collector region 14 is shown.
  • an n-type drain region may be used instead of the p-type collector region 14.
  • the buffer region 13 is omitted.
  • the n-type drain region may be formed by an n-type semiconductor substrate, and the n-type drift region 12 may be formed by an n-type epitaxial layer. It is preferable that the n-type impurity concentration of the drift region 12 is less than the n-type impurity concentration of the drain region.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the first direction X and the second direction Y are defined by the extension directions of the first to fourth side faces 5A to 5D.
  • the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically perpendicular) relationship.
  • the first direction X may be the extension direction of the third side face 5C (fourth side face 5D)
  • the second direction Y may be the extension direction of the first side face 5A (second side face 5B).
  • the first direction X may be a direction intersecting the first to fourth side faces 5A to 5D
  • the second direction Y may be a direction intersecting the first to fourth side faces 5A to 5D.
  • a chip (2) having a first main surface (3) having a rectangular shape in a plan view and a second main surface (4) opposite to the first main surface (3); An active region (6) provided on the first main surface (3) and having an element structure formed therein; a peripheral region (9) that is a region outside the active region (6), the peripheral region (9) being provided on the outer periphery of the first main surface (3) and having four corner portions (201 to 204); A drift region of a first conductivity type formed inside the chip (2); In the peripheral region (9), a plurality of second conductivity type field limiting rings (hereinafter referred to as "FLR (42)”) are formed in a surface layer portion of the first main surface (3) so as to surround the active region (6), Each of the FLRs (42) has an FLR curve portion (42A) having a curved shape in a plan view at each of the four corner portions (201 to 204), Each of the FLRs (42) has an FLR straight portion (42B) having a straight line shape in a plan view between
  • each of the FLR straight portions (42B) has a single diffusion structure consisting of only a diffusion region having the same second conductivity type impurity concentration as the first diffusion region (301).
  • each of the FLR curved portions (42A) has an inner edge (42Aa) and an outer edge (42Ab) whose planar shape is an arc
  • each of the FLR electrodes (105) has an electrode curved portion (105A) whose inner edge and outer edge have a planar shape of a circular arc at each of the corner portions (201 to 204), In each of the corners (201 to 204), the centers of curvature of the inner edge (105Aa) and the outer edge (105Ab) of each of the electrode curved portions (105A) are located on a dividing line (L0) that is a straight line dividing the apex angle of the corner (201 to 204) in half,
  • L0 dividing line
  • the first electrode curved portion (105A) has a wide region and a narrow region between its inner edge (105Aa) and outer edge (105Ab),
  • the semiconductor device according to [A7], wherein a portion of the larger width region in the first electrode curved portion (105A) is connected to the corresponding FLR (42) via the FLR connection electrode (89) penetrating the insulating film (45, 74).
  • the inner edge (42Aa) of the FLR curved portion (42A) corresponding to the first electrode curved portion (105A) has the same center of curvature as the inner edge (105Aa) of the first electrode curved portion (105A);
  • the semiconductor device according to [7], wherein an outer edge (42Ab) of the FLR curve portion (42A) corresponding to the first electrode curve portion (105A) has a center of curvature that is the same as the center of curvature of the outer edge (105Ab) of the first electrode curve portion (105A).
  • [A15] A semiconductor device according to any one of [A7] to [A14], in which the FLR connection electrode (89) for electrically connecting the first electrode curved portion (105A) to the corresponding FLR (42) is integrally formed with the first electrode curved portion (105A).
  • a channel stop region is formed in a surface layer portion of the first main surface (3) so as to surround the plurality of FLRs (42) and is covered with the insulating film (45, 74);
  • a semiconductor device according to any one of [A1] to [A16], in which the element structure includes an IGBT structure.
  • a second conductivity type channel region (20) is formed in a surface layer portion of the first main surface (3);

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004643A (ja) * 2006-06-20 2008-01-10 Toshiba Corp 半導体装置
JP2008193043A (ja) * 2007-01-11 2008-08-21 Fuji Electric Device Technology Co Ltd 電力用半導体素子
JP2009289904A (ja) * 2008-05-28 2009-12-10 Toshiba Corp 半導体装置
JP2015076437A (ja) * 2013-10-07 2015-04-20 三菱電機株式会社 半導体装置およびその製造方法
JP2017504964A (ja) * 2013-12-16 2017-02-09 アーベーベー・テクノロジー・アーゲー 半導体装置のエッジ終端および対応する製造方法
CN106409884A (zh) * 2016-11-07 2017-02-15 株洲中车时代电气股份有限公司 一种功率半导体器件终端结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004643A (ja) * 2006-06-20 2008-01-10 Toshiba Corp 半導体装置
JP2008193043A (ja) * 2007-01-11 2008-08-21 Fuji Electric Device Technology Co Ltd 電力用半導体素子
JP2009289904A (ja) * 2008-05-28 2009-12-10 Toshiba Corp 半導体装置
JP2015076437A (ja) * 2013-10-07 2015-04-20 三菱電機株式会社 半導体装置およびその製造方法
JP2017504964A (ja) * 2013-12-16 2017-02-09 アーベーベー・テクノロジー・アーゲー 半導体装置のエッジ終端および対応する製造方法
CN106409884A (zh) * 2016-11-07 2017-02-15 株洲中车时代电气股份有限公司 一种功率半导体器件终端结构

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