WO2024190271A1 - 半導体デバイス - Google Patents

半導体デバイス Download PDF

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Publication number
WO2024190271A1
WO2024190271A1 PCT/JP2024/005544 JP2024005544W WO2024190271A1 WO 2024190271 A1 WO2024190271 A1 WO 2024190271A1 JP 2024005544 W JP2024005544 W JP 2024005544W WO 2024190271 A1 WO2024190271 A1 WO 2024190271A1
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WIPO (PCT)
Prior art keywords
bonding
semiconductor
semiconductor element
semiconductor device
dummy
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Ceased
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PCT/JP2024/005544
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English (en)
French (fr)
Japanese (ja)
Inventor
利裕 宇佐
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Fujifilm Corp
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Fujifilm Corp
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Priority to JP2025506614A priority Critical patent/JPWO2024190271A1/ja
Priority to CN202480007896.8A priority patent/CN120548616A/zh
Publication of WO2024190271A1 publication Critical patent/WO2024190271A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present invention relates to a semiconductor device in which multiple semiconductor elements are stacked and electrically connected, and in particular to a semiconductor device that bonds semiconductor elements having bonding contacts that electrically connect the semiconductor elements together and dummy bonding contacts that do not electrically connect the semiconductor elements together.
  • Hybrid bonding is one method of joining semiconductor elements together, or between a semiconductor element and a substrate, etc.
  • Patent Document 1 and Patent Document 2 disclose a hybrid-bonded semiconductor device.
  • the semiconductor device of Patent Document 1 includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between a first bonding layer and a second bonding layer.
  • the first semiconductor structure includes a first interconnect layer including a first interconnect portion, and a first bonding layer including a first bonding contact. At least one of the first interconnect portions is a first dummy interconnect portion. Each of the first interconnect portions is in contact with a respective first bonding contact.
  • the second semiconductor structure includes a second interconnect layer including a second interconnect portion, and a second bonding layer including a second bonding contact. At least one of the second interconnect portions is a second dummy interconnect portion. Each of the second interconnect portions is in contact with a respective second bonding contact.
  • Each of the first bonding contacts is in contact with a respective second bonding contact at the bonding interface.
  • the semiconductor device of Patent Document 2 includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first bonding layer and the second bonding layer.
  • each first interconnect is in contact with a respective first bonding contact.
  • at least one second bonding contact is in contact with a respective second interconnect.
  • At least one other second bonding contact is separated from the second interconnect.
  • Each first bonding contact is in contact with one of the second bonding contacts at the bonding interface.
  • Patent Documents 1 and 2 include a bonding interface between the first bonding layer and the second bonding layer, i.e., a bonding surface. For this reason, even in the semiconductor devices of Patent Documents 1 and 2, it is difficult to ensure reliability due to foreign matter such as particles, as described above.
  • the object of the present invention is to provide a highly reliable semiconductor device.
  • invention [1] is a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected, the semiconductor elements have a bonding region in which bonding contacts that bond the semiconductor elements together and electrically connect the semiconductor elements together, and dummy bonding contacts that bond the semiconductor elements together and non-conductively connect the semiconductor elements together are arranged, the dummy bonding contacts are continuously provided along the outer periphery of the bonding region of the semiconductor elements, and the semiconductor elements are bonded to each other with their bonding regions facing each other, and the dummy bonding contacts are bonded to each other.
  • Invention [2] is a semiconductor device according to invention [1], in which the bonding contacts of the multiple semiconductor elements are directly bonded to each other with their bonding regions facing each other, and the dummy bonding contacts are directly bonded to each other.
  • Invention [3] is a semiconductor device according to invention [1], in which an anisotropic conductive member having conductivity in the stacking direction of the semiconductor elements is arranged between the bonding regions of a plurality of semiconductor elements, the bonding contacts are electrically connected to each other, and the dummy bonding contacts are electrically connected to each other.
  • Invention [4] is a semiconductor device according to Invention [3], in which the anisotropic conductive member has an insulating base material having electrical insulation properties and a plurality of conductive paths penetrating the insulating base material in the thickness direction and provided in a state in which the conductive paths are electrically insulated from one another.
  • Invention [5] is a semiconductor device according to any one of inventions [1] to [4], in which the Vickers hardness of the dummy bonding contact is 1/10 or less of the Vickers hardness of the area other than the bonding and dummy bonding contacts in the bonding area.
  • Invention [6] is a semiconductor device according to any one of inventions [1] to [5], in which the dummy bonding contact is made of aluminum or copper, or an alloy containing aluminum or copper.
  • the present invention provides highly reliable semiconductor devices.
  • FIG. 2 is a schematic perspective view showing an example of a semiconductor element used in the semiconductor device according to the embodiment of the present invention.
  • 1 is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention.
  • 3A to 3C are schematic cross-sectional views showing an example of a manufacturing method of a first example of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing a second example of a semiconductor device according to an embodiment of the present invention.
  • 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method of a second example of a semiconductor device according to an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention.
  • FIG. 4 is a schematic plan view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention.
  • Fig. 1 is a schematic perspective view showing an example of a semiconductor element used in a semiconductor device according to an embodiment of the present invention.
  • Fig. 2 is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention. Note that, although two semiconductor elements 12 are shown in Fig. 1, one of the two semiconductor elements 12 is shown imaginarily. In Fig. 2, the same components as those of the semiconductor element 12 shown in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted.
  • the semiconductor element 12 shown in Fig. 1 constitutes a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected. As described above, Fig. 1 shows two semiconductor elements 12.
  • the semiconductor element 12 has, for example, a rectangular outer shape in plan view and has a flat surface 12a.
  • the flat surface 12a also has a rectangular outer shape in plan view.
  • the semiconductor element 12 has a bonding region Aj on the plane 12a.
  • the bonding region Aj has, for example, a rectangular shape in a plan view.
  • the outer shape of the bonding region Aj is similar to the outer shape of the plane 12a. In the bonding region Aj, bonding contacts 20 that bond the semiconductor elements 12 together and electrically connect the semiconductor elements 12 together, and dummy bonding contacts 22 that bond the semiconductor elements 12 together and connect the semiconductor elements 12 together in a non-conductive manner are arranged.
  • the surfaces of the bonding contacts 20 and the surfaces of the dummy bonding contacts 22 do not protrude from the plane 12a and are flush with the plane 12a.
  • the dummy bonding contacts 22 are provided continuously along the outer periphery of the bonding region Aj of the semiconductor element 12. More specifically, the dummy bonding contacts 22 are strip-shaped in a plan view, and are provided continuously and uninterrupted in a ring shape along the outer periphery. For example, the outer and inner shapes of the dummy bonding contacts 22 are quadrangular in a plan view. The outer and inner shapes of the dummy bonding contacts 22 are similar shapes.
  • the bonding contacts 20 are disposed in an area Ad surrounded by the dummy bonding contacts 22.
  • the area Ad has a rectangular outer shape in a plan view.
  • the bonding contacts 20 are conductive and electrically connect the semiconductor elements 12.
  • the bonding contacts 20 allow electrical signals to be exchanged between the semiconductor elements 12.
  • the bonding contacts 20 correspond to electrodes or terminals.
  • the bonding contacts 20 have, for example, a circular outer shape in a plan view, but are not limited thereto and may also be rectangular.
  • the dummy bonding contacts 22 are, for example, conductive and connect the semiconductor elements 12 together in a non-conductive manner. That is, the dummy bonding contacts 22 join but do not electrically connect the semiconductor elements 12 together.
  • the dummy bonding contacts 22 do not contribute to the exchange of electrical signals between the semiconductor elements 12.
  • the dummy bonding contacts 22 are bonded to each other to seal the periphery of the bonding contact 20 of the semiconductor device 10 and isolate and protect the bonding contact 20 from the outside.
  • the dummy bonding contacts 22 can prevent the intrusion of oxygen, moisture, and the like into the bonding contact 20. This increases the reliability of the semiconductor device 10.
  • the dummy bonding contacts 22 increase the bonding surface, thereby maintaining the bonding strength of the semiconductor device 10.
  • the bonding contacts 20 and the dummy bonding contacts 22 are arranged as described above.
  • the semiconductor device 10 is composed of two semiconductor elements 12, the two semiconductor elements 12 are bonded to each other with their bonding contacts 20 and dummy bonding contacts 22 bonded to each other with their flat surfaces 12a facing each other and their bonding regions Aj facing each other.
  • This provides a highly reliable semiconductor device. If the bonding regions Aj have the same size and shape, even if the semiconductor elements 12 have flat surfaces 12a of different sizes, the semiconductor elements 12 can be bonded to each other to obtain a semiconductor device.
  • the semiconductor device 10 is composed of two semiconductor elements.
  • the semiconductor device 10 is, for example, a first semiconductor element 13 and a second semiconductor element 14 that are stacked in a stacking direction Ds, bonded, and electrically connected.
  • the first semiconductor element 13 and the second semiconductor element 14 have different sizes in a plan view, with the first semiconductor element 13 being larger than the second semiconductor element 14.
  • the first semiconductor element 13 like the semiconductor element 12 shown in FIG. 1, has, for example, a rectangular outer shape in a plan view, a flat surface 13a, and a bonding region (not shown) on the flat surface 13a.
  • the flat surface 13a and the bonding region both have a rectangular outer shape in plan view.
  • a bonding contact 20 and a dummy bonding contact 22 are disposed in the bonding region.
  • the first semiconductor element 13 has a first insulating layer 23.
  • a surface 23a of the first insulating layer 23 is the flat surface 13a of the first semiconductor element 13.
  • the above-mentioned bonding contacts 20 and dummy bonding contacts 22 are provided on the first insulating layer 23.
  • the surfaces of the bonding contacts 20 and the surfaces of the dummy bonding contacts 22 do not protrude beyond the surface 23a of the first insulating layer 23, and are flush with the surface 23a of the first insulating layer 23.
  • a second insulating layer 24 is provided as a lower layer on the opposite side of the first insulating layer 23 to the flat surface 13a of the first semiconductor element 13.
  • a conductive connection portion 25 is provided on the second insulating layer 24 in contact with the lower surface 20b of the bonding contact 20.
  • the connection portion 25 is electrically connected to the bonding contact 20. It should be noted that no connection portion 25 is provided for the dummy bonding contact 22 .
  • a third insulating layer 26 is provided as a lower layer on the opposite side of the second insulating layer 24 to the flat surface 13a of the first semiconductor element 13.
  • a wiring layer 27 is provided on the third insulating layer 26.
  • the wiring layer 27 is composed of a plurality of wirings 27a. Of the wirings 27a, the wiring 27a arranged below the connection portion 25 is electrically connected to the connection portion 25.
  • a fourth insulating layer 28 is provided as a lower layer on the opposite side of the third insulating layer 26 to the flat surface 13a of the first semiconductor element 13.
  • a through electrode 29 is provided in the fourth insulating layer 28.
  • the through electrode 29 is provided in contact with the wiring 27a electrically connected to the bonding contact 20.
  • the through electrode 29 is electrically connected to the wiring 27a.
  • the above-mentioned first insulating layer 23, second insulating layer 24, third insulating layer 26 and fourth insulating layer 28 all have electrical insulating properties and are made of, for example, silicon, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant dielectric, or any combination thereof.
  • the second semiconductor element 14 like the semiconductor element 12 shown in FIG. 1, has, for example, a rectangular outer shape in a plan view, a flat surface 14a, and a bonding region (not shown) on the flat surface 14a.
  • the flat surface 14a and the bonding region both have a rectangular outer shape in plan view.
  • a bonding contact 20 and a dummy bonding contact 22 are disposed in the bonding region.
  • the second semiconductor element 14 has a first insulating layer 30.
  • a surface 30a of the first insulating layer 30 is the flat surface 14a of the second semiconductor element 14.
  • the above-mentioned bonding contacts 20 and dummy bonding contacts 22 are provided on the first insulating layer 30.
  • the surfaces of the bonding contacts 20 and the surfaces of the dummy bonding contacts 22 do not protrude beyond the surface of the first insulating layer 30, and are flush with the surface 30a of the first insulating layer 30.
  • a second insulating layer 31 is provided as an upper layer on the opposite side of the first insulating layer 30 to the flat surface 14a of the second semiconductor element 14.
  • a conductive connection portion 32 is provided on the second insulating layer 31 in contact with the lower surface 20b of the bonding contact 20. The connection portion 32 is electrically connected to the bonding contact 20. It should be noted that no connection portion 32 is provided for the dummy bonding contact 22 .
  • a third insulating layer 33 is provided as an upper layer on the opposite side of the second insulating layer 31 to the flat surface 14a of the second semiconductor element 14.
  • a wiring layer 34 is provided on the third insulating layer 33.
  • the wiring layer 34 is composed of a plurality of wirings 34a. Of the wirings 34a, the wiring 34a arranged above the connection portion 32 is electrically connected to the connection portion 32.
  • a fourth insulating layer 35 is provided as an upper layer on the opposite side of the third insulating layer 33 to the flat surface 14a of the second semiconductor element 14.
  • a through electrode 36 is provided in the fourth insulating layer 35.
  • the through electrode 36 is provided in contact with the wiring 34a electrically connected to the bonding contact 20.
  • the through electrode 36 is electrically connected to the wiring 34a.
  • a fifth insulating layer 37 is provided as an upper layer on the side of the fourth insulating layer 35 opposite the plane 14a of the second semiconductor element 14.
  • a wiring layer 38 is provided on the fifth insulating layer 37.
  • the wiring layer 38 is composed of a plurality of wirings 38a. Of the wirings 38a, the wirings 38a arranged above the through electrodes 36 are electrically connected to the through electrodes 36.
  • a sixth insulating layer 39 is provided as an upper layer on the opposite side of the fifth insulating layer 37 to the flat surface 14a of the second semiconductor element 14.
  • a conductive connection portion 40 is provided on the sixth insulating layer 39 in contact with an upper surface 38b of the wiring 38a electrically connected to the through electrode 36. The connection portion 40 is electrically connected to the wiring 38a.
  • a seventh insulating layer 41 is provided as an upper layer on the opposite side of the sixth insulating layer 39 to the flat surface 14a of the second semiconductor element 14.
  • the above-mentioned bonding contacts 20 and dummy bonding contacts 22 are provided on the seventh insulating layer 41.
  • the bonding contacts 20 are provided in contact with the upper surface 40a of the connection portion 40.
  • the bonding contacts 20 are electrically connected to the connection portion 40. It should be noted that the connection portion 40 is not provided for the dummy bonding contact 22 .
  • first insulating layer 30, second insulating layer 31, third insulating layer 33, fourth insulating layer 35, fifth insulating layer 37, sixth insulating layer 39 and seventh insulating layer 41 all have electrical insulating properties and are made of, for example, silicon, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectrics, or any combination thereof.
  • the fourth insulating layer 28 provided with the through electrode 29 and the fourth insulating layer 35 provided with the through electrode 36 each have a structure similar to a TSV (Through Silicon Via), and can be made of silicon.
  • the above-mentioned bonding contacts 20, dummy bonding contacts 22, connecting parts 25, 32, 40, wiring layers 27, 34, 38, and through electrodes 29, 36 are all conductive and made of, for example, tungsten, cobalt, copper, aluminum, silicide, or a combination of these.
  • materials used for what are called terminals or electrode pads in the semiconductor element field can be used as appropriate.
  • the dummy bonding contact 22 is preferably made of a metal or alloy that is more easily deformed during bonding than semiconductors, oxides, and nitrides, and is more preferably made of aluminum or copper, or an alloy containing aluminum or copper.
  • the bonding contacts 20 of the first semiconductor element 13 and the second semiconductor element 14 are directly bonded to each other and are electrically connected. This provides electrical continuity between the bonding contacts 20, connection portion 40, wiring layer 38, through electrode 36, wiring layer 34, and connection portion 32 of the second semiconductor element 14 and the bonding contacts 20, connection portion 25, wiring layer 27, and through electrode 29 of the first semiconductor element 13, allowing electrical signals to be exchanged between the first semiconductor element 13 and the second semiconductor element 14.
  • the Vickers hardness of the dummy bonding contact 22 of the semiconductor element 12 is 1/10 or less of the Vickers hardness of the region As (see FIG. 1) other than the bonding contact 20 (see FIG. 1) and the dummy bonding contact 22 (see FIG. 1) in the bonding region Aj (see FIG. 1).
  • the dummy bonding contact 22 is softer than the region As, even if there are foreign matter such as particles, they are sandwiched between the dummy bonding contacts 22 without any gaps and bonded.
  • the periphery of the bonding contact 20 of the semiconductor device 10 can be reliably sealed, and the occurrence of bond inhibition at the bonding surface Bc of the semiconductor device 10 can be suppressed. This further increases the reliability of the semiconductor device 10.
  • the above-mentioned region As corresponds to the plane 14 a of the first semiconductor element 13 , i.e., the surface 23 a of the first insulating layer 23 , and corresponds to the plane 14 a of the second semiconductor element 14 , i.e., the surface 30 a of the first insulating layer 30 .
  • the Vickers hardness of single crystal Si is 10.6 GPa, that of SiO2 is 9.7 GPa, that of Cu (copper) is 0.80 GPa, and that of Al (aluminum) is 0.50 GPa.
  • the Vickers hardness is measured based on JIS (Japanese Industrial Standards) Z 2255:2003.
  • the interface between the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 is a bonding surface Bc.
  • the bonding contacts 20 are directly bonded to each other, and the dummy bonding contacts 22 are directly bonded to each other.
  • the dummy bonding contacts 22 are disposed so as to surround the bonding contacts 20. Therefore, the dummy bonding contacts 22 prevent oxygen, moisture, and the like from penetrating into the bonding contacts 20. This makes it possible to obtain a highly reliable semiconductor device 10.
  • direct bonding means bonding without using an intermediate layer such as solder or adhesive.
  • the semiconductor device 10 two semiconductor elements, the first semiconductor element 13 and the second semiconductor element 14, are stacked on top of each other.
  • the number of semiconductor elements may be any number as long as it is more than one, and is not limited to two.
  • a semiconductor element (not shown) having the above-mentioned bonding contacts 20 and dummy bonding contacts 22 may be stacked on the surface 41a of the seventh insulating layer 41 opposite the flat surface 14a of the second semiconductor element 14.
  • the number of stacked semiconductor elements is not particularly limited.
  • the second semiconductor element 14 shown in FIG. 2 has a layer structure symmetrical with respect to the fourth insulating layer 35 in the stacking direction Ds.
  • the second semiconductor element 14 has the above-mentioned bonding contacts 20 and dummy bonding contacts 22 arranged on the plane 14a and the surface 41a of the seventh insulating layer 41. Therefore, a plurality of second semiconductor elements 14 can be stacked in the stacking direction, electrically connecting the bonding contacts 20 to each other and electrically connecting the dummy bonding contacts 22 to each other to stack a plurality of second semiconductor elements 14. In this case, if the second semiconductor element 14 is a memory, it becomes a memory stack.
  • the number of stacked second semiconductor elements 14 is not particularly limited.
  • the first semiconductor element 13 and the second semiconductor element 14 can both be manufactured by a known manufacturing method used for manufacturing semiconductor elements.
  • FIG. 3 is a schematic cross-sectional view showing an example of a method for manufacturing a first example of a semiconductor device according to an embodiment of the present invention.
  • the same components as those of the first semiconductor element 13 and the second semiconductor element 14 shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the plane 13a of the first semiconductor element 13 and the plane 14a of the second semiconductor element 14 are placed opposite each other with their bonding regions facing each other.
  • the first semiconductor element 13 and the second semiconductor element 14 are aligned so that the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 face the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14.
  • the plane 13a of the first semiconductor element 13 and the plane 14a of the second semiconductor element 14 are brought into contact with each other to directly bond the bonding contacts 20 to each other and to directly bond the dummy bonding contacts 22 to each other.
  • the method for bonding the semiconductor elements together is not particularly limited, and for example, a bonding method used for hybrid bonding can be used.
  • a bonding method for example, DBI (Direct Bond Interconnect) or SAB (Surface Activated Bond) can be used.
  • DBI Direct Bond Interconnect
  • SAB Surface Activated Bond
  • the above-mentioned DBI is a technique in which a silicon oxide film is laminated on a semiconductor element, chemical mechanical polishing is performed, the silicon oxide film interface is activated by plasma processing, and the semiconductor elements are brought into contact with each other to bond them together.
  • the SAB technique involves surface-treating and activating each bonding surface of a semiconductor element in a vacuum. In this state, the semiconductor elements are brought into contact with each other in a room temperature environment to bond them together.
  • Ion irradiation of an inert gas such as argon, or neutral atomic beam irradiation is used for the surface treatment.
  • a conductive relay material such as solder may be provided between the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 and the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14 to join the first semiconductor element 13 and the second semiconductor element 14 to form a semiconductor device.
  • Fig. 4 is a schematic cross-sectional view showing a second example of a semiconductor device according to an embodiment of the present invention.
  • the same components as those of the first semiconductor element 13 and the second semiconductor element 14 shown in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the semiconductor device 10a shown in Fig. 4 differs from the semiconductor device 10 shown in Fig. 2 in that an anisotropic conductive member 16 having conductivity in the stacking direction Ds of the semiconductor elements is disposed between the bonding regions of a plurality of semiconductor elements.
  • the bonding surface Bc of the semiconductor device 10a is the interface between the plane 13a of the first semiconductor element 13 and the back surface 16b of the anisotropic conductive member 16, and is the interface between the plane 14a of the second semiconductor element 14 and the front surface 16a of the anisotropic conductive member 16.
  • the other configurations are the same as those of the semiconductor device 10 shown in Fig. 2.
  • the semiconductor device 10a shown in FIG. 4 is disposed such that the plane 13a of the first semiconductor element 13 faces the back surface 16b of the anisotropic conductive member 16, and the plane 14a of the second semiconductor element 14 faces the front surface 16a of the anisotropic conductive member 16.
  • the bonding contacts 20 are electrically connected to each other by the anisotropic conductive member 16, and the dummy bonding contacts 22 are electrically connected to each other.
  • the bonding contacts 20 and the dummy bonding contacts 22 are not directly bonded to each other.
  • the first semiconductor element 13 and the second semiconductor element 14 are electrically connected by bonding contacts 20 bonded to each other by the anisotropic conductive member 16. This allows the bonding contacts 20, connection portion 40, wiring layer 38, through electrode 36, wiring layer 34, and connection portion 32 of the second semiconductor element 14 to be conductive with the bonding contacts 20, connection portion 25, wiring layer 27, and through electrode 29 of the first semiconductor element 13, allowing electrical signals to be exchanged between the first semiconductor element 13 and the second semiconductor element 14. 2, in the semiconductor device 10a, the dummy bonding contacts 22 are arranged to surround the bonding contacts 20. This prevents oxygen, moisture, and the like from penetrating into the bonding contacts 20. This allows a highly reliable semiconductor device 10a to be obtained.
  • the semiconductor device 10a similar to the semiconductor device 10 shown in FIG. 2, two semiconductor elements, a first semiconductor element 13 and a second semiconductor element 14, are stacked one on the other.
  • the number of semiconductor elements may be more than one and is not limited to two.
  • a semiconductor element (not shown) having the above-mentioned bonding contacts 20 and dummy bonding contacts 22 may be stacked on the surface 41a of the seventh insulating layer 41 of the second semiconductor element 14 via the anisotropic conductive member 16.
  • the number of layers is not particularly limited.
  • the second semiconductor element 14 and the semiconductor element may be linearly bonded together without providing the anisotropic conductive member 16.
  • a plurality of second semiconductor elements 14 can be stacked in the stacking direction via the anisotropic conductive member 16, electrically connecting the bonding contacts 20 to each other, and electrically connecting the dummy bonding contacts 22 to each other to stack a plurality of second semiconductor elements 14.
  • the second semiconductor element 14 is a memory, it becomes a memory stack.
  • the number of stacked second semiconductor elements 14 is not particularly limited.
  • the bonding contacts 20 and the dummy bonding contacts 22 are disposed in the same layer. This allows the dummy bonding contacts 22 to be formed in the same process as the bonding contacts 20, and therefore does not complicate the manufacturing process of the semiconductor element.
  • the bonding contacts 20 and the dummy bonding contacts 22 are disposed in the same layer, they are formed in the same process, and therefore, for example, the bonding contacts 20 and the dummy bonding contacts 22 are made of the same metal or alloy.
  • forming them in the same process means forming them in a single film formation process, such as a plating process, a sputtering process, and a CVD (Chemical Vapor Deposition) process.
  • FIG. 5 is a schematic cross-sectional view showing an example of a method for manufacturing a second example of a semiconductor device according to an embodiment of the present invention.
  • the same components as the first semiconductor element 13, the second semiconductor element 14, and the anisotropic conductive member 16 shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are opposed to each other, and the bonding regions of the first semiconductor element 13 and the second semiconductor element 14 are opposed to each other.
  • the first semiconductor element 13 and the second semiconductor element 14 are aligned to make the bonding contacts 20 and the dummy bonding contacts 22 of the first semiconductor element 13 face the bonding contacts 20 and the dummy bonding contacts 22 of the second semiconductor element 14.
  • an anisotropic conductive member 16 is disposed between the plane 13a of the first semiconductor element 13 and the plane 14a of the second semiconductor element 14, with the back surface 16b of the anisotropic conductive member 16 facing the plane 13a of the first semiconductor element 13 and the front surface 16a of the anisotropic conductive member 16 facing the plane 14a of the second semiconductor element 14.
  • the plane 13a of the first semiconductor element 13 is brought into contact with the back surface 16b of the anisotropic conductive member 16
  • the plane 14a of the second semiconductor element 14 is brought into contact with the front surface 16a of the anisotropic conductive member 16, to bond the bonding contacts 20 together and to bond the dummy bonding contacts 22 together by the anisotropic conductive member 16.
  • the method for bonding the semiconductor elements together is not particularly limited, and for example, a bonding method used for hybrid bonding can be used.
  • a bonding method used for hybrid bonding can be used.
  • the above-mentioned DBI or SAB can be used as the bonding method.
  • a semiconductor device may be formed by providing solder between the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 and the back surface 16b of the anisotropic conductive member 16, and providing solder between the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14 and the front surface 16a of the anisotropic conductive member 16, and joining the first semiconductor element 13, the anisotropic conductive member 16, and the second semiconductor element 14.
  • Fig. 6 is a schematic cross-sectional view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention.
  • Fig. 7 is a schematic plan view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention.
  • Fig. 7 is a plan view seen from the front side of the anodized film of Fig. 6, showing a state in which the resin layer 54 is not present.
  • the anisotropically conductive member 16 shown in FIG. 6 has conductivity in the stacking direction Ds (see FIG. 2) of the semiconductor element described above.
  • the anisotropically conductive member 16 has an insulating base material 50 having electrical insulation properties, a plurality of conductive paths 52 penetrating the insulating base material 50 in a thickness direction Dt and provided in a state in which they are electrically insulated from one another, and a resin layer 54 covering at least one surface of the insulating base material 50.
  • the anisotropically conductive member 16 is disposed between the first semiconductor element 13 and the second semiconductor element 14 with the thickness direction Dt and the stacking direction Ds parallel to each other.
  • the conductive paths 52 are provided in the insulating base material 50 in a state in which they are electrically insulated from one another.
  • the insulating base material 50 has a plurality of pores 51 penetrating in the thickness direction Dt.
  • the conductive paths 52 are provided in the plurality of pores 51.
  • the conductive paths 52 protrude from the front surface 50a of the insulating base material 50.
  • the conductive paths 52 also protrude from the back surface 50b of the insulating base material 50.
  • the conductive paths 52 may protrude from one surface of the insulating base material 50 in the thickness direction Dt.
  • the resin layer 54 covers the protruding portions 52a of the conductive paths 52, and the protruding portions 52a are embedded in the resin layer 54.
  • the resin layer 54 also covers the protruding portions 52b of the conductive paths 52, and the protruding portions 52b are embedded in the resin layer 54.
  • the insulating base material 50 is formed of, for example, an anodized film.
  • a front surface 50a of the insulating base material 50 and a back surface 50b of the insulating base material 50 are surfaces that face each other in a thickness direction Dt of the insulating base material 50.
  • the anisotropically conductive member 16 has anisotropic conductivity and is conductive in the thickness direction Dt, but has sufficiently low conductivity in a direction parallel to the surface 50 a of the insulating base material 50 . 7, the anisotropically conductive member 16 has, for example, a rectangular outer shape. The outer shape and size of the anisotropically conductive member 16 are appropriately determined in accordance with the outer shape and size of the bonding region of the semiconductor element. For example, the anisotropically conductive member 16 is bonded in a state where there is no resin layer 54, or in a state where there is a resin layer 54 but nothing is present on the surface 54a.
  • the configuration of the anisotropically conductive member will be described in more detail below.
  • the anisotropically conductive member has a configuration similar to that of the structure described in WO 2022/163260, and can be manufactured in the same manner as the above-mentioned structure.
  • the insulating base material 50 is made of a conductor and electrically insulates the plurality of conductive paths 52 from one another, and has electrical insulation properties.
  • the insulating base material 50 also has a plurality of pores 51 in which the conductive paths 52 are formed. The composition of the insulating base material 50 will be described later.
  • the length of the insulating substrate 50 in the thickness direction Dt i.e., the thickness ht of the insulating substrate 50, is preferably in the range of 1 to 1000 ⁇ m, more preferably in the range of 5 to 500 ⁇ m, and even more preferably in the range of 10 to 300 ⁇ m.
  • the thickness ht of the insulating substrate 50 becomes easy to handle.
  • the thickness ht of the insulating base material 50 is preferably 30 ⁇ m or less, and more preferably 5 to 20 ⁇ m.
  • the thickness of the insulating substrate is calculated as the average value of 10 measurements taken at 10 points after cutting the insulating substrate in the thickness direction Dt using a focused ion beam (FIB) and taking surface photographs (magnification 50,000 times) of the cross section using a scanning electron microscope (SEM).
  • FIB focused ion beam
  • SEM scanning electron microscope
  • the average diameter of pores 51 is preferably 1 ⁇ m or less, more preferably 5 to 500 nm, even more preferably 20 to 400 nm, even more preferably 40 to 200 nm, and most preferably 50 to 100 nm.
  • the average diameter of the pores 51 is measured by photographing the surface of the insulating substrate 50 from directly above at a magnification of 100 to 10,000 times using a scanning electron microscope (SEM). In the photographed image, at least 20 pores that are connected in a ring shape are extracted, and their diameters are measured to determine the opening diameter.
  • the average of these opening diameters is calculated as the average diameter of the pores.
  • the magnification can be appropriately selected from the above range so that a captured image can be obtained that can extract 20 or more pores.
  • the aperture diameter is measured by measuring the maximum value of the distance between the ends of the pore portion. That is, since the shape of the opening of the pore is not limited to a substantially circular shape, when the shape of the opening is non-circular, the maximum value of the distance between the ends of the pore portion is taken as the aperture diameter. Therefore, for example, even in the case of a pore having a shape in which two or more pores are integrated, this is regarded as one pore, and the maximum value of the distance between the ends of the pore portion is taken as the aperture diameter.
  • the multiple conductive paths 52 are provided in the insulating base material 50, for example, an anodized film, in a state in which they are electrically insulated from one another.
  • the plurality of conductive paths 52 are electrically conductive.
  • the conductive paths are made of a conductive material.
  • the conductive material is not particularly limited, and may be a metal. Specific examples of metals include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), and cobalt (Co). From the viewpoint of electrical conductivity, copper, gold, aluminum, nickel, and cobalt are preferred, copper and gold are more preferred, and copper is most preferred.
  • the height of the conductive paths 52 in the thickness direction Dt is preferably 10 to 300 ⁇ m, and more preferably 20 to 30 ⁇ m.
  • the average diameter d of the conductive paths 52 is preferably 1 ⁇ m or less, more preferably 5 to 500 nm, even more preferably 20 to 400 nm, even more preferably 40 to 200 nm, and most preferably 50 to 100 nm.
  • the density of the conductive paths 52 is preferably 20,000 pieces/mm2 or more , more preferably 2 million pieces/ mm2 or more, even more preferably 10 million pieces/ mm2 or more, particularly preferably 50 million pieces/ mm2 or more, and most preferably 100 million pieces/ mm2 or more.
  • the center-to-center distance p between adjacent conductive paths 52 is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and even more preferably 50 nm to 140 nm.
  • the average diameter of the conductive paths is measured by photographing the surface of the insulating substrate from directly above with a scanning electron microscope at a magnification of 100 to 10,000. At least 20 conductive paths that are connected in a ring shape are extracted from the photographed image, and their diameters are measured to determine the opening diameter. The average of these opening diameters is calculated as the average diameter of the conductive paths.
  • the magnification can be appropriately selected from the above range so as to obtain a captured image from which 20 or more conductive paths can be extracted.
  • the maximum value of the distance between the ends of the conductive path portion is taken as the opening diameter.
  • the average diameter d of the conductive paths 52 is the same as the average diameter of the protrusions.
  • the center-to-center distance p of adjacent conductive paths 52 is determined by further determining the center positions (not shown) of the conductive paths identified in the photographed image of insulating substrate 50 obtained as described above. The distance between the center positions of adjacent conductive paths was determined at 10 locations. The average value was taken as the center-to-center distance p of adjacent conductive paths 52.
  • the center positions are the center positions of the areas corresponding to conductive paths 52 in the photographed image described above. A known image analysis method is used to calculate the center positions of the areas in the photographed image.
  • the protrusion is a part of the conductive path and has a columnar shape.
  • the protrusion is preferably cylindrical in shape because it can increase the contact area with the objects to be joined.
  • the average protrusion length ha of the protrusions 52a and the average length hb of the protrusions 52b are preferably 10 nm to 1000 nm, and more preferably 50 nm to 500 nm. When the average protrusion length ha and the average length hb are 10 nm to 1000 nm, the adhesion between the resin layer 54 and the insulating substrate 50 is good.
  • the average protrusion length ha of the protrusion 52a and the average length hb of the protrusion 52b are the average values measured by obtaining cross-sectional images of the protrusions using a scanning electron microscope as described above, and measuring the heights of the protrusions at 10 points based on the cross-sectional images.
  • the distance between adjacent protrusions is preferably 20 nm to 200 nm, and more preferably 40 nm to 100 nm.
  • the distance between the conductive paths 52 can be maintained on the front surface 50a or back surface 50b of the insulating substrate 50 of the conductive paths 52. This prevents short circuits in the conductive paths 52 when the semiconductor devices are bonded, further increasing reliability during bonding.
  • the resin layer covers at least one of the front and back surfaces of the insulating substrate, and protects the insulating substrate and the conductive paths. For example, if the conductive paths have protruding portions, the resin layer buries the protruding portions. That is, the resin layer covers the ends of the conductive paths protruding from the insulating substrate, and protects the protruding portions.
  • the resin layer preferably exhibits fluidity in a temperature range of, for example, 50° C. to 200° C. and hardens at temperatures of 200° C. or higher.
  • the resin layer is, for example, a thermoplastic layer made of a thermoplastic resin or the like, and the resin layer will be described in detail later.
  • the average thickness hm of the resin layer 54 is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less, and even more preferably 1 ⁇ m or less. If the average thickness hm of the resin layer 54 is 10 ⁇ m or less as described above, the resin layer 54 can sufficiently protect the protruding portion of the conductive path 52 and fill the periphery of the electrode when bonding the semiconductor device.
  • the average thickness hm of the resin layer 54 is the average distance from the surface 50a of the insulating substrate 50, or the average distance from the back surface 50b of the insulating substrate 50.
  • the average thickness hm of the resin layer 54 is the average value of 10 measured values when the resin layer is cut in the thickness direction Dt of the anisotropic conductive member 16, the cut cross section is observed using a scanning electron microscope, and the distance from the surface 50a of the insulating substrate 50 is measured at 10 points corresponding to the resin layer. Also, the average value of 10 measured values when the distance from the back surface 50b of the insulating substrate 50 is measured at 10 points corresponding to the resin layer.
  • the resin layer may have the following composition:
  • the composition of the resin layer will be described below:
  • the resin layer contains a polymer material and may contain an antioxidant material.
  • the resin material constituting the resin layer include thermoplastic resins such as ethylene copolymers, polyamide resins, polyester resins, polyurethane resins, polyolefin resins, acrylic resins, acrylonitrile resins, and cellulose resins. Polyacrylonitrile can also be used as the resin material constituting the resin layer 54.
  • a resin layer containing a main composition containing an acrylic polymer, an acrylic monomer, and a maleimide compound described in WO 2022/163260 can be used.
  • Examples of the functions of the semiconductor elements are distinguished by the operation of the semiconductor elements.
  • Examples of the functions of a semiconductor include calculations such as a central processing unit (CPU) or a graphics processing unit (GPU), storage such as a memory, conversion such as a converter, filters, and sensing.
  • CPU central processing unit
  • GPU graphics processing unit
  • storage such as a memory
  • conversion such as a converter
  • filters filters
  • sensing sensing
  • the semiconductor element is not particularly limited as long as it has the above-mentioned bonding contacts 20 and dummy bonding contacts 22. More specifically, examples of semiconductor elements include logic LSIs (Large Scale Integration), ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), ASSPs (Application Specific Standard Products), etc.), microprocessors (e.g., CPUs, GPUs, etc.), memory (e.g., DRAMs (Dynamic Random Access Memory), SRAMs (Static Random Access Memory), HMCs (Hybrid Memory Cubes), MRAMs (Magnetic RAMs), PCMs (Phase-Change Memory), ReRAMs (Resistive RAMs), FeRAMs (Ferroelectric RAMs), flash memories, etc.), LEDs (Light Emitting Diodes), power devices, analog ICs (Integrated Circuits), and for example, DC (Direct Current)-DC (Direct Current t) converters, insulated gate
  • composition of the semiconductor that constitutes the semiconductor element is not particularly limited.
  • semiconductor compositions include diamond, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide, and silicon-on-insulator (SOI).
  • a semiconductor device is a device in which multiple semiconductor elements are stacked and electrically connected.
  • a semiconductor device is a collection of multiple semiconductor elements that perform a specific function, but also includes devices that simply transmit electrical signals.
  • the semiconductor device may be, for example, a logic device with a two-dimensional (2D), two-and-a-half-dimensional (2.5D), or three-dimensional (3D) architecture.
  • the semiconductor device may also be, for example, a DRAM stack in which a plurality of DRAMs are stacked, or a configuration in which a DRAM stack and a logic LSI are stacked.
  • the semiconductor device may also include a printed wiring board, a heat sink, and the like.
  • the semiconductor device may have digital, analog, or mixed signal peripheral circuits. More specifically, the semiconductor device may have a peripheral device layer having one or more of a page buffer, a row decoder, a column decoder, a sense amplifier, a driver, a charge pump, a transistor, a diode, a resistor, or a capacitor.
  • the semiconductor device may also have an element region in addition to the semiconductor elements described above.
  • the element region is a region in which various element component circuits and the like for functioning as electronic elements are formed.
  • the element region may be, for example, a region in which a memory circuit such as a flash memory, a logic circuit such as a microprocessor and an FPGA (field-programmable gate array), a communication module such as a wireless tag, and a region in which wiring are formed.
  • a MEMS may be formed in the element region. Examples of MEMS include sensors, actuators, and antennas. Examples of sensors include various types of sensors such as acceleration, sound, and light sensors.
  • the present invention is basically configured as described above. Although the semiconductor device of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and various improvements and modifications may of course be made without departing from the spirit of the present invention.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054637A (ja) * 2009-08-31 2011-03-17 Sony Corp 半導体装置およびその製造方法
WO2016185883A1 (ja) * 2015-05-18 2016-11-24 ソニー株式会社 半導体装置および撮像装置
WO2022163260A1 (ja) * 2021-01-27 2022-08-04 富士フイルム株式会社 構造体、異方導電性部材の製造方法、及び保護層形成用組成物

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054637A (ja) * 2009-08-31 2011-03-17 Sony Corp 半導体装置およびその製造方法
WO2016185883A1 (ja) * 2015-05-18 2016-11-24 ソニー株式会社 半導体装置および撮像装置
WO2022163260A1 (ja) * 2021-01-27 2022-08-04 富士フイルム株式会社 構造体、異方導電性部材の製造方法、及び保護層形成用組成物

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