WO2024184718A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024184718A1
WO2024184718A1 PCT/IB2024/051794 IB2024051794W WO2024184718A1 WO 2024184718 A1 WO2024184718 A1 WO 2024184718A1 IB 2024051794 W IB2024051794 W IB 2024051794W WO 2024184718 A1 WO2024184718 A1 WO 2024184718A1
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WIPO (PCT)
Prior art keywords
insulating layer
circuit
oxide
metal oxide
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2024/051794
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English (en)
French (fr)
Japanese (ja)
Inventor
豊高耕平
八窪裕人
藤田雅史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2025504875A priority Critical patent/JPWO2024184718A1/ja
Priority to CN202480012133.2A priority patent/CN120693790A/zh
Priority to KR1020257027959A priority patent/KR20250159159A/ko
Publication of WO2024184718A1 publication Critical patent/WO2024184718A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • One aspect of the present invention relates to a semiconductor device, etc.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device (memory device), and a driving method or a manufacturing method thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and each may have a semiconductor device.
  • the semiconductor device can achieve low power consumption by power gating or the like by configuring it to save (also referred to as “evacuation,” “store,” or “backup”) or load (also referred to as “restore,” “recovery”) programs or data held in flip-flops or the like.
  • save also referred to as "evacuation,” “store,” or “backup”
  • load also referred to as "restore,” “recovery” programs or data held in flip-flops or the like.
  • Patent Document 1 shows a configuration in which an OS transistor is connected to a flip-flop, which is a volatile memory circuit, to realize a non-volatile flip-flop.
  • An object of one aspect of the present invention is to provide a novel semiconductor device or the like. Another object is to provide a power-saving semiconductor device or the like. Another object is to provide a semiconductor device or the like that can operate at high speed.
  • problems of one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not preclude the existence of other problems.
  • the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and/or other problems.
  • One aspect of the present invention has a first circuit, a second circuit, and a third circuit, the first circuit having first to fifth inverter circuits and first to fourth switches, the second circuit having an input section X and an output section Y, and the third circuit having an input section A, an input section B, and an output section Z, the output section of the first inverter circuit being electrically connected to one terminal of the first switch, the other terminal of the first switch being electrically connected to one terminal of the second switch, the other terminal of the second switch being electrically connected to the output section of the second inverter circuit, and the input section of the second inverter circuit being electrically connected to one terminal of the third switch.
  • the third switch is electrically connected to the input of the third inverter circuit and one terminal of the fourth switch
  • the output of the third inverter circuit is electrically connected to the input of the fourth inverter circuit and the input of the fifth inverter circuit
  • the output of the fourth inverter circuit is electrically connected to the other terminal of the fourth switch
  • the output of the third inverter circuit is electrically connected to the input X
  • the output Y is electrically connected to the input A
  • the input B is electrically connected to one terminal of the second switch
  • the output Z is electrically connected to one terminal of the third switch.
  • the second circuit functions as a memory circuit.
  • the second circuit has a transistor and a capacitor.
  • one of the source or drain of the transistor functions as an input unit X
  • the other of the source or drain of the transistor functions as an output unit Y.
  • the other of the source or drain of the transistor is electrically connected to one terminal of the capacitor.
  • the transistor preferably includes an oxide semiconductor in a semiconductor layer in which a channel is formed.
  • the semiconductor device has a function of supplying a signal equivalent to the signal supplied to the input of the first inverter circuit to the output of the fifth inverter circuit in synchronization with a clock signal.
  • the first switch and the fourth switch have a function of operating in synchronization with the clock signal
  • the second switch and the third switch have a function of operating in synchronization with an inverted clock signal.
  • the third circuit functions as a selection circuit.
  • the third circuit has a function of supplying a signal corresponding to the signal supplied to input section A to output section Z, a function of supplying a signal corresponding to the signal supplied to input section B to output section Z, and a function of determining the signal to be supplied to output section Z in response to the selection signal.
  • a novel semiconductor device or the like can be provided.
  • a power-saving semiconductor device or the like can be provided.
  • a semiconductor device or the like capable of high-speed operation can be provided.
  • FIG. 1 is a diagram showing a circuit configuration of a semiconductor device.
  • FIG. 2 is a diagram showing a circuit configuration of the semiconductor device.
  • Fig. 3A is a truth table of the third circuit
  • Fig. 3B is a diagram showing an example of the configuration of the third circuit.
  • Fig. 4A is a diagram showing a circuit symbol of the semiconductor device, and Fig. 4B is a timing chart explaining the operation of the semiconductor device.
  • FIG. 5 is a diagram showing a circuit configuration of the semiconductor device.
  • Fig. 6A is a diagram showing a circuit symbol of the semiconductor device, and Fig. 6B is a timing chart illustrating the operation of the semiconductor device.
  • FIG. 7 is a diagram showing a circuit configuration of a semiconductor device.
  • Fig. 1 is a diagram showing a circuit configuration of a semiconductor device.
  • FIG. 2 is a diagram showing a circuit configuration of the semiconductor device.
  • Fig. 3A is a truth table of the third circuit
  • FIG. 8A is a diagram showing a circuit symbol of the semiconductor device, and Fig. 8B is a timing chart illustrating the operation of the semiconductor device.
  • FIG. 9 is a diagram showing a circuit configuration of a semiconductor device.
  • Fig. 10A is a diagram showing an edge detection circuit, and Fig. 10B is a timing chart illustrating the operation of the edge detection circuit.
  • 11A and 11B are diagrams illustrating a configuration example of a semiconductor device.
  • 12A is a plan view of the transistor, and FIGS. 12B and 12C are cross-sectional views of the transistor.
  • 13A is a plan view of the transistor, and FIGS. 13B and 13C are cross-sectional views of the transistor.
  • 14A is a plan view of the transistor, and FIGS.
  • FIG. 14B and 14C are cross-sectional views of the transistor.
  • FIG. 15 is a diagram showing an example of a stacked structure of a semiconductor device.
  • FIG. 16 is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 17 is a block diagram illustrating the CPU.
  • 18A and 18B are perspective views of a semiconductor device.
  • 19A and 19B are perspective views of a semiconductor device.
  • 20A and 20B are diagrams showing various storage devices by hierarchical level.
  • 21A to 21J are diagrams illustrating an example of an electronic device.
  • 22A to 22C are diagrams illustrating an example of an electronic device.
  • FIG. 23 is a diagram showing an example of space equipment.
  • metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a transistor is referred to as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • ordinal numbers such as “first” and “second” are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, ordinal numbers may be added in the claims to avoid confusion between components. The ordinal numbers added in this specification may differ from those added in the claims. Even if a term has an ordinal number added in this specification, ordinal numbers may be omitted in the claims.
  • electrode used in this specification and the like do not limit the functions of these components.
  • an “electrode” may be used as a part of a “wiring,” and vice versa.
  • the terms “electrode” and “wiring” include cases where multiple “electrodes” and “wirings” are integrated together.
  • a “terminal” may be used as a part of a “wiring” or “electrode,” and vice versa.
  • terminal includes cases where multiple “electrodes,” “wirings,” “terminals,” etc. are integrated together.
  • an “electrode” can be a part of a “wiring” or “terminal,” and, for example, a “terminal” can be a part of a “wiring” or “electrode.”
  • terms such as “electrode,” “wiring,” and “terminal” may be replaced with terms such as "region” in some cases.
  • VDD high power supply potential
  • VSS low power supply potential
  • GND ground potential GND
  • voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Also, “potential” is relative, and the potential applied to wiring, etc. may change depending on the reference potential. Therefore, “voltage” and “potential” can sometimes be used interchangeably.
  • supplying a signal means supplying a predetermined potential to wiring or the like. Therefore, it may be possible to read “signal” as a term such as “potential”. It may also be possible to read terms such as “potential” as a term such as “signal”. It may also be possible to read “signal” as a term such as “potential”.
  • a “signal” may be a variable potential or a fixed potential. For example, it may be a power supply potential.
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • the term “capacitive element” may be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor.
  • the terms “capacitive element”, “parasitic capacitance”, and “gate capacitance” may be rephrased as “capacitance”.
  • the term “capacitance” may be rephrased as “capacitive element”, “parasitic capacitance”, or “gate capacitance”.
  • a “capacitive element” (including a “capacitive element” with three or more terminals) is configured to include an insulator and a pair of conductors sandwiching the insulator. Therefore, the term “pair of conductors" in a “capacitive element” may be rephrased as “pair of electrodes", “pair of conductive regions", “pair of regions", or “pair of terminals”. In addition, the term “one of the pair of terminals” may be referred to as “one terminal” or “first terminal”. In addition, the term “the other of the pair of terminals” may be referred to as “the other terminal” or “second terminal”.
  • the value of the electrostatic capacitance may be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, between 1 pF and 10 ⁇ F.
  • gate refers to a gate electrode and a part or all of a gate wiring.
  • a gate wiring refers to a wiring that electrically connects the gate electrode of at least one transistor to another electrode or another wiring.
  • source refers to a source region, a source electrode, and part or all of a source wiring.
  • a source region refers to a region of a semiconductor layer whose resistivity is equal to or lower than a certain value.
  • a source electrode refers to a conductive layer that includes a portion connected to a source region.
  • a source wiring refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or another wiring.
  • drain refers to a part or all of the drain region, drain electrode, and drain wiring.
  • the drain region refers to a region of the semiconductor layer whose resistivity is equal to or lower than a certain value.
  • the drain electrode refers to a conductive layer that includes a portion connected to the drain region.
  • the drain wiring refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or another wiring.
  • a and B are connected includes not only A and B being directly connected, but also A and B being electrically connected.
  • a and B are electrically connected means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B.
  • electrode B on insulating layer A does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • electrode B overlapping insulating layer A does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A, the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.
  • electrode B adjacent to insulating layer A does not require that insulating layer A and electrode B are formed in direct contact, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • the semiconductor device 100A has terminals D, CK, RE, BK, and Q.
  • a clock signal CLK is input to terminal CK.
  • a restore signal (also called a selection signal) is input to terminal RE.
  • a backup signal is input to terminal BK.
  • the semiconductor device 100A has a function of storing the value (potential) of terminal D and outputting the value from terminal Q when the clock signal CLK input to terminal CK becomes potential H.
  • the semiconductor device 100A also has a first circuit 110, a second circuit 120, and a third circuit 130.
  • the semiconductor device 100A also has an inverter circuit 141 that functions as an internal clock generation circuit.
  • the inverter circuit 141 has a function of outputting an inverted clock signal CLKB, which is an inverted signal of the input clock signal CLK.
  • a terminal CKB (not shown) may be provided in the semiconductor device 100A, and the inverted clock signal CLKB, which is an inverted signal of the clock signal CLK, may be input to the terminal CKB. In this case, it is not necessary to provide the inverter circuit 141 for generating the inverted clock signal CLKB.
  • the first circuit 110 has the function of supplying a signal (also called a second signal) equivalent to the signal (also called a first signal) supplied to terminal D to terminal Q in synchronization with a clock signal.
  • the first circuit 110 has a first inverter circuit 111, a second inverter circuit 114, a third inverter circuit 116, a fourth inverter circuit 118, a fifth inverter circuit 119, a first switch 112, a second switch 113, a third switch 115, and a fourth switch 117.
  • the input part of the first inverter circuit 111 is electrically connected to the terminal D, and the output part of the first inverter circuit 111 is electrically connected to one terminal of the first switch 112.
  • the other terminal of the first switch 112 is electrically connected to one terminal of the second switch 113.
  • the other terminal of the second switch 113 is electrically connected to the output part of the second inverter circuit 114.
  • the input part of the second inverter circuit 114 is electrically connected to one terminal of the third switch 115.
  • the other terminal of the third switch 115 is electrically connected to the input part of the third inverter circuit 116 and one terminal of the fourth switch 117.
  • the output part of the third inverter circuit 116 is electrically connected to the input part of the fourth inverter circuit 118, the input part of the fifth inverter circuit 119, and one of the source or drain of the transistor 121.
  • the output part of the fourth inverter circuit 118 is electrically connected to the other terminal of the fourth switch 117.
  • the output part of the fifth inverter circuit 119 is electrically connected to the terminal Q.
  • Each of the first switch 112 and the fourth switch 117 is in a conductive state (a state in which electricity can flow) between one terminal and the other terminal when the clock signal CLK is at potential H, and is in a non-conductive state between one terminal and the other terminal when the clock signal CLK is at potential L.
  • Each of the second switch 113 and the third switch 115 is in a conductive state between one terminal and the other terminal when the inverted clock signal CLKB is at potential H, and is in a non-conductive state between one terminal and the other terminal when the inverted clock signal CLKB is at potential L.
  • Analog switches may be used as the first switch 112, the second switch 113, the third switch 115, and the fourth switch 117.
  • FIG. 2 shows a circuit configuration in which the first switch 112, the second switch 113, the third switch 115, and the fourth switch 117 are replaced with analog switches.
  • OS transistors may be used as the first switch 112, the second switch 113, the third switch 115, and the fourth switch 117.
  • OS transistors have a significantly small off-state current and a high withstand voltage between the source and drain. Therefore, OS transistors are suitable as switches.
  • the second circuit 120 functions as a memory circuit.
  • the second circuit 120 has a function of holding a third signal that corresponds to the second signal.
  • the third signal is an inverted signal of the second signal, and is a signal that is supplied to the output section of the third inverter circuit 116.
  • the second circuit 120 has a transistor 121 and a capacitance element 122.
  • the gate of the transistor 121 is electrically connected to the terminal BK, and one of the source and drain is electrically connected to the output part of the third inverter circuit 116, the input part of the fourth inverter circuit 118, and the input part of the fifth inverter circuit 119.
  • the region where one of the source and drain of the transistor 121, the output part of the third inverter circuit 116, the input part of the fourth inverter circuit 118, and the input part of the fifth inverter circuit 119 are connected and always at the same potential is called "node QB".
  • the other of the source and drain of the transistor 121 is electrically connected to one terminal (or electrode) of the capacitor 122.
  • node SN the region where the other of the source and drain of the transistor 121 and one terminal of the capacitor 122 are connected and have the same potential
  • a ground potential GND is supplied to the other terminal (or electrode) of the capacitance element 122.
  • the potential supplied to the other terminal of the capacitance element 122 may be a variable potential, but a fixed potential is preferable. Furthermore, the potential supplied to the other terminal of the capacitance element 122 is not limited to the ground potential GND.
  • the potential supplied to the other terminal of the capacitance element 122 may be a reference potential (0V), a high power supply potential VDD, a low power supply potential VSS, etc.
  • one of the source and drain of the transistor 121 may be referred to as the input section X. Also, in the second circuit 120, the other of the source and drain of the transistor 121 may be referred to as the output section Y.
  • the transistor 121 Although a Si transistor may be used as the transistor 121, it is preferable to use an OS transistor. Since an OS transistor has an extremely small off-state current, the amount of charge held in the node SN is unlikely to fluctuate. Therefore, the charge supplied to the node SN can be held for a long period of time. Furthermore, almost no power is required to hold the data (charge) written to the node SN. For this reason, the second circuit 120 can be said to be a nonvolatile memory. Furthermore, the second circuit 120 rewrites data by charging and discharging the capacitor 122, so in principle there is no restriction on the number of times that data can be rewritten. Furthermore, data can be written and read at high speed with low energy.
  • a memory circuit configured using OS transistors is also called an "OS memory.” Therefore, the second circuit 120 is an OS memory.
  • a transistor having a back gate may be used as the transistor 121.
  • the threshold voltage of the transistor can be controlled by adjusting the potential supplied to the back gate.
  • the third circuit 130 functions as a selection circuit.
  • the third circuit 130 has an inverter circuit 131, a first AND circuit 132, a second AND circuit 133, and a NOR circuit 134.
  • the first AND circuit 132, the second AND circuit 133, and the NOR circuit 134 are logic circuits with two inputs and one output.
  • the first input part of the first AND circuit 132 is electrically connected to one terminal of the capacitive element 122 and the other of the source or drain of the transistor 121. Therefore, the first input part of the first AND circuit 132 is electrically connected to the node SN.
  • the second input part of the first AND circuit 132 is electrically connected to the input part of the inverter circuit 131 and the terminal RE.
  • the output part of the first AND circuit 132 is electrically connected to the first input part of the NOR circuit 134.
  • the output of the inverter circuit 131 is electrically connected to a first input of the second AND circuit 133.
  • the second input of the second AND circuit 133 is electrically connected to the other terminal of the first switch 112 and one terminal of the second switch 113.
  • the area where the second input of the second AND circuit 133, the other terminal of the first switch 112, and one terminal of the second switch 113 are connected and always at the same potential is called "node Q0".
  • the output of the second AND circuit 133 is electrically connected to the second input of the NOR circuit 134.
  • the output of the NOR circuit 134 is electrically connected to the input of the second inverter circuit 114 and one terminal of the third switch 115.
  • the area where the output of the NOR circuit 134, the input of the second inverter circuit 114, and one terminal of the third switch 115 are connected and always at the same potential is called "node Q1.”
  • the first AND circuit 132 outputs the potential of the first input section when potential H is supplied to the terminal RE. That is, when potential H is supplied to the terminal RE, it outputs a potential corresponding to the potential of the node SN. Furthermore, when potential L is supplied to the terminal RE, the first AND circuit 132 always outputs potential L.
  • the second AND circuit 133 outputs the potential of the second input section when potential L is supplied to terminal RE. That is, when potential L is supplied to terminal RE, it outputs a potential corresponding to the potential of node Q0. Furthermore, when potential H is supplied to terminal RE, the second AND circuit 133 always outputs potential L.
  • the operation of the first AND circuit 132 and the second AND circuit 133 ensures that the potential L is always supplied to either the first input section or the second input section of the NOR circuit 134. Therefore, the NOR circuit 134 outputs an inverted potential of the potential supplied to the other of the first input section or the second input section.
  • the first input part of the first AND circuit 132 may be referred to as input part A.
  • the second input part of the second AND circuit 133 may be referred to as input part B.
  • the output part of the NOR circuit 134 may be referred to as output part Z.
  • the third circuit 130 has a function of supplying a signal corresponding to the signal supplied to the input section A to the output section Z, and a function of supplying a signal corresponding to the signal supplied to the input section B to the output section Z.
  • the signal supplied to the output section Z is determined according to a selection signal input to the terminal RE.
  • the truth table of the third circuit 130 is shown in FIG. 3A.
  • the third circuit 130 When a potential H is supplied to the terminal RE as a selection signal, the third circuit 130 outputs the inverted potential of input part A to the output part Z.
  • a potential L is supplied to the terminal RE as a selection signal, the inverted potential of input part B is output to the output part Z.
  • the potential of input part A is the potential of node SN
  • the potential of input part B is the potential of node Q0
  • the potential of output part Z is the potential of node Q1.
  • the configuration of the third circuit 130 is not limited to the above configuration.
  • it can be configured using an inverter circuit and an analog switch.
  • the third inverter circuit 116, the fourth inverter circuit 118, and the fourth switch 117 function as a latch circuit 151.
  • the second AND circuit 133 and the NOR circuit 134 function as one inverter circuit.
  • the second AND circuit 133, the NOR circuit 134, the second inverter circuit 114, and the second switch 113 function as a latch circuit 152.
  • the semiconductor device 100A functions as a D flip-flop circuit having two latch circuits.
  • the semiconductor device 100A is also a D flip-flop circuit with a backup function.
  • the semiconductor device 100A functions as a memory device capable of retaining written data even when the power supply is stopped. Next, an example of the operation of the semiconductor device 100A will be described.
  • Figure 4A shows a circuit symbol of the semiconductor device 100A.
  • Figure 4B shows a timing chart for explaining the operation of the semiconductor device 100A.
  • Period T1 A period T1 is a normal operation period. During the normal operation period, when the potential supplied to the terminal D changes, the potential supplied to the terminal Q changes in synchronization with the clock signal CLK and the inverted clock signal CLKB.
  • Period T2 Prior to the power supply being stopped in the period T3, an operation of holding the potential supplied to the terminal Q in the period T2 is performed. Specifically, the potential of the node QB is held in the node SN.
  • the period T2 is a period for performing a data save operation (store).
  • FIG. 4B shows a case where the potential L is supplied to the terminal Q in the period T2.
  • the transistor 121 When a potential H is supplied to the terminal BK during period T2, the transistor 121 is turned on, and the nodes QB and SN are electrically connected. Therefore, the output of the third inverter circuit 116 is supplied to the node SN via the transistor 121.
  • a potential L is supplied to the terminal BK to turn off the transistor 121, thereby retaining the potential (charge) written to the node SN.
  • the period T3 is a period during which power gating is performed. Specifically, power supply to the semiconductor device 100A is stopped during the period T3 (Power off). When the power supply to the semiconductor device 100A is stopped, the potentials of the nodes Q0, Q1, QB, and Q become the potential L. On the other hand, the potential of the node SN is maintained even during the period T3 during which the power supply is stopped.
  • the supply of the clock signal CLK can also be stopped.
  • the generation of the inverted clock signal CLKB inside the semiconductor device 100A also stops.
  • the power consumption of the semiconductor device 100A can be reduced.
  • Period T4 is a period for performing a data restore operation. Specifically, during the period T4, an operation is performed to return the potential supplied to the terminal Q to the state immediately before power gating (period T3). Prior to the period T4, the supply of power and the supply of the clock signal CLK to the semiconductor device 100A are resumed. Note that immediately after the power supply, the potentials of the nodes Q0, Q1, QB, and Q are not determined. Therefore, the potential supplied to the terminal Q is also not determined.
  • potential H when potential H is supplied to terminal RE, the inverted potential of node SN is supplied to node Q1.
  • potential H is held at node SN, so potential L is supplied to node Q1.
  • potential H is supplied from second inverter circuit 114 to node Q0, because inverted clock signal CLKB is at potential H.
  • potential L is supplied to the input section of third inverter circuit 116, and potential H is applied from third inverter circuit 116 to node QB. Furthermore, potential L is supplied to terminal Q from fifth inverter circuit 119.
  • the semiconductor device 100A can return the potential supplied to the terminal Q to the state it was in immediately before power gating (period T3). Furthermore, the semiconductor device 100A according to one aspect of the present invention can complete period T4 in one clock cycle. Therefore, the process from resumption of power supply to data recovery can be completed in an extremely short time.
  • the semiconductor device 100A according to one aspect of the present invention can achieve both power saving through power gating and high-speed recovery from power gating.
  • ⁇ Modification 1> 5 shows the circuit configuration of a semiconductor device 100B, which is a modified example of the semiconductor device 100A.
  • the semiconductor device 100B is the semiconductor device 100A capable of executing a reset operation.
  • the semiconductor device 100B is the semiconductor device 100A to which a reset function has been added.
  • the semiconductor device 100B has a terminal RES, and a reset signal Reset is supplied to the terminal RES.
  • the semiconductor device 100B has a configuration in which the second inverter circuit 114 of the semiconductor device 100A is replaced with a NAND circuit 156, and the third inverter circuit 116 is replaced with a NAND circuit 157. Both the NAND circuit 156 and the NAND circuit 157 are two-input, one-output NAND circuits.
  • the first input part of the NAND circuit 156 is electrically connected to the output part of the NOR circuit 134 and one terminal of the third switch 115.
  • the second input part of the NAND circuit 156 is electrically connected to the terminal RES.
  • a reset signal Reset is supplied to the second input part of the NAND circuit 156.
  • the output part of the NAND circuit 156 is electrically connected to the other terminal of the second switch 113.
  • the area electrically connected to the first input part of the NAND circuit 156, the output part of the NOR circuit 134, and one terminal of the third switch 115 is called node Q1.
  • the first input part of the NAND circuit 157 is electrically connected to the terminal RES. Therefore, a reset signal Reset is supplied to the first input part of the NAND circuit 157.
  • the second input part of the NAND circuit 157 is electrically connected to the other terminal of the third switch 115 and one terminal of the fourth switch 117.
  • the output part of the NAND circuit 157 is electrically connected to the input part of the fourth inverter circuit 118, the input part of the fifth inverter circuit 119, and one of the source or drain of the transistor 121.
  • the region electrically connected to the output part of the NAND circuit 157, the input part of the fourth inverter circuit 118, the input part of the fifth inverter circuit 119, and one of the source or drain of the transistor 121 is called the node QB.
  • Figure 6A shows the circuit symbol of semiconductor device 100B.
  • Figure 6B shows a timing chart explaining the operation of semiconductor device 100B.
  • Period T5 shown in Figure 6B is the timing chart when the reset operation is performed.
  • the NAND circuit 156 When the reset signal Reset is at potential H, the NAND circuit 156 outputs an inverted potential of the potential supplied to the first input section. Also, when the reset signal Reset is at potential H, the NAND circuit 157 outputs an inverted potential of the potential supplied to the second input section. Therefore, when the reset signal Reset is at potential H, the NAND circuit 156 and the NAND circuit 157 function as an inverter circuit. Also, when the reset signal Reset is at potential L, the NAND circuit 156 and the NAND circuit 157 always output potential H.
  • the output of the NAND circuit 157 is supplied to the terminal Q via the fifth inverter circuit 119. Therefore, by supplying a potential L as a reset signal Reset to the terminal RES of the semiconductor device 100B, the potential supplied to the terminal Q can be set to potential L regardless of the potentials supplied to the terminals D and CK.
  • ⁇ Modification 2> 7 shows a circuit configuration of a semiconductor device 100C, which is a modification of the semiconductor device 100A.
  • the semiconductor device 100C is the semiconductor device 100A capable of performing a scan operation. That is, the semiconductor device 100C is the semiconductor device 100A to which a scan function for checking the operation is added.
  • the semiconductor device 100C has a terminal SEL and a terminal SD. An inspection signal is supplied to the terminal SD.
  • the semiconductor device 100C also has a transistor 159.
  • a gate of the transistor 159 is electrically connected to the terminal SEL, and one of a source or a drain is electrically connected to the terminal SD.
  • the other of the source or the drain of the transistor 159 is electrically connected to a first input portion of the first AND circuit 132, one terminal of the capacitor 122, and the other of the source or the drain of the transistor 121.
  • the region electrically connected to the other of the source or drain of the transistor 159, the first input portion of the first AND circuit 132, one terminal of the capacitor 122, and the other of the source or drain of the transistor 121 is called a node SN.
  • Figure 8A shows the circuit symbol of the semiconductor device 100C.
  • Figure 8B shows a timing chart explaining the operation of the semiconductor device 100C.
  • Period T6 shown in Figure 8B is the timing chart when the scan operation is performed.
  • the operation of the semiconductor device 100C is checked as follows. First, when a potential L is supplied to the terminal BK, the transistor 121 is in an off state, and the inverted clock signal CLKB is at a potential H, a potential H is supplied to the terminal RE. In addition, a potential H is supplied to the terminal SEL, turning on the transistor 159. The inspection signal supplied to the terminal SD is supplied to the node SN via the transistor 159.
  • a potential H is supplied to terminal SD as an inspection signal.
  • a potential L is supplied to node Q1
  • a potential H is supplied to node Q0.
  • a potential H is supplied to node QB
  • a potential L is supplied to terminal Q. If semiconductor device 100C is operating normally, the potential of terminal Q becomes a potential H when potential L is supplied to node SN as an inspection signal, and the potential of terminal Q becomes a potential L when potential H is supplied to node SN as an inspection signal. By supplying potential H or potential L as an inspection signal and comparing the potential of the inspection signal with the potential supplied to terminal Q, it can be confirmed whether semiconductor device 100C is operating correctly.
  • ⁇ Modification 3> 9 shows a circuit configuration of a semiconductor device 100D, which is a modification of the semiconductor device 100A.
  • the semiconductor device 100C has a configuration in which the terminal RE is removed from the semiconductor device 100A and an edge detection circuit 160 is added.
  • the edge detection circuit 160 has a terminal REout.
  • the terminal REout is electrically connected to the second input part of the first AND circuit 132 and the input part of the inverter circuit 131.
  • FIG. 10A A circuit configuration applicable to the edge detection circuit 160 is shown in FIG. 10A.
  • the edge detection circuit 160 shown in FIG. 10A has an inverter circuit 161, an AND circuit 162, a resistive element 163, and a capacitive element 164.
  • the input portion of the inverter circuit 161 is electrically connected to the terminal Pin and the first input portion IN1 of the AND circuit 162.
  • VDD potential H
  • the output portion of the inverter circuit 161 is electrically connected to one terminal of the resistive element 163.
  • the other terminal of the resistive element 163 is electrically connected to one terminal (or electrode) of the capacitive element 164 and the second input portion IN2 of the AND circuit 162.
  • the output portion of the AND circuit 162 is electrically connected to the terminal REout.
  • the resistor element 163 and the capacitor element 164 form a delay circuit 165. Therefore, the output part of the inverter circuit 161 and the second input part IN2 of the AND circuit 162 are connected via the delay circuit 165. In addition, a high power supply potential VDD (potential H) is supplied to the inverter circuit 161 via the terminal Pin2 as the power supply for the inverter circuit 161.
  • VDD potential H
  • Figure 10B shows a timing chart explaining the operation of the edge detection circuit 160.
  • the potential of the input section and the first input section IN1 of the inverter circuit 161 becomes potential L in conjunction with the stop of the power supply to the terminal Pin (stop of the VDD supply). Note that the power supply to the inverter circuit 161 does not stop even in period T3.
  • VDD continues to be supplied to the inverter circuit 161 via the terminal Pin2
  • a potential H is supplied to the output section of the inverter circuit 161.
  • the output section of the inverter circuit 161 and the second input section IN2 of the AND circuit 162 are connected via the delay circuit 165, the potential supplied to the second input section IN2 changes smoothly from potential L to potential H after the power supply is stopped.
  • period T3 ends and power supply is resumed (period T4)
  • potential H is supplied to the input section and first input section IN1 of inverter circuit 161, and potential L is supplied to the output section of inverter circuit 161.
  • the output section of inverter circuit 161 and second input section IN2 of AND circuit 162 are connected via delay circuit 165. Therefore, the potential supplied to second input section IN2 changes smoothly from potential H to potential L. For this reason, potential H is supplied from the output section of AND circuit 162 immediately after the start of period T4, and potential L is supplied from the output section of AND circuit 162 after a certain time has elapsed.
  • the semiconductor device 100D can reduce the number of terminals required for operation compared to the semiconductor device 100A. This reduces the number of types of signals required for operation, making it possible to realize a semiconductor device with good controllability.
  • the circuits, transistors, and the like constituting the semiconductor device 100 may be provided on the same plane, but it is preferable to provide them so that at least a portion of them overlap.
  • the semiconductor device 100A shown in Figures 11A and 11B shows a configuration example in which a first circuit 110 and a third circuit 130 are formed in a layer 10 including Si transistors, and a second circuit 120 is provided in a layer 20 including OS transistors on the layer 10.
  • a second circuit 120 is provided above the first circuit 110 and the third circuit 130, the area occupied by the semiconductor device 100A can be reduced.
  • the first circuit 110 and the third circuit 130 of the semiconductor device 100A can be configured as CMOS circuits using Si transistors, and the second circuit 120 can be configured to include OS transistors.
  • the switches can be provided in layer 20. By providing the switches in layer 20, the area occupied by the semiconductor device 100A can be reduced.
  • OS transistors may be used as some of the transistors constituting the first circuit 110, the third circuit 130, and the edge detection circuit 160 described above.
  • 12A, 12B, and 12C are a plan view and a cross-sectional view of a transistor 750 that can be used for a semiconductor device of one embodiment of the present invention.
  • the transistor 750 can be used as, for example, the transistor 121.
  • the transistor 750 may be used in part of the first circuit 110, the third circuit 130, and the edge detection circuit 160.
  • Figure 12A is a plan view of transistor 750.
  • Figures 12B and 12C are cross-sectional views of transistor 750.
  • Figure 12B is a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 12A, and is also a cross-sectional view of transistor 750 in the channel length direction.
  • Figure 12C is a cross-sectional view of the portion indicated by dashed line A3-A4 in Figure 12A, and is also a cross-sectional view of transistor 750 in the channel width direction. Note that in the plan view of Figure 12A, some elements are omitted for clarity.
  • the transistor 750 has a metal oxide 220a arranged on a substrate (not shown), a metal oxide 220b arranged on the metal oxide 220a, conductive layers 242a and 242b arranged on the metal oxide 220b at a distance from each other, an insulating layer 280 arranged on the conductive layers 242a and 242b and having an opening formed between the conductive layers 242a and 242b, a conductive layer 260 arranged in the opening, an insulating layer 250 arranged between the metal oxide 220b, the conductive layers 242a, 242b, and the insulating layer 280, and the conductive layer 260, and a metal oxide 220c arranged between the metal oxide 220b, the conductive layers 242a, 242b, the insulating layer 280, and the insulating layer 250.
  • the top surface of the conductive layer 260 is approximately the same as the top surfaces of the insulating layer 250, the insulating layer 254, the metal oxide 220c, and the insulating layer 280.
  • the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c may be collectively referred to as the metal oxide 220.
  • the conductive layer 242a and the conductive layer 242b may be collectively referred to as the conductive layer 242.
  • an insulating layer 254 is disposed between the insulating layer 224, the metal oxide 220a, the metal oxide 220b, the conductive layer 242a, the conductive layer 242b, and the metal oxide 220c and the insulating layer 280.
  • the insulating layer 254 contacts the side of the metal oxide 220c, the top and side of the conductive layer 242a, the top and side of the conductive layer 242b, the side of the metal oxide 220a and the metal oxide 220b, and the top surface of the insulating layer 224, as shown in FIGS. 12B and 12C.
  • the transistor 750 has a structure in which three layers of metal oxide 220a, metal oxide 220b, and metal oxide 220c are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof, but the present invention is not limited to this.
  • a two-layer structure of metal oxide 220b and metal oxide 220c or a stacked structure of four or more layers may be provided.
  • each of metal oxide 220a, metal oxide 220b, and metal oxide 220c may have a stacked structure of two or more layers.
  • metal oxide 220c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide
  • the first metal oxide has a composition similar to that of metal oxide 220b
  • the second metal oxide has a composition similar to that of metal oxide 220a.
  • the conductive layer 260 functions as a gate electrode of the transistor, and the conductive layer 242a and the conductive layer 242b function as a source electrode or a drain electrode.
  • the conductive layer 260 is formed so as to be embedded in the opening of the insulating layer 280 and the region sandwiched between the conductive layer 242a and the conductive layer 242b.
  • the arrangement of the conductive layer 260, the conductive layer 242a, and the conductive layer 242b is selected in a self-aligned manner with respect to the opening of the insulating layer 280. That is, in the transistor 750, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductive layer 260 can be formed without providing a margin for alignment, so that the area occupied by the transistor 750 can be reduced. This can reduce the area occupied by the semiconductor device. In addition, the integration degree of the semiconductor device can be increased.
  • the conductive layer 260 preferably includes a conductive layer 260a provided inside the insulating layer 250 and a conductive layer 260b provided so as to be embedded inside the conductive layer 260a.
  • the conductive layer 260 is shown as having a two-layer stacked structure, but the present invention is not limited to this.
  • the conductive layer 260 may have a single-layer structure or a stacked structure of three or more layers.
  • the transistor 750 preferably has an insulating layer 214 disposed on a substrate (not shown), an insulating layer 216 disposed on the insulating layer 214, a conductive layer 205 disposed so as to be embedded in the insulating layer 216, an insulating layer 222 disposed on the insulating layer 216 and the conductive layer 205, and an insulating layer 224 disposed on the insulating layer 222.
  • a metal oxide 220a is preferably disposed on the insulating layer 224.
  • an insulating layer 274 and an insulating layer 281, which function as an interlayer film, are disposed on the transistor 750.
  • the insulating layer 274 is disposed in contact with the upper surfaces of the conductive layer 260, the insulating layer 250, the insulating layer 254, the metal oxide 220c, and the insulating layer 280.
  • the insulating layer 222, the insulating layer 254, and the insulating layer 274 preferably have a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.).
  • the insulating layer 222, the insulating layer 254, and the insulating layer 274 preferably have lower hydrogen permeability than the insulating layer 224, the insulating layer 250, and the insulating layer 280.
  • the insulating layer 222 and the insulating layer 254 preferably have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).
  • the insulating layer 222 and the insulating layer 254 preferably have lower oxygen permeability than the insulating layer 224, the insulating layer 250, and the insulating layer 280.
  • the insulating layer 224, the metal oxide 220, and the insulating layer 250 are separated by the insulating layer 222 and the insulating layer 274. Therefore, impurities such as hydrogen and excess oxygen contained in the layers above the insulating layer 274 and below the insulating layer 222 can be prevented from being mixed into the insulating layer 224, the metal oxide 220, and the insulating layer 250.
  • a conductive layer 245 (conductive layer 245a and conductive layer 245b) is provided, which is electrically connected to the transistor 750 and functions as a plug.
  • an insulating layer 241 (insulating layer 241a and insulating layer 241b) is provided in contact with the side surface of the conductive layer 245 that functions as a plug. That is, the insulating layer 241 is provided in contact with the inner walls of the openings of the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281.
  • a first conductive layer of the conductive layer 245 may be provided in contact with the side surface of the insulating layer 241, and a second conductive layer of the conductive layer 245 may be provided further inside.
  • the height of the upper surface of the conductive layer 245 and the height of the upper surface of the insulating layer 281 can be made approximately the same.
  • the conductive layer 245 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by giving ordinal numbers in the order of formation.
  • the transistor 750 it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 220 (metal oxide 220a, metal oxide 220b, and metal oxide 220c) including the channel formation region.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that indium (In) and zinc (Zn) are contained. In addition to these, it is preferable that the element M is contained.
  • the element M one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg) or cobalt (Co) can be used.
  • the element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y) or tin (Sn). In addition, it is more preferable that the element M has either one or both of Ga and Sn.
  • metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as "IGTO”), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO”), and aluminum zinc oxide (Al-Zn oxide). (also written as "AZO”). Indium aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO").
  • Indium tin zinc oxide Indium Sn-Zn oxide. Indium titanium zinc oxide (In-Ti-Zn oxide). Indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO”). Indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO”). Indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO”). Or indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.
  • the field effect mobility of the transistor can be increased.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be realized.
  • a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc may be used.
  • a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin may be used.
  • a metal oxide in which the atomic ratio of indium is higher than that of tin may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of tin.
  • a metal oxide in which the atomic ratio of indium is higher than that of aluminum may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum.
  • a metal oxide in which the atomic ratio of indium is higher than that of gallium may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M may be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • a composition close thereto includes a range of ⁇ 30% of the desired atomic ratio. It is also preferable to use gallium as element M.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of element M.
  • the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of element M.
  • the atomic ratios of indium, element M, and zinc are within the above-mentioned range.
  • the composition of the metal oxide can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used to perform the analysis.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • Metal oxides can be formed by sputtering, ALD, metal organic chemical vapor deposition (MOCVD), and other methods.
  • the atomic ratio of the target may differ from the atomic ratio of the metal oxide.
  • the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • the thickness of the metal oxide 220b in the region that does not overlap with the conductive layer 242 may be thinner than the thickness of the region that overlaps with the conductive layer 242. This is formed by removing a part of the upper surface of the metal oxide 220b when forming the conductive layer 242a and the conductive layer 242b.
  • a conductive film that becomes the conductive layer 242 is formed on the upper surface of the metal oxide 220b, a low resistance region may be formed near the interface with the conductive film. In this way, by removing the low resistance region located between the conductive layer 242a and the conductive layer 242b on the upper surface of the metal oxide 220b, it is possible to prevent a channel from being formed in that region.
  • transistor 750 that can be used in a semiconductor device that is one embodiment of the present invention is described below.
  • the conductive layer 205 is arranged so as to have an overlapping region with the metal oxide 220 and the conductive layer 260. In addition, the conductive layer 205 is preferably embedded in the insulating layer 216.
  • the conductive layer 205 includes a conductive layer 205a, a conductive layer 205b, and a conductive layer 205c.
  • the conductive layer 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 216.
  • the conductive layer 205b is provided so as to be embedded in a recess formed in the conductive layer 205a.
  • the upper surface of the conductive layer 205b is lower than the upper surface of the conductive layer 205a and the upper surface of the insulating layer 216.
  • the conductive layer 205c is provided in contact with the upper surface of the conductive layer 205b and the side surface of the conductive layer 205a.
  • the height of the upper surface of the conductive layer 205c is approximately the same as the height of the upper surface of the conductive layer 205a and the height of the upper surface of the insulating layer 216.
  • the conductive layer 205b is configured to be wrapped in the conductive layer 205a and the conductive layer 205c.
  • the conductive layer 205a and the conductive layer 205c are preferably made of a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc., or a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc.
  • a conductive material having a function of suppressing diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • a conductive material having a function of reducing hydrogen diffusion for the conductive layer 205a and the conductive layer 205c it is possible to suppress the diffusion of impurities such as hydrogen contained in the conductive layer 205b to the metal oxide 220 through the insulating layer 224 or the like.
  • a conductive material having a function of suppressing oxygen diffusion for the conductive layer 205a and the conductive layer 205c it is possible to suppress the conductive layer 205b from being oxidized and its conductivity from decreasing.
  • the conductive layer 205a is formed of the above-mentioned conductive material in a single layer or a stacked layer.
  • titanium nitride may be used for the conductive layer 205a.
  • the conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductive layer 205b may be made of tungsten.
  • the conductive layer 260 may function as a first gate (also referred to as a top gate) electrode.
  • the conductive layer 205 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage (Vth) of the transistor 750 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260.
  • the Vth of the transistor 750 can be increased and the off-current can be reduced. Therefore, the drain current when the potential applied to the conductive layer 260 is 0 V can be reduced by applying a negative potential to the conductive layer 205 compared to the case where a negative potential is not applied.
  • the conductive layer 205 should be larger than the channel formation region in the metal oxide 220. In particular, as shown in FIG. 12C, it is preferable that the conductive layer 205 also extends in a region outside the end of the metal oxide 220 that intersects with the channel width direction. In other words, it is preferable that the conductive layer 205 and the conductive layer 260 overlap with each other via an insulating layer on the outside of the side surface of the metal oxide 220 in the channel width direction.
  • the channel formation region of the metal oxide 220 can be electrically surrounded by the electric field of the conductive layer 260 that functions as a first gate electrode and the electric field of the conductive layer 205 that functions as a second gate electrode.
  • the conductive layer 205 may be extended beyond the metal oxide 220 and used as wiring. However, this is not limited to this, and a conductive layer that functions as wiring may be provided below the conductive layer 205.
  • the insulating layer 214 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 750 from the substrate side. Therefore, the insulating layer 214 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms (the impurities are unlikely to permeate through the insulating material), or a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is unlikely to permeate through the insulating material).
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.)
  • oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • the insulating layer 214 it is preferable to use aluminum oxide or silicon nitride as the insulating layer 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 214 to the transistor 750 side. Alternatively, it can prevent oxygen contained in the insulating layer 224, etc. from diffusing to the substrate side of the insulating layer 214.
  • the insulating layer 216, insulating layer 280, and insulating layer 281, which function as interlayer films, preferably have a lower dielectric constant than the insulating layer 214.
  • a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, or the like may be used as appropriate for the insulating layer 216, insulating layer 280, and insulating layer 281.
  • the insulating layer 222 and the insulating layer 224 function as gate insulating layers.
  • the insulating layer 224 in contact with the metal oxide 220 releases oxygen by heating.
  • oxygen released by heating is sometimes referred to as excess oxygen.
  • the insulating layer 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate.
  • the oxide from which oxygen is released by heating is an oxide film from which the amount of oxygen released in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms/cm 3 or more, preferably 1.0 ⁇ 10 19 atoms/cm 3 or more, and more preferably 2.0 ⁇ 10 19 atoms/cm 3 or more, or 3.0 ⁇ 10 20 atoms /cm 3 or more, as determined by TDS (Thermal Desorption Spectroscopy) analysis.
  • TDS Thermal Desorption Spectroscopy
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.
  • the thickness of the insulating layer 224 in the region that does not overlap the insulating layer 254 and does not overlap the metal oxide 220b may be thinner than the thickness of the other regions. It is preferable that the thickness of the insulating layer 224 in the region that does not overlap the insulating layer 254 and does not overlap the metal oxide 220b is a thickness that allows the oxygen to be sufficiently diffused.
  • the insulating layer 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 750 from the substrate side.
  • the insulating layer 222 preferably has lower hydrogen permeability than the insulating layer 224.
  • the insulating layer 222 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).
  • oxygen e.g., at least one of oxygen atoms, oxygen molecules, etc.
  • the insulating layer 222 has lower oxygen permeability than the insulating layer 224. Since the insulating layer 222 has a function of suppressing the diffusion of oxygen and impurities, it is preferable that the diffusion of oxygen contained in the metal oxide 220 toward the substrate side can be reduced.
  • the insulating layer 222 may be an insulating layer containing an oxide of one or both of the insulating materials aluminum and hafnium.
  • an insulating layer containing an oxide of one or both of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulating layer 222 functions as a layer that suppresses the release of oxygen from the metal oxide 220 and the intrusion of impurities such as hydrogen from the periphery of the transistor 750 into the metal oxide 220.
  • the insulating layer 222 may have a structure in which three layers of silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.
  • the insulating layer 222 may be a single layer or a multilayer insulating layer containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST).
  • a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST).
  • the insulating layer 222 and the insulating layer 224 may have a laminated structure of two or more layers. In that case, they are not limited to a laminated structure made of the same material, and a laminated structure made of different materials is also possible. For example, it is also possible to configure an insulating layer similar to the insulating layer 224 to be provided under the insulating layer 222.
  • Metal oxide 220 has metal oxide 220a, metal oxide 220b on metal oxide 220a, and metal oxide 220c on metal oxide 220b.
  • metal oxide 220a below metal oxide 220b, it is possible to suppress the diffusion of impurities from structures formed below metal oxide 220a to metal oxide 220b.
  • metal oxide 220c on metal oxide 220b it is possible to suppress the diffusion of impurities from structures formed above metal oxide 220c to metal oxide 220b.
  • the metal oxide 220 preferably has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom.
  • the metal oxide 220 contains at least indium (In) and element M
  • it is preferable that the ratio of the number of atoms of element M contained in the metal oxide 220a to the number of atoms of all elements constituting the metal oxide 220a is higher than the ratio of the number of atoms of element M contained in the metal oxide 220b to the number of atoms of all elements constituting the metal oxide 220b.
  • the atomic ratio of element M contained in the metal oxide 220a to In is higher than the atomic ratio of element M contained in the metal oxide 220b to In.
  • the metal oxide 220c can be a metal oxide that can be used for the metal oxide 220a or the metal oxide 220b.
  • the energy of the conduction band minimum of the metal oxide 220a and the metal oxide 220c is preferably higher than the energy of the conduction band minimum of the metal oxide 220b.
  • the electron affinity of the metal oxide 220a and the metal oxide 220c is preferably smaller than the electron affinity of the metal oxide 220b.
  • the metal oxide 220c is preferably a metal oxide that can be used for the metal oxide 220a.
  • the ratio of the number of atoms of the element M contained in the metal oxide 220c to the number of atoms of all elements constituting the metal oxide 220c is higher than the ratio of the number of atoms of the element M contained in the metal oxide 220b to the number of atoms of all elements constituting the metal oxide 220b. It is also preferable that the atomic ratio of the element M contained in the metal oxide 220c to In is higher than the atomic ratio of the element M contained in the metal oxide 220b to In.
  • the energy level of the conduction band minimum changes gradually.
  • the energy level of the conduction band minimum at the junctions of the metal oxide 220a, the metal oxide 220b, and the metal oxide 220c changes continuously or is continuously junctioned.
  • the metal oxide 220a and the metal oxide 220b, and the metal oxide 220b and the metal oxide 220c have a common element other than oxygen (main component), so that a mixed layer with a low defect level density can be formed.
  • the metal oxide 220b is an In-Ga-Zn oxide
  • the metal oxide 220a and the metal oxide 220c may be made of In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like.
  • the metal oxide 220c may also have a laminated structure.
  • a laminated structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used.
  • a laminated structure of In-Ga-Zn oxide and an oxide not containing In may be used as the metal oxide 220c.
  • the main path of the carriers is the metal oxide 220b.
  • the defect level density at the interface between the metal oxide 220a and the metal oxide 220b and the interface between the metal oxide 220b and the metal oxide 220c can be reduced. Therefore, the influence of the interface scattering on the carrier conduction is reduced, and the transistor 750 can obtain a high on-current and high frequency characteristics.
  • the metal oxide 220c has a stacked structure, it is expected that the constituent elements of the metal oxide 220c are prevented from diffusing to the insulating layer 250 side.
  • the metal oxide 220c has a stacked structure, and an oxide that does not contain In is positioned above the stacked structure, so that In that may diffuse to the insulating layer 250 side can be suppressed. Since the insulating layer 250 functions as a gate insulating layer, if In diffuses, the transistor characteristics will be poor. Therefore, by forming the metal oxide 220c into a layered structure, it is possible to provide a highly reliable semiconductor device.
  • a conductive layer 242 (conductive layer 242a and conductive layer 242b) functioning as a source electrode and a drain electrode is provided.
  • the conductive layer 242 it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal elements, or an alloy combining the above-mentioned metal elements.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or materials that maintain their conductivity even when they absorb oxygen, and are therefore preferable.
  • the oxygen concentration may be reduced in the vicinity of the conductive layer 242 of the metal oxide 220.
  • a metal compound layer containing the metal contained in the conductive layer 242 and components of the metal oxide 220 may be formed in the vicinity of the conductive layer 242 of the metal oxide 220. In such a case, the carrier concentration increases in the region in the vicinity of the conductive layer 242 of the metal oxide 220, and the region becomes a low resistance region.
  • the region between conductive layer 242a and conductive layer 242b is formed so as to overlap the opening of insulating layer 280. This allows conductive layer 260 to be positioned in a self-aligned manner between conductive layer 242a and conductive layer 242b.
  • the insulating layer 250 functions as a gate insulating layer. It is preferable that the insulating layer 250 is disposed in contact with the upper surface of the metal oxide 220c.
  • the insulating layer 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulating layer 250 preferably has a reduced concentration of impurities such as water or hydrogen.
  • the thickness of the insulating layer 250 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulating layer 250 and the conductive layer 260.
  • the metal oxide preferably suppresses oxygen diffusion from the insulating layer 250 to the conductive layer 260. This makes it possible to suppress oxidation of the conductive layer 260 due to oxygen in the insulating layer 250.
  • the metal oxide may function as part of the gate insulating layer. Therefore, when silicon oxide or silicon oxynitride is used for the insulating layer 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant.
  • a metal oxide that is a high-k material with a high dielectric constant By forming the gate insulating layer into a laminated structure of the insulating layer 250 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.
  • EOT equivalent oxide thickness
  • metal oxides containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used.
  • aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), etc. which are insulators containing oxides of either or both aluminum and hafnium.
  • the conductive layer 260 is shown as a two-layer structure in Figures 12A to 12C, but it can be a single-layer structure or a stacked structure of three or more layers.
  • the conductive layer 260a is preferably made of a conductive layer having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( N2O , NO, NO2 , etc.), copper atoms, etc.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • the conductive layer 260a has a function of suppressing the diffusion of oxygen, which can suppress the conductive layer 260b from being oxidized by the oxygen contained in the insulating layer 250 and causing a decrease in conductivity.
  • a conductive material having a function of suppressing the diffusion of oxygen it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.
  • the conductive layer 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductive layer 260 also functions as wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductive layer 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.
  • the side of the metal oxide 220 is arranged to be covered with the conductive layer 260. This makes it easier for the electric field of the conductive layer 260, which functions as the first gate electrode, to act on the side of the metal oxide 220. This increases the on-current of the transistor 750 and improves the frequency characteristics.
  • the insulating layer 254 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 750 from the insulating layer 280 side, similar to the insulating layer 214.
  • the insulating layer 254 preferably has lower hydrogen permeability than the insulating layer 224.
  • the insulating layer 254 preferably contacts the side of the metal oxide 220c, the top and side of the conductive layer 242a, the top and side of the conductive layer 242b, the side of the metal oxide 220a and the metal oxide 220b, and the top of the insulating layer 224.
  • hydrogen contained in the insulating layer 280 can be suppressed from entering the metal oxide 220 from the top or side of the conductive layer 242a, the conductive layer 242b, the metal oxide 220a, the metal oxide 220b, and the insulating layer 224.
  • the insulating layer 254 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).
  • the insulating layer 254 has lower oxygen permeability than the insulating layer 280 or the insulating layer 224.
  • the insulating layer 254 is preferably formed by a sputtering method.
  • oxygen can be added to the region of the insulating layer 224 near the region in contact with the insulating layer 254. This allows oxygen to be supplied from this region to the metal oxide 220 through the insulating layer 224.
  • the insulating layer 254 has a function of suppressing the upward diffusion of oxygen, so that oxygen can be prevented from diffusing from the metal oxide 220 to the insulating layer 280.
  • the insulating layer 222 has a function of suppressing the downward diffusion of oxygen, so that oxygen can be prevented from diffusing from the metal oxide 220 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 220. This reduces oxygen deficiency in the metal oxide 220 and suppresses the normally-on state of the transistor.
  • an insulating layer containing an oxide of one or both of aluminum and hafnium is formed. Note that it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulating layer containing an oxide of one or both of aluminum and hafnium.
  • the insulating layer 280 is provided on the insulating layer 224, the metal oxide 220, and the conductive layer 242 via the insulating layer 254.
  • the insulating layer 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having voids.
  • silicon oxide and silicon oxynitride are preferred because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having voids are preferred because they can easily form a region containing oxygen that is released by heating.
  • the concentration of impurities such as water or hydrogen in the insulating layer 280 is reduced.
  • the upper surface of the insulating layer 280 may be flattened.
  • the insulating layer 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulating layer 280 from above.
  • the insulating layer 274 for example, an insulating layer that can be used for the insulating layer 214, the insulating layer 254, etc. may be used.
  • an insulating layer 281 that functions as an interlayer film on the insulating layer 274. It is preferable that the insulating layer 281 has a reduced impurity concentration, such as water or hydrogen, in the film, similar to the insulating layer 224, etc.
  • the conductive layer 245a and the conductive layer 245b are disposed in the openings formed in the insulating layer 281, the insulating layer 274, the insulating layer 280, and the insulating layer 254.
  • the conductive layer 245a and the conductive layer 245b are provided facing each other with the conductive layer 260 interposed therebetween. Note that the height of the upper surfaces of the conductive layer 245a and the conductive layer 245b may be flush with the upper surface of the insulating layer 281.
  • Insulating layer 241a is provided in contact with the inner walls of the openings of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and a first conductive layer of conductive layer 245a is formed in contact with the side surface.
  • Conductive layer 242a is located at least in a part of the bottom of the opening, and conductive layer 245a is in contact with conductive layer 242a.
  • insulating layer 241b is provided in contact with the inner walls of the openings of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and a first conductive layer of conductive layer 245b is formed in contact with the side surface.
  • Conductive layer 242b is located at least in a part of the bottom of the opening, and conductive layer 245b is in contact with conductive layer 242b.
  • the conductive layer 245a and the conductive layer 245b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductive layer 245a and the conductive layer 245b may have a stacked structure.
  • the conductive layer 245 has a laminated structure
  • the conductive layer having the function of suppressing the diffusion of impurities such as water or hydrogen as described above for the conductive layer in contact with the metal oxide 220a, the metal oxide 220b, the conductive layer 242, the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281.
  • the conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a laminated layer.
  • the conductive material By using the conductive material, it is possible to suppress the oxygen added to the insulating layer 280 from being absorbed by the conductive layer 245a and the conductive layer 245b. In addition, it is possible to suppress the impurities such as water or hydrogen from layers above the insulating layer 281 from being mixed into the metal oxide 220 through the conductive layer 245a and the conductive layer 245b.
  • an insulating layer that can be used for the insulating layer 254 or the like may be used. Since the insulating layer 241a and the insulating layer 241b are provided in contact with the insulating layer 254, impurities such as water or hydrogen from the insulating layer 280 or the like can be prevented from being mixed into the metal oxide 220 through the conductive layer 245a and the conductive layer 245b. In addition, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layer 245a and the conductive layer 245b.
  • a conductive layer functioning as wiring may be disposed in contact with the upper surface of the conductive layer 245a and the upper surface of the conductive layer 245b.
  • the conductive layer functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductive layer may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material.
  • the conductive layer may be formed so as to be embedded in an opening provided in the insulating layer.
  • FIG 13 shows a modification of the transistor 750 shown in FIG 12.
  • FIG 13A, FIG 13B, and FIG 13C are a plan view and a cross-sectional view of a transistor 751 which is a modification of the transistor 750. Since the transistor 751 is a modification of the transistor 750, differences between the transistor 751 and the transistor 750 will be mainly described.
  • Transistor 751 has a structure in which metal oxide 220c and conductive layer 205c are removed from the structure of transistor 750. By reducing the number of components of the transistor, production costs can be reduced. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, improving the manufacturing yield.
  • the transistor 751 has a region where the insulating layer 254 and the insulating layer 222 are in contact with each other outside the metal oxide 220, and the side surface of the insulating layer 224 is covered with the insulating layer 254.
  • the side surface of the insulating layer 224 is covered with the insulating layer 254.
  • an insulating layer may be provided between the insulating layer 280, the insulating layer 254, the conductive layer 242, and the metal oxide 220b and the insulating layer 250. It is preferable to use aluminum oxide, hafnium oxide, or the like as the insulating layer. By providing the insulating layer, it is possible to suppress the desorption of oxygen from the metal oxide 220 to the insulating layer 250 side, the excessive supply of oxygen from the insulating layer 250 side to the metal oxide 220, the oxidation of the conductive layer 242, and the like.
  • transistor 752 having a different structure from the transistors 750 and 751 will be described. Like the transistors 750 and 751, the transistor 752 can also be used in the semiconductor device of one embodiment of the present invention.
  • Figure 14A is a plan view of transistor 752.
  • Figure 14B is a cross-sectional view corresponding to the portion of dashed line A1-A2 shown in Figure 14A.
  • Figure 14C is a cross-sectional view corresponding to the portion of dashed line A3-A4 shown in Figure 14A.
  • the direction of the dashed dotted line A1-A2 is the X direction
  • the direction of the dashed dotted line A3-A4 is the Y direction
  • the direction perpendicular to the X and Y directions is the Z direction.
  • the transistor 752 shown in Figures 14A to 14C has insulating layers IS1 to IS3, insulating layer GI1, conductive layers ME1 to ME3, and a semiconductor SC1.
  • the insulating layer IS1 functions as a base film for providing the source, drain, and channel formation regions of the transistor 752 thereover, for example.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used.
  • silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies can be used.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulating layer IS1 can be made of a resin.
  • the material used for the insulating layer IS1 may be an appropriate combination of the above-mentioned insulating materials.
  • the conductive layer ME1 is a conductive layer (which may be referred to as a terminal, wiring, etc.) that functions as one of the source and drain in the transistor 752.
  • the conductive layer ME2 is a conductive layer (which may be referred to as a terminal, wiring, etc.) that functions as the other of the source and drain in the transistor 752.
  • the conductive layer ME1 is provided as a wiring so as to extend in the Y direction, as an example.
  • the conductive layer ME2 is provided as a wiring so as to extend in the X direction, as an example.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements.
  • the conductive layers ME1, ME2, and ME3 it is preferable to use, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.
  • Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize or materials that maintain their conductivity even when they absorb oxygen.
  • the conductive layer may be made of a semiconductor or silicide (e.g., nickel silicide) with high electrical conductivity, such as polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic).
  • conductive oxides may be used for the conductive layers ME1, ME2, and ME3.
  • conductive oxides include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide (also referred to as IZO (registered trademark)), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide and In-Ga-Zn oxide doped with gallium.
  • Conductive oxides containing indium are particularly preferred because of their high conductivity.
  • a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a specific example of a stacked structure of a conductive film is a stacked structure of indium oxide and a metal film containing ruthenium.
  • a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • the insulating layer IS2 functions as an interlayer film separating the source and drain in the transistor 752.
  • a material applicable to the insulating layer IS1 can be used for the insulating film IS2.
  • the semiconductor SC1 is a metal oxide that functions as an oxide semiconductor
  • silicon oxide, silicon oxynitride, or silicon oxide having vacancies These materials can easily form a region containing oxygen that is desorbed by heating, and can supply the desorbed oxygen to the metal oxide.
  • the carrier concentration of the metal oxide is reduced at the interface and near the interface of the semiconductor SC1 that is in contact with the insulating layer IS2, and the interface and near the interface of the semiconductor SC1 become i-type or substantially i-type. Therefore, the interface and near the interface of the semiconductor SC1 can function as a channel formation region in the transistor 752.
  • the semiconductor SC1 can be, for example, a metal oxide that functions as an oxide semiconductor.
  • the transistor 752 is an OS transistor.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide contains indium and zinc.
  • the element M is contained.
  • the element M one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used.
  • the element M is preferably one or more of aluminum, gallium, yttrium, and tin.
  • the element M contains one or both of gallium and tin.
  • metal oxides include indium oxide, gallium oxide, zinc oxide, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), and aluminum zinc oxide (Al-Zn oxide, also referred to as AZO).
  • In-Zn oxide also referred to as IZO (registered trademark)
  • In-Sn oxide indium titanium oxide
  • In-Ti oxide indium gallium oxide
  • In-Ga-Al oxide indium gallium tin oxide
  • Ga-Zn oxide gallium zinc oxide
  • Al-Zn oxide also referred to as AZO
  • indium aluminum zinc oxide In-Al-Zn oxide, also written as IAZO
  • indium tin zinc oxide In-Sn-Zn oxide, also written as ITZO (registered trademark)
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium zinc oxide In-Ga-Zn oxide, also written as IGZO
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also written as IGZTO
  • indium gallium aluminum zinc oxide In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO or IAGZO
  • Indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. containing silicon can be mentioned. Note that materials that do not contain Zn, such as indium oxide, are suitable because they have high affinity with Si processes. On the other hand, materials that contain Zn are suitable because they can increase crystallinity.
  • the semiconductor SC1 is a metal oxide that functions as an oxide semiconductor
  • the ALD method can be used to form a semiconductor with good coverage.
  • the microwave treatment refers to a treatment using an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • a crystalline metal oxide layer for the semiconductor SC1 For example, a metal oxide layer having a CAAC (c-axis-aligned crystalline) structure, a polycrystalline structure, a nanocrystalline (nc: nanocrystalline) structure, or the like can be used.
  • a crystalline metal oxide layer for the semiconductor SC1 the density of defect levels in the semiconductor SC1 can be reduced, and a highly reliable semiconductor device can be realized.
  • In-Ga-Zn oxide for the semiconductor SC1.
  • it is more preferable to use a metal oxide having a composition of In:Ga:Zn 1:1:1 [atomic ratio] or a composition close thereto, a composition of 4:2:3 [atomic ratio] or a composition close thereto, or a composition of 3:1:2 [atomic ratio] or a composition close thereto as the In-Ga-Zn oxide.
  • the semiconductor SC1 preferably has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom.
  • a first metal oxide and a second metal oxide formed on the first metal oxide as metal oxides.
  • each metal oxide contains at least indium (In) and element M
  • the ratio of the number of atoms of element M contained in the first metal oxide to the number of atoms of all elements constituting the first metal oxide is higher than the ratio of the number of atoms of element M contained in the second metal oxide to the number of atoms of all elements constituting the second metal oxide.
  • the atomic ratio of element M contained in the first metal oxide to In is higher than the atomic ratio of element M contained in the second metal oxide to In.
  • a composition close thereto includes a range of ⁇ 30% of the desired atomic ratio.
  • the main carrier path is the second metal oxide.
  • an opening KK1 is formed in the insulating layer IS2 in the region where the transistor 752 is provided, and the side surface is approximately perpendicular to the X-Y plane (taper angle is 70° or more and 110° or less).
  • the semiconductor SC1 including the channel formation region of the transistor 752 is provided so as to contact the conductive layers ME1 and ME2 through the opening KK1.
  • an insulating layer GI1 is provided on the semiconductor SC1. Specifically, in a plan view, the insulating layer GI1 is positioned so as to overlap the channel formation region included in the semiconductor SC1. The insulating layer GI1 functions as a gate insulating film in the transistor 752.
  • the insulating layer GI1 it is preferable to use a single layer or a laminate of insulating layers containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST).
  • high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST).
  • an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium (also called hafnium silicate, Hf x SiO y (x and y are each an arbitrary number)), an oxynitride having silicon and hafnium, or a nitride having silicon and hafnium may be used as an insulating layer having a high relative dielectric constant.
  • a material that can be used for the insulating layer IS1 may be applied.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride may be used for the insulating layer GI1.
  • the conductive layer ME3 is provided on the insulating layer GI1 so as to fill the opening KK1.
  • the conductive layer ME3 is a conductive layer (which may also be referred to as a terminal, wiring, etc.) that functions as a gate in the transistor 752.
  • the conductive layer ME3 is provided as wiring extending in the Y direction, as an example.
  • the insulating layer IS3 is, for example, a film that functions as an interlayer film. Therefore, it is preferable that the insulating layer IS3 has an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.
  • a material that can be used for insulating layer IS1 can be used for insulating layer IS3.
  • the transistor 752 shown in Figures 14A to 14C the conductive layer ME1 functioning as one of the source or drain is located below the insulating layer IS2, which serves as an interlayer film, and the conductive layer ME2 functioning as the other of the source or drain is located above the insulating layer IS2. Therefore, the transistor 752 is configured such that the channel formation region is provided along the opening of the insulating layer IS2.
  • Transistor 752 has a source and drain located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a height (vertical) component, so transistor 752 can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.
  • VFET Vertical Field Effect Transistor
  • the area occupied by the transistor can be made smaller than when the channel formation region of the transistor is provided along the X-Y plane. Therefore, by forming a circuit using one or both of the transistors 752, the area of the circuit can be made smaller. As a result, this can lead to a semiconductor device including the circuit or a miniaturization of the semiconductor device.
  • substrate When a semiconductor device including a transistor is provided on a substrate, there is no significant limitation on the material used for the substrate.
  • the substrate can be determined in consideration of the presence or absence of light transmission, heat resistance to a degree that can withstand heat treatment, and the like, depending on the purpose.
  • an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.), and resin substrates.
  • semiconductor substrates include semiconductor substrates of silicon, germanium, etc., or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, and the like. Or there are substrates having a metal nitride, substrates having a metal oxide, and the like.
  • substrates in which a conductive layer or a semiconductor is provided on an insulating substrate substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, substrates in which a semiconductor or an insulating layer is provided on a conductive substrate, etc.
  • a substrate provided with an element on such a substrate may be used.
  • the elements provided on the substrate include a capacitance element, a resistance element, a switching element, a light-emitting element, a memory element, etc.
  • an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like having insulating properties can be used.
  • an insulating material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used in a single layer or a stacked layer.
  • a plurality of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.
  • an oxynitride refers to a material that contains more nitrogen than oxygen.
  • An oxynitride refers to a material that contains more oxygen than nitrogen.
  • the content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).
  • the parasitic capacitance generated between wirings can be reduced. Therefore, it is important to select a material according to the function required for the insulating layer.
  • Insulating layers with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • Insulating layers with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resin.
  • the method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and spin coating can be used.
  • the transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulating layer (e.g., insulating layer 214, insulating layer 222, insulating layer 254, insulating layer 274, etc.) having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • an insulating layer e.g., insulating layer 214, insulating layer 222, insulating layer 254, insulating layer 274, etc.
  • an insulating layer having a function of suppressing the permeation of impurities such as hydrogen and oxygen for example, an insulating layer containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide
  • metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulating layer that functions as the gate insulating layer is preferably an insulating layer having a region that contains oxygen that is released by heating.
  • an insulating layer having a region that contains oxygen that is released by heating For example, by using a structure in which silicon oxide or silicon oxynitride having a region that contains oxygen that is released by heating is in contact with the metal oxide 220, oxygen vacancies in the metal oxide 220 can be compensated for.
  • the conductive layer it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component
  • tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed, so they are preferable.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the method for forming the conductive material is not particularly limited, and various methods such as a vapor deposition method, an ALD method, a CVD method, a sputtering method, and a spin coating method may be used.
  • a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive layer.
  • a conductive layer formed of a Cu-X alloy can be processed by a wet etching process, which makes it possible to reduce manufacturing costs.
  • an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive layer.
  • a plurality of conductive layers formed from the above materials may be stacked.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a laminate structure may also be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a laminate structure may also be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • the conductive layer functioning as the gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed.
  • the conductive material containing the above-mentioned metal element and nitrogen may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may also be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon has been added may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • semiconductor layer a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • semiconductor material for example, silicon, germanium, or the like can be used.
  • a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can be used.
  • an organic material having semiconductor properties or a metal oxide having semiconductor properties also called an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • the semiconductor layer may be made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon.
  • polycrystalline silicon low temperature polysilicon (LTPS), for example, may be used.
  • LTPS low temperature polysilicon
  • an oxide semiconductor has a band gap of 2 eV or more
  • a transistor (OS transistor) using an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed has a significantly small off-state current. Therefore, the power consumption of a semiconductor device including an OS transistor can be reduced.
  • an OS transistor operates stably even in a high-temperature environment and has little fluctuation in characteristics.
  • the off-state current hardly increases even in a high-temperature environment.
  • the off-state current hardly increases even in an environmental temperature of room temperature or higher and 200° C. or lower.
  • the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.
  • Metal oxides can be formed by sputtering, ALD, metal organic chemical vapor deposition (MOCVD), and other methods.
  • the atomic ratio of the target may differ from the atomic ratio of the metal oxide.
  • the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • Figure 15 shows an example of the stacked configuration of the semiconductor device 100A.
  • Figure 15 corresponds to the example of the stacked configuration of the semiconductor device 100A shown in Figure 11 of the above embodiment.
  • the 15 also shows a transistor 400 as an example of a transistor included in the first circuit 110 or the third circuit 130.
  • the transistor 400 is provided over a substrate 311 and has a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of a part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions.
  • the transistor 400 can be either a p-channel transistor or an n-channel transistor.
  • the substrate 311 can be, for example, a single crystal silicon substrate.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • the side and top surfaces of the semiconductor region 313 are covered with a conductive layer 316 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 400 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI (Silicon On Insulator) substrate.
  • transistor 400 shown in FIG. 15 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.
  • Layer 10 and layer 20 may be provided with a wiring layer having an interlayer film, wiring, plugs, etc. Also, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.
  • insulating layer 320, insulating layer 322, insulating layer 324, and insulating layer 326 are stacked in this order as an interlayer film.
  • Conductive layer 328 and conductive layer 330 are embedded in insulating layer 320, insulating layer 322, insulating layer 324, and insulating layer 326.
  • Conductive layer 328 and conductive layer 330 function as contact plugs or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the top surface of the insulating layer 322 may be subjected to a CMP process or the like to improve flatness.
  • a wiring layer may be provided on the insulating layer 326 and the conductive layer 330.
  • an insulating layer 350, an insulating layer 382, and an insulating layer 384 are stacked in this order on the insulating layer 326 and the conductive layer 330.
  • a conductive layer 386 is formed on the insulating layer 350, the insulating layer 382, and the insulating layer 384. The conductive layer 386 functions as a contact plug or wiring.
  • FIG. 15 illustrates an example of a transistor 121 and a capacitor 122 included in a second circuit 120 formed in the layer 20.
  • FIG. 15 an example is shown in which the transistor 751 described in the above embodiment is used as the transistor 121. To reduce repetition of the description, the description of the configuration of the transistor 751 is omitted.
  • a conductive layer 368 is embedded in insulating layer 281, insulating layer 274, insulating layer 280, insulating layer 254, insulating layer 222, insulating layer 216, and insulating layer 214.
  • the conductive layer 368 functions as a contact plug or wiring.
  • a conductive layer 283, a conductive layer 284, and an insulating layer 282 are provided on insulating layer 281.
  • One of the source and drain of transistor 121 is electrically connected to conductive layer 386 via conductive layer 283, conductive layer 368, etc.
  • an insulating layer 285 is provided over the conductive layer 283, the conductive layer 284, and the insulating layer 282.
  • a conductive layer 287 and an insulating layer 286 are provided over the insulating layer 285. The region where the conductive layer 284, the insulating layer 285, and the conductive layer 287 overlap functions as the capacitor element 122.
  • a conductive layer 289 and an insulating layer 288 are provided on the conductive layer 287 and the insulating layer 286.
  • a conductive layer 292 and an insulating layer 291 are provided on the conductive layer 289 and the insulating layer 288.
  • An insulating layer 293 is provided on the conductive layer 292 and the insulating layer 291.
  • the transistor 400 and the transistor 121 By stacking the transistor 400 and the transistor 121, the area occupied by the semiconductor device 100A can be reduced. In addition, by stacking the transistor 400 and the transistor 121, the length of the wiring electrically connecting the two can be shortened. This reduces the parasitic capacitance and wiring resistance associated with the wiring, and the power consumption of the semiconductor device 100A can be reduced. In addition, the signal propagation distance is shortened, and the operating speed of the semiconductor device 100A can be increased.
  • FIG. 16 shows a block diagram illustrating a configuration example of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 16 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 950.
  • FIG. 16 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.
  • the semiconductor device 100 (semiconductor device 100A, semiconductor device 100B, semiconductor device 100C, and semiconductor device 100D) exemplified in the above embodiment can be used for the memory cell 950.
  • the driver circuit 910 may be provided in, for example, layer 10 shown in FIG. 11.
  • the drive circuit 910 has a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 has a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added.
  • Signals BW, CE, GW, CLKK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by the control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLKK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLKK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to the memory cells 950.
  • the peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • the row decoder 941 and column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, the function of retaining the read data, etc.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 950.
  • the data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply potential of the semiconductor device 900 is V DD
  • the low power supply potential is GND (ground potential).
  • V HM is a high power supply potential used to set the word line to a high level, and is higher than V DD .
  • the on/off of the PSW 931 is controlled by a signal PON1, and the on/off of the PSW 932 is controlled by a signal PON2.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch may be provided for each power supply domain.
  • Figure 17 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in Figure 17 can be applied to, for example, a CPU (Central Processing Unit).
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • the arithmetic device 960 shown in FIG. 17 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache memory 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache memory 999 and the cache interface 989 may be provided on a separate chip.
  • the semiconductor device 100 may be used for the register 996.
  • the cache memory 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache memory 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache memory 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache memory 999.
  • the arithmetic device 960 shown in FIG. 17 is merely an example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. In addition, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state while the arithmetic device 960 is executing a program. The register controller 997 generates an address for the register 996, and reads and writes to the register 996 depending on the state of the arithmetic device 960.
  • the timing controller 995 also generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply potential to the memory cells in the register 996 can be stopped.
  • FIGs. 18A and 18B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which the memory array 920 is provided on the arithmetic device 960.
  • memory arrays 920L1, 920L2, and 920L3 are shown as the memory array 920.
  • the layer 930 is provided with memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array 920 have overlapping areas.
  • Fig. 18B shows the arithmetic device 960 and the layer 930 separated from each other.
  • connection distance between the two can be shortened. This allows the communication speed between the two to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having the memory array 920 and the arithmetic device 960 As a method for stacking the layer 930 having the memory array 920 and the arithmetic device 960, a method of stacking the layer 930 having the memory array 920 directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using a through via or conductive film bonding technology (such as Cu-Cu bonding) may be used.
  • the former method does not require consideration of misalignment during bonding, so it is possible to reduce not only the chip size but also the manufacturing cost.
  • the arithmetic device 960 does not have a cache memory 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache memory.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest storage capacity and is accessed least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger storage capacity than the cache and is accessed less frequently.
  • the arithmetic device 960 may be provided with a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989 or be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function both as a cache and as a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.
  • a layer 930 having one memory array 920 may be provided on top of the computing device 960.
  • Figure 19A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for different functions.
  • Figure 19A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With such a configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 19B shows a perspective view of semiconductor device 970C.
  • the semiconductor device 970C has a layer 930L1 having a memory array 920L1 stacked on top of a layer 930L2 having a memory array 920L2, and a layer 930L3 having a memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the computing device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 20A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that, although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.
  • Memory integrated as a register in an arithmetic processing unit such as a CPU is used for temporarily storing arithmetic results, and is therefore accessed frequently by the arithmetic processing unit. Therefore, a faster operating speed is required than a larger memory capacity.
  • the register also has a function of storing setting information of the arithmetic processing unit.
  • the semiconductor device 100 according to one embodiment of the present invention can be used as the register.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed.
  • a high-capacity, non-volatile storage device such as 3D NAND can be used.
  • the semiconductor device 100 according to one aspect of the present invention has a high operating speed and is capable of retaining data for a long period of time. Therefore, as shown in FIG. 20A, the storage device according to one aspect of the present invention is suitable for both the hierarchy where the cache is located and the hierarchy where the main memory is located. The storage device according to one aspect of the present invention can also be applied to the hierarchy where the storage is located.
  • Figure 20B also shows an example in which SRAM is used for part of the cache and an OS memory according to one aspect of the present invention is used for the other part.
  • the lowest level cache can be called an LLC (Last Level cache). Although an LLC is not required to operate faster than higher level caches, it is desirable for it to have a large storage capacity.
  • the semiconductor device 100 of one embodiment of the present invention is suitable for an LLC because it operates quickly and can retain data for a long period of time. Note that the semiconductor device 100 of one embodiment of the present invention can also be used as an FLC (Final Level cache).
  • an SRAM is used for a higher-level cache (such as an L1 cache or an L2 cache) and the semiconductor device 100 of one embodiment of the present invention is used for an LLC.
  • a higher-level cache such as an L1 cache or an L2 cache
  • the semiconductor device 100 of one embodiment of the present invention is used for an LLC.
  • an OS memory not only an OS memory but also a DRAM may be used for the main memory.
  • the semiconductor device can be used in various electronic components. For example, it can be applied to registers of microprocessors such as DSPs (Digital Signal Processors) and GPUs (Graphics Processing Units), cache memories, etc.
  • microprocessors such as DSPs (Digital Signal Processors) and GPUs (Graphics Processing Units), cache memories, etc.
  • the microprocessor may be realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).
  • the semiconductor device can be applied to, for example, various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related devices, and the like.
  • electronic devices e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.
  • IoT Internet of Things
  • healthcare-related devices e.g., etc.
  • computer includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.
  • FIGS. 21A to 21J each illustrate a state in which an electronic component 700 including the semiconductor device is included in each electronic device.
  • [mobile phone] 21A is a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.
  • an information terminal 5500 with reduced power consumption can be realized. Therefore, the usage time of the information terminal 5500 can be extended. Furthermore, the reduced power consumption reduces heat generation from the circuit, and adverse effects on the circuit itself, peripheral circuits, and modules can be reduced. Therefore, the reliability of the information terminal 5500 can be improved.
  • [Wearable devices] 21B illustrates an information terminal 5900, which is an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.
  • an information terminal 5900 with reduced power consumption can be realized. Therefore, the usage time of the information terminal 5900 can be extended. Furthermore, the reduced power consumption reduces heat generation from the circuit, and adverse effects on the circuit itself, peripheral circuits, and modules can be reduced. Therefore, the reliability of the information terminal 5900 can be improved.
  • FIG. 21C shows a desktop information terminal 5300.
  • the desktop information terminal 5300 has a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.
  • a desktop information terminal 5300 with reduced power consumption can be realized.
  • the reduced power consumption reduces heat generation from the circuit, and adverse effects on the circuit itself, peripheral circuits, and modules can be reduced. Therefore, the reliability of the desktop information terminal 5300 can be improved.
  • a smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices in Figs. 21A to 21C, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied.
  • information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.
  • [electric appliances] 21D illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance.
  • the electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).
  • a semiconductor device can be applied to an electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 can transmit and receive information such as food items stored in the electric refrigerator-freezer 5800 and expiration dates of the food items to an information terminal or the like via the Internet or the like.
  • an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, and audiovisual equipment.
  • [Gaming consoles] 21E illustrates a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
  • FIG. 21F illustrates a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a display unit that displays game images, and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob.
  • the shape of the controller 7522 is not limited to the shape shown in FIG. 21F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game.
  • a controller with a trigger as a button and a shape imitating a gun can be used.
  • a controller with a shape imitating a musical instrument, a musical device, or the like can be used.
  • a stationary game machine may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures or voice.
  • the images from the above-mentioned game machines can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.
  • the portable game machine 5200 or the stationary game machine 7500 By applying a semiconductor device according to one embodiment of the present invention to the portable game machine 5200 or the stationary game machine 7500, it is possible to realize a portable game machine 5200 with reduced power consumption or a stationary game machine 7500 with reduced power consumption. Therefore, the usage time of the portable game machine 5200 can be extended. Furthermore, the reduction in power consumption reduces heat generation from the circuit, and adverse effects on the circuit itself, peripheral circuits, and modules can be reduced. Therefore, the reliability of the portable game machine 5200 and the stationary game machine 7500 can be improved.
  • FIG. 21E shows a portable game machine.
  • FIG. 21F shows a stationary game machine for home use.
  • electronic devices according to one embodiment of the present invention are not limited to this. Examples of electronic devices according to one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.
  • the semiconductor device described in the above embodiment can be applied to automobiles, which are moving objects, and the vicinity of a driver's seat of an automobile.
  • Figure 21G illustrates an automobile 5700, which is an example of a moving object.
  • an instrument panel that can display the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. Also, around the driver's seat, a display device that shows this information may be provided.
  • the display device can display images from an imaging device (not shown) installed in the automobile 5700, thereby compensating for vision obstructed by pillars and blind spots around the driver's seat, thereby improving safety.
  • an imaging device not shown
  • blind spots can be compensated for and safety can be improved.
  • a moving body with reduced power consumption can be realized.
  • the reduced power consumption reduces heat generation from the circuit, and the adverse effects on the circuit itself, the peripheral circuits, and the module can be reduced. Therefore, the reliability of the moving body can be improved.
  • moving bodies are not limited to automobiles.
  • moving bodies can also include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).
  • Figure 21H shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated.
  • the digital camera 6240 may also be configured so that a strobe device, viewfinder, etc. can be separately attached.
  • a digital camera 6240 with reduced power consumption can be realized. Furthermore, the reduced power consumption can extend the image capture time. Furthermore, the reduced power consumption reduces heat generation from the circuit, and therefore adverse effects of heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Therefore, the reliability of the digital camera 6240 can be improved.
  • the semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 21I shows a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.
  • a video camera 6300 with reduced power consumption can be realized. Furthermore, the reduced power consumption can extend the imaging time. Furthermore, the reduced power consumption can reduce heat generation from the circuit, thereby reducing adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Therefore, the reliability of the video camera 6300 can be improved.
  • ICD implantable cardioverter defibrillator
  • FIG. 21J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is placed in the body by surgery, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.
  • the ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve through pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment is given by electric shock.
  • the ICD main body 5400 must constantly monitor the heart rate in order to perform pacing and electric shocks appropriately. For this reason, the ICD main body 5400 has a sensor for detecting the heart rate.
  • the ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of times pacing treatment has been performed, the time, etc.
  • the antenna 5404 can receive power, which is then charged into the battery 5401.
  • the ICD main body 5400 also has multiple batteries, which can increase safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.
  • an antenna that can transmit physiological signals may be provided, and a system may be configured to monitor cardiac activity such that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.
  • an ICD main body 5400 with reduced power consumption can be realized. Furthermore, the reduced power consumption can realize a smaller and lighter storage battery. Furthermore, the reduced power consumption can reduce heat generation from the ICD main body 5400, thereby reducing the load on the human body. Furthermore, the reliability of the ICD main body 5400 can be improved.
  • the computer 5600 shown in FIG. 22A is an example of a large computer (supercomputer) mainly used for scientific and technological calculations.
  • supercomputer mainly used for scientific and technological calculations.
  • a huge amount of calculations must be processed at high speed, so power consumption is high and chips generate a lot of heat.
  • the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yotta) bytes or 10 30 (quetta) bytes.
  • a supercomputer with reduced power consumption can be realized.
  • reduced power consumption reduces heat generation from the circuit, thereby reducing adverse effects of heat on the circuit itself, peripheral circuits, and modules.
  • a supercomputer with reduced power consumption can be realized. This is expected to contribute greatly to measures against global warming.
  • Computer 5600 has multiple rack-mounted computers 5620 stored in rack 5610.
  • Computer 5620 can have the configuration shown in the perspective view of FIG. 22B, for example.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.
  • the PC card 5621 shown in FIG. 22C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 22C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be used as a reference.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622.
  • Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU.
  • the electronic component 700 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • An example of the semiconductor device 5628 is a memory device.
  • the computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations, such as those required for learning and inference in artificial intelligence.
  • the power consumption of an electronic device can be reduced.
  • the reduced power consumption reduces heat generation from the circuit, and can reduce adverse effects on the circuit itself, peripheral circuits, and modules.
  • an electronic device that operates stably even in a high-temperature environment can be realized. Thus, the reliability of the electronic device can be improved.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small change in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and is therefore suitable for use in an environment where radiation may be incident.
  • the OS transistor is suitable for use in space.
  • FIG. 23 a specific example of application of the semiconductor device of one embodiment of the present invention to space equipment will be described with reference to FIG. 23 .
  • Figure 23 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown in outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver located on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • the satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor is highly reliable and preferable even in an environment where radiation may be incident.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • the semiconductor device according to one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

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