Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
  • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

• the present invention relates to a display device and a manufacturing method thereof.
• TFT thin film transistor
• TFTs thin film transistors
• semiconductor layers that constitute TFTs include polysilicon semiconductor layers made of polysilicon with high mobility, and oxide semiconductor layers made of oxide semiconductors such as In-Ga-Zn-O with low leakage current.
• TFTs having a polysilicon semiconductor layer may have unstable threshold (Vth) characteristics due to polarization of the resin substrate.
• Vth threshold
• an additional film is arranged below the polysilicon TFT (switching element) to suppress changes in characteristics due to light intrusion from the back side of the channel and to provide a back gate effect.
• the present invention was made in consideration of these points, and its purpose is to achieve both stabilization of the threshold voltage of a TFT having a polysilicon semiconductor layer provided on a base substrate, particularly a resin substrate, while maintaining the panel transmittance.
• the display device comprises a base substrate and a thin-film transistor layer provided on the base substrate, the thin-film transistor layer having a polysilicon semiconductor layer formed of a polysilicon film and defining a channel region and a conductor region, a plurality of thin-film transistors electrically connected to each other via signal wiring in the conductor region are provided corresponding to a plurality of sub-pixels constituting a display region, and a transparent backgate layer formed of an oxide semiconductor film and having a conductorized portion in which at least a portion of the oxide semiconductor film is conductorized is provided below the thin-film transistor layer, the conductorized portion overlaps at least the channel region in a plan view and is electrically connected to the signal wiring.
• the manufacturing method of the display device is a manufacturing method of a display device comprising a base substrate and a thin-film transistor layer provided on the base substrate, the thin-film transistor layer having a polysilicon semiconductor layer formed of a polysilicon film and having a channel region and a conductor region defined therein, a plurality of thin-film transistors electrically connected to each other via signal wiring in the conductor region are provided corresponding to a plurality of sub-pixels constituting a display region, and a transparent back gate layer formed of an oxide semiconductor film and having a conductorized portion in which at least a portion of the oxide semiconductor film is conductorized is provided below the thin-film transistor layer,
• the film transistor layer forming step includes a first base coat film forming step of forming a first base coat film on the base substrate, a back gate layer forming step of forming the oxide semiconductor film on the substrate surface on which the first base coat film is formed, and then patterning the oxide semiconductor film to form the back gate layer, a second base coat film forming
• the region of the back gate layer that overlaps with the channel region in a planar view is conductorized by heat treatment after the second base coat film is formed to form the conductor portion, and in the signal wiring forming process, the conductor portion and the signal wiring are electrically connected.
• the present invention makes it possible to stabilize the threshold voltage of a TFT having a polysilicon semiconductor layer provided on a base substrate, particularly a resin substrate, while maintaining the panel transmittance.
• FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.
• FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention.
• FIG. 3 is an equivalent circuit diagram showing a pixel circuit of the organic EL display device according to the first embodiment of the present invention.
• FIG. 4 is a schematic plan view showing an arrangement of pixel circuits in the organic EL display device according to the first embodiment of the present invention.
• FIG. 5 is an enlarged plan view of the area surrounded by the two-dot chain line in FIG. 4, showing the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention.
• FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.
• FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention.
• FIG. 6 is an enlarged plan view of the area within the two-dot chain line in FIG. 4, showing a modified example of the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention, and corresponds to FIG.
• FIG. 7 is an enlarged plan view of the area within the two-dot chain line in FIG. 4, showing a modified example of the first TFT constituting the pixel circuit of the organic EL display device according to the first embodiment of the present invention, and corresponds to FIG.
• FIG. 8 is a cross-sectional view of a display region and a frame region of the organic EL display device according to the first embodiment of the present invention.
• FIG. 9 is a cross-sectional view showing an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.
• FIG. 10 is a cross-sectional view of a display region and a frame region of an organic EL display device according to a second embodiment of the present invention, and corresponds to FIG.
• FIG. 11 is a cross-sectional view of a display region and a frame region of an organic EL display device according to a third embodiment of the present invention, and corresponds to FIG.
• FIG. 12 is a schematic plan view showing an arrangement of pixel circuits in an organic EL display device according to a fourth embodiment of the present invention, and corresponds to FIG.
• FIG. 13 is an enlarged plan view of the area surrounded by the two-dot chain line in FIG.
• FIG. 14 is a cross-sectional view of the display region of the organic EL display device according to the fourth embodiment of the present invention taken along the line XIV-XIV in FIG.
• FIG. 15 is an enlarged plan view of the area surrounded by the two-dot chain line in FIG. 12, showing a first TFT constituting a pixel circuit of an organic EL display device according to a fifth embodiment of the present invention.
• 16 is a cross-sectional view of the display region of the organic EL display device according to the fifth embodiment of the present invention taken along the line XVI-XVI in FIG.
• FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a of this embodiment.
• FIG. 2 is a plan view of a display region D of the organic EL display device 50a.
• FIG. 3 is an equivalent circuit diagram showing a pixel circuit C of the organic EL display device 50a.
• FIG. 4 is a schematic plan view showing an arrangement of the pixel circuits C of the organic EL display device 50a.
• FIG. 5 is an enlarged plan view of the area surrounded by a two-dot chain line in FIG. 4, showing a first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a.
• FIG. 6 is an enlarged plan view of the area surrounded by a two-dot chain line in FIG. 4, showing a modified example of the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a, and corresponds to FIG. 5.
• FIG. 7 is an enlarged plan view of the area surrounded by a two-dot chain line in FIG. 4, showing a modified example of the first TFT 9aa constituting the pixel circuit C of the organic EL display device 50a, and corresponds to FIG. 5.
• FIG. 8 is a cross-sectional view of a display region D and a frame region F of the organic EL display device 50a.
• Fig. 9 is a cross-sectional view showing an organic EL layer 23 constituting the organic EL display device 50a. Note that the upper layer of the gate electrode 14a is omitted in Figs. 5 to 7.
• the organic EL display device 50a includes, for example, a rectangular display area D for displaying images, and a frame area F arranged in a frame shape around the display area D.
• a rectangular display area D is illustrated, but this rectangular shape also includes, for example, an approximately rectangular shape with arc-shaped sides, arc-shaped corners, or a shape with a notch in one of the sides.
• a plurality of sub-pixels P are arranged in a matrix.
• a sub-pixel P having a red light-emitting region Lr for displaying red a sub-pixel P having a green light-emitting region Lg for displaying green
• a sub-pixel P having a blue light-emitting region Lb for displaying blue are arranged adjacent to each other.
• one pixel is composed of three adjacent sub-pixels P having a red light-emitting region Lr, a green light-emitting region Lg, and a blue light-emitting region Lb.
• the arrangement of the sub-pixels P is not particularly limited, and examples include a pentile arrangement and a stripe arrangement.
• a terminal portion T is provided at one end of the frame region F (the right end in FIG. 1) so as to extend in one direction (the vertical direction in FIG. 1).
• a folding portion B is provided in the frame region F between the terminal portion T and the display region D so as to extend in one direction (the vertical direction in FIG. 1), which can be folded, for example, 180° (in a U-shape) with the vertical direction in FIG. 1 as the folding axis.
• the organic EL display device 50a includes a flexible resin substrate 10 that serves as a base substrate, and a TFT layer 20a that is provided on the resin substrate 10.
• the resin substrate 10 is made of an organic resin material such as polyimide resin.
• the base substrate is not limited to the resin substrate 10 and may be, for example, a glass substrate.
• a first TFT 9aa, a second TFT 9b, and a capacitor 9c are provided as a pixel circuit C in each subpixel P.
• the pixel circuits C are arranged in a matrix corresponding to each subpixel P. Note that the black circles ( ⁇ ) shown in FIG. 3 and FIG. 4 indicate nodes.
• the TFT layer 20a includes a first base coat film 11a and a second base coat film 11b provided on a resin substrate 10, a plurality of first TFTs 9aa, a plurality of second TFTs 9b (see FIG. 3), and a plurality of capacitors 9c (see FIG. 3) provided on the second base coat film 11b for each subpixel P, and a planarization film 19 provided on each of the first TFTs 9aa, each of the second TFTs 9b, and each of the capacitors 9c.
• the TFT layer 20a is provided with a plurality of gate lines 14 as signal wirings that extend parallel to each other in the horizontal direction in the figures.
• FIGS. 1 the TFT layer 20a is provided with a plurality of gate lines 14 as signal wirings that extend parallel to each other in the horizontal direction in the figures.
• the TFT layer 20a is provided with a plurality of source lines 18f as signal wirings that extend in a direction that intersects (is perpendicular to) the plurality of gate lines 14, i.e., in the vertical direction in the figures. 2 and 3, the TFT layer 20a is provided with a plurality of power lines 18g that run parallel to each other in the vertical direction in the drawings. Each power line 18g is provided adjacent to each source line 18f as shown in FIG. 2. Each source line 18f is connected to, for example, a source driver SD as shown in FIG. 4.
• the first base coat film 11a and the second base coat film 11b the semiconductor film that will be the semiconductor layer, the gate insulating film 13, the gate line 14 (see also FIGS. 2 to 4), the gate electrode 14a, the first metal film (lower metal film) that will be the first wiring layer such as the lower conductive layer, the first interlayer insulating film 15, the second metal film that will be the second wiring layer such as the upper conductive layer, the second interlayer insulating film 17, the third metal film (upper metal film) that will be the third wiring layer such as the source line 18f (see also FIGS. 2 to 4), the source electrode 18a, the drain electrode 18b, the power line 18g, and the like, and the planarization film 19 are laminated in this order on the resin substrate 10.
• the first base coat film 11a, the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 are each composed of a single layer or a laminated film of an inorganic insulating film such as silicon nitride (SiNx (x is a positive number)), silicon oxide (SiO 2 ), silicon oxynitride (SiON), etc.
• the first base coat film 11a is preferably composed of a laminated film such as SiNx (upper layer)/SiO 2 (lower layer).
• the second base coat film 11b is preferably composed of a laminated film such as SiO 2 (upper layer)/SiNx (lower layer).
• the first metal film, the second metal film, and the third metal film are composed of, for example, a metal single layer film of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), etc., or a metal laminate film of Mo (upper layer)/Al (middle layer)/Mo (lower layer), Ti/Al/Ti, Al (upper layer)/Ti (lower layer), Cu/Mo, Cu/Ti, etc.
• Mo molybdenum
• Ti titanium
• Al aluminum
• Cu copper
• W tungsten
• the first TFT 9aa is electrically connected to the corresponding gate line 14 and source line 18f (signal wiring) in each subpixel P.
• the first TFT 9aa includes a polysilicon semiconductor layer 12 (first semiconductor layer), a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18a, and a drain electrode 18b, which are provided in this order on the second base coat film 11b.
• the first TFT 9aa can be said to be a top-gate type polysilicon TFT.
• the polysilicon semiconductor layer 12 is composed of a low-temperature polysilicon film such as LTPS (low temperature polysilicon). As shown in FIG. 8, the polysilicon semiconductor layer 12 is provided on the second base coat film 11b in an island shape in a plan view. The polysilicon semiconductor layer 12 is doped with impurity ions and partially conductorized. As a result, the polysilicon semiconductor layer 12 has a source region 12b and a drain region 12c that are defined as conductor regions spaced apart from each other, and a channel region 12a defined between the source region 12b and the drain region 12c. A plurality of first TFTs 9aa are electrically connected to the source region 12b and the drain region 12c via the corresponding gate line 14 and source line 18f (signal wiring).
• LTPS low temperature polysilicon
• the gate electrode 14a (first wiring layer) is provided on the gate insulating film 13 so as to overlap the channel region 12a of the polysilicon semiconductor layer 12.
• the gate electrode 14a is configured to control the conduction between the source region 12b and the drain region 12c of the polysilicon semiconductor layer 12.
• the gate electrode 14a is formed of a first metal film.
• the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in order to cover the gate electrode 14a, as shown in FIG. 8.
• the source electrode 18a and the drain electrode 18b (third wiring layer) are provided on the second interlayer insulating film 17 so as to be spaced apart from each other, as shown in FIG. 8.
• the source electrode 18a and the drain electrode 18b are also electrically connected to the source region 12b and the drain region 12c of the polysilicon semiconductor layer 12, respectively, via contact holes Ha and Hb formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17, as shown in FIG. 8.
• the source electrode 18a and the drain electrode 18b are formed of a third metal film.
• a back gate layer BGa is provided under the first TFT 9aa constituting the TFT layer 20a.
• the back gate layer BGa is provided between the first base coat film 11a and the second base coat film 11b constituting the first TFT 9aa.
• the back gate layer BGa may be provided in the display region D and the frame region F so as to cover the entire surface of the TFT layer 20a, or may be provided only in the region required as the conductor portion BGac described below.
• the thickness of the back gate layer BGa is, for example, about 10 to 100 nm.
• the In-Ga-Zn-O-based oxide semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited.
• the In-Ga-Zn-O-based semiconductor may be amorphous or crystalline.
• As the crystalline In-Ga-Zn-O-based semiconductor a crystalline In-Ga-Zn-O-based semiconductor in which the c-axis is oriented approximately perpendicular to the layer surface is preferable.
• another oxide semiconductor may be included.
• an In-Sn-Zn-O-based semiconductor for example, In 2 O 3 -SnO 2 -ZnO; InSnZnO
• the In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc).
• oxide semiconductors may include In-Al-Zn-O based semiconductors, In-Al-Sn-Zn-O based semiconductors, Zn-O based semiconductors, In-Zn-O based semiconductors, Zn-Ti-O based semiconductors, Cd-Ge-O based semiconductors, Cd-Pb-O based semiconductors, CdO (cadmium oxide), Mg-Zn-O based semiconductors, In-Ga-Sn-O based semiconductors, In-Ga-O based semiconductors, Zr-In-Zn-O based semiconductors, Hf-In-Zn-O based semiconductors, Al-Ga-Zn-O based semiconductors, Ga-Zn-O based semiconductors, In-Ga-Zn-Sn-O based semiconductors, InGaO 3 (ZnO) 5 , magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), and the
• the back-gate layer BGa also has a conductor portion BGac in which the oxide semiconductor film is conductorized, as shown in Figures 4 to 8.
• the conductor portion BGac can be considered a transparent conductive layer. Note that at least a portion of the back-gate layer BGa may be the conductor portion BGac, or the entire back-gate layer BGa may be the conductor portion BGac.
• the conductor portion BGac (back gate layer BGa) is integrally (band-shaped) arranged across multiple sub-pixels P (the pixel circuits C that constitute them) along the direction in which the source line 18f (signal wiring) extends in a plan view.
• the conductor portion BGac overlaps with the channel region 12a of the polysilicon semiconductor layer 12 constituting the first TFT 9aa in a planar view.
• the conductor portion BGac only needs to overlap with at least the channel region 12a of the polysilicon semiconductor layer 12 in a planar view.
• the back gate layer BGa and its conductor portion BGac may be provided in a mesh pattern corresponding to the pattern shape of the polysilicon semiconductor layer 12 in a planar view.
• the conductor portion BGac may be formed in at least a part of the mesh pattern of the back gate layer BGa (see FIG. 5), or may be formed in the entire pattern (see FIG. 6).
• the back gate layer BGa and its conductor portion BGac may be provided so as to cover the entire sub-pixel P (the pixel circuit C constituting it) in a planar view.
• the conductive portion BGac may be formed on at least a part of the pattern of the back gate layer BGa, or may be formed on the entire pattern (see FIG. 7).
• the power supply TFT is configured to apply the voltage of the power supply line 18g to the first terminal electrode of the driving TFT.
• the light emission control TFT is configured to apply the driving current to the organic EL element 25.
• the first TFT 9aa is a driving TFT.
• the driving TFT since the driving TFT affects the brightness of the organic EL element 25, it is preferable that the driving TFT is composed of a first TFT 9aa having a back gate layer BGa having a conductive portion BGac.
• the writing TFT, power supply TFT, and light emission control TFT other than the driving TFT are switching TFTs, so they may or may not have a back gate layer BGa.
• the second TFT 9b is electrically connected to the corresponding first TFT 9aa and power line 18g in each subpixel P.
• the second TFT 9b also includes a second semiconductor layer, a gate insulating film 13, a gate electrode, a first interlayer insulating film 15, a second interlayer insulating film 17, and a source electrode and a drain electrode, and has the same structure as the first TFT 9aa described above.
• the second semiconductor layer is formed, for example, of a low-temperature polysilicon film or an In-Ga-Zn-O-based oxide semiconductor film.
• the In-Ga-Zn-O-based oxide semiconductor is the same as the In-Ga-Zn-O-based oxide semiconductor described above.
• the second TFT 9b configured as above may be, for example, an n-channel TFT such as an initialization TFT, a compensation TFT, or an anode discharge TFT.
• the initialization TFT is configured to initialize the voltage applied to the gate electrode of the drive TFT.
• the compensation TFT is configured to compensate the threshold voltage of the drive TFT by putting the drive TFT into a diode-connected state in response to the selection of the gate line 14.
• the anode discharge TFT is configured to reset the charge accumulated in the first electrode 21 (described later) of the organic EL element 25 in response to the selection of the gate line 14. Note that the initialization TFT, compensation TFT, and anode discharge TFT are switching TFTs, and may or may not have a back gate layer BGa.
• the first TFT 9aa and the second TFT 9b are shown as top-gate type TFTs, but the first TFT 9aa and the second TFT 9b may be bottom-gate type TFTs. It is preferable that the first TFT 9aa is a top-gate type TFT.
• the capacitor 9c is electrically connected to the corresponding first TFT 9aa and the power supply line 18g in each subpixel P.
• the capacitor 9c includes, for example, a lower conductive layer (first wiring layer) formed of a first metal film, a first interlayer insulating film 15 provided to cover the lower conductive layer, and an upper conductive layer (second wiring layer) provided on the first interlayer insulating film 15 to overlap the lower conductive layer and formed of a second metal film.
• the upper conductive layer 16 is electrically connected to the power supply line 18g via, for example, a contact hole formed in the second interlayer insulating film 17.
• the back-gate layer BGa and its conductive portion BGac are arranged not only in the region (hereinafter also referred to as the "active region") in the display region D where multiple sub-pixels P are arranged, but also in the frame region F.
• the conductor portion BGac is electrically connected to the source line 18f (signal wiring) in an area in the frame region F where the subpixels P are not arranged (hereinafter also referred to as the "inactive region"), as shown in Figures 4 and 8.
• the conductor portion BGac and the source line 18f are electrically connected via a contact hole Hf formed in a laminate film of the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 as at least one inorganic insulating film provided between the conductor portion BGac and the source line 18f.
• the conductor portion BGac is fixed to the potential of the source line 18f.
• a conventional flexible organic EL display device that has a backgate separated by an inorganic insulating film (base coat film) below a top-gate type polysilicon TFT, and that electrically connects the backgate to a potential fixing wiring (signal wiring) within the pixel circuit C (active region) via a contact hole formed in the inorganic insulating film
• the threshold characteristics of the TFT are unstable due to impurities from the resin substrate directly below the backgate. This is thought to be due to the fact that a contact hole is provided near the TFT, and hydrogen atoms generated from the base coat film due to the opening of the contact hole adhere to the channel portion of the TFT.
• the conductor portion BGac in the back gate layer BGa is electrically connected to the source line 18f via the contact hole Hf outside the pixel circuit C (inactive region), so the above-mentioned inconvenience is unlikely to occur.
• the planarization film 19 has a flat surface in the display area D, and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.
• the organic EL display device 50a includes an organic EL element layer 31 provided as an upper layer of the TFT layer 20a as a light-emitting element layer constituting the display area D, and a sealing film 35 provided on the organic EL element layer 31.
• the organic EL element layer 31 includes a plurality of organic EL elements 25 as light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P.
• the organic EL element 25 includes a plurality of first electrodes 21 provided in order on the planarization film 19, a plurality of organic EL layers 23 provided on the first electrodes 21 for each subpixel P, and a second electrode 24 provided on the organic EL layer 23 in common to the plurality of subpixels P. As shown in FIG. 8, the organic EL element 25 is also covered with a sealing film 35.
• the first electrodes 21 are provided in a matrix on the planarization film 19 so as to correspond to a plurality of sub-pixels P. As shown in Fig. 8, each of the first electrodes 21 is electrically connected to the drain electrode 18d (or the source electrode 18c) of each of the second TFTs 9b through a contact hole formed in the planarization film 19.
• the first electrodes 21 have a function of injecting holes (positive holes) into the organic EL layer 23. It is more preferable that the first electrodes 21 are formed of a material having a large work function in order to improve the efficiency of hole injection into the organic EL layer 23.
• examples of materials constituting the first electrode 21 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn).
• the material constituting the first electrode 21 may be, for example, an alloy such as astatine (At)/astatine oxide (AtO 2 ).
• the material constituting the first electrode 21 may be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO).
• the first electrode 21 may be formed by stacking a plurality of layers made of the above materials. Examples of compound materials having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
• the peripheral edge of the first electrode 21 is covered with an edge cover 22 arranged in a lattice pattern common to multiple sub-pixels P.
• materials constituting the edge cover 22 include positive photosensitive resin materials such as polyimide resin, acrylic resin, polysiloxane resin, and novolac resin, or polysiloxane-based SOG materials.
• a part of the surface of the edge cover 22 protrudes upward in the figure and serves as an island-shaped pixel photospacer.
• each organic EL layer 23 is disposed on each first electrode 21 and arranged in a matrix to correspond to a plurality of sub-pixels P.
• each organic EL layer 23 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are arranged in this order on the first electrode 21.
• the hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 21 and the organic EL layer 23 closer together and improving the efficiency of hole injection from the first electrode 21 to the organic EL layer 23.
• materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.
• the hole transport layer 2 has the function of improving the efficiency of transporting holes from the first electrode 21 to the organic EL layer 23.
• materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, zinc selenide, etc.
• the light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 21 and the second electrode 24, respectively, and where the holes and electrons recombine when a voltage is applied by the first electrode 21 and the second electrode 24.
• the light-emitting layer 3 is formed from a material with high luminous efficiency.
• Examples of materials constituting the light-emitting layer 3 include metal oxinoid compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzthiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, polysilane, and the like.
• the electron transport layer 4 has the function of efficiently transferring electrons to the light-emitting layer 3.
• materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.
• the electron injection layer 5 has a function of bringing the energy levels of the second electrode 24 and the organic EL layer 23 closer to each other and improving the efficiency of electron injection from the second electrode 24 to the organic EL layer 23, and this function can reduce the driving voltage of the organic EL element 25.
• the electron injection layer 5 is also called a cathode buffer layer.
• examples of materials constituting the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), and barium fluoride (BaF 2 ), aluminum oxide (Al 2 O 3 ), and strontium oxide (SrO).
• the second electrode 24 is provided so as to cover each organic EL layer 23 and the edge cover 22.
• the second electrode 24 has a function of injecting electrons into the organic EL layer 23.
• the second electrode 24 is more preferably made of a material having a small work function in order to improve the efficiency of electron injection into the organic EL layer 23.
• examples of materials constituting the second electrode 24 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF).
• the second electrode 24 may be formed of an alloy such as magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/astatine oxide (AtO 2 ), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), or lithium fluoride (LiF)/calcium (Ca)/aluminum (Al).
• the second electrode 24 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO).
• the second electrode 24 may be formed by stacking a plurality of layers made of the above materials.
• materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), and lithium fluoride (LiF)/calcium (Ca)/aluminum (Al).
• the sealing film 35 includes a first sealing inorganic insulating film 32 provided to cover the second electrode 24, a sealing organic film 33 provided on the first sealing inorganic insulating film 32, and a second sealing inorganic insulating film 34 provided to cover the sealing organic film 33, and has a function of protecting the organic EL layer 23 from moisture, oxygen, and the like.
• the first sealing inorganic insulating film 32 and the second sealing inorganic insulating film 34 are made of inorganic materials such as silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride (SiNx (x is a positive number) such as trisilicon tetranitride (Si 3 N 4 ), and silicon carbonitride (SiCN).
• the sealing organic film 33 is made of organic materials such as acrylic resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.
• the organic EL display device 50a described above is configured such that, in each subpixel P, a gate signal is input to the first TFT 9aa via the gate line 14 to turn the first TFT 9aa on, a data signal is written to the gate electrode of the second TFT 9b and the capacitor 9c via the source line 18f, and a current from the power line 18g corresponding to the gate voltage of the second TFT 9b is supplied to the organic EL layer 23, causing the light-emitting layer 3 of the organic EL layer 23 to emit light and display an image.
• the organic EL display device 50a even if the first TFT 9aa is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that the light-emitting layer 3 continues to emit light until the gate signal for the next frame is input.
• the method for manufacturing the organic EL display device 50a of this embodiment includes a TFT layer formation process.
• the TFT layer forming process is a process for forming the TFT layer 20a, and includes a first base coat film forming process, a back gate layer forming process, a second base coat film forming process, a polysilicon semiconductor layer forming process, and a gate insulating film forming process.
• the method includes a gate electrode forming step, a doping step, an interlayer insulating film forming step, a contact hole forming step, and a signal wiring forming step.
• First base coat film forming step First, a silicon oxide film (about 250 nm thick) and a silicon nitride film (about 50 nm thick) are sequentially formed on a resin substrate 10 formed on a glass substrate, for example, by a plasma CVD (Chemical Vapor Deposition) method, thereby forming a first base coat film 11a composed of a laminated film such as SiNx (upper layer)/ SiO2 (lower layer).
• a plasma CVD Chemical Vapor Deposition
• an oxide semiconductor film made of an oxide semiconductor such as an InGaZnO4 film (thickness: about 30 nm) is formed by, for example, a sputtering method, and then the oxide semiconductor film is patterned to form a strip-shaped back gate layer BGa extending parallel to the direction in which the source line 18f formed in the subsequent process extends.
• a silicon nitride film (about 50 nm thick) and a silicon oxide film (about 250 nm thick) are sequentially formed by, for example, a plasma CVD method, to form a second base coat film 11b composed of a laminated film such as SiO2 (upper layer)/SiNx (lower layer).
• a part of the back gate layer BGa is conductorized by heat treatment after the formation of the second base coat film 11b, to form the conductor portion BGac.
• the conductor portion BGac is formed in an area that overlaps in plan view with at least the channel region 12a of the polysilicon semiconductor layer 12 formed in a subsequent process.
• amorphous silicon film (about 50 nm thick) is formed on the substrate surface on which the second base coat film 11b is formed, for example, by a plasma CVD method, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film made of polysilicon. The polysilicon film is then patterned to form the polysilicon semiconductor layer 12.
• a silicon oxide film (with a thickness of about 100 nm) is formed on the substrate surface on which the polysilicon semiconductor layer 12 is formed, for example, by plasma CVD, and then the silicon oxide film is patterned so as to cover the polysilicon semiconductor layer, thereby forming a gate insulating film 13.
• a first metal film such as a molybdenum film (thickness: about 200 nm) is formed, for example, by sputtering, on the substrate surface on which the gate insulating film 13 is formed, and then the first metal film is patterned to form a first wiring layer including the gate electrode 14a and the gate line 14.
• Doping process By doping the polysilicon semiconductor layer 12 with impurity ions using the gate electrode 14a as a mask, a part of the polysilicon semiconductor layer 12 is made conductive, thereby forming a source region 12b, a drain region 12c and a channel region 12a in the polysilicon semiconductor layer 12.
• Interlayer insulating film forming process At least one interlayer insulating film is formed on the substrate surface on which the gate electrode 14a is formed (the substrate surface on which a portion of the polysilicon semiconductor layer 12 is made conductive).
• a silicon nitride film (about 150 nm thick) and a silicon oxide film (about 100 nm thick) are sequentially formed on the substrate surface by, for example, a plasma CVD method, thereby forming a first interlayer insulating film 15.
• a silicon oxide film (about 100 nm thick) is formed on the substrate surface on which the first interlayer insulating film 15 is formed by, for example, a plasma CVD method, thereby forming a second interlayer insulating film 17.
• the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are appropriately patterned, for example, by dry etching, to form contact holes Ha and Hb that expose at least a part of the surface of the source region 12b and the drain region 12c in the polysilicon semiconductor layer 12.
• the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are appropriately patterned, for example, by dry etching, to form a contact hole Hf that exposes at least a part of the surface of the conductor portion BGac in the back gate layer BGa.
• a titanium film (thickness: about 50 nm), an aluminum film (thickness: about 400 nm), a titanium film (thickness: about 200 nm), etc. are formed by, for example, a sputtering method on the substrate surface on which the contact holes Ha, Hb, and Hf are formed.
• the third metal film is patterned to form a third wiring layer including a source line 18f, a source electrode 18a, a drain electrode 18b, a power line 18g, etc. Form.
• the conductor portion BGac and the source line 18f are electrically connected in the signal wiring formation process.
• a second metal film such as a molybdenum film (thickness: about 200 nm) is formed by, for example, a sputtering method, and then the second metal film is is patterned to form a second wiring layer such as an upper conductive layer.
• Planarization film formation process An acrylic photosensitive resin film (about 2 ⁇ m thick) is applied to the substrate surface on which the source lines 18 f and the like are formed, for example, by spin coating or slit coating, and then the applied film is pre-baked.
• a planarizing film 19 is formed by carrying out exposure, development and post-baking.
• the manufacturing method for the organic EL display device 50a also includes an organic EL element layer forming process and a sealing film forming process.
• a first electrode 21, an edge cover 22, and an organic EL layer 23 are formed by using a known method.
• a light-emitting layer 3 is formed to form an organic EL element 25, and an organic EL element layer 31 is formed.
• ⁇ Sealing film forming process> First, on the substrate surface on which the organic EL element layer 31 formed in the organic EL element layer forming process is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by a plasma CVD method using a CMM as a deposition mask so as to cover each organic EL element 25, thereby forming a first sealing inorganic insulating film 32. Next, an organic resin material such as an acrylic resin is formed on the first sealing inorganic insulating film 32 by, for example, an inkjet method to form a sealing organic film 33.
• an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by a plasma CVD method using a CMM as a deposition mask so as to cover each organic EL element 25, thereby forming a first sealing inorganic insulating film 32.
• a protective sheet (not shown) is attached to the surface of the substrate, and then laser light is applied from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled off. In this manner, the organic EL display device 50a can be manufactured.
• the conductor portion BGac is integrally provided so as to straddle a plurality of sub-pixels P (the pixel circuits C constituting the sub-pixels P) along the direction in which the source line 18f (signal wiring) extends in a plan view, overlaps at least with the channel portion 12a in a plan view, and is electrically connected to the source line 18f. Therefore, the first TFT 9aa is prevented from shifting in threshold value (Vth) due to polarization of the resin substrate 10, and has stable threshold characteristics.
• the conductor portion BGac and the source line 18f are electrically connected through the contact hole Hf outside the pixel circuit C (inactive region), so that hydrogen atoms generated from the first base coat film 11a are prevented from adhering to the channel portion 12a, and the threshold characteristic of the first TFT 9aa becomes more stable.
• Fig. 10 is a cross-sectional view of a display region D and a frame region F of an organic EL display device 50b of this embodiment, and corresponds to Fig. 8.
• the overall configuration of the organic EL display device 50b is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20b, and therefore a detailed description thereof will be omitted here. Also, components similar to those of the first embodiment will be denoted by the same reference numerals and descriptions thereof will be omitted.
• a metal layer M that is island-shaped in plan view is provided between the lower end of the contact hole Hf and the conductor portion BGac in the frame region F (inactive region).
• the metal layer M is disposed between the back gate layer BGa and the second base coat film 11b. As a result, the conductor portion BGac and the source line 18f are electrically connected via the metal layer M.
• the metal layer M is composed of a metal single layer film such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), etc., or a metal laminate film such as Mo (upper layer)/Al (middle layer)/Mo (lower layer), Ti/Al/Ti, Al (upper layer)/Ti (lower layer), Cu/Mo, Cu/Ti, etc.
• a metal single layer film such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), etc.
• a metal laminate film such as Mo (upper layer)/Al (middle layer)/Mo (lower layer), Ti/Al/Ti, Al (upper layer)/Ti (lower layer), Cu/Mo, Cu/Ti, etc.
• the organic EL display device 50b can be fabricated by adding the following metal layer formation process after the backgate layer formation process and before the second base coat film formation process in the TFT layer formation process of the above-described organic EL display device 50a.
• ⁇ Effects> According to the organic EL display device 50b described above, in addition to the effects of the organic EL display device 50a described above, the following effects can be obtained.
• a metal layer M is provided between the conductor portion BGac and the second base coat film 11b. This metal layer M makes it possible to prevent the conductor portion BGac from being penetrated when the contact hole Hf is formed.
• Fig. 11 is a cross-sectional view of a display region D and a frame region F of an organic EL display device 50c of this embodiment, and corresponds to Fig. 8.
• the overall configuration of the organic EL display device 50c is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20c, and therefore a detailed description thereof will be omitted here. Also, components similar to those of the first embodiment will be denoted by the same reference numerals and descriptions thereof will be omitted.
• the back gate layer BGc has a non-conductive portion BGcn in which the oxide semiconductor film is not conductive.
• the non-conductive portions BGcn are provided between adjacent sub-pixels P in the direction in which the source lines 18f extend (see FIG. 4) as signal wiring.
• the conductive portions BGcc in the back gate layer BGc are provided separately for each sub-pixel P.
• the conductive portions BGcc overlap the entire first TFT 9ac (the entire surface of the polysilicon semiconductor layer 12 that constitutes it) in a planar view. In this way, in the organic EL display device 50c, the conductive portions BGcc and the non-conductive portions BGcn are alternately arranged along the direction in which the source lines 18f extend.
• the organic EL display device 50c may be configured to include a metal layer M, similar to the organic EL display device 50b described above.
• the organic EL display device 50c can be obtained by modifying the second base coat film formation process in the TFT layer formation process of the organic EL display device 50a described above as follows. For example, a heat treatment is performed after the second base coat film 11b is formed so that the back gate layer BGc in the region between the sub-pixels P (first TFTs 9ac) adjacent to each other in the direction in which the source lines 18f extend is not affected by heat or is less affected by heat.
• FIG. 12 is a schematic plan view showing the arrangement of pixel circuits C of an organic EL display device 50d of this embodiment, and corresponds to FIG. 4.
• FIG. 13 is an enlarged plan view of the area within the two-dot chain line in FIG. 12, showing the first TFT 9ad constituting the pixel circuit C of the organic EL display device 50d.
• FIG. 14 is a cross-sectional view of the display area D of the organic EL display device 50d taken along line XIV-XIV in FIG. 13. Note that the upper layer of the gate electrode 14a is omitted in FIG. 13.
• the overall configuration of the organic EL display device 50d is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20d, and therefore detailed description thereof will be omitted here. Also, components similar to those of the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.
• the conductor portion BGdc (backgate layer BGd) is provided in an island shape for each subpixel P so as to cover the entire subpixel P in plan view. Specifically, as shown in Figures 13 and 14, the island-shaped conductor portion BGdc overlaps with the entire first TFT 9ad (the entire surface of the polysilicon semiconductor layer 12 that constitutes it) in plan view.
• the conductor portion BGdc is electrically connected to the source line 18f via the contact hole Hf.
• the organic EL display device 50d may be configured to include a metal layer M, similar to the organic EL display device 50b described above.
• the organic EL display device 50d can be obtained by modifying the back-gate layer formation process and the contact hole formation process in the TFT layer formation process of the organic EL display device 50a described above as follows.
• the pattern shape of the oxide semiconductor film is modified to form an island-shaped back-gate layer BGd that overlaps in plan view with the entire surface of the polysilicon semiconductor layer 12 (the entire first TFT 9ad) formed in the subsequent process.
• a contact hole Hf is formed in the second base coat film 11b, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 to expose at least a portion of the surface of the conductor portion BGdc.
• FIG. 15 is an enlarged plan view of the area within the two-dot chain line in FIG. 12, showing the first TFT 9ae constituting the pixel circuit C of the organic EL display device 50e of this embodiment.
• FIG. 16 is a cross-sectional view of the display area D of the organic EL display device 50e taken along the line XVI-XVI in FIG. 15. Note that the upper layer of the gate electrode 14a is omitted in FIG. 15.
• the overall configuration of the organic EL display device 50e is the same as that of the fourth embodiment described above, except for the configuration of the TFT layer 20e, and therefore detailed description thereof will be omitted here. Also, components similar to those of the fourth embodiment will be denoted by the same reference numerals and description thereof will be omitted.
• the conductor portion BGec (back gate layer BGe) is provided in an island shape for each sub-pixel P so as to cover the entire sub-pixel P in plan view. Specifically, the conductor portion BGec overlaps with the entire surface of the polysilicon semiconductor layer 12 (the entire first TFT 9ae) in plan view.
• the back gate layer BGe in the display region D (active region), has a non-conductive portion BGen where the oxide semiconductor film is not conductive.
• the non-conductive portion BGen is arranged in a frame shape along the periphery of the island-shaped conductive portion BGec in a plan view. Due to the frame-shaped non-conductive portion BGen, the conductive portion BGec in the back gate layer BGe is arranged in an isolated pattern separated for each sub-pixel P in the display region D (active region).
• the organic EL display device 50e may be configured to include a metal layer M, similar to the organic EL display device 50b described above.
• the organic EL display device 50e can be obtained by modifying the second base coat film formation process in the TFT layer formation process of the organic EL display device 50d described above as follows. For example, a heat treatment is performed after the second base coat film 11b is formed so that the back gate layer BGe around each sub-pixel P (first TFT 9ae) is not affected by heat or the effect is reduced.
• a frame-shaped non-conductive portion BGen is provided in the back gate layer BGe along the periphery of the sub-pixel P (first TFT 9ae).
• the frame-shaped non-conductive portion BGen separates the conductive portion BGec for each sub-pixel P, making it difficult for a potential difference to occur between the conductive portion BGec and the polysilicon semiconductor layer 12. As a result, it is possible to improve the stabilization of the threshold characteristics of the first TFT 9ae.
• the conductor portion is provided integrally as a signal wiring so as to straddle a plurality of sub-pixels along the direction in which the source line extends, but is not limited thereto.
• the conductor portion may be provided integrally as a signal wiring so as to straddle a plurality of sub-pixels along the direction in which the gate line extends. In this case, the conductor portion may be electrically connected to the gate line.
• an organic EL layer having a five-layer laminate structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified, but the organic EL layer may have a three-layer laminate structure of, for example, a hole injection layer/hole transport layer, a light-emitting layer, and an electron transport layer/electron injection layer.
• an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified, but the present invention can also be applied to an organic EL display device in which the layered structure of the organic EL layer is inverted, and the first electrode is a cathode and the second electrode is an anode.
• an organic EL display device is exemplified in which the electrode of the TFT connected to the first electrode is the drain electrode, but the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called the source electrode.
• an organic EL display device is used as the display device, but the present invention can also be applied to display devices such as active matrix driving type liquid crystal display devices.
• an organic EL display device has been described as an example of a display device, but the present invention is not limited to organic EL display devices and can be applied to any flexible display device.
• the present invention can be applied to a flexible display device equipped with a QLED (Quantum-dot light emitting diode), which is a light emitting element that uses a quantum dot-containing layer.
• QLED Quantum-dot light emitting diode
• the present invention is useful for flexible display devices.

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