WO2024176062A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024176062A1
WO2024176062A1 PCT/IB2024/051464 IB2024051464W WO2024176062A1 WO 2024176062 A1 WO2024176062 A1 WO 2024176062A1 IB 2024051464 W IB2024051464 W IB 2024051464W WO 2024176062 A1 WO2024176062 A1 WO 2024176062A1
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Prior art keywords
transistor
conductor
insulator
oxide
memory
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
黒川義元
松嵜隆徳
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2025501905A priority Critical patent/JPWO2024176062A1/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • One aspect of the present invention relates to a semiconductor device, etc.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices (memory devices), and driving methods or manufacturing methods thereof.
  • the CPU Central Processing Unit
  • the CPU executes a series of processes by sequentially executing operations according to the programs (data) stored in memory.
  • the data required for the processes is also stored in memory. Therefore, the speed at which the CPU accesses memory or the power consumption greatly affects the CPU's computing power or power consumption.
  • a configuration that allows equal access to data in all memories is highly versatile, but it slows down the speed at which the CPU accesses memory, resulting in reduced computing power and increased power consumption. For this reason, a hierarchical memory configuration is common, in which, in order of proximity to the CPU, cache memory made up of SRAM etc., main storage device made up of DRAM etc., auxiliary storage device such as flash memory or hard disk etc. are arranged.
  • the main memory device has a slower access speed than the cache memory but a larger storage capacity.
  • the auxiliary memory device has an even slower access speed than the main memory device but a larger storage capacity.
  • the CPU basically accesses the cache memory, but if the desired data is not stored in the cache memory, it accesses the main memory device, copies the data to the cache memory, and then accesses the data again. Furthermore, if the desired data is not stored in the main memory device either, it accesses the auxiliary memory device, copies the data to the main memory device and the cache memory, and then accesses the data again.
  • the cache memory in a hierarchical structure, i.e., arranging the primary cache memory (primary cache, L1 cache), secondary cache memory (secondary cache, L2 cache), tertiary cache memory (tertiary cache, L3 cache), etc. in order of proximity to the CPU.
  • primary cache memory primary cache, L1 cache
  • secondary cache memory secondary cache, L2 cache
  • tertiary cache memory tertiary cache, L3 cache
  • Patent Document 1 discloses a configuration in which a memory unit using a transistor including an oxide semiconductor in its semiconductor layer is applied to a register, a cache memory, or a main memory device.
  • a transistor including an oxide semiconductor in its semiconductor layer has a characteristic of having an extremely small off-state current. Therefore, by applying the transistor to a memory unit such as a register, a cache memory, or a main memory device, stored data can be retained for a long time.
  • Increasing the storage capacity of cache memory is effective in improving the computing power of a processor such as a CPU and reducing power consumption.
  • the processor which has multiple circuit units such as an arithmetic logic unit (Integer/ALU), occupies most of the limited area. Therefore, it is not easy to secure an area for arranging a memory unit in order to increase the storage capacity of the cache memory without reducing the computing power of the processor. For this reason, it has been difficult to increase the storage capacity of cache memory while improving the computing power of the processor and reducing power consumption at the same time.
  • Patent Document 1 also discloses a configuration in which a transistor containing an oxide semiconductor in its semiconductor layer is applied to a register, which is a memory unit in an arithmetic unit. A high access speed is required for a register that holds data accessed by the arithmetic unit. When a transistor containing an oxide semiconductor in its semiconductor layer is applied to a register, there is a risk that the access speed to the register may actually decrease. Furthermore, when a transistor containing an oxide semiconductor in its semiconductor layer is applied to a cache memory, which is a memory unit in a hierarchy close to the arithmetic unit, the signal propagation distance between the multiple circuit units in the arithmetic unit and the cache memory becomes longer, which may increase power consumption and decrease the operating speed.
  • problems of one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not preclude the existence of other problems.
  • the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and/or other problems.
  • One aspect of the present invention is a semiconductor device having a first element layer and a plurality of second element layers, the plurality of second element layers being provided on the first element layer, the first element layer being provided with an arithmetic unit, and each of the plurality of second element layers being provided with a memory unit, the arithmetic unit having a first transistor having a first semiconductor layer having silicon in a channel formation region, the memory unit having a second transistor having a second semiconductor layer having an oxide semiconductor in a channel formation region, and the memory unit having a function of a cache memory for the arithmetic unit.
  • One aspect of the present invention is a semiconductor device having a first element layer and a plurality of second element layers, the plurality of second element layers being provided on the first element layer, the first element layer being provided with an arithmetic unit, and each of the plurality of second element layers being provided with a memory unit, the arithmetic unit having a first transistor having a first semiconductor layer having silicon in a channel formation region, the memory unit having a second transistor having a second semiconductor layer having an oxide semiconductor in a channel formation region, the arithmetic unit having a command analysis unit, and the memory unit of at least one of the plurality of second element layers having a command cache, the command cache being provided in a region of the second element layer above the command analysis unit provided in the first element layer.
  • the oxide semiconductor is preferably a semiconductor device having at least In.
  • the semiconductor device is preferably such that the second transistor is a vertical transistor.
  • a semiconductor device in which the calculation unit of the first element layer and the memory unit of each of the multiple second element layers are electrically connected via a through electrode provided in each of the multiple second element layers.
  • a semiconductor device in which the calculation unit of the first element layer and the memory unit of each of the multiple second element layers are electrically connected via a wiring layer of the first element layer and a wiring layer of each of the multiple second element layers.
  • a semiconductor device in which the arithmetic unit of the first element layer has a flip-flop, each of the multiple second element layers has a backup circuit electrically connected to the flip-flop, the backup circuit has a function of holding a data signal written to the flip-flop, and the region in which the backup circuit is provided has a region overlapping the region in which the flip-flop is provided.
  • One aspect of the present invention can provide a novel semiconductor device, etc.
  • one aspect of the present invention can provide a semiconductor device that is excellent in terms of improved computing power, reduced power consumption, improved operating speed, miniaturization, or improved memory capacity.
  • 1A and 1B are a block diagram and a schematic diagram illustrating an example of the configuration of a semiconductor device.
  • 2A and 2B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 3A and 3B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 4A and 4B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 5A to 5C are block diagrams for explaining examples of the configuration of a semiconductor device and diagrams showing examples of circuit configurations.
  • FIG. 6 is a timing chart illustrating an example of the configuration of a semiconductor device.
  • 7A and 7B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 8A to 8H are circuit diagrams illustrating examples of the configuration of a semiconductor device.
  • FIG. 9 is a schematic diagram illustrating a configuration example of a semiconductor device.
  • 10A and 10B are schematic diagrams illustrating an example of the configuration of a computation system.
  • 11A and 11B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 12A to 12C are schematic diagrams illustrating configuration examples of a semiconductor device.
  • 13A and 13B are schematic cross-sectional views illustrating a configuration example of a semiconductor device.
  • 14A and 14B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • 15A and 15B are schematic diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 16 is a cross-sectional view illustrating an example of the configuration of a semiconductor device.
  • FIG. 17A to 17C are cross-sectional views illustrating examples of the configuration of a semiconductor device.
  • Fig. 18A is a diagram illustrating a configuration example of a semiconductor device
  • Fig. 18B is a diagram illustrating an equivalent circuit of the semiconductor device.
  • FIG. 19 is a diagram illustrating a configuration example of a semiconductor device.
  • Fig. 20A is a diagram illustrating a configuration example of a semiconductor device, and Fig. 20B is a diagram illustrating an equivalent circuit of the semiconductor device.
  • FIG. 21 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device.
  • 22A to 22C are plan views showing configuration examples of transistors included in a semiconductor device, and FIG.
  • FIG. 22D is a cross-sectional view showing the configuration example of a transistor included in the semiconductor device.
  • FIG. 23A is a plan view showing a configuration example of a transistor included in a semiconductor device
  • FIG. 23B is a cross-sectional view showing the configuration example of a transistor included in the semiconductor device.
  • FIG. 24 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device.
  • 25A and 25B are diagrams illustrating an example of an electronic component.
  • FIG. 27 is a diagram illustrating an example of space equipment.
  • FIG. 28 is a diagram illustrating an example of a storage system that can be applied to a data center.
  • the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and the source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a transistor is referred to as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • the semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like) or a device having the same circuit.
  • the semiconductor device described in this embodiment has a function as an arithmetic device having a memory portion using a transistor with extremely low off-state current.
  • FIG. 1A is a block diagram of a semiconductor device 10 described in this embodiment.
  • FIG. 1B is a schematic diagram of the semiconductor device 10 described in this embodiment.
  • FIG. 1A shows data between the element layer 20 shown in FIG. 1B and element layers 30_1 to 30_n provided on the element layer 20.
  • the element layers 30_1 to 30_n are stacked on the element layer 20.
  • the element layer is a layer in which a semiconductor element such as a transistor or a capacitor is provided.
  • the first layer of the element layers 30_1 to 30_n is indicated as element layer 30_1, the second layer as element layer 30_2, and the third layer as element layer 30_3.
  • the nth layer is indicated as element layer 30_n.
  • element layer 30 when describing matters related to the element layers 30_1 to 30_n as a whole, or when indicating matters common to each of the element layers 30_1 to 30_n, the term "element layer 30" may be used.
  • the element layer 20 has an arithmetic unit 21.
  • the element layer 20 has a transistor having silicon (Si transistor) in a semiconductor layer having a channel formation region.
  • the element layer 20 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.
  • the substrate provided in the element layer 20 is described as being a silicon substrate, but this embodiment is not limited to this.
  • the silicon substrate refers to a substrate that uses silicon as a semiconductor material, for example, a substrate made of single crystal silicon.
  • the substrate is not limited to silicon, and materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. may also be used.
  • the Si transistors in the element layer 20 use silicon with high crystallinity, such as monocrystalline silicon or polycrystalline silicon. By using silicon with high crystallinity, the element layer 20 can achieve high field effect mobility, enabling faster operation. Therefore, the arithmetic unit 21 in the element layer 20 can be provided with various circuit units, such as an instruction analysis unit (instruction decoder, Decode), a branch prediction unit (Branch Prediction), a load/store unit (Load/Store), an arithmetic logic unit (Integer/ALU), and a floating point arithmetic unit (Floating Point).
  • instruction analysis unit instruction decoder, Decode
  • Branch Prediction branch prediction unit
  • Load/Store load/store unit
  • Integer/ALU arithmetic logic unit
  • Floating Point floating point arithmetic unit
  • the calculation unit 21 like a CPU (Central Processing Unit) or GPU (Graphics Processing Unit), has the function of performing general-purpose processing such as running an operating system, controlling data, performing various calculations, and running programs.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the element layers 30_1 to 30_n have transistors having an oxide semiconductor (OS transistors) in a semiconductor layer having a channel formation region.
  • the element layers 30_1 to 30_n having OS transistors can be stacked on the element layer 20.
  • the element layers 30_1 to 30_n are stacked on the element layer 20.
  • metal oxides that can be used in OS transistors include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) also referred to as IGZO
  • it is preferable to use an oxide containing indium (In), tin (Sn), and zinc (Zn) also referred to as ITZO
  • it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) also referred to as IAZO).
  • an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) also referred to as IAGZO
  • an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) also referred to as IGZTO.
  • the metal oxide used in the OS transistor can be a metal oxide layer having two or more layers with different compositions.
  • a laminate structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be used.
  • the metal oxide used in the OS transistor is preferably crystalline.
  • crystalline oxide semiconductors include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS.
  • the OS transistor is preferably a vertical transistor in which the source electrode and the drain electrode are located at different heights.
  • a current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer.
  • the channel length direction has a height direction (vertical direction) component. Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.
  • VFET Vertical Field Effect Transistor
  • Vertical transistors have a structure in which the source region, the channel formation region, and the drain region can at least partially overlap when viewed from above, so that the area they occupy (also called the footprint) can be made small.
  • the structure allows the channel length to be small and the channel width to be large, the on-resistance can be made small (the on-current can be made large).
  • the vertical transistor can increase the memory density per unit area compared to a horizontal transistor (also called a planar structure) in which the source electrode and the drain electrode are located at the same height.
  • Vertical transistors have a small occupation area (also called a footprint), and are therefore particularly effective in a configuration in which the memory density per unit area is increased as the element layer 30 is located in the upper layer.
  • a hierarchical configuration can be formed with memory densities being different in ascending order of proximity to the element layer 20 having the arithmetic unit 21.
  • the element layers 30_1 to 30_n have a memory unit 33 in which memory cells 34 having OS transistors are provided.
  • the circuit configuration of the memory cells 34 provided in the memory unit 33 may be different for each of the element layers 30_1 to 30_n. With this configuration, a hierarchical configuration can be achieved on the element layer 20 having the operation unit 21, with the access speed being different in ascending order of proximity to the element layer 20 having the operation unit 21.
  • a memory unit 33 having memory cells 34 with different circuit configurations can be applied to the element layers 30_1 to 30_n.
  • the access speed can be different in ascending order of proximity to the element layer 20 having the operation unit 21.
  • the memory cells 34 provided in the memory unit 33 may have the same circuit configuration across multiple layers among the element layers 30_1 to 30_n. This configuration allows a manufacturing process using the same photomask to be adopted for multiple element layers. Therefore, the memory unit 33 can be manufactured using the same manufacturing process repeatedly in the vertical direction, which reduces manufacturing costs.
  • the memory units 33 of the element layers 30_1 to 30_n on the element layer 20 can be designed to have different wiring intervals or transistor sizes for each of the element layers 30_1 to 30_n.
  • the specifications of the memory units 33 such as the access speed, can be made different for each of the element layers 30_1 to 30_n, so that the memory units 33 of the same area can have different memory capacities and access speeds.
  • the off-state current of an OS transistor is extremely low. Therefore, charge corresponding to data written to the memory cell 34 can be held in the capacitor for a long time. In other words, data once written in the memory cell 34 can be held for a long time. This reduces the frequency of data refresh and reduces the power consumption of the semiconductor device 10 of one embodiment of the present invention.
  • a memory unit having a memory cell with an OS transistor is sometimes referred to as an "OS memory.”
  • the memory unit 33 provided with memory cells 34 having OS transistors can be a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • DOSRAM refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells.
  • DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside.
  • DOSRAM is a memory that utilizes the low off-current of OS transistors. Since DOSRAM is a 1T1C type memory cell, a large memory capacity can be realized in the memory unit 33. Furthermore, by using OS transistors, the data retention period can be increased compared to DRAM having Si transistors.
  • the Si transistors in DRAM have a higher off-current than OS transistors. Therefore, in order to reduce the off-current of Si transistors, the channel length needs to be increased. In order to ensure a long channel length in a limited area, it is effective to make the channel length long in the depth direction of the substrate, but in this case, it becomes difficult to make the substrate thin. In addition, the capacitance value of the capacitor needs to be increased to hold the charge. Therefore, the height of the capacitor needs to be increased, as in a trench type (deep groove type) structure. Therefore, in DRAM memory cells that have Si transistors, the cell size increases in the Z direction.
  • the off-current of the OS transistor in the DOSRAM is extremely low. Therefore, it is not necessary to increase the channel length in order to reduce the off-current.
  • the thickness of each element layer 30 can be made thinner than that of the DRAM.
  • the capacitance of the capacitor can be estimated to be small.
  • a parallel plate type capacitor can be used instead of a trench type (deep groove type).
  • a parallel plate type capacitor is easier to manufacture than a trench type capacitor. Therefore, the yield is high and the number of manufacturing steps can be reduced.
  • Such a DOSRAM configuration that allows the element layer to be thin, has a high yield, and allows the number of manufacturing steps to be reduced is particularly effective when applied to the memory portion 33 of the element layers 30_1 to 30_n of one embodiment of the present invention.
  • the memory unit 33 which is provided with memory cells 34 having OS transistors, can be a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory).
  • NOSRAM has memory cells that are two-transistor (2T) or three-transistor (3T) gain cells. NOSRAM rewrites data by charging and discharging a capacitor, so in principle there is no limit to the number of times it can be rewritten and it is low energy. NOSRAM also allows for faster data access speeds than DOSRAM. Therefore, NOSRAM is a memory that can operate at higher speeds, has lower power consumption, and is more durable against rewriting than DOSRAM.
  • NOSRAM By storing data in three or more values, NOSRAM can store a larger amount of data per memory cell than DOSRAM. NOSRAM can also read written data non-destructively, making it suitable for long-term data retention. On the other hand, DOSRAM reads written data destructively, making it suitable for use in memory hierarchies that are accessed frequently.
  • OS transistors have better electrical characteristics than Si transistors in high-temperature environments. Specifically, even at high temperatures of 125° C. or higher and 150° C. or lower, the ratio of on current to off current is large, enabling good switching operation. Furthermore, OS transistors operate well within the temperature range of -40° C. or higher and 190° C. or lower. In addition, OS transistors have excellent heat resistance. This is a good heat resistance compared to the heat resistance of phase change memory (PCM) (-40°C to 150°C), resistance random access memory (ReRAM) (-40°C to 125°C), and magnetoresistive random access memory (MRAM) (-40°C to 105°C).
  • PCM phase change memory
  • ReRAM resistance random access memory
  • MRAM magnetoresistive random access memory
  • the elements constituting the semiconductor device 10 are shown separated from each other to make the arrangement of the elements easier to understand. It is preferable that the elements provided on the same layer are formed in the same process, but this is not limited to this. For example, the elements may be formed in separate processes and integrated together using a bonding technique or the like.
  • the memory unit 33 in which the memory cells 34 are provided is stacked in a direction perpendicular or approximately perpendicular to the surface of the element layer 20.
  • the element layers 30_1 to 30_n are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate on which the element layer 20 is provided.
  • the direction perpendicular or approximately perpendicular to the surface of the element layer 20 is defined as the Z-axis direction.
  • the Z-axis direction may be referred to as the direction perpendicular to the surface of the element layer 20 in the specification.
  • approximately perpendicular refers to a state in which the elements are arranged at an angle of 85 degrees or more and 95 degrees or less.
  • the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element.
  • the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the semiconductor device 10.
  • the X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.
  • the memory unit 33 provided in the element layers 30_1 to 30_n can be a hierarchical memory unit. Therefore, the memory unit 33 can be used as a cache memory for the calculation unit 21.
  • a cache memory is a memory used to reduce delays in the main memory device and buses when the calculation unit 21, such as a CPU, inputs/outputs or updates data, instructions, etc., and to fill in the performance gap between the calculation unit 21 and an external memory device.
  • the calculation unit By configuring the calculation unit to have a memory unit that can be used as a large-capacity cache memory above the calculation unit, the frequency of access to the external memory device (main memory or auxiliary memory device) for data due to cache misses can be reduced, thereby improving power efficiency.
  • FIG. 2A shows the memory devices (including the memory units of the element layer 30 described above) included in the arithmetic processing system 100 including the semiconductor device 10, hierarchically organized in order of access speed into memory units 210, 220, 230, and 240.
  • the memory unit 210 at the top level corresponds to memory units such as registers, flip-flops, and SRAM (Static Random Access Memory) in the calculation unit 21 provided in the element layer 20.
  • the memory unit 220 at the next level corresponds to the memory unit 33 of the element layer 30.
  • the memory unit 230 corresponds to the primary storage device (main memory).
  • An example of a primary storage device (main memory) is DRAM.
  • the memory unit 240 corresponds to an auxiliary storage device.
  • An example of an auxiliary storage device is a flash memory, hard disk drive, solid state drive, etc., which are storage class memories.
  • the storage unit 220 corresponds to the cache memory described above.
  • the storage unit 220 can be subdivided into hierarchies, such as an L1 cache 221, an L2 cache 222, and an L3 cache 223, depending on the access speed and storage capacity.
  • the storage unit 220 may be configured to be subdivided into two hierarchies or four or more hierarchies.
  • the higher the hierarchical level of the memory unit the higher the speed of operation required. Also, the lower the hierarchical level of the memory unit, the higher the capacity and density (or the smaller the area per bit) required.
  • the memory unit 210 stores data used for calculations in integrated circuits and the like, so particularly high speed operation is required. Also, for example, the L1 cache, which is located at the highest hierarchical level of the memory unit 220, is accessed most frequently, so high speed operation is required. On the other hand, the L2 cache, L3 cache, and the like do not require as high speed operation as the L1 cache, but they do require large capacity and a smaller area per bit than the L1 cache.
  • One aspect of the present invention has been made in consideration of the above problems, and configures a cache memory using an element layer 30 having OS transistors that can be stacked on the operation unit 21 that functions as a CPU in the semiconductor device 10.
  • the L3 cache is stacked above the L1 cache and the L2 cache.
  • the L2 cache is stacked above the L1 cache.
  • the L1 cache is stacked above the operation unit 21.
  • the semiconductor device 10 configures the L1 cache 221, the L2 cache 222, and the L3 cache 223 using element layers 30 (element layers 30_1 to 30_4) that are provided above the element layer 20 in which the operation unit 21 having the memory unit 210 is provided.
  • L1 cache 221 is provided on the element layer 20 side, and the L2 cache 222 and the L3 cache 223 are provided on the element layer 30 side. It is also possible to provide a modified configuration in which the L1 cache 221 and the L2 cache 222 are provided on the element layer 20 side, and the storage units in the hierarchy after the L3 cache 221 (e.g., the L4 cache, etc.) are provided on the element layer 30 side. With this configuration, it is possible to increase the access speed of storage units close to the calculation unit 21, such as the L1 cache 221.
  • This configuration increases the memory capacity of the memory unit 33, which functions as a cache memory, and also makes it easier to arrange the circuit parts of the calculation unit 21, which functions as a CPU, to provide a semiconductor device that has a small area, high calculation capabilities, and low power consumption.
  • FIG. 3A is a block diagram illustrating an example of a configuration in which the above-described configuration is applied to the calculation unit 21 (the register provided in the calculation unit 21 corresponds to the memory unit 210), the L1 cache 221, the L2 cache 222, and the L3 cache 223 (corresponding to the memory unit 220).
  • FIG. 3B is a schematic diagram illustrating the arrangement of each block described in FIG. 3A.
  • FIG. 3B illustrates the arrangement of the circuit unit in the element layer 20 in which the calculation unit is provided, the arrangement of the memory unit in the element layer 30_1 in which the L1 cache and the L2 cache are provided, and the arrangement of the memory unit in the element layer 30_2 in which the L3 cache is provided.
  • FIG. 3B illustrates how the element layer 20, the element layer 30_1, and the element layer 30_2 are stacked in the Z direction.
  • the arithmetic unit 21 provided in the element layer 20 has, as an example, circuit units such as an instruction analysis unit 211 (instruction decoder), a branch prediction unit 212, a load/store unit 213, an arithmetic logic unit 214, and a floating point arithmetic unit 215.
  • the arithmetic unit 21 having multiple circuit units occupies most of the limited area. Therefore, it is not easy to increase the storage capacity of the L1 cache 221 or the L2 cache 222, which are in a hierarchy close to the arithmetic unit in the above-mentioned computing system 100, without reducing the computing capacity of the arithmetic unit 21 in the element layer 20.
  • the L1 cache 221 provided in the element layer 30_1 has a small memory capacity that is the minimum required, and is provided in the element layer 30_1, which is a different element layer from the element layer 20 in which the memory unit 210 is provided.
  • the L1 cache 221 is also configured to be divided into an instruction cache 251 and a data cache 252.
  • the L2 cache 222 is limited in memory capacity, just like the L1 cache 221.
  • the L3 cache 223 needs to have a larger memory capacity than the L1 cache 221 and the L1 cache 221, so it is configured to be provided in a different element layer from the element layer 30_1 in which the L1 cache 221 and the L2 cache 222 are provided.
  • the instruction cache 251 and data cache 252, which are the L1 cache 221, are provided in the element layer 30_1, the area of the L1 cache 221 when provided in the element layer 20 can be reduced, and the area of the arithmetic unit 21 in the element layer 20 can be reduced. Therefore, the chip size of the semiconductor device 10 in which the element layer 20 and the element layers 30_1 to 30_n are stacked can be reduced. As a result, the yield of the semiconductor device 10 can be improved.
  • the degree of freedom of the arrangement of the L1 cache 221, such as the instruction cache 251 and the data cache 252 is increased, the instruction cache 251 and the data cache 252 can be arranged in a square or approximately square shaped area.
  • the shape of the instruction cache 251 and the data cache 252 is restricted because the degree of freedom of the arrangement of the L1 cache 221 is low. If the shape of the instruction cache 251 and the data cache 252 is restricted, the access speed may decrease due to factors such as longer wiring length. In other words, the access speed of the L1 cache 221 can be improved compared to when the L1 cache 221 is placed in the element layer 20.
  • the instruction analysis unit 211 decodes the program stored in the instruction cache 251 and generates a control signal that identifies the instruction (load instruction, store instruction, arithmetic instruction, branch instruction, etc.) and the register data and memory access required to execute the instruction.
  • the branch prediction unit 212 predicts the branch condition (branch or not branch) in the branch instruction and performs speculative execution (if it predicts not to branch, it issues the address of the next instruction, and if it predicts to branch, it issues the address of the branch destination).
  • the instruction analysis unit 211 and branch prediction unit 212 need to process data stored in the instruction cache 251 at high speed, so it is effective to configure them near the instruction cache 251.
  • the instruction cache 251 provided in the element layer 30_1 is configured to be provided in an area (hatched area in FIG. 3B) above the instruction analysis unit 211 provided in the element layer 20. With this configuration, the instruction analysis unit 211 and branch prediction unit 212 can process data stored in the instruction cache 251 at high speed.
  • the load/store unit 213 has a general-purpose register 216 and the like.
  • the general-purpose register 216 corresponds to a part of the memory unit 210 in a higher hierarchy in the above-mentioned arithmetic processing system 100.
  • the load/store unit 213 stores (loads) data stored in the data cache 252 or the general-purpose register 216 into the general-purpose register 216 and the like, or stores (stores) data stored in the general-purpose register 216 and the like into the data cache 252 or the general-purpose register 216.
  • the load/store unit 213 needs to process data stored in the data cache 252 at high speed. Furthermore, since the load/store unit 213 needs to access data in the L2 cache 222 when there is no data in the data cache 252, it is effective to configure it near the data cache 252 and the L2 cache 222. In this case, it is preferable to configure the data cache 252 or the L2 cache 222 provided in the element layer 30_1 in an area above the load/store unit 213 provided in the element layer 20.
  • the data cache 252 provided in the element layer 30_1 and the load/store unit 213 provided in the element layer 20 may have an overlapping area
  • the L2 cache 222 provided in the element layer 30_1 and the load/store unit 213 provided in the element layer 20 may have an overlapping area
  • the data cache 252 and the L2 cache 222 provided in the element layer 30_1 may have an overlapping area with the load/store unit 213 provided in the element layer 20.
  • the load/store unit 213 can quickly process data stored in the data cache 252 or the L2 cache 222.
  • the arithmetic and logic unit 214 performs arithmetic operations and logical operations on data stored in the general-purpose registers 216 and the like, and stores the results in the general-purpose registers 216 and the like. Since the arithmetic and logic unit 214 needs to process data stored in the general-purpose registers 216 and the like at high speed, it is effective to place it near the load/store unit 213.
  • the floating-point arithmetic unit 215 performs floating-point arithmetic on data stored in a floating-point register or the like, and stores the results in a floating-point register (not shown) or the like.
  • the floating-point register is a register provided within the floating-point arithmetic unit 215.
  • the L2 cache 222 Since the L2 cache 222 needs to access data in the L3 cache 223 when data is not available in the L2 cache 222, it is effective to configure it close to the L3 cache 223. For example, it is preferable to configure the L3 cache 223 provided in the element layer 30_2 in an area above the L2 cache 222 provided in the element layer 30_1. For example, the L2 cache 222 provided in the element layer 30_1 and the L3 cache 223 provided in the element layer 30_2 may have an overlapping area. With this configuration, the L2 cache 222 can quickly process data stored in the L3 cache 223.
  • the above configuration increases the storage capacity of the cache memory and also facilitates the layout of each circuit section of the calculation section 21 that functions as a CPU, making it possible to provide a semiconductor device that has a small area, high calculation capability, and low power consumption.
  • Figures 3A and 3B illustrate the circuit arrangement of the calculation unit 21, L1 cache 221, L2 cache 222, and L3 cache 223 in element layer 20, element layer 30_1, and element layer 30_2, other configurations are also possible.
  • the registers in each circuit unit of the calculation unit 21 it is also possible to configure the registers in each circuit unit of the calculation unit 21 to have additional non-volatile memory for retaining (backing up) data in the registers.
  • the non-volatile memory has the function of retaining data in the registers in each circuit unit of the calculation unit 21.
  • the register of each circuit section of the calculation unit 21 can be a non-volatile register.
  • a non-volatile register is a register that can back up data in a low-power state, such as clock gating, which periodically stops the clock signal, or power gating, which stops the supply of power supply voltage.
  • FIG. 4A is a block diagram illustrating an example of a configuration having registers in each circuit unit of the calculation unit 21 and a non-volatile memory provided in the element layer 30_1 in the configuration of FIG. 3A described above.
  • FIG. 4B is a schematic diagram illustrating the arrangement of each block described in FIG. 4A.
  • the element layer 20 shown in FIG. 4A and FIG. 4B has a register 120 in each circuit unit in the calculation unit 21.
  • the register 120 provided in the element layer 20 is a circuit having a Si transistor.
  • the element layer 30_1 shown in FIG. 4A and FIG. 4B has a nonvolatile memory 131 that holds data in the register 120 in each circuit unit in the calculation unit 21.
  • the nonvolatile memory 131 is a memory that holds data by utilizing the low off-current of an OS transistor.
  • a dotted arrow is shown between the register 120 provided in the element layer 20 and the nonvolatile memory 131 provided in the element layer 30_1 to indicate data evacuation (also called save, store, or backup) and restoration (also called load, restore, or recovery).
  • the register 120 may be called a volatile register.
  • the nonvolatile memory 131 may be called a backup circuit.
  • the registers 120 are provided in areas within each circuit unit of the arithmetic unit 21. That is, the registers 120 are distributed and arranged in the instruction analysis unit 211, the branch prediction unit 212, the load/store unit 213, the arithmetic logic unit 214, and the floating point arithmetic unit 215.
  • the non-volatile memory 131 is provided in an area different from the area in which the cache memory is provided. That is, the non-volatile memory 131 is provided in an area different from the areas in which the L2 cache 222, the instruction cache 251, and the data cache 252 are provided.
  • the register 120 and non-volatile memory 131 shown with hatching in Figures 4A and 4B are preferably provided so that the areas in which the circuits are provided have overlapping areas.
  • the non-volatile memory 131 is preferably provided so that it has an overlapping area with the register 120.
  • region 120R of element layer 20 in which register 120 is provided is provided so as to have an overlapping region with region 131R of element layer 30_1 in which non-volatile memory 131 is provided.
  • This configuration shortens the signal propagation distance between register 120 and non-volatile memory 131, and significantly reduces the resistance and parasitic capacitance of the wiring between the circuits, thereby realizing reduced power consumption and signal delay.
  • FIG. 5A is a block diagram of a semiconductor device 10R having a nonvolatile register 110 composed of the register 120 and nonvolatile memory 131 described in FIGS. 4A and 4B.
  • FIG. 5B is a diagram showing an example of the circuit configuration of the nonvolatile register 110 having the register 120 and nonvolatile memory 131 described in FIGS. 4A and 4B.
  • FIG. 5C is a schematic perspective view of the nonvolatile register 110 shown in FIG. 5B.
  • FIG. 5A also illustrates a state control unit 112 that can switch the semiconductor device 10R to a low-power state such as power gating or clock gating depending on the state of the semiconductor device 10R.
  • a state control unit 112 that can switch the semiconductor device 10R to a low-power state such as power gating or clock gating depending on the state of the semiconductor device 10R.
  • the state control unit 112 is a circuit that outputs control signals for switching between and processing multiple tasks in response to signals such as an interrupt signal input from outside and a sleep signal generated by the semiconductor device 10R.
  • the state control unit 112 generates a clock signal CLK and various signals (signal BK, signal RE, signal SE).
  • the clock signal CLK and various signals are input to the semiconductor device 10R.
  • Signal BK is a signal that controls the saving of data held in the flip-flop in register 120. By saving the data, the data in register 120 is stored in non-volatile memory 131.
  • Signal RE is a signal that controls the loading of data stored in non-volatile memory 131.
  • the data stored in non-volatile memory 131 is stored in a flip-flop in register 120.
  • Signal SE is a selector switching signal.
  • Clock signal CLK is a signal for operating the flip-flop in register 120.
  • the nonvolatile register 110 shown in FIG. 5B includes a register 120 and a nonvolatile memory 131.
  • the register 120 includes a selector 121 and a flip-flop 122.
  • the nonvolatile memory 131 can be configured with OS transistors 133 and 134 and a capacitor 135.
  • the nonvolatile memory 131 uses the characteristics of the OS transistors, which have a very low off-state current, to accumulate charge in the capacitor 135 and can hold a potential corresponding to the data written to the register 120 for a long period of time.
  • Non-volatile register 110 holds data input from terminal D or data input from terminal SD of register 120 in register 120 and outputs it from terminal Q in response to clock signal CLK.
  • the data of register 120 output from terminal Q is saved in non-volatile memory 131 under control of signal BK.
  • the data of non-volatile memory 131 is output to terminal SD under control of signal RE and loaded into register 120.
  • Selector 121 has the function of transmitting the signal of terminal D or terminal SD to register 120 in response to signal SE.
  • Terminal D is a terminal that provides data input from outside non-volatile register 110.
  • Terminal SD is a terminal that provides data input from non-volatile memory 131.
  • the flip-flop 122 is illustrated as a D flip-flop in FIG. 5B, it is not limited to this. Any flip-flop prepared in a standard circuit library can be applied.
  • the transistors of the flip-flop 122 are Si transistors, and by having a circuit such as an inverter loop, it is possible to hold one piece of data.
  • the flip-flop 122 holds data at an input terminal D F in response to a clock signal CLK, and outputs the held data from an output terminal Q F to a terminal Q.
  • the nonvolatile memory 131 is connected to a terminal Q and a terminal SD.
  • a terminal (wiring) connected to the terminal Q is called an input terminal
  • a terminal (wiring) connected to the terminal SD is called an output terminal.
  • the output terminal QF of the flip-flop 122 described above is electrically connected to the input terminal of the nonvolatile memory 131
  • the input terminal DF of the flip-flop 122 is electrically connected to the output terminal of the nonvolatile memory 131.
  • the non-volatile memory 131 has a transistor 133, a transistor 134, and a capacitor 135.
  • the other electrode of the capacitor 135 is connected to the wiring CL.
  • the transistor 133 is provided between the capacitor 135 and a terminal Q.
  • the transistor 134 is provided between the capacitor 135 and a terminal SD.
  • One electrode of the capacitor 135 of the non-volatile memory 131 is illustrated as a node SN.
  • a signal BK is applied to the gate of transistor 133, and a signal RE is applied to the gate of transistor 134.
  • the signal BK is a signal for saving the data held by the flip-flop 122 in the multiple non-volatile memories 131.
  • the signal RE is a signal for loading the data held in the non-volatile memory 131 into the flip-flop 122.
  • Transistors 133 and 134 are OS transistors. Transistors 133 and 134 are shown with a backgate. The backgates of transistors 133 and 134 can be supplied with a constant voltage to control the transistor characteristics. At least transistors 133 and 134 are preferably OS transistors. OS transistors have an extremely small off-current, which makes it possible to suppress a drop in the voltage of node SN and consumes almost no power to retain data, so that nonvolatile memory 131 has nonvolatile characteristics. Data is rewritten by charging and discharging capacitor 135, so nonvolatile memory 131 is theoretically not limited in the number of rewrites and allows data to be written and read with low energy.
  • the OS transistor functions as a switch.
  • a signal applied to the gate is set to a high level (hereafter referred to as "H") to bring the source and drain into a conductive state
  • a signal applied to the gate is set to a low level (hereafter referred to as "L") to bring the source and drain into a non-conductive state.
  • a signal at terminal SD is selected by setting signal SE to a high level (hereafter referred to as "H")
  • a signal at terminal D is selected by setting signal SE to a low level (hereafter referred to as "L”).
  • the non-volatile memory 131 can be stacked on the register 120 that is configured as a silicon CMOS circuit.
  • the nonvolatile memory 131 has a much smaller number of elements than the register 120, there is no need to change the circuit configuration and layout of the register 120 in order to stack the nonvolatile memory 131. In other words, the nonvolatile memory 131 is a highly versatile circuit. In addition, because the nonvolatile memory 131 can be provided in the area in which the register 120 is formed, it is possible to reduce area overhead to zero even when the nonvolatile memory 131 is incorporated. Because little energy is required to hold data in the backup circuit, it is possible to frequently save or load data in the semiconductor device 10R.
  • the non-volatile memory 131 By providing the non-volatile memory 131, a parasitic capacitance due to the transistor 133 is added to the node Q, but since this is small compared to the parasitic capacitance due to the logic circuit connected to the node Q, it does not affect the operation of the register 120. In other words, even if the non-volatile memory 131 is provided, the performance of the non-volatile register 110 does not substantially decrease.
  • Fig. 6 shows an example of a timing chart for explaining the operation of the non-volatile register 110 shown in Fig. 5B.
  • T00 to T02 and T10 to T12 represent time.
  • Fig. 6 illustrates the clock signal CLK, terminal D, terminal Q, signal BK, signal RE, node SN, and signal SE given to the selector 121.
  • the flip-flop 122 stores data at the input terminal D- F and outputs it from the output terminal Q- F in synchronization with the rising edge (waveform switching from L level to H level) of the clock signal CLK.
  • the register 120 stores the data D1 given to the terminal D and outputs it from the output terminal Q F.
  • data D1 can be stored in non-volatile memory 131. This allows clock gating of clock signal CLK and power gating of semiconductor device 10R, etc. to be achieved.
  • the register 120 stores the data D2 applied to the terminal D and outputs it from the output terminal Q F.
  • the terminal D is also provided with data D3.
  • the register 120 stores the data D3 applied to the terminal D and outputs it from the output terminal QF .
  • the data of the interrupted task can be saved and the data of the task to be resumed can be loaded.
  • the data saved when the task is switched can be stored in a data retention circuit.
  • the program processing can be executed sequentially by saving and loading the data when the interrupt signal is input. This makes it possible to process data more efficiently.
  • non-volatile memory 131 provided above the register 120 it is possible to configure the non-volatile memory 131 provided above the register 120 to be provided across multiple element layers 30_1 to 30_n.
  • the register 120 provided in the element layer 20 it is possible to configure the register 120 provided in the element layer 20 to have a non-volatile memory 131[1] provided in the element layer 30_1 and a non-volatile memory 131[2] provided in the element layer 30_2.
  • the region 120R in which the register 120 is provided, the region 131R[1] in which the non-volatile memory 131[1] is provided, and the region 131R[2] in which the non-volatile memory 131[2] is provided, shown in FIG. 7A, have overlapping regions.
  • the transistors and capacitors of each circuit provided in the element layer 20, the element layers 30_1, and 30_2 can be arranged as shown in FIG. 7B.
  • BK[1], BK[2], RE[1], and RE[2] are signals for controlling backup circuits provided in different element layers.
  • Nodes SN[1] and SN[2] are nodes provided in different element layers.
  • the configuration shown in Figures 7A and 7B shortens the signal propagation distance between register 120 and non-volatile memories 131[1], 131[2], and significantly reduces the resistance and parasitic capacitance of the wiring between the circuits, thereby reducing power consumption and signal delay.
  • the configuration shown in Figures 7A and 7B can hold separate data signals in nodes SN[1], SN[2], so that the held data signal can be switched by saving or loading the data signal, which is particularly effective for operations such as switching between multiple tasks.
  • the above configuration makes it possible to provide a semiconductor device that can back up data and perform clock gating and power gating of registers, thereby reducing power consumption.
  • processing can be resumed from where it left off at the time of the previous calculation, making it possible to provide a semiconductor device with improved calculation performance.
  • FIGS. 8A to 8H are circuit diagrams illustrating examples of the configuration of a memory cell having an OS transistor that can be applied to the memory cell 34 described above.
  • DOSRAM or NOSRAM can be given.
  • FIG. 8A shows an example of a memory cell of a 1T1C type DOSRAM that can be used as memory cell 34.
  • Memory cell 34A shown in FIG. 8A is electrically connected to a word line WL, a bit line BL, a wiring CDL that functions as a capacitance line, and a wiring BGL that functions as a wiring that supplies a backgate voltage.
  • Memory cell 34A has a transistor 35 and a capacitor 36. The backgate of transistor 35 is electrically connected to the wiring BGL.
  • Transistor 35 is an OS transistor. OS transistors have an extremely low off-state current. Therefore, memory cell 34A can reduce the frequency of data refresh. Therefore, the power required to hold data can be reduced.
  • FIG. 8B shows another example of the configuration of a memory cell of a 1T1C type DOSRAM.
  • Memory cell 32B shown in FIG. 8B differs from memory cell 34A shown in FIG. 8A in that transistor 35 is an OS transistor that does not have a backgate.
  • FIG. 8C shows an example of a NOSRAM memory cell that is a two-transistor type (2T) gain cell that can be used for memory cell 34.
  • Memory cell 34C shown in FIG. 8C has transistors 35A and 35B and a capacitor 36. Note that the capacitor 36 in the NOSRAM memory cell can be omitted by using parasitic capacitance such as the gate capacitance of the transistor.
  • Transistor 35A is a write transistor
  • transistor 35B is a read transistor.
  • the back gates of transistors 35A and 35B are electrically connected to wiring BGL.
  • memory cell 34C Since the write transistor is an OS transistor, it is possible to continue to hold the charge corresponding to the data by turning off the write transistor. Therefore, memory cell 34C does not consume power to hold the data. Therefore, memory cell 34C can function as a low-power memory cell that can hold data for a long period of time.
  • Memory cell 34D shown in FIG. 8D is a 3T type gain cell, and has transistors 35A, 35B, 35C, and a capacitor 36.
  • Transistors 35A, 35B, and 35C are a write transistor, a read transistor, and a select transistor, respectively.
  • the back gates of transistors 35A, 35B, and 35C are electrically connected to wiring BGL.
  • Memory cell 34D is electrically connected to wirings RWL, WWL, wirings RBL, WBL, wiring CDL, and power supply line PL2. For example, voltage GND (low-level power supply voltage) is input to wiring CDL and wiring PL2.
  • voltage GND low-level power supply voltage
  • FIG. 8E shows another example of the configuration of a 2T-type gain cell.
  • Memory cell 34E shown in FIG. 8E differs from memory cell 34C shown in FIG. 8C in that the read transistor is an OS transistor that does not have a backgate.
  • FIG. 8F shows another example of the configuration of a 3T-type gain cell.
  • Memory cell 34F shown in FIG. 8F differs from memory cell 34D shown in FIG. 8D in that it is configured with OS transistors without backgates as read transistors and selection transistors.
  • FIG. 8G shows another example of the configuration of a 2T-type gain cell.
  • Memory cell 34G shown in FIG. 8G differs from memory cell 34C shown in FIG. 8C in that transistors 35A and 35B are configured as OS transistors without a backgate and that capacitor 36 is omitted.
  • FIG. 8H shows another example of the configuration of a 3T-type gain cell.
  • Memory cell 34H shown in FIG. 8H differs from memory cell 34D shown in FIG. 8D in that transistors 35A, 35B, and 35C are OS transistors without a backgate, and capacitor 36 is omitted.
  • a voltage that turns off the access transistor can be applied to the wiring (word lines WL and WWL in FIGS. 8A to 8H) connected to the gate of the transistor, and other parts can be power-gated. With this configuration, the supply of power supply voltage can be stopped with data stored in the memory cell 34.
  • the instruction cache 251 formed in the element layer 30_1 stacked above the instruction analysis unit 211 and the branch prediction unit 212 as described in FIG. 3B is preferably configured with NOSRAM memory cells, which are advantageous for high-speed operation.
  • the data cache 252 and the L2 cache 222 as described in FIG. 3B are preferably configured with NOSRAM, which are advantageous for high-speed operation.
  • the L2 cache 222 may be DOSRAM, which is advantageous for high memory density.
  • the L3 cache 223 as described in FIG. 3B is preferably DOSRAM, which is advantageous for high density.
  • FIG. 9 is a diagram showing a configuration example of a semiconductor device 10M in which memory cells with different circuit configurations are applied to element layers 30 in different layers.
  • the element layer 30 provided on the element layer 20 is divided into element layer 30_A, which is the lower element layer 30, and element layer 30_B, which is the upper element layer 30.
  • memory cell 34C which is the NOSRAM memory cell described in FIG. 8C
  • memory cell 34A which is the DOSRAM memory cell described in FIG. 8A
  • a semiconductor device can be obtained in which high-speed operation and high memory density are achieved in the memory unit 220 that functions as a cache memory.
  • the storage units at the L3 cache 223 and higher hierarchical levels are configured as DOSRAM using the VFETs described above.
  • the storage unit 230 which corresponds to the main memory, can be configured as DOSRAM using VFETs to achieve high density storage capacity.
  • the storage unit 230 can be used as a cache memory, similar to the storage unit 220. Therefore, as in the computation processing system 100B shown in FIG. 10A, the hierarchical level that functions as a cache memory (the hatched hierarchical level in FIG. 10A) can be made larger. In other words, by employing OS memory as the storage unit in the storage unit hierarchy after the cache memory, it is possible to provide a storage unit hierarchy that differs from that of conventional computation processing systems.
  • the memory unit 230 which corresponds to the main memory, is preferably provided in an upper layer of the element layer 30 in which the memory unit 220 functioning as a cache memory is provided.
  • the memory unit 230 is provided in the element layer 30 (element layers 30_3 to 30_8) provided in the upper layer of the element layer 30 (element layers 30_1 and 30_2) in which the memory unit 220 is provided.
  • a semiconductor device 10B can be formed in which the arithmetic unit, main memory, and cache memory are integrated.
  • the configuration of semiconductor device 10B in which a calculation unit, main memory, and cache memory are integrated, makes it possible to reduce the size of connection wiring, etc., compared to a technique in which a memory unit and a calculation unit are bonded together using through electrodes such as TSVs. This makes it possible to increase the amount of data accessed between memory units such as the calculation unit, main memory, and cache memory. In other words, it becomes possible to improve the bandwidth (also called memory bandwidth) of the memory (memory unit). Bandwidth is the amount of data transferred per unit time. Furthermore, the configuration of semiconductor device 10B can improve either or both of the memory bandwidth and the access latency. Access latency is the time from access to when data exchange begins.
  • FIGS. 11A and 11B are schematic diagrams illustrating a configuration in which the above-mentioned semiconductor device 10 is applied to an integrated circuit (called an IC chip).
  • the semiconductor device 10 can be made into a single IC chip by mounting multiple element layers on a packaging substrate. An example of the configuration is shown in FIG. 11A and FIG. 11B.
  • FIG. 11A The schematic cross-sectional view of IC chip 11A shown in FIG. 11A illustrates the configuration of a semiconductor device having an element layer 20 serving as a base die on a package substrate 101, and as an example, four element layers 30_1 to 30_4 stacked on element layer 20.
  • FIG. 11A also illustrates a Si transistor 59 in element layer 20 and an OS transistor 57 in element layers 30_1 to 30_4.
  • the package substrate 101 is provided with solder balls 102 for connecting the semiconductor device 10 to a printed circuit board or the like.
  • the element layers 30_1 to 30_4 are provided with through electrodes 54 that penetrate the element layers.
  • the element layers 30_1 to 30_4 are bonded to each other using electrodes 56 that are exposed on the surfaces.
  • Cu-Cu bonding can be used as a technique for electrically bonding different layers using the electrodes 56.
  • Cu-Cu bonding is a technique for achieving electrical conductivity by connecting Cu (copper) pads together.
  • the element layers 30_1 to 30_4 are stacked three-dimensionally as shown in FIG. 11A, the element layers are electrically connected to each other using a technology that uses through electrodes such as TSVs (Through Silicon Vias) or Cu-Cu direct bonding technology.
  • TSVs Through Silicon Vias
  • Cu-Cu direct bonding technology With this configuration, signals and the like supplied to each element layer can be distributed by wiring within each element layer.
  • OS transistors it is possible to reduce power consumption by taking advantage of the extremely low off-current characteristics of OS transistors.
  • the schematic cross-sectional view of IC chip 11B shown in FIG. 11B illustrates the configuration of a semiconductor device having an element layer 20 serving as a base die on a package substrate 101, and as an example, four element layers 30_1 to 30_4 stacked on element layer 20. Electrodes 58 for electrically connecting element layer 20 and element layers 30_1 to 30_4 can be provided in the process of manufacturing Si transistor 59 or OS transistor 57.
  • connection between element layer 20 having Si transistor 59 and element layers 30_1 to 30_4 having OS transistor 57 can be a monolithic configuration without using a technique using a through electrode such as a TSV or a Cu-Cu direct bonding technique.
  • Element layers 30_1 to 30_4 on element layer 20 can be configured to use wiring provided together with OS transistor 57 of element layers 30_1 to 30_4 as electrodes 58 for connecting to upper or lower element layers.
  • the spacing between the wirings provided together with the OS transistors 57 can be finely processed, compared to through electrodes used in TSV or Cu-Cu direct bonding technology. Therefore, in the configuration of IC chip 11B shown in FIG. 11B, the number of electrodes for connecting to upper or lower element layers can be increased. Therefore, the number of wirings (number of signal lines) between memory unit 33 having memory cells provided in element layers 30_1 to 30_4 and calculation unit 21 provided in element layer 20, as described in FIG. 1B and other figures, can be increased. Therefore, the transfer amount (bandwidth) of signals transmitted and received between element layer 20 and element layer 30 can be increased. By increasing the bandwidth, the amount of data transferred between memory unit 33 and calculation unit 21 per unit time can be increased.
  • FIG. 12A is a diagram explaining an element layer 30B having a different configuration from the element layer 30 explained in FIG. 1B
  • FIG. 12B is a diagram explaining a configuration example of a semiconductor device 10E in which the element layer 30B (element layers 30B_1 to 30B_n) shown in FIG. 12A is stacked on the element layer 20
  • FIG. 12C is a schematic diagram of the element layer 30B (element layers 30B_1 to 30B_n) stacked on the element layer 20.
  • the element layer 30B shown in FIG. 12A has an element layer 62 stacked on the element layer 61.
  • the element layer 61 is an element layer having Si transistors, similar to the element layer 20.
  • the element layer 61 has a functional circuit section 32 having functions such as an arithmetic circuit, a driver circuit, or a control circuit, such as a CPU or GPU, which can be configured with Si transistors.
  • the element layer 62 is an element layer having OS transistors, similar to the element layer 30.
  • the element layer 62 has a memory section 33.
  • the electrode 58 for electrically connecting the memory unit 33 and the functional circuit unit 32 is the electrode 58 described in FIG. 11B above.
  • the electrode 58 is a wiring that can be formed in the same manner as the layer in which the OS transistor is provided. Therefore, it is possible to increase the number of wirings (number of signal lines) between the memory unit 33 provided in the element layer 62 and the functional circuit unit 32 provided in the element layer 61.
  • the semiconductor device 10E is configured to input and output data between the arithmetic unit 21 and the memory unit 33 via the through electrodes 54 provided in the element layers 61 and 62 and the metal bumps 53 provided between the through electrodes 54.
  • the through electrodes 54 and the metal bumps 53 (also called microbumps) can shorten the distance between the arithmetic unit 21 and the memory unit 33.
  • the functional circuit units 32 having the functions of the arithmetic unit can be distributed and arranged. Therefore, in the semiconductor device 10E, it is possible to distribute and arrange the functions of the arithmetic unit 21 in the functional circuit units 32. For example, it is also possible to configure a multi-core by operating multiple CPU cores in parallel.
  • the through electrodes 54 of each of the element layers 30B_1 to 30B_n may be connected using Cu-Cu bonding without using the metal bumps 53.
  • the through electrodes 54 may also be directly connected to each other without using a Cu (copper) pad.
  • FIGS. 13A and 13B are schematic cross-sectional views illustrating the direct connection configuration between element layer 20 and element layer 30B, as described in FIGS. 12B and 12C.
  • the 13A includes an OS transistor M OS included in the memory cell 34 of the memory unit 33.
  • the element layer 61 shown in FIG. 13A includes a Si transistor M Si included in the calculation unit 21, and an electrode M CU .
  • the electrode M CU is an electrode that is connected when forming the through electrode 54.
  • Cu copper
  • Au gold
  • the bonding layer 52 provided on the element layer 62 is preferably made of silicon oxide (SiOx), which flattens the bonding surface with the element layer 20 and allows hydroxyl groups on the bonding layer 52 and the surface of the element layer 20 to form bonds with each other.
  • Silicon oxide ( SiOx ) is preferable because it can improve the flatness of the surface compared to silicon nitride (SiN).
  • the layer formed on the surface of the element layer 20 and the bonding layer 52 are each formed of a layer containing silicon oxide ( SiOx ) and the flatness of the silicon oxide is improved, the hydroxyl groups (OH groups) on the silicon oxide surface formed on the surface of the element layer 20 and the hydroxyl groups (OH groups) on the silicon oxide surface of the bonding layer 52 are bonded by van der Waals forces, and there is a possibility that Si-O-Si bonds and H2O molecules are generated by subsequent heat treatment.
  • the element layer 30B is attached face-down to the element layer 20 (face-down bonding).
  • the element layer 20 has a Si transistor M Si and an electrode M CU of the calculation unit 21.
  • the through electrodes 54 provided in the element layers 61, 62, and 20 are provided to connect the electrode M CU of the element layer 61 and the electrode M CU of the element layer 20.
  • the bonding between the element layer 20 and the element layer 30B can be performed at an upper limit of 350° C. to 450° C., without exposing them to high temperatures of 1000° C. or higher, by improving the flatness of the bonding layer 52, for example. That is, the bonding between the element layer 20 and the element layer 30B can be performed without exposing them to high temperatures. This makes it possible to suppress fluctuations in the electrical characteristics of the OS transistor MOS that would occur if the element layer 30B were exposed to high temperatures. In addition, since the Si transistor is not exposed to high temperatures when the element layer 20 and the element layer 30B are bonded together, copper wiring can be used.
  • the element layer 62 may be stacked in multiple layers on the element layer 61.
  • An example of the element layer configuration in this case is shown in FIG. 14B.
  • the electrode 58 for electrically connecting the memory unit 33 (memory units 33_1 to 33_3) of each layer to the functional circuit unit 32 is the electrode 58 described in FIG. 11B above.
  • the electrode 58 is a wiring that can be formed in the same manner as the layer in which the OS transistor is provided. Therefore, the number of wirings (number of signal lines) between the memory unit 33 provided in the element layer 62 and the functional circuit unit 32 provided in the element layer 61 can be increased.
  • the functional circuit unit 32 is preferably used as a drive circuit for the memory cells of the stacked memory units 33 (memory units 33_1 to 33_3).
  • a specific example of using the functional circuit unit 32 as a drive circuit for the memory unit 33 will be described with reference to FIG. 15A and FIG. 15B.
  • FIG. 15A shows a schematic perspective view of element layer 30C according to one embodiment of the present invention.
  • FIG. 15B shows a block diagram of element layer 30C according to one embodiment of the present invention.
  • the element layer 30C shown in Figures 15A and 15B has an element layer 61 and n element layers 62 (n is an integer equal to or greater than 1).
  • Each element layer 62 has a memory unit 33 (memory units 33_1 to 33_n).
  • the memory units 33 have a plurality of memory cells 34.
  • the n-layer element layer 62 is provided on the element layer 61.
  • the area occupied by the element layer 30C can be reduced.
  • the memory capacity per unit area can be increased.
  • the functional circuit section 32 which functions as a drive circuit of the element layer 61, has a PSW 82 (power switch), a PSW 83, and a peripheral circuit 71.
  • the peripheral circuit 71 has a peripheral circuit 41, a control circuit 72, and a voltage generation circuit 73.
  • the circuits, signals, and voltages can be selected or removed as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • Signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data, and signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 72.
  • the control circuit 72 is a logic circuit that has the function of controlling the overall operation of the element layer 30C. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the element layer 30C. Alternatively, the control circuit 72 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the element layer 30C.
  • the control circuit 72 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 73 has the function of generating a negative voltage.
  • the signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 73. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 73, and the voltage generation circuit 73 generates a negative voltage.
  • the peripheral circuit 71 is a circuit for writing and reading data to the memory cells 34.
  • the peripheral circuit 71 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
  • the row decoder 42 and column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WWL (write word line) or wiring RWL (read word line) specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the memory cell 34, the function of reading data from the memory cell 34, and the function of retaining the read data.
  • the column driver 45 has the function of selecting the wiring WBL (write bit line) and wiring RBL (read bit line) specified by the column decoder 44.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written to the memory cell 34.
  • the data (Dout) read from the memory cell 34 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the element layer 30C.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW82 has a function of controlling the supply of VDD to the peripheral circuit 71.
  • PSW83 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the element layer 30C is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • Signal PON1 controls the on/off of PSW82
  • signal PON2 controls the on/off of PSW83.
  • the number of power supply domains to which VDD is supplied in the peripheral circuit 71 is one, but it is also possible to have multiple power supply domains. In this case, a power switch can be provided for each power supply domain.
  • Each of the n-layer element layers 62 has a memory unit 33.
  • the memory unit 33 has a plurality of memory cells 34.
  • Figures 15A and 15B show an example in which the memory unit 33 has a plurality of memory cells 34 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more).
  • rows and columns extend in directions perpendicular to each other.
  • the X direction is referred to as “rows” and the Y direction is referred to as “columns”, but there are also cases where the X direction is referred to as “columns” and the Y direction is referred to as "rows”.
  • the memory cell 34 located in the first row and first column is indicated as memory cell 34[1,1]
  • the memory cell 34 located in the pth row and qth column is indicated as memory cell 34[p,q].
  • the memory cell 34 located in the ith row and jth column (i is an integer between 1 and p, and j is an integer between 1 and q) is indicated as memory cell 34[i,j].
  • the element layer 62 when the element layer 62 is configured to be stacked, it is preferable to arrange the wiring WBL and wiring RBL in a direction perpendicular to the substrate surface.
  • the signal propagation distance between the wiring WBL and the sense amplifier connected to the wiring RBL can be shortened, and the resistance and parasitic capacitance of the wiring WBL and wiring RBL can be significantly reduced, thereby realizing a reduction in power consumption and signal delay.
  • Embodiment 2 In this embodiment, a cross-sectional structure example of an element layer including stacked OS transistors that can be applied to a semiconductor device or the like will be described. In this embodiment, an example of a schematic cross-sectional view that can be applied to a circuit configuration such as a DOSRAM or a NOSRAM will be described.
  • ⁇ DOSRAM Configuration Example 1> 16 shows a cross-sectional configuration example in the case where a DOSRAM circuit configuration is used.
  • element layers 700[1] to 700[4] are stacked on an element layer 701.
  • the element layer 701 corresponds to, for example, the element layer 20 described in the above embodiment.
  • the element layer 700 corresponds to, for example, the element layer 30 described in the above embodiment.
  • the transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 that is part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.
  • Transistor 550 may be either a p-channel type or an n-channel type.
  • Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.
  • the conductor 316 that functions as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.
  • a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.
  • Transistor 550 may be formed using an SOI (Silicon on Insulator) substrate, etc.
  • transistor 550 shown in FIG. 16 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between the element layer 701 and the element layer 700, or between the kth element layer 700 and the k+1th element layer 700.
  • the kth element layer 700 may be referred to as element layer 700[k]
  • the k+1th element layer 700 may be referred to as element layer 700[k+1].
  • k is an integer between 1 and N.
  • the solutions of "k+ ⁇ " and "k- ⁇ ” are integers between 1 and N.
  • wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film.
  • Conductors 328 and the like are embedded in the insulators 320 and 322.
  • Conductors 330 and the like are embedded in the insulators 324 and 326.
  • Conductors 328 and 330 function as contact plugs or wiring.
  • Insulators 320, 322, 324, and 326 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath.
  • the top surface of the insulator 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having barrier properties that prevent hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 550 to the region in which the transistor 500 in the element layers 700[1] to 700[4] is provided.
  • a film having barrier properties against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550.
  • a film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.
  • the insulator 326 has a lower dielectric constant than the insulator 324.
  • the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • insulator 350, insulator 357, insulator 352, and insulator 354 are stacked in this order on the insulator 326 and the conductor 330.
  • Conductor 356 is formed on insulator 350, insulator 357, and insulator 352. Conductor 356 functions as a contact plug or wiring.
  • the materials for each plug and wiring can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, either in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferable. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • the insulator 514 of the element layer 700[1] is provided on the insulator 354.
  • a conductor 358 is embedded in the insulator 514 and the insulator 354.
  • the conductor 358 functions as a contact plug or wiring.
  • the bit line BL and the transistor 550 are electrically connected via the conductor 358, the conductor 356, and the conductor 330.
  • the insulator 350 is an insulator having a barrier property against hydrogen, similar to the insulator 324. It is also preferable that the conductor 356 includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
  • a conductor having a barrier property against hydrogen for example, tantalum nitride or the like can be used.
  • tantalum nitride As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like can be used.
  • tantalum nitride and highly conductive tungsten it is possible to suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring.
  • the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.
  • the element layers 700[1] to 700[4] shown in FIG. 16 show an example in which two memory cells MC are electrically connected to one bit line BL.
  • the memory cell MC shown in FIG. 16 has a transistor M1 and a capacitor C.
  • An OS transistor can be used as the transistor M1.
  • Figures 17A and 17B are schematic cross-sectional views of a transistor 500 that can be used as transistor M1.
  • the transistor 500 has a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed therebetween overlapping the conductors 542a and 542b, an insulator 545 disposed on the bottom and side surfaces of the opening, and a conductor 560 disposed on the surface on which the insulator 545 is formed.
  • an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580.
  • the conductor 560 has a conductor 560a disposed inside the insulator 545 and a conductor 560b disposed so as to be embedded inside the conductor 560a.
  • an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.
  • oxide 530a and oxide 530b may be collectively referred to as oxide 530.
  • the present invention is not limited to this.
  • a structure in which a single layer of oxide 530b is provided, or a stacked structure of three or more layers may be provided.
  • the conductor 560 is shown as having a two-layer stacked structure, but the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a stacked structure of three or more layers.
  • the transistor 500 shown in FIG. 17A is only one example, and the present invention is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc.
  • the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode and drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region between the conductors 542a and 542b.
  • the arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.
  • conductor 560 is formed in a self-aligned manner in the region between conductor 542a and conductor 542b, conductor 560 does not have a region that overlaps with conductor 542a or conductor 542b. This makes it possible to reduce the parasitic capacitance formed between conductor 560 and conductor 542a and conductor 542b. This makes it possible to improve the switching speed of transistor 500 and provide it with high frequency characteristics.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560.
  • the threshold voltage of the transistor 500 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when a negative potential is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.
  • the transistor structure in which the electric field of the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure.
  • the S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure.
  • the S-channel structure disclosed in this specification can also be considered as a type of Fin type structure.
  • the Fin type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.).
  • the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said that the S-channel structure is substantially equivalent to a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure.
  • GAA Gate All Around
  • LGAA Layer Advanced Gate All Around
  • the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be the entire bulk of the oxide 530. Therefore, it is possible to improve the current density flowing through the transistor, which is expected to improve the on-current of the transistor or the field effect mobility of the transistor.
  • the conductor 503 has a structure similar to that of the conductor 518, with the conductor 503a being formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b being formed further inward.
  • the transistor 500 shows a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this.
  • the conductor 503 may be configured as a single layer or a stacked structure of three or more layers.
  • the conductor 503a is made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (the impurities are less likely to permeate).
  • the conductor 503a is made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).
  • the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen mentioned above.
  • conductor 503a has the function of suppressing the diffusion of oxygen, which can prevent conductor 503b from being oxidized and causing a decrease in conductivity.
  • the conductor 503 when the conductor 503 also functions as wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that in this embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single layer structure.
  • Insulator 520, insulator 522, and insulator 524 function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition.
  • the oxygen is easily released from the film by heating.
  • oxygen released by heating may be referred to as "excess oxygen”. That is, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region").
  • the vacancies may function as donors and generate electrons that are carriers.
  • some of the hydrogen may bond to oxygen that is bonded to a metal atom and generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics.
  • hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field, and therefore, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • oxide semiconductor with sufficiently reduced VOH it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also referred to as “dehydration” or “dehydrogenation treatment”) and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as “oxygenation treatment”).
  • impurities such as moisture and hydrogen
  • oxygen treatment also referred to as “oxygenation treatment”
  • an oxide material from which part of oxygen is released by heating is an oxide film from which the amount of oxygen released in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms/cm 3 or more, preferably 1.0 ⁇ 10 19 atoms/cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms/cm 3 or more, or 3.0 ⁇ 10 20 atoms/cm 3 or more, in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other and subjected to one or more of heat treatment, microwave treatment, and RF treatment.
  • heat treatment microwave treatment, and RF treatment.
  • water or hydrogen in the oxide 530 can be removed.
  • a reaction occurs in the oxide 530 in which the bond of VoH is broken, in other words, a reaction of " VOH ⁇ Vo+H" occurs, and dehydrogenation can be performed.
  • some of the generated hydrogen may be combined with oxygen to become H 2 O and removed from the oxide 530 or the insulator near the oxide 530.
  • some of the hydrogen may be gettered to the conductors 542a and 542b.
  • the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side.
  • high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530.
  • the pressure of the microwave treatment may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 50% or less, preferably 10% or more and 30% or less.
  • the heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher.
  • the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O ).
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher in order to compensate for desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere.
  • heat treatment may be successively performed in a nitrogen gas or inert gas atmosphere.
  • oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O ⁇ null" can be promoted. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 530, so that the hydrogen can be removed as H2O (dehydrated). This can prevent hydrogen remaining in the oxide 530 from recombining with the oxygen vacancies to form VOH .
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).
  • oxygen e.g., oxygen atoms, oxygen molecules, etc.
  • the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., so that the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable.
  • the conductor 503 can be suppressed from reacting with the oxygen contained in the insulator 524, the oxide 530, etc.
  • the insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST).
  • a so-called high-k material such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr)TiO 3 (BST).
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials that have the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate).
  • an insulator containing an oxide of one or both of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530, or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators.
  • the insulator 520 is thermally stable.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • by combining a high-k material insulator with silicon oxide or silicon oxynitride it is possible to obtain an insulator 520 having a layered structure that is thermally stable and has a high relative dielectric constant.
  • insulator 520, insulator 522, and insulator 524 are illustrated as the second gate insulating film having a three-layer stack structure, but the second gate insulating film may have a single layer, two layers, or a stack structure of four or more layers. In that case, it is not limited to a stack structure made of the same material, and may be a stack structure made of different materials.
  • the transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530, which includes the channel formation region.
  • the metal oxide that functions as an oxide semiconductor may be formed by sputtering or ALD (Atomic Layer Deposition).
  • ALD Advanced Deposition
  • the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.
  • a metal oxide that functions as a channel formation region in the oxide 530 with a band gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced.
  • oxide 530 By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.
  • the oxide 530 has a structure of multiple oxide layers with different atomic ratios of each metal atom.
  • the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b.
  • the atomic ratio of element M to In in the metal oxide used for the oxide 530a is larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b.
  • the atomic ratio of In to element M in the metal oxide used for the oxide 530b is larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.
  • the energy of the conduction band minimum of the oxide 530a is higher than the energy of the conduction band minimum of the oxide 530b.
  • the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.
  • the energy level of the conduction band minimum changes smoothly.
  • the energy level of the conduction band minimum at the junction between oxide 530a and oxide 530b changes continuously or can be said to be a continuous junction.
  • oxide 530a is In-Ga-Zn oxide
  • oxide 530b is In-Ga-Zn oxide
  • the main carrier path is oxide 530b.
  • oxide 530a As described above, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a large on-current.
  • Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on oxide 530b.
  • Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements, or an alloy combining the above-mentioned metal elements.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.
  • metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.
  • FIG. 17A shows conductor 542a and conductor 542b as a single layer structure, they may be laminated with two or more layers.
  • a tantalum nitride film and a tungsten film may be laminated.
  • a titanium film and an aluminum film may also be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.
  • Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed on top of that; and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed on top of that.
  • a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.
  • regions 543a and 543b may be formed as low-resistance regions at and near the interface of oxide 530 with conductor 542a (conductor 542b).
  • region 543a functions as one of the source region and drain region
  • region 543b functions as the other of the source region and drain region.
  • a channel formation region is formed in the region sandwiched between regions 543a and 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced.
  • a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.
  • the insulator 544 is provided to cover the conductors 542a and 542b, and suppresses oxidation of the conductors 542a and 542b.
  • the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used.
  • silicon nitride oxide or silicon nitride can also be used as the insulator 544.
  • an insulator containing an oxide of either or both of aluminum and hafnium such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).
  • hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process.
  • the conductors 542a and 542b are made of a material that is resistant to oxidation, or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.
  • insulator 544 can prevent impurities such as water and hydrogen contained in insulator 580 from diffusing into oxide 530b.
  • the presence of excess oxygen in insulator 580 can prevent conductors 542a and 542b from oxidizing.
  • the insulator 545 functions as a first gate insulating film. As with the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen when heated.
  • silicon oxide with excess oxygen silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies can be used.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • insulator 545 By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. As with insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 be reduced.
  • the film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 545 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed.
  • a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 545 may have a layered structure, similar to the second gate insulating film.
  • problems such as off-current may occur due to thinner gate insulating films. Therefore, by making the insulator that functions as the gate insulating film a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a layered structure that is thermally stable and has a high relative dielectric constant can be achieved.
  • the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in Figures 17A and 17B, but may have a single-layer structure or a stacked structure of three or more layers.
  • the conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.
  • an oxide semiconductor that can be applied to the oxide 530 can be used as the conductor 560a.
  • the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a to make it a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 560b is made of a conductive material containing tungsten, copper, or aluminum as a main component. Moreover, since the conductor 560b also functions as wiring, it is preferable that a conductor with high conductivity is used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resin.
  • silicon oxide and silicon oxynitride are preferred because they are thermally stable.
  • silicon oxide and silicon oxide with voids are preferred because they allow for easy formation of excess oxygen regions in a later process.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released when heated, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.
  • the opening of insulator 580 is formed so as to overlap the region between conductor 542a and conductor 542b. This allows conductor 560 to be formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.
  • the conductor 560 When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the thickness of the conductor 560 is increased in order to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the process.
  • the insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545.
  • an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.
  • the insulator 574 may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc.
  • Aluminum oxide in particular, has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.
  • an insulator 581 that functions as an interlayer film on the insulator 574.
  • the concentration of impurities such as water or hydrogen in the insulator 581 is reduced.
  • conductors 540a and 540b are arranged in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are arranged facing each other with conductor 560 in between. Conductors 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.
  • Insulator 582 is provided on insulator 581. It is preferable that insulator 582 is made of a material that has barrier properties against oxygen, hydrogen, and the like. Therefore, the same material as insulator 514 can be used for insulator 582. For example, it is preferable that insulator 582 is made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
  • Aluminum oxide in particular, has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the insulator 586 can be made of the same material as the insulator 320. Furthermore, by using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance that occurs between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.
  • conductors 546 and 548 are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.
  • the conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550.
  • the conductor 546 and the conductor 548 can be formed using the same material as the conductor 328 and the conductor 330.
  • an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening.
  • an insulator with high barrier properties against hydrogen or water By wrapping the transistor 500 in the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.
  • a plurality of transistors 500 may be wrapped together in an insulator with high barrier properties against hydrogen or water.
  • the insulator with high barrier properties against hydrogen or water for example, a material similar to the insulator 522 or the insulator 514 may be used.
  • the transistor that can be used in the present invention is not limited to the transistor 500 shown in Figures 17A and 17B.
  • a transistor 500 having the structure shown in Figure 17C may be used.
  • the transistor 500 shown in Figure 17C differs from the transistor shown in Figures 17A and 17B in that an insulator 555 is used and that the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) have a layered structure.
  • Conductor 542a has a layered structure of conductor 542a1 and conductor 542a2 on conductor 542a
  • conductor 542b has a layered structure of conductor 542b1 and conductor 542b2 on conductor 542b1.
  • Conductor 542a1 and conductor 542b1 in contact with oxide 530b are preferably conductors that are difficult to oxidize, such as metal nitrides. This can prevent conductor 542a and conductor 542b from being excessively oxidized by oxygen contained in oxide 530b.
  • Conductors 542a2 and conductor 542b2 are preferably conductors such as metal layers that are more conductive than conductor 542a1 and conductor 542b1.
  • conductor 542a and conductor 542b to function as highly conductive wiring or electrodes.
  • a semiconductor device can be provided in which conductors 542a and 542b, which function as wiring or electrodes, are provided in contact with the upper surface of oxide 530, which functions as an active layer.
  • a metal nitride for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum.
  • a nitride containing tantalum is particularly preferable.
  • ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.
  • conductor 542a2 and conductor 542b2 have higher conductivity than conductor 542a1 and conductor 542b1.
  • the film thickness of conductor 542a2 and conductor 542b2 is greater than the film thickness of conductor 542a1 and conductor 542b1.
  • Conductors 542a2 and conductor 542b2 may be conductors that can be used for conductor 560b.
  • tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.
  • the distance between conductor 542a1 and conductor 542b1 is smaller than the distance between conductor 542a2 and conductor 542b2.
  • the insulator 555 is preferably an insulator that is difficult to oxidize, such as a nitride.
  • the insulator 555 is formed in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2, and has the function of protecting the conductor 542a2 and the conductor 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, it is preferable that the insulator 555 is an inorganic insulator that is difficult to oxidize.
  • the insulator 555 is in contact with the conductor 542a2 and the conductor 542b2, it is preferable that the insulator 555 is an inorganic insulator that is difficult to oxidize the conductors 542a2 and 542b2. Therefore, it is preferable that the insulator 555 is made of an insulating material that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 555.
  • 17C is formed by forming an opening in the insulator 580 and the insulator 544, forming an insulator 555 in contact with the sidewall of the opening, and then dividing the conductor 542a1 and the conductor 542b1 using a mask.
  • the opening overlaps with the region between the conductor 542a2 and the conductor 542b2.
  • parts of the conductor 542a1 and the conductor 542b1 are formed to protrude into the opening.
  • the insulator 555 contacts the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 within the opening.
  • the insulator 545 contacts the top surface of the oxide 530 in the region between the conductor 542a1 and the conductor 542b1.
  • the conductor 542a1 and the conductor 542b1 After separating the conductor 542a1 and the conductor 542b1, it is preferable to perform heat treatment in an atmosphere containing oxygen before forming the insulator 545. This allows oxygen to be supplied to the oxide 530a and the oxide 530b, thereby reducing oxygen deficiency. Furthermore, since the insulator 555 is formed in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2, excessive oxidation of the conductor 542a2 and the conductor 542b2 can be prevented. As a result, the electrical characteristics and reliability of the transistor can be improved. In addition, the variation in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed.
  • the insulator 524 may be formed in an island shape as shown in FIG. 17C.
  • the insulator 524 may be formed so that the side ends thereof roughly coincide with the oxide 530.
  • the insulator 522 may be in contact with the insulator 516 and the conductor 503.
  • the transistor 500 may be configured without the insulator 520 shown in FIG. 17A and FIG. 17B.
  • FIG. 18A shows an example of a cross-sectional structure of element layer 700[k] that can be applied to element layers 700[1] to 700[4] shown in FIG. 16.
  • FIG. 18B shows an equivalent circuit diagram of FIG. 18A.
  • FIG. 18A shows an example in which two memory cells MC are electrically connected to one bit line BL.
  • transistor M1 is a modified version of transistor 500. Specifically, transistor M1 differs from transistor 500 in that conductor 542a and conductor 542b extend beyond the ends of metal oxide 531 (metal oxide 531a and metal oxide 531b).
  • the memory cell MC shown in FIG. 18A also has a conductor 156 that functions as one terminal of the capacitor C, an insulator 153 that functions as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) that functions as the other terminal of the capacitor C.
  • Conductor 156 is electrically connected to a portion of conductor 542b.
  • Conductor 160 is also electrically connected to wiring PL (not shown in FIG. 18A).
  • Capacitor C is formed in an opening created by removing a portion of insulator 574, insulator 580, and insulator 554. Conductor 156, insulator 580, and insulator 554 are formed along the side of the opening, so it is preferable to form the films using the ALD method, CVD method, or the like.
  • conductor 156 and conductor 160 may be made of a conductor that can be used for conductor 505 or conductor 560.
  • titanium nitride formed using the ALD method may be used for conductor 156.
  • Titanium nitride formed using the ALD method may be used for conductor 160a, and tungsten formed using the CVD method may be used for conductor 160b. Note that if the adhesion of tungsten to insulator 153 is sufficiently high, a single layer film of tungsten formed using the CVD method may be used for conductor 160.
  • the insulator 153 is preferably made of a high-k material (material with a high relative dielectric constant).
  • a high-k material material with a high relative dielectric constant
  • an oxide, oxynitride, oxynitride, or nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium can be used as the high-k insulator.
  • Silicon may also be contained in the oxide, oxynitride, oxynitride, or nitride. Insulating layers made of the above materials can also be stacked.
  • the insulator 153 may be, for example, a three-layered structure of zirconium oxide, aluminum oxide, and zirconium oxide. The three-layered structure of zirconium oxide, aluminum oxide, and zirconium oxide is sometimes called ZAZ.
  • the high dielectric constant material insulator may be aluminum oxide, hafnium oxide, zirconium oxide, oxide having aluminum and hafnium, oxynitride having aluminum and hafnium, oxide having silicon and hafnium, oxynitride having silicon and hafnium, oxide having silicon and zirconium, oxynitride having silicon and zirconium, oxide having hafnium and zirconium, oxynitride having hafnium and zirconium, etc.
  • the insulator 153 can be made thick enough to suppress the off current, and the capacitance of the capacitor C can be sufficiently ensured.
  • a laminated insulating layer made of the above materials it is preferable to use a laminated structure of a high dielectric constant material and a material having a higher dielectric strength than the high dielectric constant material.
  • an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 153.
  • an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.
  • an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • a material that can have ferroelectricity may be used as the insulating layer 153.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • materials that can have ferroelectricity include a material obtained by adding an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide.
  • the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of the element J1 may be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include a material obtained by adding an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1: 1 or close to 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
  • Fig. 19 shows a cross-sectional configuration example when a circuit configuration of a NOSRAM memory cell is used.
  • Fig. 19 is also a modified example of Fig. 16.
  • Fig. 20A shows a cross-sectional structure example of an element layer 700[k].
  • Fig. 20B shows an equivalent circuit diagram of Fig. 20A.
  • the memory cell MC shown in Figures 19 and 20A has transistors M1, M2, and M3 on an insulator 514.
  • a conductor 515 is provided on the insulator 514.
  • the conductor 515 can be formed simultaneously with the conductor 505 using the same material and in the same process.
  • the transistors M2 and M3 shown in Figures 19 and 20A share one island-shaped metal oxide 531.
  • a part of the island-shaped metal oxide 531 functions as a channel formation region for the transistor M2, and another part functions as a channel formation region for the transistor M3.
  • the source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are also shared. Therefore, the area occupied by the transistors is smaller than when the transistors M2 and M3 are provided independently.
  • an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287.
  • an insulator 514 of the element layer 700[k+1] is provided on the insulator 287 and the conductor 161.
  • conductor 515 of element layer 700[k+1] functions as one terminal of capacitor C
  • insulator 514 of element layer 700[k+1] functions as a dielectric of capacitor C
  • conductor 161 functions as the other terminal of capacitor C.
  • the other of the source or drain of transistor M1 is electrically connected to conductor 161 via a contact plug
  • the gate of transistor M2 is electrically connected to conductor 161 via another contact plug.
  • ⁇ DOSRAM Configuration Example 2> 21 shows a cross-sectional example of an element layer including stacked OS transistors that can be applied to a semiconductor device or the like of one embodiment of the present invention, which is different from that in FIG. 16 to FIG. 20A and FIG. 20B , in a semiconductor device 10V shown in FIG. 21 , a capacitor C is provided below a transistor M1 in memory cells MC included in element layers 700[1] to 700[3] shown in FIG.
  • each of the multiple element layers 700 has multiple memory cells MC.
  • a transistor M1 and a capacitor C are illustrated.
  • the interlayer film between the element layer 701 and the element layer 700 is filled with conductors 363a, 363b, and 363c.
  • the insulator 592 described below is filled with conductor 365.
  • the insulator 593, 594, 553, and 595 described below are filled with conductor 366.
  • the insulator 596, 583, 542b, 555, and 597 described below are filled with conductor 367.
  • the conductors 363a, 363b, 363c, 365, 366, and 367 function as vias, contact plugs, or wiring.
  • FIG. 22A is a plan view showing an example of the configuration of a memory cell MC and its periphery included in each of the multiple element layers 700 of the semiconductor device 10V described above.
  • transistor 500A corresponds to transistor M1 in FIG. 21
  • capacitance 600A corresponds to capacitor C in FIG. 21.
  • FIG. 22D is a cross-sectional view of dashed dotted line A1-A2 shown in FIG. 22A.
  • some of the components of transistor M1, such as insulators are omitted.
  • some of the components, such as insulators are also omitted.
  • capacitance 600A has insulator 593, insulator 594, insulator 553, insulator 595, conductor 563, conductor 564, and conductor 542a.
  • the conductor 563 is embedded in the conductor 563.
  • the conductor 563 can be wiring PL extending in the Y direction.
  • insulators 593 and 594 are formed in this order on insulator 592 and conductor 563.
  • An opening is provided in the area of insulator 593 and insulator 594 that overlaps with conductor 563.
  • Conductor 564 is formed on the bottom surface (on conductor 563) and side surface of the opening. In FIG. 22D, conductor 564 is also formed on the top surface of insulator 594.
  • Insulator 553 is formed on insulator 594 and conductor 564.
  • Conductor 542a is formed so as to cover the area of insulator 553 that overlaps with conductor 564.
  • Insulator 595 is formed on conductor 542a and insulator 553.
  • the height of the top surface of insulator 595 and the height of the top surface of conductor 542a are approximately the same. For this reason, it is preferable that the insulator 595 and the conductor 542a are planarized by a planarization process using, for example, a chemical mechanical polishing (CMP) method.
  • CMP chemical mechanical polishing
  • the conductor 564 corresponds to, for example, one of a pair of terminals in the capacitance 600A.
  • the conductor 542a corresponds to, for example, the other of the pair of terminals in the capacitance 600A.
  • the insulator 553 functions as a dielectric sandwiched between a pair of terminals, for example, at a capacitance of 600A.
  • Transistor 500A is provided above conductor 542a and insulator 595 with a capacitance of 600A.
  • Transistor 500A is configured such that the direction of the channel length is not approximately parallel to substrate 311, but is aligned with the side of an opening provided in insulator 583, which will be described later.
  • the transistor 500A has a conductor 542a that functions as one of the source electrode or drain electrode, a conductor 542b that functions as the other of the source electrode or drain electrode, a metal oxide 533, an insulator 555, and a conductor 565 that functions as a gate electrode.
  • FIG. 22A shows an example in which the conductor 542b extends in a direction perpendicular to the conductor 542a and the conductor 565.
  • the conductor 542a also functions as the other of the pair of electrodes of the capacitance 600A.
  • the metal oxide 533 can be made of, for example, a material that can be used for the oxide 530 contained in the transistor 500 described above.
  • the direction in which the conductor 542b extends is the X direction.
  • the direction perpendicular to the X direction and parallel to the top surface of the conductor 563 for example, is the Y direction, and the direction perpendicular to the top surface of the conductor 563 is the Z direction.
  • the definitions of the X direction, Y direction, and Z direction may be the same in the subsequent drawings.
  • the X direction, Y direction, and Z direction may be perpendicular to each other.
  • the X direction may be referred to as the right side or left side
  • the Y direction may be referred to as the upper side or lower side.
  • the right side may be referred to as the X direction, the left side as the -X direction, the upper side as the Y direction, and the lower side as the -Y direction.
  • the conductor 542a functions as one of the source electrode or drain electrode of the transistor 500A.
  • the conductor 542b functions as the other of the source electrode or drain electrode of the transistor 500A.
  • the insulator 555 functions as the gate insulating layer of the transistor 500A.
  • the conductor 565 functions as the gate electrode of the transistor 500A.
  • the entire region of the metal oxide 533 that overlaps with the gate electrode via the gate insulating layer between the source electrode and drain electrode functions as a channel formation region.
  • the metal oxide 533 having a region that functions as a channel formation region is sometimes called a semiconductor layer.
  • the region of the metal oxide 533 that contacts the source electrode functions as a source region, and the region that contacts the drain electrode functions as a drain region.
  • An insulator 596 is provided on the insulator 595 and on the conductor 542a.
  • the insulator 596 can function as an interlayer insulating layer.
  • the interlayer insulating layer here can be a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules).
  • Insulator 583 (insulator 583a and insulator 583b) is provided on insulator 596, and conductor 542b is provided on insulator 583.
  • Insulator 583 can function as an interlayer insulating layer.
  • the interlayer insulating layer here can be an interlayer film for isolating the source electrode and gate electrode at 500A.
  • the insulator 583a is preferably made of, for example, an oxide or an oxynitride.
  • the insulator 583a is preferably made of a film that releases oxygen when heated.
  • the insulator 583a can be made of, for example, silicon oxide or silicon oxynitride.
  • the insulator 583a can supply oxygen to the metal oxide 533 by releasing oxygen.
  • the insulator 583a can supply oxygen to the metal oxide 533 by supplying oxygen from the insulator 583a to the metal oxide 533, particularly to the channel formation region of the metal oxide 533, thereby reducing oxygen vacancies in the metal oxide 533 and hydrogen that has entered the oxygen vacancies.
  • the transistor 500A can be a highly reliable transistor that exhibits good electrical characteristics.
  • the insulator 583b has a region with a higher nitrogen content than the insulator 583a.
  • silicon nitride or silicon nitride oxide can be suitably used for the insulator 583b.
  • the insulator 583b can be a blocking layer that suppresses oxygen from being released from the insulator 583a.
  • the insulating layer 583 may be a single layer.
  • the insulating layer 583 may be a barrier insulating film, typically silicon nitride, that suppresses the diffusion of impurities such as water and hydrogen (for example, one or both of hydrogen atoms and hydrogen molecules).
  • Insulator 596 and insulator 583 have an opening 601 that reaches conductor 542a.
  • Conductor 542b has an opening 603 that reaches opening 601. In other words, opening 603 has an area that overlaps with opening 601.
  • FIG. 22A conductor 542a, conductor 542b, metal oxide 533, conductor 565, opening 601, and opening 603 are shown as components of transistor 500A.
  • FIG. 22B shows a configuration example in which conductor 565 is omitted from the elements shown in FIG. 22A. That is, FIG. 22B shows conductor 542a, conductor 542b, metal oxide 533, opening 601, and opening 603.
  • FIG. 22C shows a configuration example in which metal oxide 533 is further omitted from the elements shown in FIG. 22B. That is, FIG. 22C shows conductor 542a, conductor 542b, opening 601, and opening 603.
  • conductor 542b has an opening 603 in the area where it overlaps with conductor 542a.
  • conductor 542b can be configured to cover the entire outer periphery of opening 601 in a plan view.
  • conductor 542b is preferably not provided inside opening 601. In other words, conductor 542b is preferably not in contact with the side of insulator 583 facing opening 601.
  • FIG. 22A to 22C show an example in which the shape of the openings 601 and 603 is circular in a plan view.
  • the processing accuracy when forming the openings 601 and 603 can be improved, and the openings 601 and 603 can be formed in fine sizes.
  • a circle is not limited to a perfect circle.
  • the planar shapes of the openings 601 and 603 may be elliptical, or may be a shape including a curve. Or, they may be polygonal.
  • the end of the conductor 542b on the opening 603 side coincides with or roughly coincides with the end of the insulator 583 on the opening 601 side. It can also be said that the planar shape of the opening 603 coincides with or roughly coincides with the planar shape of the opening 601.
  • the end of the conductor 542b on the opening 603 side refers to the bottom end of the conductor 542b on the opening 603 side.
  • the bottom surface of the conductor 542b refers to the surface on the insulator 583 side.
  • the end of the insulator 583 on the opening 601 side refers to the top end of the insulator 583 on the opening 601 side.
  • the top surface of the insulator 583 refers to the surface on the conductor 542b side.
  • the planar shape of the opening 603 refers to the planar shape of the bottom end of the conductor 542b on the opening 603 side.
  • the planar shape of the opening 601 refers to the planar shape of the top end of the insulator 583 on the opening 601 side.
  • ends that match or roughly match can also be said to mean that the ends are aligned or roughly aligned.
  • ends are aligned or roughly aligned, and when the planar shapes are aligned or roughly aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or partially using the same mask pattern.
  • the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, in which case it is also said that the ends are roughly aligned or the planar shapes are roughly aligned.
  • the opening 601 can be formed, for example, by using the resist mask used to form the opening 603. Specifically, first, an insulator 596 is formed on the conductor 542a and on the insulator 595, an insulator 583 is formed on the insulator 596, a conductive film that will become the conductor 542b on the insulator 583, and a resist mask is formed on the conductive film. Then, an opening 603 is formed in the conductive film using the resist mask, and then an opening 601 is formed in the insulator 596 and the insulator 583 using the resist mask, so that the edge of the opening 601 and the edge of the opening 603 can be aligned or approximately aligned. Such a configuration can simplify the process.
  • the metal oxide 533 is provided so as to cover the openings 601 and 603 and have a region located inside the openings 601 and 603.
  • the metal oxide 533 has a shape that follows the shapes of the upper surface and side surfaces of the conductor 542b, the side surfaces of the insulator 583, the side surfaces of the insulator 596, and the upper surface of the conductor 542a.
  • the metal oxide 533 has a region that contacts, for example, the upper surface and side surfaces of the conductor 542b, the side surfaces of the insulator 583, and the upper surface of the conductor 542a.
  • metal oxide 533 covers the end of conductor 542b on the opening 603 side.
  • FIG. 22D shows a configuration in which the end of metal oxide 533 is located on conductor 542b. It can also be said that the end of metal oxide 533 is in contact with the upper surface of conductor 542b.
  • the metal oxide 533 has a single-layer structure in FIG. 22D, one embodiment of the present invention is not limited to this.
  • the metal oxide 533 may have a stacked structure of two or more layers.
  • the insulator 555 which functions as a gate insulating layer of the transistor 500A, is provided so as to cover the openings 601 and 603 and have a region located inside the openings 601 and 603.
  • the insulator 555 is provided on the metal oxide 533, the conductor 542b, and the insulator 583.
  • the insulator 555 can have a region in contact with the top and side surfaces of the metal oxide 533, the top and side surfaces of the conductor 542b, the top surface of the insulator 583, and the top surface of the insulator 596.
  • the insulator 555 has a shape that follows the shapes of the top surface of the insulator 596, the top surface of the insulator 583, the top surface and side surfaces of the conductor 542b, and the top and side surfaces of the metal oxide 533.
  • the conductor 565 which functions as the gate electrode of the transistor 500A, is provided on the insulator 555 and can have a region in contact with the top surface of the insulator 555.
  • the conductor 565 has a region that overlaps with the metal oxide 533 via the insulator 555.
  • the conductor 565 has a shape that follows the shape of the top surface of the insulator 555.
  • conductor 565 in openings 601 and 603, conductor 565 has an area where it overlaps with metal oxide 533 via insulator 555.
  • conductor 565 has an area where it overlaps with conductor 542a and conductor 542b via insulator 555 and metal oxide 533.
  • Conductor 565 covers the entire metal oxide 533.
  • Transistor 500A is a so-called top-gate type transistor that has a gate electrode above metal oxide 533. Furthermore, since the bottom surface of metal oxide 533 has an area in contact with the source electrode and drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor.
  • TGBC Top Gate Bottom Contact
  • Transistor 500A is a transistor in which at least a portion of a semiconductor layer including a channel formation region is provided along a side surface of an insulating layer in an opening formed in the insulating layer. In this specification and the like, such a transistor may be referred to as a vertical transistor.
  • the source electrode and drain electrode are located at different heights, so current flows in the height direction (vertical direction) in the channel formation region of the semiconductor layer.
  • the channel length direction has a height direction (vertical direction) component. Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, or a vertical channel transistor.
  • VFET Vertical Field Effect Transistor
  • the source region, the channel formation region, and the drain region can be at least partially overlapped when viewed from above, so the area occupied (also called the footprint) can be made small.
  • the area occupied also called the footprint
  • the on-resistance can be made small (the on-current can be made large).
  • Figure 23A is an enlarged plan view showing an example of the configuration of transistor 500A shown in Figure 22A and its surroundings.
  • Figure 23B is an enlarged cross-sectional view showing an example of the configuration of transistor 500A shown in Figure 22D and its surroundings.
  • the region in contact with the conductor 542a functions as one of the source region and the drain region
  • the region in contact with the conductor 542b functions as the other of the source region and the drain region
  • the region between the source region and the drain region functions as a channel formation region
  • the channel length of transistor 500A is the distance between the source region and the drain region.
  • the channel length L500 of transistor 500A is indicated by a dashed double-headed arrow.
  • channel length L500 is the distance between the end of the region where metal oxide 533 and conductor 542a contact, and the end of the region where metal oxide 533 and conductor 542b contact.
  • the channel length L500 of the transistor 500A corresponds to the length of the side of the insulator 583 on the opening 601 side when viewed from the XZ plane.
  • the channel length L500 is determined by the film thickness T583 of the edge 596 and the insulator 583, and is not affected by the performance of the exposure device used to fabricate the transistor. Therefore, the channel length L500 can be made smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • the channel length L500 is preferably 0.0010 ⁇ m or more, that is, 1 nm or more, and is preferably 0.010 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.050 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.15 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, and even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m.
  • the thickness is 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably, 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably, 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably, 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably, 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably, 0.40 ⁇ m or more and less than 1.0 ⁇ m, even more preferably, 0.50 ⁇ m or more and less than 1.0 ⁇ m.
  • the thickness T583 of the insulator 583 is indicated by a dashed line with a double-headed arrow.
  • the memory cell MC can be miniaturized. This allows the memory density to be increased, resulting in a semiconductor device with a large memory capacity.
  • the on-current of the transistor 500A can be increased, allowing the memory cell MC to be driven at high speed.
  • the channel length L500 can be controlled by adjusting the film thickness T583 of the insulator 596 and the insulator 583.
  • the film thickness T583 of the insulator 596 and the insulator 583 is preferably 0.0010 ⁇ m or more, i.e., 1 nm or more, and is preferably 0.010 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.050 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.15 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, and even more preferably 0.20 ⁇ m or more and less than 2.
  • 0.20 ⁇ m or more and less than 2.0 ⁇ m is even more preferable
  • 0.20 ⁇ m or more and less than 1.5 ⁇ m is even more preferable
  • 0.30 ⁇ m or more and less than 1.5 ⁇ m is even more preferable
  • 0.30 ⁇ m or more and 1.2 ⁇ m or less is even more preferable
  • 0.40 ⁇ m or more and 1.2 ⁇ m or less is even more preferable
  • 0.40 ⁇ m or more and 1.0 ⁇ m or less is even more preferable
  • 0.50 ⁇ m or more and 1.0 ⁇ m or less is even more preferable.
  • FIG. 23B shows a configuration in which the shape of the side of insulator 596 and insulator 583 on the opening 601 side is straight in cross section, but this is not a limitation of one embodiment of the present invention.
  • the shape of the side of insulator 596 and insulator 583 on the opening 601 side may be curved, and the side may have both straight and curved regions.
  • the channel width of the transistor 500A is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction.
  • the channel width is the width of the region where the metal oxide 533 and the conductor 542a contact, or the width of the region where the metal oxide 533 and the conductor 542b contact, in a direction perpendicular to the channel length direction.
  • the channel width of the transistor 500A is described as the width of the region where the metal oxide 533 and the conductor 542b contact, in a direction perpendicular to the channel length direction.
  • the channel width W500 of the transistor 500A is indicated by a solid double-headed arrow.
  • the channel width W500 is the length of the bottom end of the conductor 542b on the opening 603 side in a plan view.
  • the channel width W500 is determined by the planar shape of the opening 603.
  • the width D500 of the opening 603 is indicated by a two-dot dashed line with a double arrow.
  • the width D500 indicates the short side of the smallest rectangle that circumscribes the opening 603 in a planar view.
  • the width D500 of the opening 603 is equal to or greater than the limit resolution of the exposure device.
  • the width D500 is, for example, preferably 0.20 ⁇ m or more and less than 5.0 ⁇ m, more preferably 0.20 ⁇ m or more and less than 4.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 4.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and
  • the width D500 corresponds to the diameter of the opening 603
  • the channel width W500 can be made equal to the length of the outer periphery of the opening 603 in a planar view, and can be calculated as "D500 x ⁇ ".
  • the application of the transistor 500A to the element layer 700 can increase the memory density, and therefore a semiconductor device having a memory portion with a high memory capacity can be provided.
  • the operation of the transistor 500A is fast, the application of the transistor 500A to a semiconductor device can provide a semiconductor device with a high driving speed.
  • the electrical characteristics of the transistor 500A are stable, the application of the transistor 500A to a semiconductor device can provide a highly reliable semiconductor device.
  • the application of the transistor 500A to a semiconductor device can provide a semiconductor device with low power consumption.
  • the transistor 500A can also be used, for example, as a transistor in a circuit other than the memory cell MC. It can also be used in combination with another transistor configuration, such as the semiconductor device 10V_2 shown in FIG. 24, in which an element layer 800 having the transistor 500 described in FIG. 17 is used. This configuration allows transistors with different transistor characteristics to be stacked, allowing a circuit layout according to the switching characteristics.
  • Embodiment 3 electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described.
  • the electronic components, electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • FIG. 25A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted.
  • the electronic component 709 shown in FIG. 25A has a semiconductor device 710 in a mold 711. In FIG. 25A, some parts are omitted in order to show the inside of the electronic component 709.
  • the electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are monolithically stacked.
  • OS transistors By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to configure the memory layer 716 as a monolithic stack compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in the monolithic stack configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • the interposer that implements the HBM requires fine, high-density wiring. For this reason, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • silicon interposers Furthermore, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be used that combines a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 25B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • FIG. 26A a perspective view of an electronic device 6500 is shown in FIG. 26A.
  • the electronic device 6500 shown in FIG. 26A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a semiconductor device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 26B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 has a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 has, for example, one or more selected from a CPU, a GPU, and a semiconductor device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616 is preferable because power consumption can be reduced.
  • Fig. 26C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 26C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • Computer 5620 can be configured, for example, as shown in the perspective view of FIG. 26D.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to motherboard 5630.
  • PC card 5621 shown in FIG. 26E is an example of a processing board equipped with a CPU, a GPU, a semiconductor device, and the like.
  • PC card 5621 has board 5622.
  • Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629.
  • FIG. 26E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for those semiconductor devices, please refer to the explanation of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5628 include a semiconductor device.
  • the electronic component 709 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.
  • the semiconductor device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • FIG. 27 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • FIG. 27 shows a planet 6804 in outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the power required for the operation of the satellite 6800 is generated.
  • the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated.
  • the solar panel may be called a solar cell module.
  • Satellite 6800 can generate a signal.
  • the signal is transmitted via antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a semiconductor device.
  • a semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor. For example, by configuring it to have a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited to this.
  • a semiconductor device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term management of data, such as by ensuring the immutability of the data.
  • it is necessary to increase the size of the building for example, by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • FIG. 28 shows a storage system that can be applied to a data center.
  • the storage system 7000 shown in FIG. 28 has multiple servers 7001sb as hosts 7001. It also has multiple semiconductor devices 7003md as storage 7003.
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 and a storage control circuit 7002.
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • cache memory is usually provided within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring it to hold a potential according to the data, it is possible to reduce the frequency of refreshing and lower power consumption.
  • configuring the memory cell array in a stacked structure it is possible to reduce the size.
  • the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • the content described in one embodiment can be applied to, combined with, or replaced with another content described in that embodiment (or even a part of the content) and/or the content described in one or more other embodiments (or even a part of the content).
  • a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and/or with one or more figures (or a part of it) described in another embodiment to form even more figures.
  • the components in the block diagrams are classified by function and shown as independent blocks.
  • it is difficult to separate components by function and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits.
  • the blocks in the block diagrams are not limited to the components described in the specification and may be rephrased appropriately depending on the situation.
  • the terms "one of the source or drain” (or first electrode or first terminal) and “the other of the source or drain” (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.
  • electrode and “wiring” used in this specification and elsewhere do not limit the functionality of these components.
  • an “electrode” may be used as part of a “wiring”, and vice versa.
  • the terms “electrode” and “wiring” also include cases where multiple “electrodes” or “wirings” are formed as a single unit.
  • Voltage refers to the potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.
  • film and “layer” may be interchangeable depending on the circumstances.
  • conductive layer may be changed to the term “conductive film.”
  • insulating film may be changed to the term “insulating layer.”
  • a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.
  • a switch refers to a device that has the function of selecting and switching the path through which a current flows.
  • the channel length of a planar transistor refers to, for example, the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate overlap in a top view of the transistor, or in the region where the channel is formed.
  • the channel width refers to, for example, the length of the area where the semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the part where the source and drain face each other in the area where the channel is formed.
  • a node can be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, wiring, etc. can be referred to as a node.
  • a and B are connected means that A and B are electrically connected.
  • a and B are electrically connected means a connection that allows transmission of an electrical signal between A and B when an object (referring to an element such as a switch, transistor element, or diode, or a circuit including said element and wiring) exists between A and B.
  • a and B being electrically connected includes the case where A and B are directly connected.
  • a and B being directly connected means a connection that allows transmission of an electrical signal between A and B via wiring (or electrodes) between A and B, without going through the object.
  • a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015207763A (ja) * 2014-04-11 2015-11-19 株式会社半導体エネルギー研究所 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2019047006A (ja) * 2017-09-05 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、電子機器
WO2022029541A1 (ja) * 2020-08-03 2022-02-10 株式会社半導体エネルギー研究所 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015207763A (ja) * 2014-04-11 2015-11-19 株式会社半導体エネルギー研究所 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2019047006A (ja) * 2017-09-05 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、電子機器
WO2022029541A1 (ja) * 2020-08-03 2022-02-10 株式会社半導体エネルギー研究所 半導体装置

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