WO2024161946A1 - 積層セラミックコンデンサ - Google Patents
積層セラミックコンデンサ Download PDFInfo
- Publication number
- WO2024161946A1 WO2024161946A1 PCT/JP2024/000593 JP2024000593W WO2024161946A1 WO 2024161946 A1 WO2024161946 A1 WO 2024161946A1 JP 2024000593 W JP2024000593 W JP 2024000593W WO 2024161946 A1 WO2024161946 A1 WO 2024161946A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ceramic capacitor
- multilayer ceramic
- pores
- section
- porous metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
Definitions
- the present invention relates to a multilayer ceramic capacitor.
- a multilayer ceramic capacitor in which dielectric layers and internal electrodes are alternately stacked, the internal electrodes are pulled out every other layer to a pair of opposing pull-out surfaces parallel to the stacking direction, the pulled-out internal electrodes are connected to each other by external electrodes, and the external electrodes are formed so as to wrap around from the pull-out surfaces to the surface of a ceramic cover layer arranged at the end in the stacking direction (see, for example, Patent Document 1).
- a multilayer ceramic capacitor having the above-mentioned structure is mounted on a circuit board by connecting the portion of the external electrode that wraps around the surface of the cover layer to the circuit board as a terminal portion.
- bending of the circuit board causes stress to concentrate near the end of the terminal portion located on the opposite side to the pull-out surface.
- a multilayer ceramic capacitor having the above-mentioned structure is required to suppress peeling of the external electrode from the cover layer, cracks occurring in the cover layer, and short circuit failures caused by cracks reaching the internal electrodes.
- Patent Documents 1 and 2 each disclose that the external electrodes contain ceramics such as glass, with the content being specific depending on the position.
- Patent Document 3 also discloses that the cover layer contains multiple pores oriented in a direction perpendicular to the lamination direction in order to reduce stress and distortion that occurs in the multilayer ceramic capacitor while achieving high reliability.
- Patent Document 4 discloses that, when manufacturing a multilayer ceramic capacitor, cracks caused by differences in the firing shrinkage behavior between the external electrode paste and the ceramic laminate are suppressed, while the amount of co-material added to the external electrode paste is reduced to reduce adverse effects on the plating process. This means using a co-material with a smaller thermal expansion coefficient than the main component of the cover layer for the external electrode.
- the present invention aims to provide a multilayer ceramic capacitor that, when mounted on a circuit board, can reduce the concentration of stress caused by the flexural deformation of the circuit board.
- the inventors conducted various studies to solve the above-mentioned problems and discovered that by incorporating multiple voids (pores) in the terminal portion of the external electrode, the external electrode becomes more susceptible to localized deformation due to stress, and stress concentration in specific locations can be alleviated, which led to the completion of the present invention.
- the first aspect of the present invention for solving the above problem is a multilayer ceramic capacitor comprising a capacitance section in which dielectric layers made of dielectric ceramic and internal electrodes mainly made of metal are alternately laminated, and a protective section including cover layers made of dielectric ceramic arranged at both ends of the capacitance section in the lamination direction and side margin layers made of dielectric ceramic arranged at both ends in the direction perpendicular to the lamination direction of the capacitance section, the multilayer chip having a pull-out surface from which the internal electrodes are pulled out, and an external electrode that electrically connects the internal electrodes pulled out on the pull-out surface of the multilayer chip, has terminal parts formed on the surface of the protective part, and the terminal parts are in contact with the protective part and have a porous metal part containing nickel as a main component and including a plurality of flat pores oriented along the surface of the terminal part.
- a second aspect of the present invention for solving the above problem includes preparing an external electrode paste containing metal particles mainly composed of nickel and boron nitride particles, preparing a powder of a dielectric ceramic composition, mixing the powder of the dielectric ceramic composition with a binder and forming it into a sheet to obtain a green sheet, forming an internal electrode pattern containing a metal on the green sheet, stacking a predetermined number of the green sheets on which the internal pattern has been formed, arranging green sheets for cover layers at both ends in the stacking direction, and then pressing the stacked sheets together to obtain a green laminate, dicing the green laminate into individual pieces, and forming a drawing surface from which the internal electrode pattern is drawn out.
- the method for manufacturing a multilayer ceramic capacitor includes obtaining a pre-fired laminated chip having a green sheet for a protective portion including a green sheet for a side margin layer perpendicular to the drawing surface and the green sheet for the cover layer, and the green sheet for the cover layer; removing the binder from the pre-fired laminated chip; forming a pair of external electrode patterns by applying the external electrode paste to the surface of the green sheet for the protective portion of the pre-fired laminated chip after the binder removal so as to be spaced apart from each other; and firing the pre-fired laminated chip with the external electrode patterns formed thereon to obtain a sintered body.
- the present invention provides a multilayer ceramic capacitor that, when mounted on a circuit board, can reduce the concentration of stress caused by the flexural deformation of the circuit board.
- FIG. 1 is a schematic diagram (longitudinal cross-sectional view) illustrating a structure of a multilayer ceramic capacitor according to a first embodiment of the present invention.
- 1 is a schematic diagram (width direction cross-sectional view) illustrating a structure of a multilayer ceramic capacitor according to a first embodiment of the present invention.
- 4 is a schematic diagram showing the state in which pores are oriented along the surface of a terminal portion, and the major and minor axes of the pores.
- FIG. FIG. 2 is a schematic diagram (longitudinal cross-sectional view) illustrating a structure of a multilayer ceramic capacitor according to a first modified example of the first embodiment.
- FIG. 4 is a schematic diagram (longitudinal cross-sectional view) illustrating a structure of a multilayer ceramic capacitor according to a second modified example of the first embodiment.
- FIG. 11 is a schematic diagram (longitudinal cross-sectional view) illustrating a structure of a multilayer ceramic capacitor according to a third modified example of the first embodiment.
- FIG. 1 shows an embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention as a first embodiment.
- the multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and has a pair of faces perpendicular to three mutually perpendicular axes, i.e., an L axis in the length direction, a W axis in the width direction, and a T axis in the height direction.
- the rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, and may have any shape that is recognized as a rectangular parallelepiped when the overall shape is observed.
- the length (L) dimension, width (W) dimension, and height (T) dimension of the ceramic capacitor 100 can each independently take any value, and the magnitude relationship between them is not limited.
- the relationship may be (dimension in L direction) > (dimension in W direction) ⁇ (dimension in T direction), or the relationship may be (dimension in W direction) > (dimension in L direction), or the relationship may be (dimension in T direction) > (dimension in W direction).
- the multilayer ceramic capacitor 100 includes a laminated chip 30 in which dielectric layers 10 made of dielectric ceramic and internal electrodes 20 mainly made of metal are alternately laminated in the T direction, as shown in the cross-sectional views of FIG. 1 (LT cross section) and FIG. 2 (WT cross section).
- the laminated chip 30 includes cover layers 50 made of dielectric ceramic at both ends in the lamination direction (T direction).
- the laminated chip 30 also has a pair of pull-out surfaces 40a and 40b that face each other in the length direction (L direction) and from which the internal electrodes 20 are pulled out.
- the laminated chip 30 has a pull-out surface 40a from which the internal electrodes 20a are pulled out in the L direction, and a pull-out surface 40b from which the internal electrodes 20b are pulled out in the L direction.
- the laminated chip 30 includes a side margin layer 60 on a pair of side surfaces that face each other in the W direction, i.e., on the pull-out surfaces 40a and 40b, and on the side surfaces perpendicular to the respective cover layers 50.
- the multilayer ceramic capacitor 100 according to the first embodiment includes a pair of external electrodes 70a and 70b that electrically connect the internal electrodes drawn out on the drawing surfaces 40a and 40b of the multilayer chip 30 and form terminal portions 71a and 71b, respectively, on one surface of the cover layer 50.
- the terminal portions 71a and 71b are formed on the surface of the cover layer 50, but in the multilayer ceramic capacitor according to the first side, the terminal portions 71a and 71b may be formed on the surface of the side margin layer 60.
- the dielectric layer 10 is formed of a dielectric ceramic.
- the composition of the dielectric ceramic is not particularly limited and may be appropriately selected according to the characteristics required for the multilayer ceramic capacitor.
- a preferable composition of the dielectric ceramic is, for example, one that contains barium titanate (BaTiO 3 ) as a main component.
- the dielectric layer 10 may contain the following additive elements. Examples of the additive elements include at least one selected from Mo, Nb, Ta, W, Mg, Mn, V, Cr, and rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), as well as Co, Ni, Li, B, Na, K, and Si.
- the additive elements may be contained as simple elements, or may be contained in the form of compounds such as oxides, nitrides, and carbides.
- the additive elements may exist in a state of solid solution in the main component barium titanate, or may form a different phase with the elements constituting the main component or other additive elements.
- the internal electrode 20 is mainly composed of a metal.
- the type of metal is not particularly limited, but it is preferable to use a metal having nickel (Ni) as the main component element because it can be fired simultaneously with the dielectric layer 10 and is inexpensive.
- Ni nickel
- the term "main component element" in this specification means the element having the largest content expressed in atomic percentage (atomic %).
- the internal electrode 20 may contain dielectric powder having a composition similar to that of the dielectric ceramic that constitutes the dielectric layer 10, or glass components.
- the cover layer 50 and the side margin layer 60 function as a protective portion that protects the dielectric layer 10 and the internal electrodes 20 .
- the materials of the cover layer 50 and the side margin layer 60 are not limited as long as they have high electrical insulation and low permeability to deterioration factors such as moisture. From the standpoint of making the shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 uniform and mitigating internal stress within the multilayer ceramic capacitor 100, it is preferable that the materials of the cover layer 50 and the side margin layer 60 are the same as the dielectric ceramic that forms the dielectric layer 10.
- the external electrode 70a electrically connects the internal electrodes 20a drawn onto the drawing surface 40a of the laminated chip 30, and forms a terminal portion 71a on the surface of one of the cover layers 50.
- the external electrode 70b electrically connects the internal electrodes 20b drawn onto the drawing surface 40b of the laminated chip 30, and forms a terminal portion 71b on the surface of the cover layer on which the terminal portion 71a is formed, with a predetermined distance from the terminal portion 71a.
- the external electrodes 70a and 70b may be formed so as to wrap around from the drawing surfaces 40a and 40b to the cover layer 50 and the side margin layer 60 on which the terminal portions 71a and 71b are not formed, respectively.
- the terminal portions 71a and 71b each have a porous metal portion 72a and 72b that is in contact with the cover layer 50, has nickel as its main component element, and includes a plurality of flat pores p oriented along the surface of the terminal portions 71a and 71b.
- the porous metal portions 72a and 72b have a low Young's modulus due to the presence of a plurality of pores p, and are easily deformed in response to stress received from a circuit board when mounted on the board.
- the stress applied to the interface between the terminal portions 71a and 71b and the cover layer 50, and to the cover layer 50 can be alleviated, thereby preventing the terminal portions 71a and 71b from peeling off and the occurrence of cracks in the cover layer 50.
- the arrangement and shape of the multiple pores p are flat and oriented along the surfaces of the terminal portions 71a and 71b, so that the degree of decrease in Young's modulus in the thickness direction (T direction) can be suppressed compared to the in-plane direction (LW in-plane direction), and the change in mounting height of the multilayer ceramic capacitor 100 caused by deformation in the T direction of the porous metal portions 72a and 72b that occurs when stress is relieved can be suppressed.
- porous metal parts 72a and 72b are formed over the entire portions of the external electrodes 70a and 70b that contact the multilayer chip 30, which makes it possible to suppress the occurrence of cracks due to thermal stress during firing.
- the present invention is not limited to this form, and as long as the porous metal parts 72a and 72b are formed at the locations where the terminal parts 71a and 71b contact the cover layer 50, the porous metal parts 72a and 72b do not have to be formed in the portions that contact the pull-out surfaces 40a and 40b.
- oriented along the surface of the terminal portion refers to a state in which, when the multilayer ceramic capacitor 100 is cut along any plane perpendicular to the drawing faces 40a and 40b and the porous metal portions 72a and 72b are observed under a microscope as shown in Fig. 3, of the pores p observed in the field of view, the angle ⁇ between the major axis lp , which is the maximum distance between two points located on the surface, and the surface s t of the terminal portion is 0° or more and 15° or less, and the percentage of the percentage of the number of pores p observed in the field of view is 30% or more.
- the percentage of the number of pores p observed in the field of view is preferably 50% or more, and more preferably 70% or more.
- a "flat pore” means a pore p whose major axis lp is 1.5 times or more larger than its minor axis wp , which is the maximum dimension in the direction perpendicular to the major axis lp, when observed in the porous metal portions 72a and 72b described above.
- the average value of the major axis lp of the pores p is preferably 0.5 ⁇ m or more and 6.0 ⁇ m or less.
- the average value of the major axis lp of the pores p is 0.5 ⁇ m or more, the above-mentioned stress relaxation effect becomes remarkable.
- the average value of the major axis lp of the pores p is 6.0 ⁇ m or less, the mechanical strength and conductivity of the terminals 71a and 71b can be maintained. From the viewpoint of achieving a more excellent stress relaxation effect while ensuring sufficient mechanical strength and conductivity, it is more preferable that the average value of the major axis lp of the pores p is 1.0 ⁇ m or more and 3.0 ⁇ m or less.
- the average value of the major axis lp of the pores p is determined by measuring the major axis lp of 10 or more pores p selected arbitrarily in the above-mentioned microscopic observation of the porous metal portions 72a and 72b, and calculating the average value.
- 10 or more pores p are observed in the field of view of the microscope, it is preferable to calculate the average value of the major axis lp of all pores p observed in the field of view in order to reduce bias in the data when selecting pores p.
- the porous metal parts 72a and 72b may have a region 720 containing boron oxide around the pores p.
- the region 720 containing boron oxide in the porous metal parts 72a and 72b has increased strength due to improved sintering properties. Therefore, when boron oxide is contained around the pores p, the strength of this region is increased, and the reduction in the breaking strength of the external electrode due to the presence of the pores p can be suppressed.
- porous metal portions 72a and 72b have a region 720 containing boron oxide around the pores p can be confirmed, for example, by a transmission electron microscope equipped with an energy dispersive X-ray spectrometer (EDS) or a wavelength dispersive X-ray spectrometer (WDS).
- EDS energy dispersive X-ray spectrometer
- WDS wavelength dispersive X-ray spectrometer
- the area percentage of the pores p in the cross section parallel to the lamination direction of the porous metal parts 72a and 72b is preferably 0.2% or more and 5.0% or less.
- the area percentage is 0.2% or more, the above-mentioned stress relaxation effect becomes significant.
- the area percentage is 5.0% or less, the mechanical strength and conductivity of the terminal parts 71a and 71b can be maintained.
- the area percentage is preferably 0.5% or more and 2.0% or less. It is preferable that the pores p with such an area percentage are independent and do not have any connection with each other. In addition, it is preferable that the pores p are closed pores inside the porous metal parts 72a and 72b.
- the area percentage is calculated as a percentage of the total area of pores p observed in the field of view in microscopic observation of the porous metal parts 72a and 72b described above, relative to the area of the field of view.
- a method can be used in which the microscope image is binarized at an appropriate threshold value using image processing software, and then the area of the region corresponding to the pores p is automatically calculated.
- the thickness of the porous metal parts 72a and 72b i.e., the dimension in the T direction, is preferably 0.5 ⁇ m or more and 30 ⁇ m or less.
- the thickness of the porous metal parts 72a and 72b is 0.5 ⁇ m or more, the above-mentioned stress relaxation effect becomes significant.
- the thickness of the porous metal parts 72a and 72b is 30 ⁇ m or less, the multilayer ceramic capacitor 100 can be made smaller. From the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while achieving a better stress relaxation effect, it is more preferable that the thickness of the porous metal parts 72a and 72b is 0.7 ⁇ m or more and 8 ⁇ m or less.
- the porous metal parts 72a and 72b contain nickel (Ni) as the main component element.
- Ni nickel
- they can be fired simultaneously with the laminated chip 30, thereby obtaining a structure with multiple pores p inside.
- the material of the parts of the external electrodes 70a and 70b other than the porous metal parts 72a and 72b is not limited as long as it is conductive. Examples of materials include, in addition to Ni, metals such as copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys containing any of these as the main component element, and conductive resins.
- the external electrodes 70a and 70b may be made of one or more of these materials other than the terminal parts 71a and 71b.
- the external electrodes 70a and 70b may also have a laminated structure in which the terminal parts 71a and 71b have one or more layers selected from these materials formed on the surfaces of the porous metal parts 72a and 72b.
- the external electrodes 70a and 70b have a laminated structure in which a Cu layer 73, a Ni layer 74, and a Sn layer 75 are formed in this order on the surfaces of the porous metal portions 72a and 72b.
- An example of a first modified example of the first embodiment is one in which the porous metal parts 72a and 72b have inner layers 721a and 721b located on the stacked chip side, and outer layers 722a and 722b located on the opposite side of the stacked chip from the inner layers 721a and 721b, respectively, as shown in Figure 4, and the area percentages of pores p in a cross section parallel to the stacking direction are different between the inner layer 721a and the outer layer 722a, and between the inner layer 721b and the outer layer 722b.
- the multilayer ceramic capacitor according to the first modification may satisfy R1>R2, where R1 is the area percentage of the pores p in a cross section parallel to the lamination direction of the inner layers 721a and 721b, and R2 is the area percentage of the pores p in a cross section parallel to the lamination direction of the outer layers 722a and 722b .
- R1 and R2 makes the Young's modulus of the inner layers 721a and 721b closer to that of the cover layer 50 in contact therewith, and can suppress the occurrence of cracks due to thermal stress during firing.
- the R 1 and R 2 may satisfy R 2 > R 1.
- R 1 and R 2 have such a relationship, the thermal conductivity of the outer layers 722a and 722b is reduced, and heat from the outside is less likely to be transmitted to the inside, improving the heat resistance when soldering to a circuit board.
- the thermal expansion coefficient decreases stepwise in the order of (Cu layer 73) > (outer layers 722a and 722b) > (inner layers 721a and 721b) > (cover layer 50). Therefore, there is also an advantage that the stress from the outside is easily relaxed and cracks are less likely to occur.
- the porous metal portions 72a and 72b are not formed at the portions where the external electrodes 70a and 70b contact the lead-out surfaces 40a and 40b, respectively. Since the external electrodes 70a and 70b do not include pores at the contact points with the lead-out surfaces 40a and 40b, respectively, a sufficient contact area with the internal electrodes 20a and 20b led out to the lead-out surfaces 40a and 40b can be ensured, and a multilayer ceramic capacitor with excellent electrical properties can be obtained.
- the cover layer 50 having terminals 71a and 72b formed on its surface includes a plurality of flat pores p oriented along its surface.
- the cover layer 50 in contact with the terminals 71a and 72b also includes pores p, which reduces the Young's modulus of the cover layer 50 and further reduces the stress applied to the interfaces between the terminals 71a and 71b and the cover layer 50, and to the cover layer 50.
- the terminal portions 71a and 71b are formed on the surface of the cover layer 50, but in the multilayer ceramic capacitors according to these modifications, the terminal portions 71a and 71b may be formed on the surface of the side margin layer 60.
- a method for manufacturing a multilayer ceramic capacitor according to a second aspect of the present invention includes the steps of preparing an external electrode paste containing metal particles mainly composed of nickel and boron nitride particles, preparing a powder of a dielectric ceramic composition, mixing the powder of the dielectric ceramic composition with a binder and forming the powder into a sheet to obtain a green sheet, forming an internal electrode pattern containing a metal on the green sheet, stacking a predetermined number of the green sheets on which the internal pattern has been formed, arranging green sheets for cover layers at both ends in the stacking direction, and then pressing the stacked sheets together to obtain a green laminate, dicing the green laminate into individual pieces, and forming a green laminate having the internal electrode pattern thereon.
- the method includes obtaining a pre-fired laminated chip having an extraction surface from which a side margin layer green sheet is drawn out and perpendicular to the extraction surface and the cover layer green sheet, and a protective portion green sheet formed from the cover layer green sheet, removing the binder from the pre-fired laminated chip, adhering the external electrode paste to the surface of the protective portion green sheet of the pre-fired laminated chip after the binder removal so as to be spaced apart from each other to form a pair of external electrode patterns, and firing the pre-fired laminated chip with the external electrode patterns formed thereon to obtain a sintered body.
- a pre-fired laminated chip having an extraction surface from which a side margin layer green sheet is drawn out and perpendicular to the extraction surface and the cover layer green sheet, and a protective portion green sheet formed from the cover layer green sheet, removing the binder from the pre-fired laminated chip, adhering the external electrode paste to the surface of the protective portion green sheet of the pre-fired laminated chip after the binder
- the external electrode paste is prepared by mixing metal particles mainly composed of nickel, boron nitride particles, and a vehicle.
- the external electrode paste may also be prepared by mixing boron nitride particles with a commercially available conductor paste. A commonly used device such as a three-roll mill may be used for mixing.
- the internal electrode paste may contain glass frit and dielectric ceramic composition particles in addition to the above-mentioned components.
- the metal particles containing nickel as the main component may be metallic nickel particles, or may be particles of an alloy containing the highest proportion of nickel in atomic percentage (at%).
- the particle size of the metal particles and particles of the same size as those used in ordinary nickel paste or nickel alloy paste can be used.
- the shape and particle size of the boron nitride particles, and the amount contained in the external electrode paste are not limited.
- the boron nitride particles are a component that becomes the prototype of the pores that are formed in the external electrode when the green body is fired, so the amount may be determined appropriately depending on the shape, diameter and amount of the pores to be formed.
- Examples of the amount contained in the external electrode paste include 0.01% by mass or more and 1.0% by mass or less.
- the boron nitride particles are preferably hexagonal boron nitride particles having a hexagonal crystal structure.
- boron nitride (BN), cubic boron nitride (cBN) and hexagonal boron nitride (hBN) are known due to differences in crystal structure. Since hBN has a particle shape that is disk-like or flat and has a high aspect ratio, the shape of the pores formed in the external electrode can be flat and have a high aspect ratio.
- the type and amount of binder and solvent used in the vehicle are not limited, and may be determined appropriately taking into consideration the viscosity of the external electrode paste, ease of handling, etc.
- the powder of the dielectric ceramic composition is obtained by mixing various raw material powders containing the constituent elements in a predetermined ratio and pre-firing (calcining).
- various additives such as the above-mentioned additive elements and sintering aids may be further added, and these various additives may be further added to the powder after calcination.
- the method for mixing the raw material powders is not particularly limited as long as the powders are mixed uniformly while preventing the inclusion of impurities, and either dry mixing or wet mixing may be used.
- dry mixing using a ball mill for example, partially stabilized zirconia (PSZ) balls are used, and the mixture is stirred for about 8 to 60 hours in a ball mill using an organic solvent such as ethanol or water as the dispersion medium, and then the dispersion medium is evaporated and dried.
- PSZ partially stabilized zirconia
- the conditions for pre-firing the raw material powder mixture are not particularly limited, so long as the various raw material powders described above react to obtain the desired dielectric ceramic composition.
- One example is firing in air at a temperature of 800°C to 1100°C for 1 hour to 10 hours.
- the powder after pre-firing may be processed into a green sheet as is, but crushing using a ball mill or stamp mill is preferable because a smooth green sheet can be obtained through a uniform slurry and sinterability is improved.
- the subsequent operations may be carried out on this powder without carrying out the mixing and pre-firing of the raw material powders described above.
- the green sheet is obtained by mixing the powder of the above-mentioned dielectric ceramic composition with a binder and a dispersion medium to prepare a slurry, and forming the slurry into a sheet.
- the binder used should be one that can maintain the shape of the green sheet and volatilizes without leaving behind any carbon or other residues during the binder removal process prior to firing.
- binders that can be used include polyvinyl alcohol, polyvinyl butyral, cellulose, urethane and vinyl acetate binders.
- the dispersion medium used should be one that does not cause the calcined powder and binder to aggregate and can be easily removed by volatilization or other methods after forming into a green sheet, as described below.
- Examples of dispersion media that can be used include water and alcohol-based solvents.
- Components that adjust the properties of the slurry such as dispersants, plasticizers, and thickeners, may be added to the slurry.
- the method for mixing the mixed powder with the binder and dispersion medium is not particularly limited as long as it is possible to mix each component uniformly while preventing the inclusion of impurities.
- One example is ball mill mixing.
- the prepared slurry can be formed into a sheet to obtain a green sheet by a commonly used method such as the doctor blade method.
- the formation of the internal electrode pattern containing metal on the green sheet described above can be carried out by a method of printing or applying an internal electrode paste onto the green sheet in a predetermined pattern, or by a method of forming a metal film on the green sheet in a predetermined pattern by vapor deposition or sputtering.
- the internal electrode paste used is obtained by mixing the metal particles that form the internal electrodes and a vehicle in a three-roll mill.
- the internal electrode paste may also contain glass frit and dielectric ceramic composition particles.
- the type and amount of binder and solvent contained in the vehicle used are not limited, and may be selected appropriately taking into consideration the viscosity of the internal electrode paste, ease of handling, compatibility with the green sheet, etc.
- the printing of the internal electrode paste on the green sheet can be carried out, for example, using a screen mask on which a specified internal electrode pattern is formed.
- a space that will become the side margin when the multilayer ceramic capacitor is made can be left.
- the green laminate is obtained by stacking a predetermined number of green sheets on which internal electrode patterns are formed and pressing the green sheets together.
- the stacking and pressing may be performed by a conventional method, such as pressing the stacked green sheets together in the stacking direction while heating them, and thermocompression bonding by the action of a binder.
- the added green sheets may have the same composition as the green sheets on which the internal electrode patterns are printed, or a different composition. From the viewpoint of making the shrinkage rate during firing uniform, it is preferable that the composition of the added green sheets is the same as or similar to that of the green sheets on which the aforementioned internal electrode patterns are formed.
- the cover layer includes a plurality of flat pores oriented along its surface, as in the third modified example of the first embodiment described above, boron nitride particles can be mixed into the green sheets for forming the cover layer.
- the pre-fired laminated chips are obtained by dividing the green laminate into individual laminated chip shapes.
- the singulation forms an extraction surface from which the internal electrode patterns are extracted.
- a commonly used means such as a dicing saw or a laser cutting machine can be used.
- the obtained pre-fired laminated chip is heated to remove the binder by volatilization.
- the heating conditions may be appropriately set in consideration of the volatilization temperature and content of the binder.
- the chip may be held in a nitrogen (N 2 ) atmosphere at a temperature of 200° C. to 500° C. for 5 to 20 hours.
- the application of the external electrode paste is carried out by applying the above-mentioned external electrode paste to the surface of at least one of the cover layer green sheets of the pre-fired laminated chip from which the binder has been removed, so that the sheets are positioned at intervals from each other.
- Methods for applying the external electrode paste include printing and dipping.
- the paste for the external electrodes may be applied to the pull-out surface of the pre-fired laminated chip, depending on the structure of the laminated ceramic capacitor to be manufactured, and may also be applied to the surface of the other opposing green sheet for the cover layer.
- the external electrode has a porous metal portion in which the pore area percentages in a cross section parallel to the lamination direction differ between the inner layer and the outer layer, as in the first modified example of the first embodiment described above, multiple types of external electrode pastes with different boron nitride particle contents can be prepared and applied in sequence.
- the external electrode does not have a porous metal portion formed in the portion that contacts the pull-out surface
- a separately prepared external electrode paste that does not contain boron nitride particles can be applied to the pull-out surface, and then an external electrode paste that contains boron nitride particles can be applied to the cover layer.
- the external electrode paste that contains boron nitride particles can be applied only to the cover layer raw sheet, and then the firing described below can be performed, and the remainder of the external electrode can be formed on the pull-out surface.
- the pre-fired laminated chip is fired by heating the pre-fired laminated chip to which the external electrode paste is attached to a predetermined temperature.
- the firing conditions may be appropriately set in consideration of the sinterability of the dielectric ceramic composition and the heat resistance and oxidation resistance of the metals contained in the internal electrode paste and the external electrode paste.
- An example of the firing conditions is holding at 1000°C to 1350°C for 5 minutes to 2 hours in a reducing atmosphere containing a mixture of nitrogen (N 2 ), hydrogen (H 2 ), and water vapor (H 2 O).
- a reoxidation treatment may be performed in which the chip is held at 600°C to 1000°C in a nitrogen (N 2 ) gas atmosphere or a low-oxygen atmosphere.
- N 2 nitrogen
- the powder of the dielectric ceramic composition is sintered to become a dielectric layer
- the internal electrode pattern is sintered to become an internal electrode
- the external electrode paste is sintered to become an external electrode.
- the boron nitride particles in the external electrode paste are stable up to about 1000°C, at which time the dielectric sintering proceeds and the fine structure of the dielectric ceramic is formed to some extent, due to their large particle size and the fact that the firing atmosphere is a reducing atmosphere. Then, with further heating and temperature retention, the boron (B) is decomposed by releasing nitrogen ( N2 ), and part of the boron ( B ) is volatilized, while the remainder forms B2O3 and diffuses into the protective layer, disappearing from the place where it existed before firing.
- pores corresponding to the shape of the boron nitride particles are left in the places where the boron nitride particles in the external electrode paste were present.
- a region containing boron oxide is formed in the metal part located around the pore. In this way, a porous metal part is formed in the external electrode.
- the above-mentioned pore formation process is specific to the case where the external electrode paste containing boron nitride particles is fired in a reducing atmosphere. Even when an external electrode paste containing boron nitride particles is used, when fired in an oxidizing atmosphere such as air, boron nitride turns into B 2 O 3 at a low temperature and disappears, and the parts where the boron nitride has disappeared are filled by the grain growth of metal particles, so pores with sufficient stress relaxation are not easily formed. In addition, in an external electrode paste containing a material that disappears at a lower temperature, such as a particulate resin, the parts where the material has disappeared are filled by the grain growth of metal particles, so pores are not formed. Furthermore, in an external electrode paste containing ceramic particles that do not disappear at the firing temperature, the material remains as it is, so pores are not formed.
- the sintered body obtained by firing is turned into a multilayer ceramic capacitor by forming an external electrode on the drawing surface as necessary.
- a conductive layer may be formed by plating, vapor deposition or other means on the external electrode formed on the surface of the sintered body, and then the multilayer ceramic capacitor may be formed.
- the multilayer ceramic capacitor obtained in the second embodiment has a porous metal portion formed in the external electrode by the process described above, and therefore boron is present near the boundary with the pores in the porous metal portion.
- the boron concentration in the porous metal portion decreases the further away from the pores. Therefore, it is possible to assume that a multilayer ceramic capacitor in which a porous metal portion exists in the external electrode, boron is detected near the pores, and the concentration of the boron decreases the further away from the pores is the one obtained in the second embodiment.
- the presence of boron in the porous metal portion and its concentration distribution can be confirmed by a transmission electron microscope equipped with an energy dispersive X-ray spectrometer (EDS) or a wavelength dispersive X-ray spectrometer (WDS).
- EDS energy dispersive X-ray spectrometer
- WDS wavelength dispersive X-ray spectrometer
- (Appendix 1) a capacitance section in which dielectric layers made of dielectric ceramic and internal electrodes mainly made of metal are alternately laminated, and a protective section including cover layers made of dielectric ceramic and disposed at both ends of the capacitance section in a lamination direction, and side margin layers made of dielectric ceramic and disposed at both ends of the capacitance section in a direction perpendicular to the lamination direction, the protective section including the cover layers being made of dielectric ceramic, the side margin layers being made of dielectric ceramic, and the protective section being disposed at both ends of the capacitance section in a direction perpendicular to the lamination direction, the protective section having an extraction surface from which the internal electrodes are extracted, and electrically connecting the internal electrodes extracted on the extraction surface of the laminated chip, a multilayer ceramic capacitor having a terminal portion formed on a surface of the protective portion, the terminal portion being in contact with the protective portion, the multilayer ceramic capacitor comprising an external electrode having a porous metal portion having nickel as a main component element and including a
- (Appendix 4) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 3), wherein an average value of the major axis of the pores is 0.5 ⁇ m or more and 6.0 ⁇ m or less.
- (Appendix 5) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 4), wherein the area percentage of the pores in a cross section of the porous metal portion parallel to the lamination direction is 0.2% or more and 5.0% or less.
- (Appendix 6) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 5), wherein the porous metal portion has a thickness of 0.5 ⁇ m or more and 30 ⁇ m or less.
- (Appendix 7) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 6), wherein the porous metal portion has an inner layer located on the laminated chip side and an outer layer located on the opposite side of the inner layer from the laminated chip, and when the area percentage of the pores in a cross section parallel to the lamination direction of the inner layer is R1 and the area percentage of the pores in a cross section parallel to the lamination direction of the outer layer is R2 , R1 > R2 is satisfied.
- (Appendix 8) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 6), wherein the porous metal portion has an inner layer located on the laminated chip side and an outer layer located on the opposite side of the inner layer from the laminated chip, and when the area percentage of the pores in a cross section parallel to the lamination direction of the inner layer is R1 and the area percentage of the pores in a cross section parallel to the lamination direction of the outer layer is R2 , R2 > R1 is satisfied.
- (Appendix 11) Preparing an external electrode paste containing metal particles mainly composed of nickel and boron nitride particles; Providing a powder of a dielectric ceramic composition; mixing the powder of the dielectric ceramic composition with a binder and forming the mixture into a sheet to obtain a green sheet; forming an internal electrode pattern comprising a metal on the green sheet; a predetermined number of green sheets having the internal pattern formed thereon are stacked, green sheets for cover layers are disposed on both ends in the stacking direction, and the green sheets are then pressed together to obtain a green laminate; the green laminate is singulated to obtain a pre-fired laminated chip having an extraction surface from which the internal electrode pattern is extracted, and a green sheet for a protective portion including a green sheet for a side margin layer perpendicular to the extraction surface and the green sheet for a cover layer, and the green sheet for a cover layer; removing binder from the pre-fired laminated chips; a method for manufacturing a multilayer ceramic capacitor, comprising: applying
- the present invention provides a multilayer ceramic capacitor that, when mounted on a circuit board, can reduce the concentration of stress caused by the flexural deformation of the circuit board.
- a multilayer ceramic capacitor is useful in that it can be used for in-vehicle circuit boards, which have particularly strict conditions for flexural tests.
- Multilayer ceramic capacitor 10 Dielectric layers 20, 20a, 20b Internal electrode 30 Multilayer chip 40a, 40b Lead surface 50 Cover layer 60 Side margin layers 70a, 70b External electrodes 71a, 71b Terminal portion 72a, 72b Porous metal portion 720 Region containing boron oxide 721a, 721b Inner layer 722a, 722b Outer layer 73 Cu layer 74 Ni layer 75 Sn layer p Pore l p Long axis of pore w p Short axis of pore s t Surface of terminal portion
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024574375A JPWO2024161946A1 (https=) | 2023-01-30 | 2024-01-12 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023-012256 | 2023-01-30 | ||
| JP2023012256 | 2023-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2024161946A1 true WO2024161946A1 (ja) | 2024-08-08 |
Family
ID=92146489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2024/000593 Ceased WO2024161946A1 (ja) | 2023-01-30 | 2024-01-12 | 積層セラミックコンデンサ |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPWO2024161946A1 (https=) |
| WO (1) | WO2024161946A1 (https=) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04236412A (ja) * | 1991-01-21 | 1992-08-25 | Toshiba Corp | セラミック電子部品 |
| JPH053132A (ja) * | 1991-06-25 | 1993-01-08 | Mitsubishi Materials Corp | チツプ型積層セラミツクスコンデンサ |
| JPH0555076A (ja) * | 1991-08-29 | 1993-03-05 | Dai Ichi Kogyo Seiyaku Co Ltd | セラミツクコンデンサー電極用導体ペースト |
| JP2001250740A (ja) * | 2000-03-08 | 2001-09-14 | Murata Mfg Co Ltd | セラミック電子部品 |
| JP2004235375A (ja) * | 2003-01-29 | 2004-08-19 | Kyocera Corp | セラミック電子部品 |
| JP2012033621A (ja) * | 2010-07-29 | 2012-02-16 | Kyocera Corp | 積層セラミックコンデンサ |
| WO2015045625A1 (ja) * | 2013-09-24 | 2015-04-02 | 株式会社村田製作所 | 積層セラミック電子部品 |
| JP2020126958A (ja) * | 2019-02-06 | 2020-08-20 | Tdk株式会社 | 電子部品 |
| JP2020141091A (ja) * | 2019-03-01 | 2020-09-03 | 太陽誘電株式会社 | 積層セラミックコンデンサ及びその製造方法 |
-
2024
- 2024-01-12 JP JP2024574375A patent/JPWO2024161946A1/ja active Pending
- 2024-01-12 WO PCT/JP2024/000593 patent/WO2024161946A1/ja not_active Ceased
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04236412A (ja) * | 1991-01-21 | 1992-08-25 | Toshiba Corp | セラミック電子部品 |
| JPH053132A (ja) * | 1991-06-25 | 1993-01-08 | Mitsubishi Materials Corp | チツプ型積層セラミツクスコンデンサ |
| JPH0555076A (ja) * | 1991-08-29 | 1993-03-05 | Dai Ichi Kogyo Seiyaku Co Ltd | セラミツクコンデンサー電極用導体ペースト |
| JP2001250740A (ja) * | 2000-03-08 | 2001-09-14 | Murata Mfg Co Ltd | セラミック電子部品 |
| JP2004235375A (ja) * | 2003-01-29 | 2004-08-19 | Kyocera Corp | セラミック電子部品 |
| JP2012033621A (ja) * | 2010-07-29 | 2012-02-16 | Kyocera Corp | 積層セラミックコンデンサ |
| WO2015045625A1 (ja) * | 2013-09-24 | 2015-04-02 | 株式会社村田製作所 | 積層セラミック電子部品 |
| JP2020126958A (ja) * | 2019-02-06 | 2020-08-20 | Tdk株式会社 | 電子部品 |
| JP2020141091A (ja) * | 2019-03-01 | 2020-09-03 | 太陽誘電株式会社 | 積層セラミックコンデンサ及びその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2024161946A1 (https=) | 2024-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102498100B1 (ko) | 적층 세라믹 콘덴서 | |
| CN109920644B (zh) | 陶瓷电子器件及陶瓷电子器件的制造方法 | |
| JP7262181B2 (ja) | 積層セラミックコンデンサおよびその製造方法 | |
| JP7759731B2 (ja) | セラミック電子部品およびその製造方法 | |
| CN109390150B (zh) | 多层陶瓷电容器及多层陶瓷电容器的制造方法 | |
| CN108695072B (zh) | 多层陶瓷电容器及多层陶瓷电容器的制造方法 | |
| JP5566434B2 (ja) | 積層セラミックコンデンサ | |
| JPH11251173A (ja) | 積層セラミック電子部品 | |
| KR20190118957A (ko) | 적층 세라믹 콘덴서 및 그 제조 방법 | |
| KR100673932B1 (ko) | 세라믹 전자 부품 및 그 제조 방법 | |
| CN1841598B (zh) | 叠层陶瓷电子部件及其制造方法 | |
| JP4370217B2 (ja) | 積層セラミックコンデンサ | |
| CN108878147A (zh) | 多层陶瓷电容器以及多层陶瓷电容器的制造方法 | |
| CN112687467B (zh) | 陶瓷电子器件及其制造方法 | |
| CN100483577C (zh) | 电介质陶瓷组合物、电子部件以及多层陶瓷电容器 | |
| JP7151520B2 (ja) | 積層電子部品 | |
| JP7807875B2 (ja) | セラミック電子部品およびその製造方法 | |
| JP6946907B2 (ja) | 積層電子部品 | |
| WO2024161946A1 (ja) | 積層セラミックコンデンサ | |
| CN116721865A (zh) | 层叠陶瓷电子部件 | |
| JP4968309B2 (ja) | ペースト組成物、電子部品および積層セラミックコンデンサの製造方法 | |
| JP2007234330A (ja) | 導電体ペーストおよび電子部品 | |
| WO2025041651A1 (ja) | 積層セラミック電子部品及びその製造方法 | |
| US20250343004A1 (en) | Multilayer ceramic capacitor and method of manufacturing the same | |
| JP2024132655A (ja) | 積層セラミックコンデンサ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 24749901 Country of ref document: EP Kind code of ref document: A1 |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 2024574375 Country of ref document: JP |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 24749901 Country of ref document: EP Kind code of ref document: A1 |