WO2024154354A1 - デバイスおよびデバイスの製造方法 - Google Patents

デバイスおよびデバイスの製造方法 Download PDF

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Publication number
WO2024154354A1
WO2024154354A1 PCT/JP2023/001769 JP2023001769W WO2024154354A1 WO 2024154354 A1 WO2024154354 A1 WO 2024154354A1 JP 2023001769 W JP2023001769 W JP 2023001769W WO 2024154354 A1 WO2024154354 A1 WO 2024154354A1
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Prior art keywords
wiring
substrate
wiring pattern
insulating film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2023/001769
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English (en)
French (fr)
Japanese (ja)
Inventor
中村誠
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Fujitsu Ltd
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Fujitsu Ltd
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Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to EP23917567.2A priority Critical patent/EP4654808A4/en
Priority to PCT/JP2023/001769 priority patent/WO2024154354A1/ja
Priority to JP2024571592A priority patent/JPWO2024154354A1/ja
Publication of WO2024154354A1 publication Critical patent/WO2024154354A1/ja
Priority to US19/227,604 priority patent/US20250301921A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H10N60/815—Containers; Mountings for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/805—Constructional details for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

Definitions

  • the present invention relates to a device and a method for manufacturing the device.
  • Interposers are known, which are relay substrates that use through-hole electrodes to ensure electrical continuity between circuits on the front and back sides. For example, it is known to flip-chip mount quantum bit chips on interposers (see, for example, Patent Documents 1 to 3). There is also a known configuration in which quantum bits and passive elements provided on the front and back sides of a substrate are connected by through-hole electrodes (see, for example, Patent Document 4).
  • first wiring pattern formed on the first surface of the substrate, the second wiring pattern formed on the second surface opposite the first surface, and the through electrode formed in the through hole between the first surface and the second surface are formed in separate processes, the manufacturing man-hours will increase.
  • One aspect is to reduce manufacturing labor.
  • a method for manufacturing a device includes the steps of forming a conductive film made of a superconducting material on a substrate having a first surface, a second surface opposite the first surface, and a through hole penetrating between the first surface and the second surface, the conductive film extending from the first surface to the second surface via the side of the through hole, patterning the conductive film on the first surface to form a first wiring pattern, patterning the conductive film on the second surface to form a second wiring pattern, and forming a quantum bit element connected to the first wiring pattern.
  • the device includes a substrate having a first surface, a second surface opposite the first surface, and a through hole penetrating between the first surface and the second surface, a through electrode made of a superconducting material extending from the first surface to the second surface via the side of the through hole, a first wiring pattern provided on the first surface and made of the same material as the through electrode, a second wiring pattern provided on the second surface and made of the same material as the through electrode, and a quantum bit element connected to the first wiring pattern.
  • One aspect is that it can reduce manufacturing labor.
  • FIG. 1 is a cross-sectional view of a device according to a first embodiment.
  • 2A to 2C are cross-sectional views (part 1) illustrating a method for manufacturing a device according to the first embodiment.
  • 3A to 3C are cross-sectional views (part 2) illustrating the method for manufacturing the device according to the first embodiment.
  • 4A to 4C are cross-sectional views (part 3) illustrating the method for manufacturing the device according to the first embodiment.
  • 5A to 5C are cross-sectional views (part 4) illustrating the method for manufacturing the device according to the first embodiment.
  • FIG. 6 is a cross-sectional view showing an example of the formation of a conductive film in the first embodiment.
  • 7A and 7B are cross-sectional views showing a method for manufacturing a device according to the second embodiment.
  • FIG. 8A to 8C are cross-sectional views (part 1) illustrating a method for manufacturing a device according to the third embodiment.
  • 9A to 9C are cross-sectional views (part 2) illustrating a method for manufacturing a device according to the third embodiment.
  • FIG. 10 is a cross-sectional view of a device according to the fourth embodiment.
  • FIG. 11(a) is a plan view of a quantum bit element in Example 4, and
  • FIG. 11(b) is a cross-sectional view taken along line AA of FIG. 11(a).
  • 12A to 12C are cross-sectional views (part 1) illustrating a method for manufacturing a device according to the fourth embodiment.
  • 13A to 13C are cross-sectional views (part 2) illustrating a method for manufacturing a device according to the fourth embodiment.
  • 14A to 14C are cross-sectional views (part 1) illustrating a method for manufacturing a quantum bit element and a seventh wiring pattern in the fourth embodiment.
  • 15A to 15C are cross-sectional views (part 2) illustrating a method for manufacturing a quantum bit element and a seventh wiring pattern in the fourth embodiment.
  • 16A to 16C are cross-sectional views (part 1) showing a method for manufacturing a device according to a comparative example.
  • 17A to 17C are cross-sectional views (part 2) showing a method for manufacturing a device according to a comparative example.
  • FIG. 18 is a cross-sectional view of a case where a plurality of wiring layers are stacked on the substrate side of the quantum bit element.
  • 19A to 19C are cross-sectional views showing a method for manufacturing a device according to the fifth embodiment.
  • FIG. 1 is a cross-sectional view of a device according to Example 1.
  • Example 1 shows an example in which device 100 is an interposer. The directions parallel to and perpendicular to first surface 11 of substrate 10 are defined as X-axis and Y-axis, and the thickness direction of substrate 10 is defined as Z-axis.
  • device 100 according to Example 1 has substrate 10 having first surface 11 and second surface 12 opposite to first surface 11, and through-hole 13 penetrating between first surface 11 and second surface 12.
  • Substrate 10 is, for example, a silicon substrate, a glass substrate, or a quartz substrate.
  • Through-hole 13 has, for example, a diameter of about 5 ⁇ m to 15 ⁇ m and a depth of about 100 ⁇ m to 300 ⁇ m.
  • a through electrode 20 is provided in the through hole 13.
  • the through electrode 20 has a cylindrical shape extending from the first surface 11 along the side of the through hole 13 onto the second surface 12.
  • An insulating film 30 is provided between the side of the through hole 13 and the through electrode 20.
  • the through electrode 20 is made of, for example, titanium nitride, and has a thickness of, for example, about 50 nm to 150 nm.
  • the insulating film 30 is made of, for example, silicon oxide, and has a thickness of, for example, 50 nm to 150 nm.
  • One or more first wiring patterns 40 are provided on the first surface 11 of the substrate 10 via an insulating film 31. At least a part of the one or more first wiring patterns 40 is connected to the through electrode 20.
  • the first wiring pattern 40 is formed of the same material as the through electrode 20 (e.g., titanium nitride) and has the same thickness as the through electrode 20.
  • the one or more first wiring patterns 40 may include dummy wiring that does not flow current and is at ground potential when the chip mounted on the first surface 11 and the second surface 12 of the substrate 10 is in operation.
  • the insulating film 31 is formed of, for example, silicon oxide and has a thickness of, for example, about 50 nm to 150 nm.
  • the thickness of the first wiring pattern 40 being the same as the thickness of the through electrode 20 does not necessarily mean that they are completely the same, but rather that a difference of the order of manufacturing error is allowed.
  • the thickness of the first wiring pattern 40 is 90% to 110% of the thickness of the through electrode 20, and may be 95% to 105%.
  • An insulating film 32 is provided on the first surface 11 of the substrate 10, covering one or more first wiring patterns 40. Through wiring 41 is provided, embedded in an opening provided in the insulating film 32 and connected to the first wiring pattern 40.
  • a first terminal electrode 42 is provided on the insulating film 32, connected to the through wiring 41 and serving as a terminal for external connection.
  • the insulating film 32 is formed of, for example, silicon oxide, and has a thickness of, for example, 100 nm to 300 nm.
  • the first terminal electrode 42 is formed of a high-melting point metal material, such as vanadium, molybdenum, hafnium, or tantalum.
  • the through wiring 41 may be formed of the same material as the first terminal electrode 42, or may be formed of a different material.
  • One or more second wiring patterns 43 are provided on the second surface 12 of the substrate 10 via an insulating film 33. At least a part of the one or more second wiring patterns 43 is connected to the through electrode 20.
  • the second wiring pattern 43 is formed of the same material as the through electrode 20 (e.g., titanium nitride) and has the same thickness as the through electrode 20.
  • the one or more second wiring patterns 43 may include dummy wiring that does not flow current and is at ground potential when the chip mounted on the first surface 11 and the second surface 12 of the substrate 10 is in operation.
  • the insulating film 33 is formed of, for example, silicon oxide and has a thickness of, for example, about 50 nm to 150 nm.
  • the thickness of the second wiring pattern 43 is not limited to being completely the same as the thickness of the through electrode 20, but allows for a difference of the order of manufacturing error.
  • the thickness of the second wiring pattern 43 is 90% to 110% of the thickness of the through electrode 20, and may be 95% to 105%.
  • An insulating film 34 is provided on the second surface 12 of the substrate 10, covering one or more second wiring patterns 43. Through wiring 44 is provided, embedded in an opening provided in the insulating film 34 and connected to the second wiring pattern 43.
  • a second terminal electrode 45 is provided on the insulating film 34, connected to the through wiring 44 and serving as a terminal for external connection.
  • a bump electrode 46 is provided on the surface of the second terminal electrode 45.
  • the insulating film 34 is formed of, for example, silicon oxide, and has a thickness of, for example, 100 nm to 300 nm.
  • the second terminal electrode 45 is formed of a high-melting point metal material, like the first terminal electrode 42.
  • the through wiring 44 may be formed of the same material as the second terminal electrode 45, or may be formed of a different material.
  • the bump electrode 46 is formed of, for example, indium, gallium, or solder.
  • An insulating film 35 is provided inside the through hole 13 to cover the surface of the through electrode 20.
  • a cavity 36 is formed in the through hole 13 on the central side of the insulating film 35.
  • the insulating film 35 is formed of, for example, silicon oxide and has a thickness of, for example, about 25 nm to 75 nm. Note that the central side of the through hole 13 on the central side of the through electrode 20 may be filled with the insulating film 35 without forming the cavity 36, or the insulating film 35 may be filled with another film made of a different material.
  • the total area of the faces 48 of the one or more first wiring patterns 40 opposite the substrate 10 is the same as the total area of the faces 49 of the one or more second wiring patterns 43 opposite the substrate 10.
  • the areas being the same does not necessarily mean that they are completely the same, but rather allows for differences of the order of manufacturing error.
  • the total area of the faces 48 of the one or more first wiring patterns 40 is 90% to 110% of the total area of the faces 49 of the one or more second wiring patterns 43, and may be 95% to 105%.
  • the electrodes and wiring are preferably formed of a superconducting material that exhibits superconductivity at extremely low temperatures (for example, 10 Kelvin or less). That is, the first wiring pattern 40, the second wiring pattern 43, the first terminal electrode 42, the second terminal electrode 45, the through-wires 41, 44, and the bump electrodes 46 are preferably formed of a superconducting material. Examples of superconducting materials include aluminum, titanium, vanadium, zinc, gallium, zirconium, niobium, molybdenum, technetium, cadmium, indium, tin, hafnium, tantalum, niobium nitride, and titanium nitride. Furthermore, when a chip other than a quantum bit chip is implemented in device 100, the electrodes and wiring may be formed of copper, tungsten, or the like in addition to the above materials.
  • FIG. 2(a) to 5(c) are cross-sectional views showing a method for manufacturing a device according to Example 1.
  • a substrate 10 which is a silicon substrate
  • the substrate 10 is heated in an oxidizing atmosphere to form a thermal oxide film 80, which is a silicon oxide film, on the first surface 11 and the second surface 12 of the substrate 10.
  • the thickness of the thermal oxide film 80 is, for example, 100 nm.
  • a resist is applied onto the thermal oxide film 80 formed on the first surface 11 of the substrate 10 to form a resist film 81.
  • the resist film 81 is exposed to light and developed to form an opening in the resist film 81.
  • a hard mask layer may be formed between the resist film 81 and the thermal oxide film 80.
  • a recess 82 is formed in the substrate 10.
  • the recess 82 is formed, for example, using the Bosch process.
  • the recess 82 corresponds to the through hole 13 in FIG. 1 and has a diameter of, for example, 10 ⁇ m and a depth of, for example, 200 ⁇ m.
  • the substrate 10 is turned upside down and the thermal oxide film 80 is bonded to a support substrate 84 with an adhesive 83.
  • the support substrate 84 is, for example, a silicon substrate.
  • the substrate 10 is thinned from the second surface 12 side by grinding and polishing (for example, by chemical mechanical polishing (CMP)) to expose the recess 82.
  • CMP chemical mechanical polishing
  • the substrate 10 is heated in an oxidizing atmosphere to form an insulating film 33, which is a silicon oxide film, on the second surface 12 of the substrate 10, and an insulating film 30, which is a silicon oxide film, on the side surface of the through hole 13.
  • the thickness of the insulating films 30 and 33 is, for example, 100 nm.
  • the insulating films 30 and 33 may be formed using a chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • a conductive film 85 extending from the first surface 11 of the substrate 10 to the second surface 12 via the side of the through hole 13 is formed by a single film formation process using, for example, atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • a conductive film 85 made of titanium nitride is formed by ALD using Ti[N(CH 3 ) 2 ] 4 gas and NH 3 gas.
  • the thickness of the conductive film 85 is, for example, 100 nm.
  • N 2 H 4 gas may be used instead of NH 3 gas.
  • an insulating film 86 made of a silicon oxide film covering the surface of the conductive film 85 is formed by, for example, ALD.
  • the thickness of the insulating film 86 is, for example, 50 nm.
  • the insulating film 86 is formed in order to suppress alteration due to exposure of the conductive film 85 and to suppress unintended conduction of the conductive film 85.
  • FIG. 6 is a cross-sectional view showing an example of the formation of a conductive film in Example 1.
  • the substrate 10 is placed on a support (not shown) such as a quartz basket and placed in a film formation chamber 87 of an ALD apparatus.
  • Ti[N(CH 3 ) 2 ] 4 gas and NH 3 gas are introduced from the inlet In toward the outlet Out into the film formation chamber 87 to form a conductive film 85 on the substrate 10.
  • a conductive film 85 of uniform thickness is formed not only on the first surface 11 of the substrate 10 but also on the second surface 12 and the side of the through hole 13.
  • FIG. 6 shows an example in which the ALD apparatus is, for example, a Hot Wall ALD apparatus having a heating unit 88 beside the film formation chamber 87.
  • a batch type is shown as an example, a single-wafer type may also be used.
  • an opening is formed in an insulating film 86 formed on the first surface 11 of the substrate 10 by reactive ion etching (RIE) using, for example, a fluorine-based gas.
  • RIE reactive ion etching
  • the conductive film 85 formed on the first surface 11 of the substrate 10 is patterned by RIE using, for example, a chlorine-based gas to form one or more first wiring patterns 40.
  • the first wiring patterns 40 are formed on the first surface 11 of the substrate 10 via an insulating film 31 made of a thermal oxide film 80.
  • an insulating film made of a silicon oxide film is formed on the first surface 11 of the substrate 10, for example by using a CVD method, and an insulating film 32 that covers one or more first wiring patterns 40 together with an insulating film 86 is formed on the insulating film 31.
  • the thickness of the insulating film 32 is, for example, 200 nm.
  • the substrate 10 is turned upside down, and an opening is formed in the insulating film 86 formed on the second surface 12 of the substrate 10, for example, by RIE using a fluorine-based gas. Then, the conductive film 85 formed on the second surface 12 of the substrate 10 is patterned, for example, by RIE using a chlorine-based gas, to form one or more second wiring patterns 43.
  • the second wiring patterns 43 are formed on the second surface 12 of the substrate 10 via the insulating film 33.
  • a cylindrical through electrode 20 made of the conductive film 85 is formed on the side of the through hole 13, connected to the first wiring pattern 40 and the second wiring pattern 43.
  • an insulating film made of a silicon oxide film is formed on the second surface 12 of the substrate 10, for example, by using a CVD method, and an insulating film 34 that covers one or more second wiring patterns 43 together with the insulating film 86 is formed on the insulating film 33.
  • the thickness of the insulating film 34 is 200 nm.
  • An insulating film 35 that covers the surface of the through electrode 20 is formed on the center side of the through hole 13 relative to the through electrode 20.
  • a cavity 36 is formed on the center side of the through hole 13 relative to the insulating film 35.
  • the substrate 10 is turned upside down, and an opening is formed in the insulating film 32 by, for example, RIE using a fluorine-based gas, to expose the first wiring pattern 40.
  • a sputtering method is used to form a through wiring 41 that is embedded in the opening formed in the insulating film 32 and connects to the first wiring pattern 40.
  • a first terminal electrode 42 that connects to the through wiring 41 is formed on the insulating film 32 by, for example, a sputtering method and an etching method.
  • the through wiring 41 and the first terminal electrode 42 are not limited to being formed in separate steps, and may be formed simultaneously in the same step.
  • a through wire 44 that connects to the second wiring pattern 43 is formed in the insulating film 34 by the same method as for the through wire 41 and the first terminal electrode 42, and a second terminal electrode 45 that connects to the through wire 44 is formed.
  • the through wire 44 and the second terminal electrode 45 are not limited to being formed in separate processes, and may be formed simultaneously in the same process.
  • a bump electrode 46 is formed on the surface of the second terminal electrode 45. In this manner, the device 100 according to the first embodiment is formed.
  • the through wiring 41 and the first terminal electrode 42 are formed, and then the through wiring 44 and the second terminal electrode 45 are formed, but they may be formed in the opposite order.
  • the bump electrode 46 may be formed on the first terminal electrode 42 without being formed on the second terminal electrode 45, or may be formed on both the first terminal electrode 42 and the second terminal electrode 45, or may not be formed on both.
  • a conductive film 85 is formed that extends from the first surface 11 of the substrate 10 via the side of the through hole 13 onto the second surface 12.
  • the conductive film 85 formed on the first surface 11 of the substrate 10 is patterned to form one or more first wiring patterns 40.
  • the conductive film 85 formed on the second surface 12 of the substrate 10 is patterned to form one or more second wiring patterns 43.
  • a through electrode 20 is formed from the conductive film 85 that extends from the first surface 11 onto the second surface 12 via the side of the through hole 13.
  • the one or more first wiring patterns 40 formed on the first surface 11 and the one or more second wiring patterns 43 formed on the second surface 12 are formed of the same material as the through electrode 20 and have the same thickness as the through electrode 20. This allows for a reduction in manufacturing man-hours compared to when the first wiring pattern 40, the second wiring pattern 43, and the through electrode 20 are formed as separate films. This allows for a reduction in energy and materials used during manufacturing. Having the same thickness does not necessarily mean that they are completely the same, but allows for differences of the order of manufacturing error. For example, the thickness of the first wiring pattern 40 and the second wiring pattern 43 is 90% to 110% of the thickness of the through electrode 20, and may be 95% to 105%.
  • Example 1 as shown in FIG. 3(c), the conductive film 85 is formed by the ALD method. This allows the conductive film 85 to be formed with the same thickness on the first surface 11, the second surface 12, and the side surface of the through hole 13 of the substrate 10, even if the aspect ratio of the through hole 13 is large.
  • the first wiring pattern 40 and the second wiring pattern 43 are formed so that the total area of the surface 48 of the one or more first wiring patterns 40 opposite the substrate 10 is the same as the total area of the surface 49 of the one or more second wiring patterns 43 opposite the substrate 10. This reduces warping of the substrate 10. This improves the bonding reliability when flip-chip mounting a chip on the substrate 10, and also improves the yield in forming the first terminal electrodes 42 and the second terminal electrodes 45.
  • the areas being the same does not necessarily mean that they are completely the same, but rather means that differences of the order of manufacturing error are allowed.
  • the total area of the surface 48 of the one or more first wiring patterns 40 is 90% to 110% of the total area of the surface 49 of the one or more second wiring patterns 43, and may be 95% to 105%.
  • Example 1 As shown in FIG. 5(b), a first terminal electrode 42 for external connection connected to one or more first wiring patterns 40 is formed on the first surface 11 of the substrate 10. As shown in FIG. 5(c), a second terminal electrode 45 for external connection connected to one or more second wiring patterns 43 is formed on the second surface 12 of the substrate 10. This allows the device 100 of Example 1 to be used as an interposer.
  • the conductive film 85 is made of titanium nitride. In this way, by forming the conductive film 85 from a superconducting material, the device 100 can be used as an interposer on which a quantum bit chip is mounted.
  • FIG. 7(a) and 7(b) are cross-sectional views showing a method for manufacturing a device according to Example 2.
  • a quantum bit chip 50 is flip-chip mounted on a first surface 11 of a substrate 10 constituting a device 100.
  • the quantum bit chip 50 is bonded to a first terminal electrode 42 by a bump electrode 52.
  • a quantum bit element is formed on the quantum bit chip 50, although not shown.
  • a circuit chip 51 is flip-chip mounted on a second surface 12 of the substrate 10.
  • the circuit chip 51 is bonded to a second terminal electrode 45 by a bump electrode 46.
  • An active element such as a CMOS element and/or a passive element such as an inductor or a capacitor is formed on the circuit chip 51, although not shown. In this way, a device 200 according to Example 2 is formed.
  • a quantum bit chip 50 is mounted on the first surface 11 of the substrate 10.
  • a circuit chip 51 is mounted on the second surface 12 of the substrate 10. This results in a device 200 in which the quantum bit chip 50 and the circuit chip 51 are mounted on the substrate 10. Furthermore, when the total area of the surfaces 48 of the one or more first wiring patterns 40 is the same as the total area of the surfaces 49 of the one or more second wiring patterns 43, warping of the substrate 10 is reduced, improving the reliability of the connections between the substrate 10 and the quantum bit chip 50 and the circuit chip 51.
  • the circuit chip 51 may be mounted on the first surface 11 of the substrate 10, and the quantum bit chip 50 may be mounted on the second surface 12.
  • FIG. 8(a) to FIG. 9(c) are cross-sectional views showing a method for manufacturing a device according to Example 3. As shown in FIG. 8(a), the same steps as those shown in FIG. 2(a) to FIG. 5(a) of Example 1 are carried out to obtain FIG. 8(a).
  • an opening is formed in the insulating film 32 by RIE using, for example, a fluorine-based gas to expose the first wiring pattern 40, and a through-wire 60 is formed by, for example, a sputtering method so as to fill the opening.
  • a conductive film is formed on the first surface 11 of the substrate 10 by, for example, a sputtering method, and then the conductive film is patterned by RIE using, for example, a chlorine-based gas to form one or more third wiring patterns 61.
  • the third wiring pattern 61 is formed of, for example, titanium nitride.
  • an insulating film 62 which is a silicon oxide film, is formed on the first surface 11 of the substrate 10 by, for example, a CVD method.
  • the insulating film 62 is formed on the insulating film 32, covering the one or more third wiring patterns 61.
  • a wiring layer 66 including the one or more third wiring patterns 61 and the insulating film 62 is formed.
  • an opening is formed in the insulating film 62 to expose the third wiring pattern 61, and a through wiring 63 is formed to fill the opening.
  • One or more fourth wiring patterns 64 connected to the through wiring 63 are formed on the insulating film 62.
  • the fourth wiring pattern 64 is formed of, for example, titanium nitride.
  • An insulating film 65 is formed on the insulating film 62 so as to cover the one or more fourth wiring patterns 64. This forms a wiring layer 67 including the one or more fourth wiring patterns 64 and the insulating film 65.
  • the substrate 10 is turned upside down, an opening is formed in the insulating film 34 to expose the second wiring pattern 43, and the through wiring 70 is formed so as to fill the opening.
  • a conductive film is formed on the second surface 12 of the substrate 10, and the conductive film is patterned to form one or more fifth wiring patterns 71.
  • the fifth wiring pattern 71 is formed of, for example, the same material as the third wiring pattern 61.
  • an insulating film 72 which is a silicon oxide film, is formed on the second surface 12 of the substrate 10.
  • the insulating film 72 is formed on the insulating film 34, covering the one or more fifth wiring patterns 71.
  • a wiring layer 76 including one or more fifth wiring patterns 71 and the insulating film 72 is formed.
  • the thickness of the one or more fifth wiring patterns 71 included in the wiring layer 76 and the total area of the surface opposite to the substrate 10 are set to be the same as the thickness of the one or more third wiring patterns 61 included in the wiring layer 66 and the total area of the surface opposite to the substrate 10.
  • an opening is formed in the insulating film 72 to expose the fifth wiring pattern 71, and a through wiring 73 is formed to fill the opening.
  • One or more sixth wiring patterns 74 connected to the through wiring 73 are formed on the insulating film 72.
  • the sixth wiring pattern 74 is formed of, for example, the same material as the fourth wiring pattern 64.
  • An insulating film 75 is formed on the insulating film 72 so as to cover the one or more sixth wiring patterns 74. This forms a wiring layer 77 including one or more sixth wiring patterns 74 and the insulating film 75.
  • the thickness of the one or more sixth wiring patterns 74 included in the wiring layer 77 and the total area of the surface opposite the substrate 10 are set to be the same as the thickness of the one or more fourth wiring patterns 64 included in the wiring layer 67 and the total area of the surface opposite the substrate 10.
  • a through wiring 68 connected to the fourth wiring pattern 64 is formed in the insulating film 65, and a first terminal electrode 42 connected to the through wiring 68 is formed on the insulating film 65.
  • a through wiring 78 connected to the sixth wiring pattern 74 is formed in the insulating film 75, and a second terminal electrode 45 connected to the through wiring 78 is formed on the insulating film 75. In this way, the device 300 according to the third embodiment is formed.
  • one or more wiring layers 66, 67 are formed on the opposite side of the substrate 10 to one or more first wiring patterns 40.
  • one or more wiring layers 76, 77 second wiring layers having the same number of layers as the one or more wiring layers 66, 67 are formed on the opposite side of the substrate 10 to one or more second wiring patterns 43. This makes it possible to make the number of wiring layers formed on the first surface 11 of the substrate 10 the same as the number of wiring layers formed on the second surface 12, thereby reducing warping of the substrate 10.
  • one or more wiring layers 66, 67 and one or more wiring layers 76, 77 are formed so that the thickness of the wiring patterns in the same layer from the substrate 10 and the total area of the surface opposite the substrate 10 are the same. That is, one or more third wiring patterns 61 of the wiring layer 66 and one or more fifth wiring patterns 71 of the wiring layer 76, which are layers from the substrate 10, are formed so that they have the same thickness and total area on the surface opposite the substrate 10. Similarly, one or more fourth wiring patterns 64 of the wiring layer 67 and one or more sixth wiring patterns 74 of the wiring layer 77, which are layers from the substrate 10, are formed so that they have the same thickness and total area on the surface opposite the substrate 10. This can reduce warping of the substrate 10.
  • the thickness and total area are not limited to being completely the same, but allow for differences of the order of manufacturing error.
  • the thickness and total area of the wiring pattern on one layer may be 90% or more and 110% or less of the thickness and total area of the wiring pattern on the other layer, and may be 95% or more and 105% or less.
  • FIG. 10 is a cross-sectional view of a device according to Example 4.
  • a quantum bit element 90 and one or more seventh wiring patterns 91 are provided on an insulating film 32.
  • the quantum bit element 90 is connected to the through electrode 20 via the seventh wiring pattern 91 and the first wiring pattern 40.
  • An insulating film 37 that covers the quantum bit element 90 and the seventh wiring pattern 91 is provided on the insulating film 32.
  • the insulating film 37 is, for example, a silicon oxide film, and has a thickness of, for example, 100 nm to 300 nm.
  • the other configurations are the same as those in Example 1, so a description thereof will be omitted.
  • the quantum bit element 90 is a Josephson junction element having a lower superconducting film 92, an insulating film 93, and an upper superconducting film 94.
  • the lower superconducting film 92 and the upper superconducting film 94 extend crossing each other.
  • the insulating film 93 is provided between the lower superconducting film 92 and the upper superconducting film 94 at least at the intersection of the lower superconducting film 92 and the upper superconducting film 94.
  • the lower superconducting film 92 and the upper superconducting film 94 are made of a superconducting material such as aluminum.
  • the insulating film 93 is made of aluminum oxide, for example.
  • FIG. 12(a) to 13(c) are cross-sectional views showing a method for manufacturing a device according to Example 4. First, the same steps as those shown in Fig. 2(a) to Fig. 5(a) of Example 1 are carried out to obtain Fig. 12(a).
  • the insulating film 34 is bonded to the support substrate 84 with adhesive 83.
  • a mask layer (not shown) formed on the insulating film 32 is used as a mask to form an opening 95 in the insulating film 32 that exposes the first wiring pattern 40, for example, by RIE using a fluorine-based gas.
  • a quantum bit element 90 and one or more seventh wiring patterns 91 are formed on an insulating film 32.
  • the quantum bit element 90 is connected to the first wiring pattern 40 via the seventh wiring pattern 91.
  • a method for forming the quantum bit element 90 and the seventh wiring pattern 91 will be described with reference to FIG. 14(a) to FIG. 15(c).
  • FIGS. 14(a) to 15(c) are cross-sectional views showing a method for manufacturing a quantum bit element and a seventh wiring pattern in Example 4.
  • a lower superconducting film 92 is formed on an insulating film 32, for example, by using a vapor deposition method.
  • An insulating film 93 is formed on the lower superconducting film 92, for example, by using an ALD method.
  • An upper superconducting film 94 is formed on the insulating film 93, for example, by using a vapor deposition method.
  • a mask layer 96 which is, for example, a silicon oxide film, is formed on the upper superconducting film 94 by, for example, a CVD method. Then, the mask layer 96 is patterned.
  • the mask layer 96 is used as a mask to etch the upper superconducting film 94 by RIE using, for example, a chlorine-based gas.
  • the mask layer 96 is used as a mask to etch the insulating film 93, for example, by milling.
  • the mask layer 96 is used as a mask to etch the lower superconducting film 92 by RIE using, for example, a chlorine-based gas.
  • the mask layer 96 is removed. This results in the formation of the quantum bit element 90, which is made up of the lower superconducting film 92, the insulating film 93, and the upper superconducting film 94.
  • the seventh wiring pattern 91 is also formed by the lower superconducting film 92, the insulating film 93, and the upper superconducting film 94.
  • the quantum bit element 90 is connected to the first wiring pattern 40 via the seventh wiring pattern 91.
  • an insulating film 37 made of a silicon oxide film is formed on the insulating film 32, for example, by using a CVD method.
  • the thickness of the insulating film 37 is, for example, 200 nm.
  • the insulating film 37 is formed on the insulating film 32, covering the quantum bit element 90 and the seventh wiring pattern 91.
  • the support substrate 84 is peeled off. Then, by a method similar to that shown in FIG. 5(c) of Example 1, a through-wire 44 is formed in the insulating film 34, and a second terminal electrode 45 is formed on the through-wire 44. A bump electrode 46 is formed on the surface of the second terminal electrode 45. In this manner, the device 400 according to Example 4 is formed.
  • FIG. 16(a) to 17(c) are cross-sectional views showing a method for manufacturing a device according to a comparative example.
  • a substrate 110 is heated in an oxidizing atmosphere to form a thermal oxide film 180 on a first surface 111 and a second surface 112 of the substrate 110.
  • a quantum bit element 190 is formed on the thermal oxide film 180 formed on the first surface 111 of the substrate 110.
  • an insulating film 130 which is a silicon oxide film, is formed on the first surface 111 of the substrate 110 by, for example, a CVD method.
  • the insulating film 130 is formed on the thermal oxide film 180, covering the quantum bit element 190.
  • an opening 150 is formed in the insulating film 130, exposing the quantum bit element 190, for example, by RIE using a fluorine-based gas.
  • a conductive film 140 is formed on the first surface 111 of the substrate 110 by, for example, a sputtering method.
  • the conductive film 140 is also formed so as to be embedded in the opening 150 formed in the insulating film 130.
  • the conductive film 140 is formed of, for example, titanium nitride.
  • the conductive film 140 is patterned by RIE using, for example, a chlorine-based gas to form one or more wiring patterns 142. Some of the one or more wiring patterns 142 are connected to the quantum bit element 190.
  • an insulating film 132 which is a silicon oxide film, is formed on the first surface 111 of the substrate 110 by, for example, a CVD method.
  • the insulating film 132 is formed on the insulating film 130, covering the wiring pattern 142.
  • the insulating film 130 is formed and processed, the conductive film 140 is formed and processed, and the insulating film 132 is formed.
  • the insulating films 130 and 132 are formed, for example, by the CVD method. In the CVD method, the temperature of the substrate 110 reaches several hundred degrees Celsius, which may damage the quantum bit element 190.
  • the conductive film 140 is formed, for example, by the sputtering method, and the insulating film 130 and the conductive film 140 are processed by RIE.
  • the insulating film 130 and the conductive film 140 are irradiated with charged particles, which may also damage the quantum bit element 190. For these reasons, it is considered that the characteristics of the quantum bit element 190 are deteriorated.
  • Example 4 after forming one or more first wiring patterns 40 and one or more second wiring patterns 43 as shown in FIG. 12(a), quantum bit elements 90 connected to one or more first wiring patterns 40 are formed as shown in FIG. 13(a).
  • quantum bit elements 90 connected to one or more first wiring patterns 40 are formed as shown in FIG. 13(a).
  • the quantum bit element 90 is formed on the first surface 11 of the substrate 10, but may be formed on the second surface 12.
  • the wiring layer formed on the substrate 10 side of the quantum bit element 90 may have a multi-layer wiring structure.
  • FIG. 18 is a cross-sectional view of a case where multiple wiring layers are stacked on the substrate side of the quantum bit element.
  • the quantum bit element 90 is preferably formed in the wiring layer 67, which is the furthest from the substrate 10, of the multiple wiring layers 66, 67, 69 formed on the first surface 11 of the substrate 10.
  • the quantum bit element 90 is preferably formed after the wiring patterns in all of the wiring layers 66, 67, 69 formed on the first surface 11 side of the substrate 10.
  • FIG. 19 is a cross-sectional view showing a method for manufacturing a device according to Example 5.
  • a circuit chip 51 is flip-chip mounted on the second surface 12 of a substrate 10 constituting a device 400.
  • the circuit chip 51 is joined to a second terminal electrode 45 by a bump electrode 46. In this way, a device 500 according to Example 5 is formed.
  • the first terminal electrode 42 may be formed on the first surface 11.
  • the quantum bit chip 50 may be flip-chip mounted to the first terminal electrode 42.
  • the circuit chip 51 may be flip-chip mounted to the first terminal electrode 42, and the quantum bit chip 50 may be flip-chip mounted to the second terminal electrode 45.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2023/001769 2023-01-20 2023-01-20 デバイスおよびデバイスの製造方法 Ceased WO2024154354A1 (ja)

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JP2024571592A JPWO2024154354A1 (https=) 2023-01-20 2023-01-20
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