CN112466831A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN112466831A
CN112466831A CN202010011432.8A CN202010011432A CN112466831A CN 112466831 A CN112466831 A CN 112466831A CN 202010011432 A CN202010011432 A CN 202010011432A CN 112466831 A CN112466831 A CN 112466831A
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interconnect layer
semiconductor device
device package
interconnect
connection structure
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CN202010011432.8A
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Inventor
凃顺财
罗培仁
谢丰任
翁承恩
黄敏龙
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112466831A publication Critical patent/CN112466831A/zh
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Abstract

本发明涉及一种半导体装置封装及其制造方法，所述半导体装置封装包含：连接结构，其具有第一部分以及从所述第一部分延伸的第二部分，所述第二部分具有小于所述第一部分的宽度；以及介电层，其围绕所述连接结构，其中所述介电层和所述连接结构的所述第二部分限定空间。

Description

半导体装置封装及其制造方法
技术领域
除了别的之外，本发明涉及半导体装置封装及其制造方法。
背景技术
半导体装置封装可包含堆叠到彼此的一些半导体装置。混合接合技术可用于形成半导体装置封装，所述混合接合技术可以指涉及两种或大于两种材料的接合(例如，cu到cu接合以及介电质到介电质接合)。然而，在热循环期间或在热循环之后两种或大于两种材料的热膨胀系数(CTE)不匹配可能引起分层问题(例如，分层发生在两个介电层的交接面上)，这不利地影响半导体装置封装的可靠性或性能。
发明内容
根据本公开的一些实例实施例，半导体装置封装包含连接结构和介电层。连接结构具有第一部分以及从第一部分延伸的第二部分。第二部分具有小于第一部分的宽度。介电层围绕连接结构。介电层和连接结构的第二部分限定空间。
根据本公开的一些实例实施例，半导体装置封装包含连接结构和介电层。连接结构具有第一部分以及安置在第一部分上的第二部分。介电层暴露连接结构的第一部分的上表面的部分。介电层和连接结构的第一部分的上表面的暴露的部分限定空间。
根据本公开的一些实例实施例，制造半导体装置封装的方法包含：在衬底上形成连接结构的第一部分；在第一部分上形成连接结构的第二部分；以及形成介电层以围绕连接结构并且通过连接结构来限定空间。
附图说明
当结合附图阅读时，从以下详细描述容易理解本发明的方面。应注意，各种特征可能并不按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各种特征的尺寸。
图1A是根据本发明的一些实施例的半导体装置的截面图。
图1B是如图1A中所示的连接结构的放大视图。
图1C是如图1A中所示的连接结构的放大视图。
图1D说明了如图1C中所示的连接结构的晶格方向。
图1E是根据本发明的一些实施例的半导体装置封装的截面图。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K、图2L、图2M、图2N、图2O和图2P说明了根据本申请的一些实施例用于制造半导体装置封装的方法的各个阶段。
图3A是根据本发明的一些实施例的另一半导体装置的截面图。
图3B是如图3A中所示的连接结构的放大视图。
图3C是如图3A中所示的连接结构的放大视图。
图3D说明了如图3C中所示的连接结构的晶格方向。
图3E是根据本发明的一些实施例的另一半导体装置封装的截面图。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I、图4J、图4K、图4L、图4M、图4N、图4O和图4P说明了根据本申请的一些实施例用于制造半导体装置封装的方法的各个阶段。
图5A是根据本发明的一些实施例的另一连接结构的截面图。
图5B是根据本发明的一些实施例的另一连接结构的截面图。
图5C是根据本发明的一些实施例的另一连接结构的截面图。
贯穿图式和详细描述使用共同参考标号来指示相同或类似元件。根据以下结合附图作出的详细描述，本发明将更加显而易见。
具体实施方式
以下公开内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例。当然，这些仅是实例且并不意图是限制性的。在本发明中，在以下描述中对第一特征在第二特征之上或上的形成的参考可包含第一特征与第二特征直接接触形成的实施例，并且还可包含额外特征可形成于第一特征与第二特征之间从而使得第一特征与第二特征可能不直接接触的实施例。另外，本发明可能在各种实例中重复参考标号和/或字母。此重复是出于简单和清晰的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
下文详细论述本发明的实施例。然而，应了解，本发明提供了可在多种多样的特定情境中实施的许多适用的概念。所论述的特定实施例仅仅是说明性的且并不限制本发明的范围。
图1A是根据本发明的一些实施例的半导体装置1A的截面图。
参考图1A，半导体装置1A可包含例如但不限于微控制器(MCU)、微处理器(例如，单核或多核)、存储器装置、存储器控制器、芯片组、图形装置、高带宽存储器(HBM)，或专用集成电路(ASIC)等。
半导体装置1A可包含载体10a、一些连接结构1a和介电层12。
载体10a可包含半导体材料、玻璃或其它合适的材料。
载体10a可包含电连接到连接结构1a的电路(未在图1A中示出)。载体10a可包含电连接到连接结构1a的再分布层(RDL)结构(未在图1A中示出)。半导体衬底10a可包含电连接到连接结构1a的导电衬垫、迹线或通孔(未在图1A中出)。
连接结构1a可包含导电材料，例如但不限于，铜(Cu)、金(Au)、铝(Al)，或其它合适的材料。
连接结构1a可以由介电层12围绕。连接结构1a可以由介电层12包围。
连接结构1a可以由介电层12覆盖。连接结构1a可以由介电层12部分地覆盖。
连接结构1a可以嵌入在介电层12内。连接结构1a可以彼此分离或间隔开。连接结构1a可以按一定距离与另一连接结构1a分离。连接结构1a可以通过介电层12分离或间隔开。
连接结构1a可包含两个部分14a和14b。部分14a可以形成或安置在载体10a上。部分14b可以形成或安置在部分14a上。部分14a和14b可以具有不同宽度。部分14a可以具有大于部分14b的宽度。
部分14a可包含上表面(未在图1A中表示)、下表面(未在图1A中表示)以及在上表面与下表面之间延伸的横向表面(未在图1A中表示)。部分14a的下表面可以与载体10a直接接触。部分14a的横向表面可以与介电层12直接接触。部分14a的上表面可以与部分14b直接接触。部分14a的上表面可以是暴露的。部分14a的上表面可以与介电层12直接接触。
部分14b可包含上表面(未在图1A中表示)、下表面(未在图1A中表示)以及在上表面与下表面之间延伸的横向表面(未在图1A中表示)。部分14b的下表面可以与部分14a直接接触。部分14b的横向表面可以通过空间18与介电层12分离或间隔开。部分14b的横向表面可以是暴露的。部分14b的横向表面可以暴露于空间18。
图1B是如图1A中所示的连接结构1a的放大视图。
参考图1B，连接结构1a可包含两个部分14a和14b。部分14a具有宽度W1，并且部分14b具有宽度W2。宽度W1可以大于宽度W2。
部分14a可包含一些互连层14a1、14a2和14a3。
部分14b可包含一些互连层14b1、14b2和14b3。
互连层14a1、14a2、14a3、14b1、14b2和14b3中的每一个可包含例如但不限于，铝(Al)、铜(Cu)、钛(Ti)、钨(W)或其它合适的材料(例如，金属、合金或非金属导电材料)。
部分14b的部分可以嵌入在部分14a中。举例来说，互连层14b3的部分可以嵌入在部分14a中。
互连层14a1可以具有矩形或类矩形轮廓。互连层14a1可以具有圆形或类圆形轮廓。
互连层14a1可以围绕互连层14b3。互连层14a1可以包围互连层14b3。
互连层14a1可以暴露于空间18。互连层14a1可以暴露于空间18中的空气。互连层14a1可以由介电层12覆盖。互连层14a1可以与介电层12直接接触。
互连层14a2可以具有U形或类U形结构。互连层14a2可包含杯子或类杯子结构。互连层14a2可以围绕互连层14a1。互连层14a2可以包围互连层14a1。互连层14a2可以与互连层14a1直接接触。互连层14a2可以与介电层12直接接触。互连层14a2可以由介电层12覆盖。互连层14a2可以安置在互连层14a1与互连层14a3之间。
互连层14a3可以具有U形或类U形结构。互连层14a3可包含杯子或类杯子结构。互连层14a3可以围绕互连层14a1。互连层14a3可以围绕互连层14a2。互连层14a3可以包围互连层14a1。互连层14a3可以包围互连层14a2。互连层14a3可以与互连层14a2直接接触。互连层14a3可以与介电层12直接接触。互连层14a3可以与载体10a直接接触。互连层14a3可以由介电层12覆盖。互连层14a3可以安置在互连层14a2与介电层12之间。
互连层14b2可以形成或安置在互连层14b3上。互连层14b1可以形成或安置在互连层14b2上。互连层14b1可以具有基本上与互连层14b2相同的宽度。互连层14b1可以具有基本上与互连层14b3相同的宽度。
互连层14a1的上表面S1的部分S11可以通过介电层12暴露。互连层14a1的上表面S1的部分S11可以暴露于空间18。互连层14a1的上表面S1的部分S12可以由介电层12覆盖。互连层14a1的上表面S1的部分S12可以与介电层12直接接触。
互连层14b2的横向表面可以暴露于空间18。互连层14b2的横向表面可以与空间18中的空气直接接触。互连层14b1的横向表面可以暴露于空间18。互连层14b1的横向表面可以与空间18中的空气直接接触。
空间18可以是真空的。在空间18中可存在空气。空间18可以通过互连层14a1的上表面S1的部分S11、互连层14b1的横向表面、互连层14b2的横向表面以及介电层12的横向表面限定或围绕。空间18的边界可以通过互连层14a1的上表面S1的部分S11、互连层14b1的横向表面、互连层14b2的横向表面以及介电层12的横向表面形成或限定。
图1C是如图1A中所示的连接结构1a的放大视图。
参考图1C，连接结构1a类似于如参考图1B所说明和描述的连接结构1a，不同之处在于互连层14b3可以由互连层14a1围绕。整个互连层14b3可以由互连层14a1围绕。互连层14b3可以由互连层14a1包围。整个互连层14b3可以由互连层14a1包围。互连层14b3可以嵌入在互连层14a1内。整个互连层14b3可以嵌入在互连层14a1内。互连层14a1的上表面可以与互连层14b3的上表面基本上共面。
图1D说明了如图1C中所示的连接结构的晶格方向。
参考图1D，互连层14b1可以具有晶体结构。互连层14b1可以具有如通过箭头D1表示的结晶方向或晶格方向。结晶方向或晶格方向D1可包含(111)的方向(米勒指数)。
图1E是根据本发明的一些实施例的半导体装置封装1的截面图。
参考图1E，半导体装置封装1可包含两个半导体装置1A和1B。半导体装置1A可包含在载体10a上的多个连接结构1a。半导体装置1B可包含在载体10b上的多个连接结构1b。
半导体装置1B可以与半导体装置1A相同或类似。半导体装置1B可以不同于半导体装置1A。
连接结构1b可以与连接结构1a相同或类似。连接结构1b可以不同于连接结构1a。
混合接合技术可用于形成半导体装置封装1。半导体装置封装1可以通过加热和压缩操作形成。混合接合可以指涉及两种或大于两种材料的接合(例如，金属到金属接合以及介电质到介电质接合)。连接结构1a的互连层(例如，互连层14b1)可以接合到连接结构1b的互连层(例如，互连层14b1)。连接结构1a的介电层12可以接合到连接结构1b的介电层12。
半导体装置1A可包含具有如图1D中所示的晶格方向的互连结构1a。半导体装置1B可包含具有如图1D中所示的晶格方向的互连结构1b。半导体装置1A的互连层14b1与半导体装置1B的互连层14b1之间的接合可以在相对较低的温度下执行或实现，原因是其晶格方向(例如，(111)方向)。换句话说，需要相对较少的热量以将半导体装置1A的互连层14b1接合到半导体装置1B的互连层14b1。
与介电层12相比具有相对较大热膨胀系数(CTE)的互连层14b可以通过空间18安置成远离介电层12。空间18可充当缓冲区，使得由在热循环期间或在热循环之后的CTE不匹配产生的可靠性问题(例如，分层问题)可以得到缓和或缓解。
举例来说，可以由加热和压缩操作产生的张应力TS在加热和压缩操作之后可仍然在介电层12中。残余的张应力TS可以从下部介电层12剥离上部介电层12。然而，具有与互连层14b相比相对较大的宽度的互连层14a可以充当可以抵抗张应力TS的支撑结构。换句话说，可以避免可发生或出现在上部介电层12与下部介电层12之间的交接面(或边界)处的分层。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K、图2L、图2M、图2N、图2O和图2P说明了根据本申请的一些实施例用于制造半导体装置封装1的方法的各个阶段。
参考图2A，介电层12a可以形成或沉积载体10a。介电层12a可以通过例如但不限于溅镀、沉积(例如，化学气相沉积(CVD))技术或其它合适的技术来形成。介电层12a可包含例如但不限于氧化硅或其它合适的材料。
参考图2B，经图案化掩模13a可以形成在介电层12a上以暴露介电层12a。经图案化掩模(或光掩模)13a可包含例如但不限于光阻剂(PR)材料或其它合适的材料。经图案化掩模12a可以通过例如但不限于光刻技术(其可涉及涂覆、曝光、显影)或其它合适的技术来形成。
参考图2C，可以移除未由经图案化掩模13a覆盖的介电层12a的部分。移除操作可通过例如但不限于蚀刻(例如，干式蚀刻)技术或其它合适的技术来执行。
参考图2D，可以移除经图案化掩模13a。经图案化掩模13a可以通过例如但不限于分割法、蚀刻或其它合适的技术来移除。
参考图2E，互连层14a2可以形成在介电层12a和载体10a的安置好的部分上。互连层14a1可以形成在互连层14a2上。可以进一步包含互连层14a3(未在图2E中表示)以围绕互连层14a3。
互连层14a1和14a2可以通过例如但不限于溅镀、沉积(例如，物理气相沉积(PVD))或其它合适的技术来形成。互连层14a1和14a2可以通过例如但不限于蚀刻或其它合适的技术来形成。
参考图2F，可以执行平坦化操作以暴露互连层14a2。平坦化操作可以通过例如但不限于化学机械抛光(CMP)、研磨、干式抛光、蚀刻或其它合适的技术来形成。
参考图2G，介电层12b可以相应地形成或沉积。介电层12b可以通过例如但不限于溅镀、沉积(例如，化学气相沉积(CVD))技术或其它合适的技术来形成。介电层12b可包含例如但不限于氧化硅或其它合适材料。
参考图2H，经图案化掩模13b可以形成在介电层12上以暴露介电层12。经图案化掩模(或光掩模)13b可包含例如但不限于光阻剂(PR)材料或其它合适的材料。经图案化掩模13b可以通过例如但不限于光刻技术(其可涉及涂覆、曝光、显影)或其它合适的技术来形成。
参考图2I，可以移除未由经图案化掩模13b覆盖的介电层12的部分。移除操作可通过例如但不限于蚀刻(例如，干式蚀刻)技术或其它合适的技术来执行。
参考图2J，可以移除经图案化掩模13b。经图案化掩模13b可以通过例如但不限于分割法、蚀刻或其它合适的技术来移除。
参考图2K，互连层14b2可以形成在介电层12和互连层41a1的安置好的部分上。互连层14b2可以通过例如但不限于溅镀、沉积(例如，物理气相沉积(PVD))或其它合适的技术来形成。
参考图2L，经图案化掩模13c可以形成在互连层14b2上以暴露互连层14b2。经图案化掩模(或光掩模)13b可包含例如但不限于光阻剂(PR)材料或其它合适的材料。经图案化掩模13c可以通过例如但不限于光刻技术(其可涉及涂覆、曝光、显影)或其它合适的技术来形成。
参考图2M，互连层14b1可以形成在介电层12上并且由经图案化掩模13c围绕。互连层14b1可以通过例如但不限于溅镀、沉积(例如，物理气相沉积(PVD))或其它合适的技术来形成。
参考图2N，可以移除经图案化掩模13c。经图案化掩模13c可以通过例如但不限于分割法、蚀刻或其它合适的技术来移除。
参考图2O，可以移除未由互连层14b1覆盖的互连层14b2的部分。移除操作可通过例如但不限于蚀刻(例如，干式蚀刻)技术或其它合适的技术来执行。
参考图2P，可以执行平坦化操作使得互连层14b1可以与介电层12基本上共面。平坦化操作可以通过例如但不限于化学机械抛光(CMP)、研磨、干式抛光、蚀刻或其它合适的技术来形成。
图3A是根据本发明的一些实施例的另一半导体封装1A的截面图。
参考图3A，根据若干不同实施例，半导体装置1A可包含例如但不限于微控制器(MCU)、微处理器(例如，单核或多核)、存储器装置、存储器控制器、芯片组、图形装置、高带宽存储器(HBM)，或专用集成电路(ASIC)。
半导体装置1A可包含载体10a、一些连接结构1a和介电层12。
载体10a可包含半导体材料、玻璃或其它合适的材料。
载体10a可包含电连接到连接结构1a的电路(未在图3A中示出)。载体10a可包含电连接到连接结构1a的再分布层(RDL)结构(未在图3A中示出)。半导体衬底10a可包含电连接到连接结构1a的导电衬垫、迹线或通孔(未在图3A中示出)。
连接结构1a可包含导电材料，例如但不限于，铜(Cu)、金(Au)、铝(Al)，或其它合适的材料。
连接结构1a可以由介电层12围绕。连接结构1a可以由介电层12包围。
连接结构1a可以由介电层12覆盖。连接结构1a可以由介电层12部分地覆盖。
连接结构1a可以嵌入在介电层12内。连接结构1a可以彼此分离或间隔开。连接结构1a可以按一定距离与另一连接结构1a分离。连接结构1a可以通过介电层12分离或间隔开。
连接结构1a可包含两个部分14a和14b。部分14a可以形成或安置在载体10a上。部分14b可以形成或安置在部分14a上。部分14a和14b可以具有不同宽度。部分14a可以具有大于部分14b的宽度。
部分14a可包含上表面(未在图3A中表示)、下表面(未在图3A中表示)以及在上表面与下表面之间延伸的横向表面(未在图3A中表示)。部分14a的下表面可以与载体10a直接接触。部分14a的横向表面可以与介电层12直接接触。部分14a的上表面可以与部分14b直接接触。部分14a的上表面可以是暴露的。部分14a的上表面可以与介电层12直接接触。
部分14b可包含上表面(未在图3A中表示)、下表面(未在图3A中表示)以及在上表面与下表面之间延伸的横向表面(未在图3A中表示)。部分14b的下表面可以与部分14a直接接触。部分14b的横向表面可以通过空间18与介电层12分离或间隔开。部分14b的横向表面可以是暴露的。部分14b的横向表面可以暴露于空间18。
图3B是如图3A中所示的连接结构1a的放大视图。
参考图3B，连接结构1a可包含两个部分14a和14b。部分14a具有宽度W1，并且部分14b具有宽度W2。宽度W1可以大于宽度W2。
部分14a可包含一些互连层14a1、14a2和14a3。
部分14b可包含一些互连层14b1、14b2和14b3。
互连层14a1、14a2、14a3、14b1、14b2和14b3中的每一个可包含例如但不限于，铝(Al)、铜(Cu)、钛(Ti)、钨(W)或其它合适的材料(例如，金属、合金或非金属导电材料)。
互连层14a1可以具有矩形或类矩形轮廓。互连层14a1可以具有圆形或类圆形轮廓。
互连层14a1可以暴露于空间18。互连层14a1可以暴露于空间18中的空气。互连层14a1可以由介电层12覆盖。互连层14a1可以与介电层12直接接触。
互连层14a2可以具有U形或类U形结构。互连层14a2可包含杯子或类杯子结构。互连层14a2可以围绕互连层14a1。互连层14a2可以包围互连层14a1。互连层14a2可以与互连层14a1直接接触。互连层14a2可以与介电层12直接接触。互连层14a2可以由介电层12覆盖。互连层14a2可以安置在互连层14a1与互连层14a3之间。
互连层14a3可以具有U形或类U形结构。互连层14a3可包含杯子或类杯子结构。互连层14a3可以围绕互连层14a1。互连层14a3可以围绕互连层14a2。互连层14a3可以包围互连层14a1。互连层14a3可以包围互连层14a2。互连层14a3可以与互连层14a2直接接触。互连层14a3可以与介电层12直接接触。互连层14a3可以与载体10a直接接触。互连层14a3可以由介电层12覆盖。互连层14a3可以安置在互连层14a2与介电层12之间。
互连层14a1的上表面S1的部分S11可以通过介电层12暴露。互连层14a1的上表面S1的部分S11可以暴露于空间18。互连层14a1的上表面S1的部分S12可以由介电层12覆盖。互连层14a1的上表面S1的部分S12可以与介电层12直接接触。
互连层14b1可以具有矩形或类矩形轮廓。互连层14b1可以具有圆形或类圆形轮廓。
互连层14b2可以具有U形或类U形结构。互连层14b2可包含杯子或类杯子结构。互连层14b2可以围绕互连层14b1。互连层14b2可以包围互连层14b1。互连层14b2可以与互连层14b1直接接触。互连层14b2可以与互连层14b1直接接触。互连层14b2可以安置在互连层14b1与互连层14b3之间。
互连层14b3可以具有U形或类U形结构。互连层14b3可包含杯子或类杯子结构。互连层14b3可以围绕互连层14b1。互连层14b3可以围绕互连层14b2。互连层14b3可以包围互连层14b1。互连层14b3可以包围互连层14b2。互连层14b3可以与互连层14b2直接接触。互连层14b3可以安置在互连层14b2与空间18之间。
互连层14b3的横向表面可以暴露于空间18。空间18可以是真空的。在空间18中可存在空气。互连层14b3的横向表面可以与空间18中的空气直接接触。空间18可以通过互连层14a1的上表面S1的部分S11、互连层14b3的横向表面以及介电层12的横向表面限定或围绕。空间18的边界可以通过互连层14a1的上表面S1的部分S11、互连层14b3的横向表面以及介电层12的横向表面形成或限定。
图3C是如图3A中所示的连接结构1a的放大视图。参考图3C，连接结构1a类似于如参考图3B所说明和描述的连接结构1a，不同之处在于互连层14a1的上表面S1的部分S11是不均匀的或粗糙的，这是由于通过蚀刻(例如，干式蚀刻)技术或其它合适的技术的过度蚀刻。
参考图3D，连接结构1a类似于如参考图3C所说明和描述的连接结构1a，不同之处在于可以进一步说明互连层14b1的晶格。参考图3D，互连层14b1可以具有晶体结构。互连层14b1可以具有如通过箭头D1表示的结晶方向或晶格方向。结晶方向或晶格方向D1可包含(111)的方向(米勒指数)。互连层14b1的晶格可以朝向来自互连层14b2的至少两个不同方向延伸。互连层14b1的晶格可以沿若干方向D1、D2和D3延伸。
图3E是根据本发明的一些实施例的半导体装置封装1的截面图。半导体装置封装1可包含两个半导体装置1A和1B。联合对1A可包含在载体10a上的多个连接结构1a。联合对1B可包含在载体10b上的多个连接结构1b。
混合接合技术可用于形成半导体装置封装1。混合接合可以指涉及两种或大于两种材料的接合(例如，金属到金属接合以及介电质到介电质接合)。部分1a的互连层可以接合到部分1b的互连层。部分1a的介电层可以接合到部分1b的介电层。
然而，在热循环期间或在热循环之后的两种或大于两种材料的热膨胀系数(CTE)不匹配可能引起分层问题(例如，分层发生在两个介电层的交接面上)，这不利地影响半导体装置封装1的可靠性或性能。
当CTE不匹配发生时，空间18可以用作沟槽或缓冲区。由于CTE不匹配，材料的接触面将不被损坏或降级。因此，在热循环期间，可以防止半导体装置封装1发生分层，方法是在互连层与介电层之间布置空间18。
在热循环期间，由于热膨胀，压缩应力CS可以相应地从部分14a和14b中产生。另一张应力TS可从对应于上述压缩应力CS的介电层中产生。部分14a可以具有大于部分14b的宽度。部分14a的上表面和横向表面直接地接触介电层12。因此，张应力TS的一部分可以通过部分14a的压缩应力CS得到抵消或补偿。因此，可以进一步减少分层或降级。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I、图4J、图4K、图4L、图4M、图4N、图4O和图4P说明根据本申请的一些实施例用于制造半导体装置封装1的方法的各个阶段。图4A到图4K类似于如参考图2A到图2K所说明和描述的那些，并且将不再进一步说明。
参考图4K，可以相应地形成或沉积互连层14b2。互连层14b2可以通过例如但不限于溅镀、沉积(例如，物理气相沉积(PVD))或其它合适的技术来形成。
参考图4L，互连层14b1可以形成在互连层14b2上。互连层14b1可以通过例如但不限于溅镀、沉积(例如，物理气相沉积(PVD))或其它合适的技术来形成。
参考图4M，可以执行平坦化操作以暴露互连层14b2和介电层12。平坦化操作可以通过例如但不限于化学机械抛光(CMP)、研磨、干式抛光、蚀刻或其它合适的技术来形成。
参考图4N，经图案化掩模13c可以形成在介电层12上以暴露互连层14b1和14b2。经图案化掩模(或光掩模)13c可包含例如但不限于光阻剂(PR)材料或其它合适的材料。经图案化掩模12c可以通过例如但不限于光刻技术(其可能涉及涂覆、曝光、显影)或其它合适的技术来形成。
参考图4O，可以移除未由经图案化掩模13c覆盖的介电层12的部分。移除操作可通过例如但不限于蚀刻(例如，干式蚀刻)技术或其它合适的技术来执行。
参考图4P，可以执行平坦化操作，使得互连层14b1和14b2可以与介电层12基本上共面。平坦化操作可以通过例如但不限于化学机械抛光(CMP)、研磨、干式抛光、蚀刻或其它合适的技术来形成。
图5A是根据本发明的一些实施例的另一连接结构的截面图。
参考图5A，连接结构2a具有互连结构24a和互连结构24b。互连结构24a具有互连层24a1、24a2和24a3。互连结构24b具有互连层24b1、24b2和24b3。互连结构24a具有与互连结构24b相比相对较小的宽度。
连接结构2a可以通过移除在互连结构24b周围或邻近于互连结构24b的介电层22来形成。然而，相对不均匀的底部表面(例如，限定空间18a的底部表面可以高于限定空间18b的底部表面)可以在介电层22的移除之后形成。
此外，相对粗糙的表面22s可以在介电层22的移除之后形成。分层可以出现在介电层22与互连结构24b(例如，互连结构24b3)之间的交接面处。
图5B是根据本发明的一些实施例的另一连接结构的截面图。
参考图5B，连接结构2a'可以通过与制造如图5A中所示的连接结构2a类似的过程形成，不同之处在于仅导电材料被移除但是与互连层24b3直接接触的介电层22保留。举例来说，可以移除如图5A中所示的互连结构24b1和互连层24b2的部分以形成互连结构24b1'和互连结构24b2'，而互连层24b3可以保留。互连结构24a具有与互连结构24b'相比相对较小的宽度。
互连层24b3具有与介电层22相比相对较大的CTE。在热循环期间或在热循环之后由于CTE不匹配，分层可以出现在介电层22与互连结构24b(例如，互连结构24b3)之间的交接面处。
图5C是根据本发明的一些实施例的另一连接结构的截面图。
参考图5C，连接结构2a”类似于如参考图5B所描述和说明的连接结构2a'，不同之处在于互连层24b1'被互连层24b1”代替。
如本文中所使用，例如“在……下方”、“低于”、“下部”、“高于”、“上部”、“下部”、“左侧”、“右侧”及类似者的空间相对术语可以在本文中为易于描述而使用以描述如图中所说明的一个元件或特征与另一元件或特征的关系。除了图中所描绘的定向之外，空间相对术语意图涵盖在使用或操作中的装置的不同定向。所述设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的与空间相关的描述词可类似地相应地进行解释。应理解，当一元件被称作“连接到”或“耦合到”另一元件时，其可直接连接或耦合到另一元件，或可存在中间元件。
如本文中所使用，术语“近似地”、“基本上”、“基本”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确地发生的例子以及事件或情况极近似地发生的例子。如本文中相对于给定值或范围所使用，术语“约”通常意味着在给定值或范围的±10％、±5％、±1％或±0.5％内。范围可在本文中表示为自一个端点至另一端点或在两个端点之间。除非另外规定，否则本文中所公开的所有范围包括端点。术语“基本上共面”可指沿同一平面定位的在数微米(μm)内的两个表面，例如，沿着同一平面定位的在10μm内、5μm内、1μm内或0.5μm内。当参考“基本上”相同的数值或特性时，术语可指处于所述值的平均值的±10％、±5％、±1％或±0.5％内的值。
前文概述本发明的若干实施例及细节方面的特征。本发明中描述的实施例可容易地用作用于设计或修改其它过程的基础以及用于执行相同或相似目的和/或获得引入本文中的实施例的相同或相似优点的结构。此类等效构造并不脱离本发明的精神和范围，并且可在不脱离本发明的精神和范围的情况下作出各种改变、替代和变化。

Claims (30)

1.一种半导体装置封装，其包括：
连接结构，其具有第一部分以及从所述第一部分延伸的第二部分，所述第二部分具有小于所述第一部分的宽度；以及
介电层，其围绕所述连接结构，
其中所述介电层和所述连接结构的所述第二部分限定空间。
2.根据权利要求1所述的半导体装置封装，其中所述连接结构的所述第一部分包括第一互连层，并且其中所述第一互连层具有杯子结构。
3.根据权利要求1所述的半导体装置封装，其中所述连接结构的所述第一部分包括第一互连层，并且其中所述第一互连层具有U形或类U形结构。
4.根据权利要求2或3所述的半导体装置封装，其中所述连接结构的所述第一部分包括围绕所述第一互连层的第二互连层。
5.根据权利要求3所述的半导体装置封装，其中所述连接结构的所述第一部分的第一部分由所述介电层覆盖并且所述连接结构的所述第一部分的第二部分通过所述介电层暴露。
6.根据权利要求2所述的半导体装置封装，其中所述连接结构的所述第一部分的所述第二部分、所述介电层和所述连接结构的所述第二部分限定所述空间。
7.根据权利要求2所述的半导体装置封装，其中所述第二部分包括第三互连层和第四互连层，并且所述第三互连层形成在所述第四互连层上。
8.根据权利要求7所述的半导体装置封装，其中所述第四互连层的一部分由所述第一互连层围绕。
9.根据权利要求7所述的半导体装置封装，其中所述第三互连层的横向表面的至少一个部分与所述空间接触。
10.根据权利要求9所述的半导体装置封装，其中所述第二部分进一步包括在所述第三互连层上的第五互连层，并且所述第五互连层的晶格朝向来自所述第三互连层的方向延伸。
11.根据权利要求10所述的半导体装置封装，其中所述方向是(111)方向。
12.根据权利要求7所述的半导体装置封装，其中所述第三互连层具有U形或类U形结构。
13.根据权利要求7所述的半导体装置封装，其中所述第二部分进一步包括在所述第三互连层上的第五互连层，并且所述第五互连层的晶格朝向来自所述第三互连层的至少两个不同方向延伸。
14.一种半导体装置封装，其包括：
连接结构，其具有第一部分以及安置在所述第一部分上的第二部分；以及
介电层，其暴露所述连接结构的所述第一部分的上表面的部分，
其中所述介电层和所述连接结构的所述第一部分的所述上表面的所述暴露的部分限定空间。
15.根据权利要求14所述的半导体装置封装，其中所述连接结构的所述第一部分包括第一互连层，并且其中所述第一互连层具有杯子结构。
16.根据权利要求14所述的半导体装置封装，其中所述连接结构的所述第一部分包括第一互连层，并且其中所述第一互连层具有U形或类U形结构。
17.根据权利要求15或16所述的半导体装置封装，其中所述连接结构的所述第一部分包括围绕所述第一互连层的第二互连层。
18.根据权利要求16所述的半导体装置封装，其中所述连接结构的所述第一部分的第一部分由所述介电层覆盖并且所述连接结构的所述第一部分的第二部分通过所述介电层暴露。
19.根据权利要求16所述的半导体装置封装，其中所述第一互连层和所述第二互连层的部分由所述介电层覆盖。
20.根据权利要求19所述的半导体装置封装，其中所述第一部分的上表面的一部分接触所述空间。
21.根据权利要求19所述的半导体装置封装，其中所述第二部分包括第三互连层和第四互连层，并且所述第四互连层具有基本上等于所述第五互连层的宽度。
22.根据权利要求21所述的半导体装置封装，其中所述第三互连层的横向表面的至少一部分暴露于所述空间。
23.根据权利要求21所述的半导体装置封装，其中所述第五互连层的晶格朝向来自所述第三互连层的方向延伸。
24.根据权利要求19所述的半导体装置封装，其中所述第二部分包括围绕所述第五互连层如同U形或类U形结构的第三互连层和第四互连层。
25.根据权利要求24所述的半导体装置封装，其中所述第四互连层的横向表面暴露于所述空间。
26.根据权利要求24所述的半导体装置封装，其中所述第五互连层的晶格朝向来自所述第三互连层的至少两个不同方向延伸。
27.一种制造半导体装置封装的方法，其包括：
在衬底上形成连接结构的第一部分；
在所述第一部分上形成连接结构的第二部分；以及
形成介电层以围绕所述连接结构并且通过所述连接结构限定空间。
28.根据权利要求27所述的方法，其进一步包括：
形成所述第一部分的第一互连层；以及
形成具有小于所述第一互连层的宽度的所述第二部分的第五互连层。
29.根据权利要求28所述的方法，其中所述第五互连层的横向表面暴露于所述空间。
30.根据权利要求29所述的方法，其进一步包括形成所述第二部分的第三互连层和第四互连层以围绕所述第一互连层如同U形或类U形。
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