CA1213679A - Semiconductor structures and manufacturing methods - Google Patents
Semiconductor structures and manufacturing methodsInfo
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- CA1213679A CA1213679A CA000485449A CA485449A CA1213679A CA 1213679 A CA1213679 A CA 1213679A CA 000485449 A CA000485449 A CA 000485449A CA 485449 A CA485449 A CA 485449A CA 1213679 A CA1213679 A CA 1213679A
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- mesa
- diodes
- layer
- diode
- heat sink
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
Abstract of the Disclosure A plurality of microwave semiconductor devices is pro-vided by plating a thin heat sink layer on a surface of a wafer of semiconductor material, masking selected portions of the heat sink layer, and plating unmasked portions of the heat sink layer to form a support layer. Substantial portions of the semiconductor material are removed to form a plurality of mesa shaped diodes, at least one semiconductor mesa shaped diode being formed in each region of the semiconductor material disposed on the masked portions of the heat sink layer. Thus each mesa shaped diode, or sets of mesa shaped diodes, has formed on one surface thereof a thin heat sink layer while the mesa shaped diodes are supported by the support layer for subsequent processing. Upper electrodes for the diodes are formed interconnecting the mesa shaped diodes. The individual diodes, or sets thereof, are then separated from the support structure to provide individual single diode, or multiple diode devices.
Abstract of the Disclosure A plurality of microwave semiconductor devices is pro-vided by plating a thin heat sink layer on a surface of a wafer of semiconductor material, masking selected portions of the heat sink layer, and plating unmasked portions of the heat sink layer to form a support layer. Substantial portions of the semiconductor material are removed to form a plurality of mesa shaped diodes, at least one semiconductor mesa shaped diode being formed in each region of the semiconductor material disposed on the masked portions of the heat sink layer. Thus each mesa shaped diode, or sets of mesa shaped diodes, has formed on one surface thereof a thin heat sink layer while the mesa shaped diodes are supported by the support layer for subsequent processing. Upper electrodes for the diodes are formed interconnecting the mesa shaped diodes. The individual diodes, or sets thereof, are then separated from the support structure to provide individual single diode, or multiple diode devices.
Description
~213~
This is a divisional application of copending Canadian patent application Serial No. 414,043 filed October 22, 1982, assigned to Raytheon Company.
This invention relates yenerally to semiconductor de~ices and more particularly to semiconductor devices adapted to operate with high levels of microwave power.
As is known in the art, it is frequently desirable to use microwave diodes in a variety of high power applications.
When used in such applications the diode may be mounted to a pedestal shaped heat sink used to extract heat from the diode.
Further, in the fabrication of individually mesa shaped diodes, prior to dicing the wafer into individual diodes a wafer used to form such diodes has disposed on the entire back surface thereof a thick plated heat sink. After separating the diodes thls thick plated heat sink is mounted to the pedestal shaped heat sink. When the material of the pedestal heat sink has a higher thermal conductivity than the material of the thick plated heat sink forming part of the mesa shaped diode, it is desirable to minimize the thickness of the thick plated heat sink in order to minimize the thermal resistance of the diode. However, a thick plated heat sink generally is required to provide structural integrity to the wafer after the diodes have been formed into mesas. This is because after mesa definition, the wafer of mesa shaped diodes is supported only by the gold plated heat sink structure and further photo-lithographic steps and processing steps are still generally required after the mesa definition. Therefore, if the heat sink is too thin the structure supporting the mesa shaped diodes may flex, bend, or crease making it difficult to handle during the additional photolithographic and processing 12~3~
steps, thus resulting in lower device yields.
As also known in the art, a critical step in the assembly of microwave power diodes is the step of mounting the diode in a microwave package and the subsequent interconnection of the diode to the package terminals. Generally, the inter-connection is accomplished by soldering the plated heat sink into the package to form a first contact and using a wire pre-form attached to the top of -the mesa shape diode as a second contact. The wire preform is typically ultrasonically bonded to the top of the mesa shaped diode. This packaging technique has several short comings, however, particularly when applied to millimeter wave diodes. The mesas shaped millimeter wave diodes are comparatively small and fragile compared to X-band diodes, for example. This imposes several constraints on the bondiny operations and the preform lead wires: bonding forces and ultrasonic power must be kept to a minimum, often producing a bond of questionable strength, bonding tool diameters must be small in order to avoid excessive force on the mesas tops and damage by off center bonds, and lead preforms are difficult to precisely shape leading to unpredictable package parasitics, resulting in degraded device performance~ Moreover, lead bonding is a costly and time consuming process requiring a high degree of bonding operator skill.
As is also known in the art, it is frequently desir-able to use a plurality of individual mesa-shaped diodes with the mesa shaped diodes having a total area equal to an equival-ent single mesa shaped diode. A plurality of individual diodes adapted to operate at X-band may be individually mounted in a package. However when the diodes are designed to operate at multimeter wavelengths, for example, their size is so small ~213~
that mounting them individually to provide a plurality of diodes in such a package is difficult.
In accordance with one aspect of the invention a wafer including a plurality of mesa shaped diodes, each having a thin plated heat sink attached to one surface thereof, is supported, for metallization processing by a thicker support structure having a plurality of apertures, such apertures defining the areas of the thin plated heat sink. After metallization and subsequent dicing each diode device has a relatively thin plated heat sink. The diode device thus will have a lower thermal resistance than diode devices having thicker plated heat sinks, a feature particularly desirable when the diode device is mounted on a material having a higher thermal conductivity than that of the plated heat sink. The support structure pro-vides the necessary structural integrity to the plurality of mesa diodes for the metallization processing. In addition, the apertures provided in the thick support may be used to align a dicing mask used for dicing the wafer into individual mesa shaped diode devices.
In accordance with another aspect of the invention a multi-mesa shaped diode device is provided having an upper elec-trode formed by depositing a layer of photoresist over top sur-faces of the diodes forming a plurality of apertures in the photoresist layer aligned with the top surfaces of the mesa shap-ed diodes, substantially levelling the photoresist layer to the top surfaces of the mesa shaped diodes, providing a layer of an adherent material on the photoresist layer, and providing a layer of a conductive material on the adherent layer. A
plurality of apertures having a diameter smaller than the corresponding diameter of the top surfaces of the mesa shaped ~LZ~ r~oi~3 diodes is formed through the adherent layer and layer of con-ductive material. A second layer of photoresist is then provided which defines an upper electrode pattern such as over-lay or beam lead pattern. The electrode pattern is then plated directly to the top surfaces of the diodes thus forming the upper electrode pattern for the device. With such a structure a multi-mesa diode device having a top electrode pattern on a top surface thereof interconnecting each of the individual mesa shaped diodes is realized. The top electrode pattern provides support for the multi-mesa diode structure after dicing. During packaging, the top electrode pattern provies a lead pattern which can be made thicker, wider and heavier than that used with ultrasonically bonded preform leads thereby reducing the series, resistance and inductance of the diode.
Further a multi-diode device adapted to operate at multimeter wavelengths may be easily packaged since the plurality of diodes are integrally formed as a single device.
In accordance with one aspect of the invention a multimesa diode device having a thin heat sink attached to one surface of each mesa shaped diode and an upper electrode attach-ed to a second surface thereof is provided by: plating a heat sink layer on a surface of a wafer of semiconductor material;
masking selected portions of the plated heat sink layer; and plating the unmasked portions of the layer to increase the thick-ness thereof to provide a support layer. A plurality of multi-mesa diodes are formed in regions of the semiconductor material disposed on the masked portions of the plated heat sink layer Upper electrodes used to support the multimesa diode of the device after dicing of the wafer are provided by: depositing a layer of photoresist on the heat sink layer and the mesa shaped diodes; providing apertures in the photoresist layer; levelling ~Zl;3Çi ~'9 the photoresist layer to the mesa tops; providing a metaliza-tion layer on the photoresist layer; and providing a plurality of undersized apertures in the metalization layer aligned with the mesa tops. A second layer of photoresist is then provided on the metalization layer and is patterned to expose portions of the metalization layerO The upper electrodes are then plated directly onto por~ions of the metalization layer ex-posed by the photoresist layer. The photoresist layers and metalization layer are removed and the multimesa diode devices are diced apart. With such an arrangement a multimesa diode device is provided with a thin heat sink on one surface and a top electrode on the second surface. The thermal transfer advantages of the multimesa diode device are thus realized without the packaging and handling difficulties generally asso-ciated with individual diodes.
Broadly, according to one broad aspect, the invention of this divisional application provides a semiconductor device comprising: a mesa-shaped diode having upper and lower mesa portions; a first electrode contact disposed on a first one of upper and lower mesa portions of said mesa~shaped diode;
and a second electrode contact comprising a thermally conduc-tive material having a thickness in the range of one micron to two microns disposed on a second, different one of upper and lower mesa portions of the mesa-shaped diode, with said second electrode contact providing a heat sink portion of said mesa-shaped diode.
According to another broad aspect, the invention pro-vides a semiconductor device comprising: a plurality of mesa-shaped diodes, each mesa having upper and lower mesa portions and each interconnected by a first electrode contact disposed lZ13~
on a corresponding first one of upper and lower mesa portions of said plurality of mesa-shaped diodes; and a plurality of second electrode contacts comprising a thermally conductive material having a thickness in the range of one micron to two microns disposed on a corresponding second, different one of upper and lower mesa portions of each of said mesa-shaped diodes, with said second electrode contacts each providing a heat sink portion of the corresponding mesa-shaped diode.
-5a-12~36~9 Brief Description of the Drawings For a better understanding of the invention, reference is made in the following detailed description to the drawings wherein:
FIGS. 1-4 are a series of fragmentary isometric cross-sectional views showing steps in the construction of single mesa shaped diode device having a thin heat sink layer in accordance within the invention;
FIG. 5A is a cross-sectional view useful in under-standing a dicing operation of a wafer of diodes having the thin heat sink layer provided in accordance with Figs. 1-4;
FIG. 5B is a top view of the cross-sectional view of Fig. SA showing the photoresist pattern used in the dicing step;
FIG. 5C is a cross-sectional view of a mesa shaped diode having a heat sink in accordance with the invention;
FIGS. 6-8 are a series of fragmentary isometric partially broken away views showing steps in the construction of a multimesa diode device having a thin heat sink layer and beam leads;
FIG. 9 is a isometric view of a multimesa diode device constructed in accordance with Figs. 6-~ having thin heat sink layer and beam leads;
FIG. 10 is a fragmentary isometric partially broken away view showing the diode cluster of Fig. 7 with a first layer of photoresist used in fabricating interconnect patterns in accordance with the invention;
FIGS. 11-13 are a series of cross-sectional views showing steps in the construction of the interconnect patterns;
FIGS. 14-15 are a series of fragmentary isometric partially 3~9 bro~en away views showing the steps in the construction of an overlay in accordance with the invention on a wafer at the stage of processing shown in Fi~. 13;
FIG. l~A is a isometric view of a plurality of diodes interconnected by a overlay in accordance with the invention.
FIGS. 16-17 are a series of fragmentary isometric partially broken away views showing the steps in the con-struction of beam leads, for a single mesa diode device in accordance with the invention;
FIG. 17~ is an isometric view of a diode device having a beam lead pattern in accordance with the invention;
FIG. 18 is a top view of an interdigitated beam lead pa~tern;
FIG. 19 is a cross sectional view of a single mesa diode device having a thin heat sink layer and beam leads, mounted in a ceramic ring package in accordance with the invention;
and FIG. 20 is a cross-sectional view of a multimesa diode device having a thin heatsink and overlays mounted in a ceramic ring package in accordance with the invention.
12~3~*79 Description of the Preferred Embodiments -Construction of semiconductor devices having thin heat sink layers in accordance with the teachings of the present invention will be described in conjunction with the isometric cross-sectional views of Figs. 1 through 4. Referring first to Fig. 1, a substrate 25, here conductive gallium arsenide (GaAs~, is shown to include an active layer 24 of epitaxially grown semiconductor GaAs. Active layer 24 may have one of many different doping density profiles depending upon the particular application for the diode. here, for example, a doping density profile described in my U. S. Patent 4,160,992 issued July 10, 1979 and assigned to the assignee oL this invention is used. A first metal layer 26, here of platinum (Pt), is sputtered upon the active layer 24 to a thickness in the range of 10~ Angstroms to 200 Angstoms ~A). A second metal layer 28, here of titanium (Ti), is then sputtered over the platinum layer 26 to a thickness of 1000 A to 2000 A. Titanium is the preferred material although tungsten, hafninum, or other refractory metals may be used for layer 28. Upon the layer 28 a 1000 A to 2000 A thick layer 29 of highly conductive gold is evaporated, forming the lower contact for the diode device. Next, a thermally and electrically conductive heat sink layer 30, here of gold one to two microns thick, is plated over evaporated gold layer 29. A layer 31 of photoresist is then deposited on the plated gold layer 30, as shown.
Referring now to Fig. 2, the photoresist layer 31 is masked, developed, and chemically etched away in selective areas using well known photoresist techniques, to leave portions 32, thereof, remaining over selected regions of the plated gold 3n heat sink layer 30, as shown.
~213~9 Now referring to Figure 3, a support layer 36 is formed by plating the unmasked portions of the thin heat sink layer 30 with gold, here to a thickness of ten microns. The regions 32 (Figure 2) of photoresist layer 31 are removed leaving an apertured support layer 36. It is noted that the heat sink layer 30 remains at the original thickness but the support layer 36 is made sufficiently thick to provide struc-tural integrity for -the diodes to be formed in wafer 21 in a manner to be described hereinafter. Suffice it to say here, however, that the support layer 36 has formed therein a plur-ality of apertures 34 corresponding to areas where the photo-resist pattern 32 (Figure 2) was provided. The plurality of apertures 34 define the areas of the thin plated heat sink layer 30.
Referring now also to Figure 4, the substrate 25, is thinned to a predetermined thickness, a plurality of top con-tacts 22 are provided on the top of the thinned substrate 25 and a plurality of mesa shaped diodes 20 are formed from the thinned substrate 25 and active layer 24 between the top contact 22 and platinum layer 26, as shown. Where the doping profile of the active layer 24 is as described in above-mentioned U.S. Patent 4,160,992, the mesa-shaped diodes are IMPATT (impact avalanche transit time) diodes. The plurality of top contacts 22 are formed by first depositing a photo-resist layer (not shown) on the thinned substrate 25. The photoresist layer is masked, developed, and chemically etched away in predetermined locations using well-~nown photoresist techniques leaving a plurality of here circular apertures on the photoresist layer (not shown). Each circular aperture (not shown) is precisely aligned with a corresponding one of 121~ 9 the plurality of apertures 34 in the thick gold plated support 36. The circular apertures (not shown) are then plated with gold forming the previously mentioned top contacts 22. The alignment for the top contacts 22 to the apertures 34 is realized by a front to back alignment -9a-~21367~
step of the top contact mas~ (not shown) used to provide the photoresist pattern for the circular gold contacts 22. A
general front to back alignment procedure is described in U. S.
Patent No. 4,169,992, previously~mentioned. The plurality of mesas diodes 20 are formed between the top contacts 22 and the platinum layer 26. The mesa diodes 20 are formed by providing a pattern in photoresist on the thinned su~strAte 25, using well known photoresist techniques. The alignment of the mesa forming mas~ (not shown~ used in forming the pattern for the mesa diodes 20 is realized by the front to back alignment technique as described in U. S. Patent No. 4,169,992, referred to above. After mask alignment, the mesa diodes 20 are formed ~y chemically etching away portions of the thinned substrate 25 and active layer 24 between the the top contact layer 22 and the platinum layer 26, as shown. Thus mesa diodes 20 formed from the thinned substrate 25 and active layer 24 are supported by the support layer 36.
Referring now to Figs. SA and SB, the wafer 21 having a plurality of mesa diodes 20 is mounted on a wafer support 40 with a non-reactive wax 44 filling the space between and around mesa diodes 20 and gold contacts 22, as shown. The wafer 21 with the wax protected mesa diodes 20 is pressed against the upper surface of support 40. A photoresist layer is deposited on the plated support layer 36 of the wafer 21. A dicing mask (not shown) is provided on the plated support layer 36 of the wafer 21, and using well known photoresist techniques, a dicing pattern 38 of photoresist is produced. The apertures 34 in the thick plated support layer 36 are here used to align the dicing mask. The diodes 20 are diced from the wafer 21 within regions 39 provided in the dicing pattern 38 of photoresist.
~213679 The wafer 21 is here placed in a spray etching system of a type described in U. S. Patent 4,160,9~2 mentioned previously.
The spray etch system (not shown) provides an etchant (not shown) which completely etches through the exposed portions 3g of layers 30, 29, 28 and 26 to separate the diode devices from the thick support layer 36. After dlcing, the individual diode devices 46 an exemplary one thereof being shown in Fig. SC, may be collected and cleaned using any well known technique.
Referring now to Fig. 6, a wafer 121, includes a plurality of clusters, or sets, of mesa shaped diodes 42 (each cluster of mesa diodes 42 having a total area equal to a single mesa diode equivalent) formed over a corresponding plurality of apertures 34 provided by the thick plated support 36, as shown. The wa~er 121 is formed in a similar manner as wafer 21 shown in Fig. 4 except during mesa definition a cluster mask (not shown) is provided to produce a pattern in a layer of photoresist corresponding to a plurality of clusters of mesa diodes. This cluster mask (not shown) is front to back aligned as explained in U. S. Patent 4,160,992, previously mentioned. The plurality of the clusters of mesas diodes 42 are formed by chemically etching away portions of the substrate 25 between the top contact layer 22 and the platinum layer 26, as previously explained.
Now referring to Fig. 7, the wafer 121 is placed in a sputter etching system (not shown) and portions of the layer 26 of platinum unmasked by the di~des 20 are removed. A chemical etch here a two percent solution of hydrofloric acid (2~ HF:H2O) is then used to remove portions of layer 28 unmasked by diodes 20. The wafer 121 at this point has the layer 26 of platinum and the layer 28 of titanium removed in all areas except for 6 ~'~
those areas forming part of the individual mesa diodes 20 of each cluster of mesa diodes 42, leaving gold layer 29 exposed on the mesa diode side of the wafer 121. Exposing gold on the mesa diode side of wafer 121 is used to particular advantage in a dicing op~ration to be described in conjunction with Fig.
8 and Fig. 9.
Now referring to Fig. 8 and Fig. 9, beam leads 48 are here shown attached to the cluster of mesa diodes 42 for reasons to be described in cor.nection with Figs. 16-17. Suffice it to say here, however, that the thick plated support layer 36 is used to support the individual mesa diodes 20 at this stage in the processing while the attached gold plated beam leads 48 provide support for the individual mesa diodes 20 during and after the dicing operation. As shown in Fig. 8, gold is exposed on the upper s~rfaces of the wafer 121. A layer of wax 45 is here provided on the bottom side of the wafer 121, completely filling in the apertures 34 of the gold plated support layer 36.
The wafer 121 and wax layer 45 are supported by a wafer support 41. Since gold is exposed on both sides of the wafer 121 a gold etching solution is here used to etch from the mesa diode side of the wafer with the plated heat sink side mounted down.
Here, the wafer 121 is placed in a conventional emersion bath of etchant (not shown). The etchant flows on the mesa side of the wafer 121, but substantially below the tops of the mult-mesa diode device 120, and thus the etchant does not attack the beam leads 48. This technique,uses the mesa shaped diodes 20 themselves as a mask during the dicing procedure. Since the gold layers 29, 30 exposed on the mesa diode side within the aperture 34 of the thick gold plated support layer 36 are substantially thinner than other exposed gold areas, the 12~3Çi7~
portions of the gold in layers 29, 30 disposed over the aperture 34 will etch âway beore other gold areâs of the diode cluster 42 âre significantly disturbed thus forming clusters, or sets, of here four diodes in each device 120 as shown in Fig. 9.
Referring now to Fig. 10, a wafer 121' will be processed in âccordance with an âlternative embodiment of the invention.
Thus, wâfer 121' is shown in Fig. 10 at an equivalent stage of processing âS the wafer 121 shown in Fig. 7, however here wafer 121' is provided with a first thick layer of photores~st 60, as shown. A plurality of apertures 66 aligned with the mesa top contacts 22 are formed in the photoresist 60 to exposure the top contacts 22 using well known photoresist techniques. The photoresist layer 60 is then levelled with the top contacts 22 by conventional techniques such as controlled light exposure or mechanical lapping.
Referring now to Fig. 11, zn adherent layer 62 here of titanium, approximately 200 A thick is sputtered over the to?
of the wafer section 121'. Other metals such as molybedenum, nickel, nickel-chrome and similar metals or metallic systems may be used for the adherent layer 62. A conductive layer 64 here a 200 A thick layer of gold is sputtered over the adherent layer 62 of titanium. Other conductive metals such as platinum, silver and copper may be used for conductive layer 64. The preferred combination, however, is titanium-gold, because this combination provides a contact system virtuâlly alloyless and is not subject to loss of adhesion.
The adherent layer 62 is sputtered within the apertures 66 (Fig. 10) formed in the photoresist 60. The adherent layer 62 provides a contact layer interconnecting the individual diodes 20 (Fig~ 10) in each cluster of diode 42 (Fig. 2).
~2136~
Now to referring to Fig . 12, the wafer 121' is provided with a second layer 68 of photoresist. The layer 68 of photoresist is masked, developed, and etched away in selective areas using well known photoresist techniques to provide a pattern in the photoresist layer 68 of a plurality undersized circular aperatures 67 aligned to the diode top contacts 22.
Referring now to Fig. 13 the first layer 62 and the second layer 64 are selectively removed from the mesa tops 22, within each of the apertures 67 formed in the photoresist layer 68.
A plurality of apertures 69 are thus formed in layers 62 and 64. A thin layer of the first layer 62 and the second layer 64, thus remain attached to the eZges of the mesa tops 22, because the apertures 69 are smaller than the mesa diode top contacts 22. The wafer 121' at this stage of processing may be provided with either a plurality of top electrode contacts su~h as the overlays shown in Fig. 15 or the beam leads shown in Fi~. 17. Selection between the gold overlay pattern (Fig. 15) or the beam lead pattern (Fig. 17) is here primarily determined by the physical size of the mesa diodes.
For example, for X band quadramesa diodes where the mesas are relatively large in comparison to millimeter wave mesas, the use of a beam lead interconnect is here impractical. This is because on a given wafer of semi-insulating material such as GaAs as used here, relatively few beam lead devices can be manufactured for X-band diodès due to the relatively long lengths of the beam leads in relation to the size o the mesa diodes. Here, the gold overlay structure is provided to inter-connect the quadramesas X-band diodes to provide a more eficient interconnection scheme and thus a more efficient utilization of the area of the wafer 121'. However, for - 14 ~
12136~9 millimeter wave quadramesa diodes having relatively small mesas compared to X-band mesa diodes, a dense pattern of beam leads is plated to the mesa diodes to provide the interconnect portion for the mesa diodes. Fabrication of beam leads diodes are described in conjunction with Figs. 16 and 17.
Referring now to Figs. 14 and 15 fabrication of an overlay 70 (Fig. 15) for interconnecting each mesa diode 20 of the cluster of mesa diode 42 in accordance with the invention will now be described. Referring first to Fig. 14, a wafer 121' in the same stage of fabrication as that shown in Fig. 13, is provided with a layer of photoresist 71. The photoresist layer 71 is deposited on the second layer 54 and is masked, developed and etched away in selective locations using well known photo-resist techniques to form a plurality of apertures 72.
Referring now to Fig. 15, the gold overlay 70 is plated to a thickness of here four microns within the areas exposed by the apertures 72. These overlays 70 interconnect each of the diodes 20 within each of the plurality of clusters of diodes 42. Further the overlay provides the support for each diode 20 of the cluster of diodes 42, after dicing. The overlay pattern 70 may be plated to any desired thickness, typically however, the thickness is in the range of four microns to ten microns.
After plating the titanium layer 62, the gold layer 64, the thick photoresist layer 60, and the photoresist pattern 72 are removed from the wafer by conventional means leaving the ~afer, as shown. Since gold is exposed on both sides of the wafer 121', a gold etching solution is here used to etch from the mesa diode side of the wafer 121'. The emersion etching technique described in conjunction with Fig. 8 is here used to dice the wafer 121'. Thus, the quadramesa diodes 12136~9 interconnected by the gold overlay 70 are used as a mask during the dicing operation. Since gold exposed in the region of the aperture 34 of the thick plated support 36 is substantially thinner than other exposed gold areas the gold in the region of the aperture 34 will etch through before other gold areas of the cluster of mesa diodes 42 or the gold overlay 70 are significantly disturbed thereby ~orming four diode devices, an exemplary one thereof~ here device 50, as shown in Fig. 15A.
Fabrication of mesa diodes having plated beam leads 80 is next described in conjunction with Fig. 16 and Fig. 17.
Re~erring first to Fig. 16 a wafer section 21', in the same stage of construction as that shown in Fig. 13, includes a plurality of individual diode elements 20, as shown. The wafer 21' now is provided with a second layer 82 of photoresist.
This photoresist layer 82 is disposed on the second layer 64, and is masked, developed and etched away in selective locations using well known photoresist techniques to form a pattern 84 for the beam leads.
Referring now also to Fig. 17 the ~eam lead pattern 84 is plated to the diodes 20 in the areas exposed within the photo-resist layer 82. The beam lead pattern may be plated to any desired thickness, typically however, the thickness is in the range of four microns to ten microns. The photoresist layer 82, titanium layer 62, the gold layer 64 and the thick photoresist layer 60 are then removed using well known techniques leaving the mesa diodes 20 with plated beam leads 48, as shown. Since gold is exposed on both sides of the wafer 21 a gold etching solution is here used to etched from the mesa diode side of the wafer 21 as previously explained in conjunction with Fig. 8 to separate the diodes into individual devices 52, and 13~79 exemplary one thereof, here device 52, as shown in Fig. 17A.
Alternatively, the overlays 70 or the beam leads 48 may be formed on the diodes after the wafer has been diced, as explained in conjunction wlth Fig. 8. In this case, the wafer having been diced is still supported by a wafer support 41 and a wax layer 45 filling in the apertures 34 o the support 36, as shown in Fig. lS and Fig. 17. The beam lead or overlay interconnect patterns are then formed as explained above, and the diodes with the plated interconnects are then dismounted from the wax 45. This provides a method whereby the inter-connect structure is not exposed to the etchant used in the dicing operation, since the interconnect pattern is no~ present during the wafer dicing step.
Now referring to Fig. 18, a portion of a tightly packed beam lead pattern 84 which may be plated directly to an entire wafer provides a plurality of mesa diodes, as shown. This pattern is provided for interconnecting single mesa or multi-mesa diodes.
Referring again to Figs. 8-9, the beam lead quadramesa diode 120 having the plated beam leads is for~ed in the same manner as the single mesa diode device 52 having plated beam leads, except for the use of a multimesa mask, for defining the diode mesas. The beam lead pattern as shown in Fig. 18 is here also used to provide the pattern of beam leads in photoreslst for the multi-mesa diode.
Referring now ~o Fig. 15, the single mesa diode device 52 having plated beam leads is here mounted in a package 10, as shown. The package 10 includes a conventional stub support 18 here of copper having a screw slot 19, for package mounting.
The stub support 18 here supports a pedestal 16 which is h~re of lZ~L3~9 gold plated diamond. The thicXness of the gold plating on the diàmond pedestal 16 is here 2 microns thick. Alternatively the pedestal 16 may be embedded in the stub support 18 or may be formed from the stub support 18.- A conductive ring 17 here gold plated copper is spaced from the stub 18 by a insulating ring spacer 14. The insulating ring spacer 14 is here ceramic but may be quartz or any other suitable insulating material.
The plated heat sink side of the diode 20 is here mounted to the pedestal 16 by a thermal compression bond. Mounting the diode 88 to the pedestal 16 causes the beam leads 48 to bend upward and extend up toward the edge of the con2uctlve ring 17. Thermal compression bonds are here used to bond each of the beam leads to the conductive ring 17. A conductive lid 19 is then provided to add further support to the package 10.
The lid 19, here gold plated copper is thermal compression bonded to the conductive ring 17 and may form a hermetic seal between ring 17 and lead 19. This structure provides a package 10 wherein a diode 20 having extended beam leads 48 as top electrodes, which are bonded to the conductive ring 17 using a thermal compression bond on the plated leads, without having to bond a lead to the diode mesa itself. Diode package 10 should have lower parasitic capacitance and inductance than other diode packages, thus enhancing the diode's electrical charac-teristics.
Referring now to FIG. 20, a multi-mesa diode device 50 interconnected by an overlay pattern is pac~age in a diode package 90 as shown. The package 90 includes a conventional stub support 18 here of copper having a screw slot 19, for package mounting. The stub support 18 here supports a pedestal 16 which is here of gold plated diamond. Alternatively, the ~213~i79 pedestal 16 may be embedded in the stub support 18 or may be formed from the stub support 18. A conductive flange 13 here gold plated copper is spaced from the stub 18 by an insulating ceramic ring spacer 14. The insulating ring spacer is here ceramic buy may be quartz or any other suitable insulating material. The plated heatsin~ side of the multimesa diode device 50 is here mounted to the pedestal 16 by a thermal compression bond. A gold ribbon strip 15 is then thermally compression bonded to the conductive flange 13 and the overlay 70. A conductive lid 19 is then provided to add further support to the package 10. The lid 19, here gold plated copper is thermal compression bonded to the conductive flange 13 and may form a hermetic seal between flange 13 and lid 19.
From the foregoing, it will be apparent that all of the objectives of this invention have been achieved by the structures shown and described herein. It also will be apparent, however, that various changes may be made by those skilled in the art without departing from the spirit of the invention as expressed in the appended claims. It is to be understood, therefore, that all matter shown and described herein is to be interpreted as illustrative and not in a limiting sense.
DGM:jp Case No. 32784
This is a divisional application of copending Canadian patent application Serial No. 414,043 filed October 22, 1982, assigned to Raytheon Company.
This invention relates yenerally to semiconductor de~ices and more particularly to semiconductor devices adapted to operate with high levels of microwave power.
As is known in the art, it is frequently desirable to use microwave diodes in a variety of high power applications.
When used in such applications the diode may be mounted to a pedestal shaped heat sink used to extract heat from the diode.
Further, in the fabrication of individually mesa shaped diodes, prior to dicing the wafer into individual diodes a wafer used to form such diodes has disposed on the entire back surface thereof a thick plated heat sink. After separating the diodes thls thick plated heat sink is mounted to the pedestal shaped heat sink. When the material of the pedestal heat sink has a higher thermal conductivity than the material of the thick plated heat sink forming part of the mesa shaped diode, it is desirable to minimize the thickness of the thick plated heat sink in order to minimize the thermal resistance of the diode. However, a thick plated heat sink generally is required to provide structural integrity to the wafer after the diodes have been formed into mesas. This is because after mesa definition, the wafer of mesa shaped diodes is supported only by the gold plated heat sink structure and further photo-lithographic steps and processing steps are still generally required after the mesa definition. Therefore, if the heat sink is too thin the structure supporting the mesa shaped diodes may flex, bend, or crease making it difficult to handle during the additional photolithographic and processing 12~3~
steps, thus resulting in lower device yields.
As also known in the art, a critical step in the assembly of microwave power diodes is the step of mounting the diode in a microwave package and the subsequent interconnection of the diode to the package terminals. Generally, the inter-connection is accomplished by soldering the plated heat sink into the package to form a first contact and using a wire pre-form attached to the top of -the mesa shape diode as a second contact. The wire preform is typically ultrasonically bonded to the top of the mesa shaped diode. This packaging technique has several short comings, however, particularly when applied to millimeter wave diodes. The mesas shaped millimeter wave diodes are comparatively small and fragile compared to X-band diodes, for example. This imposes several constraints on the bondiny operations and the preform lead wires: bonding forces and ultrasonic power must be kept to a minimum, often producing a bond of questionable strength, bonding tool diameters must be small in order to avoid excessive force on the mesas tops and damage by off center bonds, and lead preforms are difficult to precisely shape leading to unpredictable package parasitics, resulting in degraded device performance~ Moreover, lead bonding is a costly and time consuming process requiring a high degree of bonding operator skill.
As is also known in the art, it is frequently desir-able to use a plurality of individual mesa-shaped diodes with the mesa shaped diodes having a total area equal to an equival-ent single mesa shaped diode. A plurality of individual diodes adapted to operate at X-band may be individually mounted in a package. However when the diodes are designed to operate at multimeter wavelengths, for example, their size is so small ~213~
that mounting them individually to provide a plurality of diodes in such a package is difficult.
In accordance with one aspect of the invention a wafer including a plurality of mesa shaped diodes, each having a thin plated heat sink attached to one surface thereof, is supported, for metallization processing by a thicker support structure having a plurality of apertures, such apertures defining the areas of the thin plated heat sink. After metallization and subsequent dicing each diode device has a relatively thin plated heat sink. The diode device thus will have a lower thermal resistance than diode devices having thicker plated heat sinks, a feature particularly desirable when the diode device is mounted on a material having a higher thermal conductivity than that of the plated heat sink. The support structure pro-vides the necessary structural integrity to the plurality of mesa diodes for the metallization processing. In addition, the apertures provided in the thick support may be used to align a dicing mask used for dicing the wafer into individual mesa shaped diode devices.
In accordance with another aspect of the invention a multi-mesa shaped diode device is provided having an upper elec-trode formed by depositing a layer of photoresist over top sur-faces of the diodes forming a plurality of apertures in the photoresist layer aligned with the top surfaces of the mesa shap-ed diodes, substantially levelling the photoresist layer to the top surfaces of the mesa shaped diodes, providing a layer of an adherent material on the photoresist layer, and providing a layer of a conductive material on the adherent layer. A
plurality of apertures having a diameter smaller than the corresponding diameter of the top surfaces of the mesa shaped ~LZ~ r~oi~3 diodes is formed through the adherent layer and layer of con-ductive material. A second layer of photoresist is then provided which defines an upper electrode pattern such as over-lay or beam lead pattern. The electrode pattern is then plated directly to the top surfaces of the diodes thus forming the upper electrode pattern for the device. With such a structure a multi-mesa diode device having a top electrode pattern on a top surface thereof interconnecting each of the individual mesa shaped diodes is realized. The top electrode pattern provides support for the multi-mesa diode structure after dicing. During packaging, the top electrode pattern provies a lead pattern which can be made thicker, wider and heavier than that used with ultrasonically bonded preform leads thereby reducing the series, resistance and inductance of the diode.
Further a multi-diode device adapted to operate at multimeter wavelengths may be easily packaged since the plurality of diodes are integrally formed as a single device.
In accordance with one aspect of the invention a multimesa diode device having a thin heat sink attached to one surface of each mesa shaped diode and an upper electrode attach-ed to a second surface thereof is provided by: plating a heat sink layer on a surface of a wafer of semiconductor material;
masking selected portions of the plated heat sink layer; and plating the unmasked portions of the layer to increase the thick-ness thereof to provide a support layer. A plurality of multi-mesa diodes are formed in regions of the semiconductor material disposed on the masked portions of the plated heat sink layer Upper electrodes used to support the multimesa diode of the device after dicing of the wafer are provided by: depositing a layer of photoresist on the heat sink layer and the mesa shaped diodes; providing apertures in the photoresist layer; levelling ~Zl;3Çi ~'9 the photoresist layer to the mesa tops; providing a metaliza-tion layer on the photoresist layer; and providing a plurality of undersized apertures in the metalization layer aligned with the mesa tops. A second layer of photoresist is then provided on the metalization layer and is patterned to expose portions of the metalization layerO The upper electrodes are then plated directly onto por~ions of the metalization layer ex-posed by the photoresist layer. The photoresist layers and metalization layer are removed and the multimesa diode devices are diced apart. With such an arrangement a multimesa diode device is provided with a thin heat sink on one surface and a top electrode on the second surface. The thermal transfer advantages of the multimesa diode device are thus realized without the packaging and handling difficulties generally asso-ciated with individual diodes.
Broadly, according to one broad aspect, the invention of this divisional application provides a semiconductor device comprising: a mesa-shaped diode having upper and lower mesa portions; a first electrode contact disposed on a first one of upper and lower mesa portions of said mesa~shaped diode;
and a second electrode contact comprising a thermally conduc-tive material having a thickness in the range of one micron to two microns disposed on a second, different one of upper and lower mesa portions of the mesa-shaped diode, with said second electrode contact providing a heat sink portion of said mesa-shaped diode.
According to another broad aspect, the invention pro-vides a semiconductor device comprising: a plurality of mesa-shaped diodes, each mesa having upper and lower mesa portions and each interconnected by a first electrode contact disposed lZ13~
on a corresponding first one of upper and lower mesa portions of said plurality of mesa-shaped diodes; and a plurality of second electrode contacts comprising a thermally conductive material having a thickness in the range of one micron to two microns disposed on a corresponding second, different one of upper and lower mesa portions of each of said mesa-shaped diodes, with said second electrode contacts each providing a heat sink portion of the corresponding mesa-shaped diode.
-5a-12~36~9 Brief Description of the Drawings For a better understanding of the invention, reference is made in the following detailed description to the drawings wherein:
FIGS. 1-4 are a series of fragmentary isometric cross-sectional views showing steps in the construction of single mesa shaped diode device having a thin heat sink layer in accordance within the invention;
FIG. 5A is a cross-sectional view useful in under-standing a dicing operation of a wafer of diodes having the thin heat sink layer provided in accordance with Figs. 1-4;
FIG. 5B is a top view of the cross-sectional view of Fig. SA showing the photoresist pattern used in the dicing step;
FIG. 5C is a cross-sectional view of a mesa shaped diode having a heat sink in accordance with the invention;
FIGS. 6-8 are a series of fragmentary isometric partially broken away views showing steps in the construction of a multimesa diode device having a thin heat sink layer and beam leads;
FIG. 9 is a isometric view of a multimesa diode device constructed in accordance with Figs. 6-~ having thin heat sink layer and beam leads;
FIG. 10 is a fragmentary isometric partially broken away view showing the diode cluster of Fig. 7 with a first layer of photoresist used in fabricating interconnect patterns in accordance with the invention;
FIGS. 11-13 are a series of cross-sectional views showing steps in the construction of the interconnect patterns;
FIGS. 14-15 are a series of fragmentary isometric partially 3~9 bro~en away views showing the steps in the construction of an overlay in accordance with the invention on a wafer at the stage of processing shown in Fi~. 13;
FIG. l~A is a isometric view of a plurality of diodes interconnected by a overlay in accordance with the invention.
FIGS. 16-17 are a series of fragmentary isometric partially broken away views showing the steps in the con-struction of beam leads, for a single mesa diode device in accordance with the invention;
FIG. 17~ is an isometric view of a diode device having a beam lead pattern in accordance with the invention;
FIG. 18 is a top view of an interdigitated beam lead pa~tern;
FIG. 19 is a cross sectional view of a single mesa diode device having a thin heat sink layer and beam leads, mounted in a ceramic ring package in accordance with the invention;
and FIG. 20 is a cross-sectional view of a multimesa diode device having a thin heatsink and overlays mounted in a ceramic ring package in accordance with the invention.
12~3~*79 Description of the Preferred Embodiments -Construction of semiconductor devices having thin heat sink layers in accordance with the teachings of the present invention will be described in conjunction with the isometric cross-sectional views of Figs. 1 through 4. Referring first to Fig. 1, a substrate 25, here conductive gallium arsenide (GaAs~, is shown to include an active layer 24 of epitaxially grown semiconductor GaAs. Active layer 24 may have one of many different doping density profiles depending upon the particular application for the diode. here, for example, a doping density profile described in my U. S. Patent 4,160,992 issued July 10, 1979 and assigned to the assignee oL this invention is used. A first metal layer 26, here of platinum (Pt), is sputtered upon the active layer 24 to a thickness in the range of 10~ Angstroms to 200 Angstoms ~A). A second metal layer 28, here of titanium (Ti), is then sputtered over the platinum layer 26 to a thickness of 1000 A to 2000 A. Titanium is the preferred material although tungsten, hafninum, or other refractory metals may be used for layer 28. Upon the layer 28 a 1000 A to 2000 A thick layer 29 of highly conductive gold is evaporated, forming the lower contact for the diode device. Next, a thermally and electrically conductive heat sink layer 30, here of gold one to two microns thick, is plated over evaporated gold layer 29. A layer 31 of photoresist is then deposited on the plated gold layer 30, as shown.
Referring now to Fig. 2, the photoresist layer 31 is masked, developed, and chemically etched away in selective areas using well known photoresist techniques, to leave portions 32, thereof, remaining over selected regions of the plated gold 3n heat sink layer 30, as shown.
~213~9 Now referring to Figure 3, a support layer 36 is formed by plating the unmasked portions of the thin heat sink layer 30 with gold, here to a thickness of ten microns. The regions 32 (Figure 2) of photoresist layer 31 are removed leaving an apertured support layer 36. It is noted that the heat sink layer 30 remains at the original thickness but the support layer 36 is made sufficiently thick to provide struc-tural integrity for -the diodes to be formed in wafer 21 in a manner to be described hereinafter. Suffice it to say here, however, that the support layer 36 has formed therein a plur-ality of apertures 34 corresponding to areas where the photo-resist pattern 32 (Figure 2) was provided. The plurality of apertures 34 define the areas of the thin plated heat sink layer 30.
Referring now also to Figure 4, the substrate 25, is thinned to a predetermined thickness, a plurality of top con-tacts 22 are provided on the top of the thinned substrate 25 and a plurality of mesa shaped diodes 20 are formed from the thinned substrate 25 and active layer 24 between the top contact 22 and platinum layer 26, as shown. Where the doping profile of the active layer 24 is as described in above-mentioned U.S. Patent 4,160,992, the mesa-shaped diodes are IMPATT (impact avalanche transit time) diodes. The plurality of top contacts 22 are formed by first depositing a photo-resist layer (not shown) on the thinned substrate 25. The photoresist layer is masked, developed, and chemically etched away in predetermined locations using well-~nown photoresist techniques leaving a plurality of here circular apertures on the photoresist layer (not shown). Each circular aperture (not shown) is precisely aligned with a corresponding one of 121~ 9 the plurality of apertures 34 in the thick gold plated support 36. The circular apertures (not shown) are then plated with gold forming the previously mentioned top contacts 22. The alignment for the top contacts 22 to the apertures 34 is realized by a front to back alignment -9a-~21367~
step of the top contact mas~ (not shown) used to provide the photoresist pattern for the circular gold contacts 22. A
general front to back alignment procedure is described in U. S.
Patent No. 4,169,992, previously~mentioned. The plurality of mesas diodes 20 are formed between the top contacts 22 and the platinum layer 26. The mesa diodes 20 are formed by providing a pattern in photoresist on the thinned su~strAte 25, using well known photoresist techniques. The alignment of the mesa forming mas~ (not shown~ used in forming the pattern for the mesa diodes 20 is realized by the front to back alignment technique as described in U. S. Patent No. 4,169,992, referred to above. After mask alignment, the mesa diodes 20 are formed ~y chemically etching away portions of the thinned substrate 25 and active layer 24 between the the top contact layer 22 and the platinum layer 26, as shown. Thus mesa diodes 20 formed from the thinned substrate 25 and active layer 24 are supported by the support layer 36.
Referring now to Figs. SA and SB, the wafer 21 having a plurality of mesa diodes 20 is mounted on a wafer support 40 with a non-reactive wax 44 filling the space between and around mesa diodes 20 and gold contacts 22, as shown. The wafer 21 with the wax protected mesa diodes 20 is pressed against the upper surface of support 40. A photoresist layer is deposited on the plated support layer 36 of the wafer 21. A dicing mask (not shown) is provided on the plated support layer 36 of the wafer 21, and using well known photoresist techniques, a dicing pattern 38 of photoresist is produced. The apertures 34 in the thick plated support layer 36 are here used to align the dicing mask. The diodes 20 are diced from the wafer 21 within regions 39 provided in the dicing pattern 38 of photoresist.
~213679 The wafer 21 is here placed in a spray etching system of a type described in U. S. Patent 4,160,9~2 mentioned previously.
The spray etch system (not shown) provides an etchant (not shown) which completely etches through the exposed portions 3g of layers 30, 29, 28 and 26 to separate the diode devices from the thick support layer 36. After dlcing, the individual diode devices 46 an exemplary one thereof being shown in Fig. SC, may be collected and cleaned using any well known technique.
Referring now to Fig. 6, a wafer 121, includes a plurality of clusters, or sets, of mesa shaped diodes 42 (each cluster of mesa diodes 42 having a total area equal to a single mesa diode equivalent) formed over a corresponding plurality of apertures 34 provided by the thick plated support 36, as shown. The wa~er 121 is formed in a similar manner as wafer 21 shown in Fig. 4 except during mesa definition a cluster mask (not shown) is provided to produce a pattern in a layer of photoresist corresponding to a plurality of clusters of mesa diodes. This cluster mask (not shown) is front to back aligned as explained in U. S. Patent 4,160,992, previously mentioned. The plurality of the clusters of mesas diodes 42 are formed by chemically etching away portions of the substrate 25 between the top contact layer 22 and the platinum layer 26, as previously explained.
Now referring to Fig. 7, the wafer 121 is placed in a sputter etching system (not shown) and portions of the layer 26 of platinum unmasked by the di~des 20 are removed. A chemical etch here a two percent solution of hydrofloric acid (2~ HF:H2O) is then used to remove portions of layer 28 unmasked by diodes 20. The wafer 121 at this point has the layer 26 of platinum and the layer 28 of titanium removed in all areas except for 6 ~'~
those areas forming part of the individual mesa diodes 20 of each cluster of mesa diodes 42, leaving gold layer 29 exposed on the mesa diode side of the wafer 121. Exposing gold on the mesa diode side of wafer 121 is used to particular advantage in a dicing op~ration to be described in conjunction with Fig.
8 and Fig. 9.
Now referring to Fig. 8 and Fig. 9, beam leads 48 are here shown attached to the cluster of mesa diodes 42 for reasons to be described in cor.nection with Figs. 16-17. Suffice it to say here, however, that the thick plated support layer 36 is used to support the individual mesa diodes 20 at this stage in the processing while the attached gold plated beam leads 48 provide support for the individual mesa diodes 20 during and after the dicing operation. As shown in Fig. 8, gold is exposed on the upper s~rfaces of the wafer 121. A layer of wax 45 is here provided on the bottom side of the wafer 121, completely filling in the apertures 34 of the gold plated support layer 36.
The wafer 121 and wax layer 45 are supported by a wafer support 41. Since gold is exposed on both sides of the wafer 121 a gold etching solution is here used to etch from the mesa diode side of the wafer with the plated heat sink side mounted down.
Here, the wafer 121 is placed in a conventional emersion bath of etchant (not shown). The etchant flows on the mesa side of the wafer 121, but substantially below the tops of the mult-mesa diode device 120, and thus the etchant does not attack the beam leads 48. This technique,uses the mesa shaped diodes 20 themselves as a mask during the dicing procedure. Since the gold layers 29, 30 exposed on the mesa diode side within the aperture 34 of the thick gold plated support layer 36 are substantially thinner than other exposed gold areas, the 12~3Çi7~
portions of the gold in layers 29, 30 disposed over the aperture 34 will etch âway beore other gold areâs of the diode cluster 42 âre significantly disturbed thus forming clusters, or sets, of here four diodes in each device 120 as shown in Fig. 9.
Referring now to Fig. 10, a wafer 121' will be processed in âccordance with an âlternative embodiment of the invention.
Thus, wâfer 121' is shown in Fig. 10 at an equivalent stage of processing âS the wafer 121 shown in Fig. 7, however here wafer 121' is provided with a first thick layer of photores~st 60, as shown. A plurality of apertures 66 aligned with the mesa top contacts 22 are formed in the photoresist 60 to exposure the top contacts 22 using well known photoresist techniques. The photoresist layer 60 is then levelled with the top contacts 22 by conventional techniques such as controlled light exposure or mechanical lapping.
Referring now to Fig. 11, zn adherent layer 62 here of titanium, approximately 200 A thick is sputtered over the to?
of the wafer section 121'. Other metals such as molybedenum, nickel, nickel-chrome and similar metals or metallic systems may be used for the adherent layer 62. A conductive layer 64 here a 200 A thick layer of gold is sputtered over the adherent layer 62 of titanium. Other conductive metals such as platinum, silver and copper may be used for conductive layer 64. The preferred combination, however, is titanium-gold, because this combination provides a contact system virtuâlly alloyless and is not subject to loss of adhesion.
The adherent layer 62 is sputtered within the apertures 66 (Fig. 10) formed in the photoresist 60. The adherent layer 62 provides a contact layer interconnecting the individual diodes 20 (Fig~ 10) in each cluster of diode 42 (Fig. 2).
~2136~
Now to referring to Fig . 12, the wafer 121' is provided with a second layer 68 of photoresist. The layer 68 of photoresist is masked, developed, and etched away in selective areas using well known photoresist techniques to provide a pattern in the photoresist layer 68 of a plurality undersized circular aperatures 67 aligned to the diode top contacts 22.
Referring now to Fig. 13 the first layer 62 and the second layer 64 are selectively removed from the mesa tops 22, within each of the apertures 67 formed in the photoresist layer 68.
A plurality of apertures 69 are thus formed in layers 62 and 64. A thin layer of the first layer 62 and the second layer 64, thus remain attached to the eZges of the mesa tops 22, because the apertures 69 are smaller than the mesa diode top contacts 22. The wafer 121' at this stage of processing may be provided with either a plurality of top electrode contacts su~h as the overlays shown in Fig. 15 or the beam leads shown in Fi~. 17. Selection between the gold overlay pattern (Fig. 15) or the beam lead pattern (Fig. 17) is here primarily determined by the physical size of the mesa diodes.
For example, for X band quadramesa diodes where the mesas are relatively large in comparison to millimeter wave mesas, the use of a beam lead interconnect is here impractical. This is because on a given wafer of semi-insulating material such as GaAs as used here, relatively few beam lead devices can be manufactured for X-band diodès due to the relatively long lengths of the beam leads in relation to the size o the mesa diodes. Here, the gold overlay structure is provided to inter-connect the quadramesas X-band diodes to provide a more eficient interconnection scheme and thus a more efficient utilization of the area of the wafer 121'. However, for - 14 ~
12136~9 millimeter wave quadramesa diodes having relatively small mesas compared to X-band mesa diodes, a dense pattern of beam leads is plated to the mesa diodes to provide the interconnect portion for the mesa diodes. Fabrication of beam leads diodes are described in conjunction with Figs. 16 and 17.
Referring now to Figs. 14 and 15 fabrication of an overlay 70 (Fig. 15) for interconnecting each mesa diode 20 of the cluster of mesa diode 42 in accordance with the invention will now be described. Referring first to Fig. 14, a wafer 121' in the same stage of fabrication as that shown in Fig. 13, is provided with a layer of photoresist 71. The photoresist layer 71 is deposited on the second layer 54 and is masked, developed and etched away in selective locations using well known photo-resist techniques to form a plurality of apertures 72.
Referring now to Fig. 15, the gold overlay 70 is plated to a thickness of here four microns within the areas exposed by the apertures 72. These overlays 70 interconnect each of the diodes 20 within each of the plurality of clusters of diodes 42. Further the overlay provides the support for each diode 20 of the cluster of diodes 42, after dicing. The overlay pattern 70 may be plated to any desired thickness, typically however, the thickness is in the range of four microns to ten microns.
After plating the titanium layer 62, the gold layer 64, the thick photoresist layer 60, and the photoresist pattern 72 are removed from the wafer by conventional means leaving the ~afer, as shown. Since gold is exposed on both sides of the wafer 121', a gold etching solution is here used to etch from the mesa diode side of the wafer 121'. The emersion etching technique described in conjunction with Fig. 8 is here used to dice the wafer 121'. Thus, the quadramesa diodes 12136~9 interconnected by the gold overlay 70 are used as a mask during the dicing operation. Since gold exposed in the region of the aperture 34 of the thick plated support 36 is substantially thinner than other exposed gold areas the gold in the region of the aperture 34 will etch through before other gold areas of the cluster of mesa diodes 42 or the gold overlay 70 are significantly disturbed thereby ~orming four diode devices, an exemplary one thereof~ here device 50, as shown in Fig. 15A.
Fabrication of mesa diodes having plated beam leads 80 is next described in conjunction with Fig. 16 and Fig. 17.
Re~erring first to Fig. 16 a wafer section 21', in the same stage of construction as that shown in Fig. 13, includes a plurality of individual diode elements 20, as shown. The wafer 21' now is provided with a second layer 82 of photoresist.
This photoresist layer 82 is disposed on the second layer 64, and is masked, developed and etched away in selective locations using well known photoresist techniques to form a pattern 84 for the beam leads.
Referring now also to Fig. 17 the ~eam lead pattern 84 is plated to the diodes 20 in the areas exposed within the photo-resist layer 82. The beam lead pattern may be plated to any desired thickness, typically however, the thickness is in the range of four microns to ten microns. The photoresist layer 82, titanium layer 62, the gold layer 64 and the thick photoresist layer 60 are then removed using well known techniques leaving the mesa diodes 20 with plated beam leads 48, as shown. Since gold is exposed on both sides of the wafer 21 a gold etching solution is here used to etched from the mesa diode side of the wafer 21 as previously explained in conjunction with Fig. 8 to separate the diodes into individual devices 52, and 13~79 exemplary one thereof, here device 52, as shown in Fig. 17A.
Alternatively, the overlays 70 or the beam leads 48 may be formed on the diodes after the wafer has been diced, as explained in conjunction wlth Fig. 8. In this case, the wafer having been diced is still supported by a wafer support 41 and a wax layer 45 filling in the apertures 34 o the support 36, as shown in Fig. lS and Fig. 17. The beam lead or overlay interconnect patterns are then formed as explained above, and the diodes with the plated interconnects are then dismounted from the wax 45. This provides a method whereby the inter-connect structure is not exposed to the etchant used in the dicing operation, since the interconnect pattern is no~ present during the wafer dicing step.
Now referring to Fig. 18, a portion of a tightly packed beam lead pattern 84 which may be plated directly to an entire wafer provides a plurality of mesa diodes, as shown. This pattern is provided for interconnecting single mesa or multi-mesa diodes.
Referring again to Figs. 8-9, the beam lead quadramesa diode 120 having the plated beam leads is for~ed in the same manner as the single mesa diode device 52 having plated beam leads, except for the use of a multimesa mask, for defining the diode mesas. The beam lead pattern as shown in Fig. 18 is here also used to provide the pattern of beam leads in photoreslst for the multi-mesa diode.
Referring now ~o Fig. 15, the single mesa diode device 52 having plated beam leads is here mounted in a package 10, as shown. The package 10 includes a conventional stub support 18 here of copper having a screw slot 19, for package mounting.
The stub support 18 here supports a pedestal 16 which is h~re of lZ~L3~9 gold plated diamond. The thicXness of the gold plating on the diàmond pedestal 16 is here 2 microns thick. Alternatively the pedestal 16 may be embedded in the stub support 18 or may be formed from the stub support 18.- A conductive ring 17 here gold plated copper is spaced from the stub 18 by a insulating ring spacer 14. The insulating ring spacer 14 is here ceramic but may be quartz or any other suitable insulating material.
The plated heat sink side of the diode 20 is here mounted to the pedestal 16 by a thermal compression bond. Mounting the diode 88 to the pedestal 16 causes the beam leads 48 to bend upward and extend up toward the edge of the con2uctlve ring 17. Thermal compression bonds are here used to bond each of the beam leads to the conductive ring 17. A conductive lid 19 is then provided to add further support to the package 10.
The lid 19, here gold plated copper is thermal compression bonded to the conductive ring 17 and may form a hermetic seal between ring 17 and lead 19. This structure provides a package 10 wherein a diode 20 having extended beam leads 48 as top electrodes, which are bonded to the conductive ring 17 using a thermal compression bond on the plated leads, without having to bond a lead to the diode mesa itself. Diode package 10 should have lower parasitic capacitance and inductance than other diode packages, thus enhancing the diode's electrical charac-teristics.
Referring now to FIG. 20, a multi-mesa diode device 50 interconnected by an overlay pattern is pac~age in a diode package 90 as shown. The package 90 includes a conventional stub support 18 here of copper having a screw slot 19, for package mounting. The stub support 18 here supports a pedestal 16 which is here of gold plated diamond. Alternatively, the ~213~i79 pedestal 16 may be embedded in the stub support 18 or may be formed from the stub support 18. A conductive flange 13 here gold plated copper is spaced from the stub 18 by an insulating ceramic ring spacer 14. The insulating ring spacer is here ceramic buy may be quartz or any other suitable insulating material. The plated heatsin~ side of the multimesa diode device 50 is here mounted to the pedestal 16 by a thermal compression bond. A gold ribbon strip 15 is then thermally compression bonded to the conductive flange 13 and the overlay 70. A conductive lid 19 is then provided to add further support to the package 10. The lid 19, here gold plated copper is thermal compression bonded to the conductive flange 13 and may form a hermetic seal between flange 13 and lid 19.
From the foregoing, it will be apparent that all of the objectives of this invention have been achieved by the structures shown and described herein. It also will be apparent, however, that various changes may be made by those skilled in the art without departing from the spirit of the invention as expressed in the appended claims. It is to be understood, therefore, that all matter shown and described herein is to be interpreted as illustrative and not in a limiting sense.
DGM:jp Case No. 32784
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semi-conductor device comprising:
a mesa-shaped diode having upper and lower mesa portions;
a first electrode contact disposed on a first one of upper and lower mesa portions of said mesa-shaped diode; and a second electrode contact comprising a thermally conductive material having a thickness in the range of one micron to two microns disposed on a second, different one of upper and lower mesa portions of the mesa-shaped diode, with said second electrode contact providing a heat sink portion of said mesa-shaped diode.
a mesa-shaped diode having upper and lower mesa portions;
a first electrode contact disposed on a first one of upper and lower mesa portions of said mesa-shaped diode; and a second electrode contact comprising a thermally conductive material having a thickness in the range of one micron to two microns disposed on a second, different one of upper and lower mesa portions of the mesa-shaped diode, with said second electrode contact providing a heat sink portion of said mesa-shaped diode.
2. A semiconductor device comprising:
a plurality of mesa-shaped diodes, each mesa having upper and lower mesa portions and each interconnected by a first electrode contact disposed on a corresponding first one of upper and lower mesa portions of said plurality of mesa-shaped diodes; and a plurality of second electrode contacts comprising a thermally conductive material having a thickness in the range of one micron to two microns disposed on a corresponding second, different one of upper and lower mesa portions of each of said mesa-shaped diodes, with said second electrode contacts each providing a heat sink portion of the corre-sponding mesa-shaped diode.
a plurality of mesa-shaped diodes, each mesa having upper and lower mesa portions and each interconnected by a first electrode contact disposed on a corresponding first one of upper and lower mesa portions of said plurality of mesa-shaped diodes; and a plurality of second electrode contacts comprising a thermally conductive material having a thickness in the range of one micron to two microns disposed on a corresponding second, different one of upper and lower mesa portions of each of said mesa-shaped diodes, with said second electrode contacts each providing a heat sink portion of the corre-sponding mesa-shaped diode.
3. The semiconductor device of claim 1 wherein said mesa-shaped diode is an IMPATT diode.
4. The semiconductor device of claim 2 wherein said mesa-shaped diode is an IMPATT diode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US323,781 | 1981-11-23 | ||
| US06/323,781 US4536469A (en) | 1981-11-23 | 1981-11-23 | Semiconductor structures and manufacturing methods |
| CA000414043A CA1201537A (en) | 1981-11-23 | 1982-10-22 | Semiconductor structures and manufacturing methods |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000485449A Division CA1213679A (en) | 1981-11-23 | 1985-06-26 | Semiconductor structures and manufacturing methods |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000485449A Division CA1213679A (en) | 1981-11-23 | 1985-06-26 | Semiconductor structures and manufacturing methods |
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| Publication Number | Publication Date |
|---|---|
| CA1213679A true CA1213679A (en) | 1986-11-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000485450A Expired CA1212181A (en) | 1981-11-23 | 1985-06-26 | Semiconductor structures and manufacturing methods |
| CA000485449A Expired CA1213679A (en) | 1981-11-23 | 1985-06-26 | Semiconductor structures and manufacturing methods |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000485450A Expired CA1212181A (en) | 1981-11-23 | 1985-06-26 | Semiconductor structures and manufacturing methods |
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| Country | Link |
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| CA (2) | CA1212181A (en) |
-
1985
- 1985-06-26 CA CA000485450A patent/CA1212181A/en not_active Expired
- 1985-06-26 CA CA000485449A patent/CA1213679A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA1212181A (en) | 1986-09-30 |
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| Date | Code | Title | Description |
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