WO2024150303A1 - パワーモジュール - Google Patents

パワーモジュール Download PDF

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Publication number
WO2024150303A1
WO2024150303A1 PCT/JP2023/000401 JP2023000401W WO2024150303A1 WO 2024150303 A1 WO2024150303 A1 WO 2024150303A1 JP 2023000401 W JP2023000401 W JP 2023000401W WO 2024150303 A1 WO2024150303 A1 WO 2024150303A1
Authority
WO
WIPO (PCT)
Prior art keywords
power module
semiconductor element
power semiconductor
conductor
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/000401
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
耕三 原田
穂隆 六分一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to CN202380089468.XA priority Critical patent/CN120457545A/zh
Priority to PCT/JP2023/000401 priority patent/WO2024150303A1/ja
Priority to DE112023005535.1T priority patent/DE112023005535T5/de
Priority to JP2024522041A priority patent/JP7520273B1/ja
Publication of WO2024150303A1 publication Critical patent/WO2024150303A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/13—Containers comprising a conductive base serving as an interconnection
    • H10W76/138—Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/184—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components inserted in holes through the PCBs and wherein terminals of the components are connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • This disclosure relates to a power module.
  • Power modules equipped with vertical power semiconductor elements are used as power conversion devices in a wide range of fields, including industrial equipment, automobiles, and railways.
  • the electrodes of the power semiconductor element are connected to one end of a lead frame that serves as an external terminal via a bonding wire, and the power semiconductor element, the one end of the lead frame, and the bonding wire are sealed with resin.
  • Patent Document 1 discloses a semiconductor device in which the main electrodes of a semiconductor element mounted on an insulating substrate are electrically connected to the metal foil of a printed circuit board arranged above the semiconductor element via multiple post electrodes.
  • the electrode of the power semiconductor element connected via a bonding wire and the one end of the lead frame must be spaced apart in a plan view, so there is also a structural limit to reducing the dimensions in a plan view.
  • the insulating substrate, semiconductor element, post electrodes, and printed circuit board are arranged in parallel in the thickness direction, so there are structural limitations to how thin the device can be made.
  • the main objective of this disclosure is to provide a power module that, compared to conventional power modules, simultaneously achieves reduced wiring inductance associated with high-speed switching operations, as well as being smaller and thinner.
  • the power module comprises a first substrate having a first surface, a first power semiconductor element mounted on the first surface, a printed circuit board having a first opposing portion arranged to overlap the first surface of the first substrate in a first direction perpendicular to the first surface, and a first conductor post electrically connecting the first power semiconductor element and the first opposing portion.
  • a first recess is formed in the first opposing portion to accommodate the first power semiconductor element and the first conductor post therein.
  • This disclosure makes it possible to provide a power module that, compared to conventional power modules, simultaneously achieves reduced wiring inductance associated with high-speed switching operations, as well as being smaller and thinner.
  • FIG. 1 is a plan view perspective view showing a power module according to a first embodiment
  • FIG. 2 is a bottom perspective view showing the power module shown in FIG. 1
  • 3 is a cross-sectional view taken along the line III-III in FIG. 1.
  • 2 is a cross-sectional view for explaining one step of a method for manufacturing the power module shown in FIG. 1.
  • FIG. 11 is a plan view perspective view showing a modified example of the power module according to the first embodiment. 6 is a cross-sectional view for explaining one step of a method for manufacturing the power module shown in FIG. 5 .
  • FIG. 11 is a plan view perspective view showing a power module according to a second embodiment.
  • FIG. 8 is a bottom perspective view showing the power module shown in FIG. 7 .
  • FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. 7.
  • 8 is a cross-sectional view for explaining one step of a method for manufacturing the power module shown in FIG. 7.
  • FIG. 11 is a cross-sectional view showing a power module according to a third embodiment.
  • 12 is a cross-sectional view for explaining a semiconductor package included in the power module shown in FIG. 11.
  • FIG. 11 is a cross-sectional view showing a power module according to a fourth embodiment.
  • FIG. 13 is a cross-sectional view showing a modified example of the power module according to the fourth embodiment.
  • FIG. 13 is a cross-sectional view showing a power module according to a fifth embodiment.
  • FIG. 13 is a cross-sectional view showing a power module according to a sixth embodiment.
  • FIG. 13 is a cross-sectional view showing a modified example of the power module according to the sixth embodiment.
  • FIG. 13 is a cross-sectional view showing a power module according to a seventh embodiment.
  • FIG. 13 is a cross-sectional view showing a power module according to an eighth embodiment.
  • FIG. 2 is a plan view perspective view showing a power module according to a first comparative example.
  • FIG. 21 is a cross-sectional view showing Comparative Example 1 shown in FIG. 20 .
  • FIG. 11 is a plan view perspective view showing a power module according to Comparative Example 2.
  • FIG. 23 is a cross-sectional view showing Comparative Example 2 shown in FIG. 22 .
  • FIG. 11 is a plan view perspective view showing a power module according to Comparative Example 3.
  • FIG. 25 is a cross-sectional view showing Comparative Example 3 shown in FIG. 24 .
  • FIG. 11 is a plan view perspective view showing a power module according to Comparative Example 4.
  • FIG. 27 is a cross-sectional view showing Comparative Example 4 shown in FIG. 26 .
  • a power module 101 includes a first insulating substrate 1A (first substrate), a second insulating substrate 1B (second substrate), a first power semiconductor element 2A, a second power semiconductor element 2B, a plurality of first conductor posts 3A, a plurality of second conductor posts 3B, and a printed circuit board 4.
  • the first insulating substrate 1A has a first surface 1A1 on which the first power semiconductor element 2A is mounted.
  • the direction perpendicular to the first surface 1A1 is referred to as the first direction Z.
  • the first insulating substrate 1A includes a base material 10, a first conductor layer 11, and a second conductor layer 12.
  • the first conductor layer 11 and the second conductor layer 12 are arranged to sandwich the base material 10 in the first direction Z.
  • Each of the first conductor layer 11 and the second conductor layer 12 is bonded to the base material 10, for example.
  • the first surface 1A1 is constituted by the surface of the first conductor layer 11 of the first insulating substrate 1A opposite to the surface bonded to the base material 10.
  • the material constituting the substrate 10 may be any material that has electrical insulation properties.
  • the substrate 10 is, for example, a ceramic plate.
  • the material constituting the first conductor layer 11 and the second conductor layer 12 may be any material that has electrical conductivity, for example, a metal material.
  • the second insulating substrate 1B has a second surface 1B1 on which the second power semiconductor element 2B is mounted.
  • the second insulating substrate 1B has, for example, the same configuration as the first insulating substrate 1A.
  • the second insulating substrate 1B includes a base material 10, a first conductor layer 11, and a second conductor layer 12.
  • the second surface 1B1 is formed by the surface of the first conductor layer 11 of the second insulating substrate 1B opposite to the surface that is joined to the base material 10.
  • the first insulating substrate 1A and the second insulating substrate 1B are arranged next to each other in a first direction along the first surface 1A1.
  • the second surface 1B1 faces the same side as the first surface 1A1.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are, for example, vertical power semiconductor elements.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a bipolar transistor, or a freewheeling diode.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are, for example, the same type of semiconductor element. Note that the first power semiconductor element 2A and the second power semiconductor element 2B may be different types of semiconductor elements.
  • the first power semiconductor element 2A has a back surface facing the first insulating substrate 1A in the first direction Z, and a front surface located on the opposite side to the back surface facing the printed circuit board 4 in the first direction Z.
  • a back electrode (not shown) is formed on the back surface of the first power semiconductor element 2A. The back electrode is bonded to the first conductor layer 11 of the first insulating substrate 1A via a bonding material 5.
  • a main electrode 21A and a control electrode 22A are formed on the front surface of the first power semiconductor element 2A. Each of the main electrode 21A and the control electrode 22A of the first power semiconductor element 2A is electrically connected to the first conductor post 3A.
  • the main electrode 21A is electrically connected to the first wiring layer 41 of the printed circuit board 4 described later via the first conductor post 3A.
  • the control electrode 22A is electrically connected to the first wiring layer 41 of the printed circuit board 4 described later via the first conductor post 3A.
  • the second power semiconductor element 2B has a back surface facing the second insulating substrate 1B in the first direction Z, and a front surface located on the opposite side to the back surface facing the printed circuit board 4 in the first direction Z.
  • a back electrode (not shown) is formed on the back surface of the second power semiconductor element 2B.
  • the back electrode is bonded to the first conductor layer 11 of the second insulating substrate 1B via a bonding material 5.
  • a main electrode 21B and a control electrode 22B are formed on the front surface of the second power semiconductor element 2B.
  • Each of the main electrode 21B and the control electrode 22B of the second power semiconductor element 2B is electrically connected to the second conductor post 3B.
  • the main electrode 21B is electrically connected to the first wiring layer 41 of the printed circuit board 4 described later via the second conductor post 3B.
  • the control electrode 22B is electrically connected to the first wiring layer 41 of the printed circuit board 4 described later via the second conductor post 3B.
  • Each of the multiple first conductor posts 3A and the multiple second conductor posts 3B is a columnar body extending along the first direction Z.
  • the material constituting each of the multiple first conductor posts 3A and the multiple second conductor posts 3B may be any material that has electrical conductivity.
  • each of the first conductor posts 3A in the first direction Z is joined to the main electrode 21A or the control electrode 22A of the first power semiconductor element 2A via a bonding material (not shown) such as solder.
  • the other end of each of the first conductor posts 3A in the first direction Z is joined to the first wiring layer 41 of the printed circuit board 4 (described later) via a bonding material (not shown) such as solder.
  • each of the second conductor posts 3B in the first direction Z is joined to the main electrode 21B or the control electrode 22B of the second power semiconductor element 2B via a bonding material such as solder (not shown).
  • the other end of each of the second conductor posts 3B in the first direction Z is joined to the first wiring layer 41 of the printed circuit board 4 (described later) via a bonding material such as solder (not shown).
  • the printed circuit board 4 includes a first wiring layer 41, a second wiring layer 42, an insulator layer 44, a through via 45, a first protective layer 46, and a second protective layer 47.
  • the first protective layer 46, the first wiring layer 41, the insulator layer 44, the second wiring layer 42, and the second protective layer 47 are stacked in the first direction Z in the order described above.
  • the first wiring layer 41 includes a plurality of patterns that are spaced apart from each other on the same plane perpendicular to the first direction Z and are electrically isolated from each other.
  • the patterns of the first wiring layer 41 are formed by patterning the same conductor layer and are electrically isolated from each other.
  • the second wiring layer 42 includes a plurality of patterns that are spaced apart from each other on the same plane perpendicular to the first direction Z and are electrically isolated from each other.
  • the patterns of the second wiring layer 42 are formed by patterning the same conductor layer.
  • the first wiring layer 41 and the second wiring layer 42 are electrically connected via the through via 45.
  • the first protective layer 46 and the second protective layer 47 are for protecting the surfaces of the first wiring layer 41 and the second wiring layer 42.
  • the through via 45 is formed, for example, so as to fill the entire through hole penetrating the insulator layer 44.
  • the through via 45 is, for example, a metal material pressed into the through hole of the insulator layer 44.
  • the through via 45 may be a metal thin film formed by plating on the wall surface of the through hole of the insulator layer 44.
  • the first protective layer 46 and the second protective layer 47 are, for example, resist layers.
  • the first protective layer 46 includes a portion included in the first opposing portion 4A and a portion included in the second opposing portion 4B, and is formed so that both portions are continuous in the second direction Y and the third direction X.
  • the second protective layer 47 is arranged around the first recess 4C in a plan view.
  • the printed circuit board 4 includes a first opposing portion 4A arranged to overlap the first surface 1A1 of the first insulating substrate 1A in the first direction Z, and a second opposing portion 4B arranged to overlap the second surface 1B1 of the second insulating substrate 1B in the first direction Z.
  • the first opposing portion 4A is arranged side by side with the second opposing portion 4B in the second direction Y.
  • the first opposing portion 4A includes a portion of each of the first wiring layer 41, the second wiring layer 42, the insulator layer 44, the first protective layer 46, and the second protective layer 47.
  • the second opposing portion 4B includes another portion of each of the first wiring layer 41, the second wiring layer 42, the insulator layer 44, the first protective layer 46, and the second protective layer 47.
  • the first opposing portion 4A has a first recess 4C (spot recess) that accommodates the first power semiconductor element 2A and the first conductive posts 3A.
  • the first recess 4C is recessed in the first direction Z with respect to the lower surface of the first opposing portion 4A facing the first insulating substrate 1A.
  • the lower surface of the first opposing portion 4A is joined to the first surface 1A1 of the first insulating substrate 1A.
  • the first recess 4C has a bottom surface facing the first surface 1A1 via the first power semiconductor element 2A in the first direction Z, and wall surfaces that protrude from the outer periphery of the bottom surface in the first direction Z and face the side surfaces of the first power semiconductor element 2A and each of the first conductor posts 3A in each of the second direction Y and the third direction X.
  • the lower end of the wall surface of the first recess 4C is connected to the inner periphery of the lower surface of the first opposing portion 4A.
  • Each of the lower surface of the first opposing portion 4A and the bottom surface and wall surface of the first recess 4C may be a single flat or curved surface, or may be an uneven surface formed by connecting multiple flat or curved surfaces to each other.
  • At least the first wiring layer 41 and the first protective layer 46 may be formed on the bottom surface of the first recess 4C.
  • another wiring layer stacked with the first wiring layer 41 in the first direction Z, and an insulating layer separating the wiring layer from the first wiring layer 41 are not formed on the bottom surface of the first recess 4C.
  • each of the first wiring layer 41 and the first protective layer 46 is exposed on the bottom surface of the first recess 4C.
  • the first wiring layer 41 exposed on the bottom surface of the first recess 4C is joined to the other end of each of the first conductor posts 3A in the first direction Z via a bonding material such as solder.
  • a portion of each of the insulator layer 44 and the second wiring layer 42 is exposed on the wall surface of the first recess 4C.
  • the second wiring layer 42 exposed on the lower surface of the first opposing portion 4A is bonded to the conductor layer 11 of the first insulating substrate 1A via a bonding material such as solder.
  • the second wiring layer 42 exposed on the lower surface of the first opposing portion 4A is continuously arranged so as to surround the entire circumference of the first recess 4C.
  • the conductor layer 11 of the first insulating substrate 1A is continuously arranged so as to surround the entire circumference of the first power semiconductor element 2A.
  • the bonding material that bonds the second wiring layer 42 and the conductor layer 11 is continuously arranged so as to surround the entire circumference of the first power semiconductor element 2A and the first recess 4C that houses it. As a result, the inside of the first recess 4C is sealed by the first insulating substrate 1A and the bonding material.
  • the second opposing portion 4B has a second recess 4D (spot recess) that accommodates the second power semiconductor element 2B and the multiple second conductor posts 3B inside.
  • the second recess 4D is recessed in the first direction Z with respect to the lower surface of the second opposing portion 4B facing the second insulating substrate 1B side.
  • the lower surface of the second opposing portion 4B faces the second surface 1B1 of the second insulating substrate 1B without the second power semiconductor element 2B.
  • the second recess 4D has a bottom surface that faces the second surface 1B1 through the second power semiconductor element 2B in the first direction Z, and a wall surface that protrudes from the outer periphery of the bottom surface in the first direction Z and faces each side of the second power semiconductor element 2B and the multiple second conductor posts 3B in each of the second direction Y and the third direction X.
  • the lower end of the wall surface of the second recess 4D is connected to the inner periphery of the lower surface of the second opposing portion 4B.
  • the lower surface of the second opposing portion 4B and the bottom and wall surfaces of the second recess 4D may each be a single flat or curved surface, or may be an uneven surface formed by connecting multiple flat or curved surfaces to each other.
  • the second opposing portion 4B includes a first wiring layer 41, a second wiring layer 42, an insulator layer 44, a first protective layer 46, and a second protective layer 47.
  • the first protective layer 46, the first wiring layer 41, the insulator layer 44, the second wiring layer 42, and the second protective layer 47 are stacked in the first direction Z in the order described above.
  • At least the first wiring layer 41 and the first protective layer 46 may be formed on the bottom surface of the second recess 4D.
  • another wiring layer stacked with the first wiring layer 41 in the first direction Z, and an insulating layer separating the wiring layer from the first wiring layer 41 are not formed on the bottom surface of the second recess 4D.
  • each of the first wiring layer 41 and the first protective layer 46 is exposed on the bottom surface of the second recess 4D.
  • Each of the first wiring layers 41 exposed on the bottom surface of the second recess 4D is joined to the other end of each of the multiple second conductor posts 3B in the first direction Z via a bonding material such as solder.
  • a portion of each of the insulator layer 44 and the second wiring layer 42 is exposed on the wall surface of the second recess 4D.
  • the second wiring layer 42 exposed on the lower surface of the second opposing portion 4B is joined to the conductor layer 11 of the second insulating substrate 1B via a bonding material such as solder.
  • the second wiring layer 42 exposed on the lower surface of the second opposing portion 4B is continuously arranged so as to surround the entire circumference of the second recess 4D.
  • the conductor layer 11 of the second insulating substrate 1B is continuously arranged so as to surround the entire circumference of the second power semiconductor element 2B.
  • the bonding material that bonds the second wiring layer 42 and the conductor layer 11 is continuously arranged so as to surround the entire circumference of the second power semiconductor element 2B and the second recess 4D that houses it. As a result, the inside of the second recess 4D is sealed by the second insulating substrate 1B and the bonding material.
  • the inside of the first recess 4C and the second recess 4D is filled with a gas such as air.
  • a part of the first wiring layer 41 of the printed circuit board 4 is exposed from the first protective layer 46 and the second protective layer 47 to form a first external connection terminal 41A connected to an external device in the power module 101.
  • a part of the first wiring layer 41 is exposed from the first protective layer 46 and the second protective layer 47 to form second external connection terminals 41B, 41C connected to an external device in the power module 101.
  • the second external connection terminals 41A, 41B are control external terminals.
  • a part of the second wiring layer 42 of the printed circuit board 4 is exposed from the first protective layer 46 and the second protective layer 47 to form third external connection terminals 42A, 42B connected to an external device in the power module 101.
  • solder is used as an example of the bonding material included in the power module 101, but this is not limited to this.
  • Sintered silver, conductive adhesive, liquid tank diffusion bonding technology, etc. may also be used to bond the components included in the power module 101.
  • a signal input to the third external connection terminal 42A passes through the second wiring layer 42 and the conductor layer 11 of the first insulating substrate 1A, reaches the back electrode of the first power semiconductor element 2A, and is output from the main electrode 21A of the first power semiconductor element 2A.
  • a signal output from the main electrode 21A of the first power semiconductor element 2A passes through the first conductor post 3A, the first wiring layer 41, the through via 45, and the conductor layer 11 of the second insulating substrate 1B, reaches the back electrode of the second power semiconductor element 2B, and is output from the main electrode 21B of the second power semiconductor element 2B.
  • a signal output from the main electrode 21B of the second power semiconductor element 2B passes through the second conductor post 3B and the first wiring layer 41, reaches the first external connection terminal 41A, and is output to an external device.
  • a control signal is input from an external device to the control electrodes 22A, 22B of the first power semiconductor element 2A and the second power semiconductor element 2B via the second external connection terminals 41B, 41C, the first wiring layer 41, and the first conductor post 3A or the second conductor post 3B.
  • ⁇ Power module manufacturing method> An example of a method for manufacturing the power module 101 will be described below with reference to Fig. 4. As shown in Fig. 4, first, a first semi-finished product 201, a second semi-finished product 202, and a printed circuit board 4 are prepared.
  • the first semi-finished product 201 is an integral part of the first insulating substrate 1A, the first power semiconductor element 2A, and the multiple first conductor posts 3A.
  • the first power semiconductor element 2A is joined to the conductor layer 11 of the first insulating substrate 1A by solder or the like, and each of the multiple first conductor posts 3A is joined to the main electrode 21A or the control electrode 22A of the first power semiconductor element 2A by solder or the like.
  • the second semi-finished product 202 is an integral part of the second insulating substrate 1B, the second power semiconductor element 2B, and the plurality of second conductor posts 3B.
  • the second power semiconductor element 2B is joined to the conductor layer 11 of the second insulating substrate 1B by solder or the like, and each of the plurality of second conductor posts 3B is joined to the main electrode 21B or the control electrode 22B of the second power semiconductor element 2B by solder or the like.
  • the printed circuit board 4 includes a first opposing portion 4A and a second opposing portion 4B.
  • the first opposing portion 4A is a portion that is intended to be arranged so as to overlap the first surface 1A1 of the first insulating substrate 1A in the first direction Z.
  • the second opposing portion 4B is a portion that is intended to be arranged so as to overlap the second surface 1B1 of the second insulating substrate 1B in the first direction Z.
  • a first recess 4C is formed in the first opposing portion 4A.
  • a portion of each of the first wiring layer 41 and the first protective layer 46 is exposed on the bottom surface of the first recess 4C.
  • a portion of each of the insulator layer 44 and the third wiring layer is exposed on the wall surface of the first recess 4C.
  • another portion of each of the insulator layer 44 and the third wiring layer is exposed on the lower surface of the first opposing portion 4A.
  • the second wiring layer 42 exposed on the lower surface of the first opposing portion 4A is continuously arranged so as to surround the entire circumference of the first recess 4C.
  • the conductor layer 11 of the first insulating substrate 1A is continuously arranged so as to surround the entire circumference of the first power semiconductor element 2A.
  • a second recess 4D is formed in the second opposing portion 4B.
  • a portion of each of the first wiring layer 41 and the first protective layer 46 is exposed on the bottom surface of the second recess 4D.
  • a portion of each of the insulator layer 44 and the third wiring layer is exposed on the wall surface of the second recess 4D.
  • another portion of each of the insulator layer 44 and the third wiring layer is exposed on the lower surface of the second opposing portion 4B.
  • the second wiring layer 42 exposed on the lower surface of the second opposing portion 4B is continuously arranged so as to surround the entire circumference of the second recess 4D.
  • the conductor layer 11 of the second insulating substrate 1B is continuously arranged so as to surround the entire circumference of the second power semiconductor element 2B.
  • a bonding material such as solder is continuously arranged on the conductor layer 11 so as to surround the entire periphery of the first power semiconductor element 2A. Furthermore, a bonding material such as solder is arranged on the main electrode 21A and the control electrode 22A of the first power semiconductor element 2A. Similarly, a bonding material such as solder is continuously arranged on the conductor layer 11 so as to surround the entire periphery of the second power semiconductor element 2B. A bonding material such as solder is arranged on the main electrode 21B and the control electrode 22B of the second power semiconductor element 2B.
  • the first opposing portion 4A is arranged to overlap the first surface 1A1 of the first insulating substrate 1A in the first direction Z
  • the second opposing portion 4B is arranged to overlap the second surface 1B1 of the second insulating substrate 1B in the first direction Z.
  • the first recess 4C is arranged to overlap the first power semiconductor element 2A and the multiple first conductor posts 3A in the first direction Z.
  • the second recess 4D is arranged to overlap the second power semiconductor element 2B and the multiple second conductor posts 3B in the first direction Z.
  • each of the first conductor posts 3A is joined to the first wiring layer 41 exposed on the bottom surface of the first recess 4C by the above-mentioned bonding material, and the conductor layer 11 of the first insulating substrate 1A is joined to the second wiring layer 42 exposed on the underside of the first opposing portion 4A by the above-mentioned bonding material.
  • each of the second conductor posts 3B is joined to the first wiring layer 41 exposed on the bottom surface of the second recess 4D by the above-mentioned bonding material, and the conductor layer 11 of the second insulating substrate 1B is joined to the second wiring layer 42 exposed on the underside of the second opposing portion 4B by the above-mentioned bonding material.
  • the first recess 4C is sealed by the first insulating substrate 1A and the bonding material.
  • the second recess 4D is sealed by the second insulating substrate 1B and the bonding material.
  • the first power semiconductor element 2A and the multiple first conductor posts 3A are housed in the first recess 4C.
  • the second power semiconductor element 2B and the multiple second conductor posts 3B are housed in the second recess 4D.
  • the power module 300 according to Comparative Example 1 includes a plurality of insulating substrates 301, a plurality of power semiconductor elements 302, a plurality of bonding wires 303, and a plurality of lead frames 304.
  • Each bonding wire 303 electrically connects between the power semiconductor element 302 and the conductor layer of the insulating substrate 301, or between the power semiconductor element 302 and the lead frame 304.
  • the plurality of lead frames 304 are manufactured by punching a metal plate made of copper or iron, and therefore the inner leads 304A, which are the bonding areas with the bonding wires 303 in each of the plurality of lead frames 304, are arranged on the same plane.
  • the lead frames 304 are arranged so as not to overlap the power semiconductor elements 302 in a planar view, and furthermore, in a planar view, the portions 304B forming the external connection terminals of each of the multiple lead frames 304 are arranged outside the inner leads 304A, making it difficult to reduce the area of the power module 300 in a planar view.
  • the electrical path between the power semiconductor element and the external connection terminal is long because it includes the bonding wire 303 and the lead frame 304 that are connected in series with each other. Therefore, it is difficult to reduce the wiring inductance L of the power module 300.
  • the power module 310 according to Comparative Example 2 shown in Figures 22 and 23, the power module 320 according to Comparative Example 3 shown in Figures 24 and 25, and the power module 330 according to Comparative Example 4 shown in Figures 26 and 27 each include an insulating substrate 311, a first power semiconductor element 312A, a second power semiconductor element 312B, a conductor post 313, and a printed circuit board 314, just like the power module 101, but differ from the power module 101 in that no recess is formed in the printed circuit board 314.
  • the wiring layer 315 in the printed circuit board 314 forms an external connection terminal, and the electrical path between each power semiconductor element and the wiring layer 315 does not include a bonding wire or an inner lead, but instead includes a conductor post 313.
  • the conductor post 313 electrically connects the first power semiconductor element 312A or the second power semiconductor element 312B, which are arranged so as to overlap each other in a plan view, to the wiring layer in the printed circuit board 314. Therefore, in the power module 310, the length of the conductor post 313 can be made shorter than the combined length of the bonding wire and the inner lead, and the wiring inductance L can be made lower than that of the power module 300.
  • the entire printed circuit board 314 is disposed on the power semiconductor element 312. Therefore, it is difficult to reduce the dimensions of the power module 310 in the first direction Z, and in some cases the dimensions of the power module 310 in the first direction Z may be larger than those of the power module 300.
  • the power module 310 also requires a conductor block 317 for electrically connecting the opposing insulating substrate 311 and wiring layer 315 of the printed circuit board 314 without passing through the power semiconductor element 312.
  • the length of this conductor block 317 in the first direction Z is longer than that of the conductor post 313 by the thickness of the power semiconductor element. Therefore, it is difficult to reduce the manufacturing cost of the power module 310.
  • the printed circuit board 314 includes a conductor via 318 for electrically connecting the wiring layer 315 and the wiring layer 316 stacked in the first direction Z. Therefore, the manufacturing cost of the power module 310, which includes both the conductor block 317 and the conductor via 318, is high.
  • an external connection terminal 315A corresponding to the third external connection terminal 42A of the power module 101 and an external connection terminal 316A corresponding to the first external connection terminal 41A of the power module 101 are arranged on one end side of the power module 310 in the second direction Y.
  • the external connection terminal 315A, the conductor block 317, the first conductor layer of the insulating substrate 314, the power semiconductor element 312A, the wiring layer 315, the conductor block 317, the second conductor layer of the insulator layer 314, the power semiconductor element 312B, the conductor via 318, the wiring layer 316, and the external connection terminal 316A are electrically connected in this order.
  • the power module 320 according to Comparative Example 3 differs from the power module 310 in that the printed circuit board 314 does not include a conductor via 318. Inside such a power module 320, only a portion of the current path formed inside the power module 310 is formed, and the remainder of the current path must be formed outside the power module 320. Arrow C in FIG. 24 shows a schematic representation of the current path within the power module 320. In the power module 320, an external connection terminal 315C for connecting to external wiring forming the remainder of the current path is disposed on the end side opposite to the external connection terminal 315A corresponding to the third external connection terminal 42A of the power module 101.
  • the external connection terminal 315A, the conductor block 317, the first conductor layer of the insulating substrate 314, the power semiconductor element 312A, the wiring layer 315, the conductor block 317, the second conductor layer of the insulating layer 314, the power semiconductor element 312B, the wiring layer 315, and the external connection terminal 315C are electrically connected in this order. Therefore, the total length of the current path and the external wiring in the power module 320 is longer than the length of the current path electrically connecting the external connection terminal 315A and the external connection terminal 316A in the power module 310.
  • the power module 330 according to Comparative Example 4 shown in Figs. 26 and 27 differs from the power module 310 in that the printed circuit board 314 does not include the conductor via 318.
  • the power module 330 also differs from the power module 320 in that a current path equivalent to the current path formed inside the power module 310 is formed inside the power module 330.
  • the arrow C shown in Figs. 26 and 27 shows a schematic current path inside the power module 330.
  • the external connection terminal 315A, the conductor block 317, the first conductor layer of the insulating substrate 314, the power semiconductor element 312A, the wiring layer 315D, the conductor block 317, the second conductor layer of the insulating layer 314, the power semiconductor element 312B, the wiring layer 315E, and the external connection terminal 315F are electrically connected in this order.
  • the wiring layer 315D and the wiring layer 315E are arranged side by side between the control terminal 315G connected to the first power semiconductor element 312A and the control terminal 315G connected to the second power semiconductor element 312B. Therefore, in order to increase the dimension W2 of the wiring layer 315D in the third direction X to keep the wiring inductance low, it is necessary to increase the dimension of the power module 330 in the third direction X.
  • the power module 101 has a first conductor post 3A and a second conductor post 3B instead of a bonding wire 303 and a lead frame 304, so the wiring inductance L of the power module 101 can be lower than the wiring inductance L of the power module 300.
  • the thickness of a portion of the first opposing portion 4A that is arranged to overlap the first power semiconductor element 2A in the first direction Z is thinner than the thickness of the printed circuit board 314 that is arranged to overlap the power semiconductor elements 312A and 312B in the power modules 310 to 330.
  • power module 101 simultaneously achieves lower wiring inductance and smaller size due to high-speed switching operation compared to power module 300, and simultaneously achieves lower wiring inductance and thinner size due to high-speed switching operation compared to power modules 310 to 330.
  • the first recess 4C and the second recess 4D are formed in the printed circuit board 4, so the conductor block 317 that was required in the power modules 310 to 330, which do not have the first recess 4C and the second recess 4D, is not necessary. Therefore, the manufacturing cost of the power module 101 can be reduced compared to the power modules 310 to 330.
  • the power module 101 shown in Fig. 5 has a configuration basically similar to that of the power module 101 shown in Fig. 1 to Fig. 3, but differs from the power module 101 shown in Fig. 1 to Fig. 3 in that it includes a printed circuit board 4 that does not include a through via 45 and a conductor block 48 instead of the printed circuit board 4 that includes the through via 45.
  • the conductor block 48 is shown only in the second recess 4D, but it is sufficient that the conductor block 48 is disposed inside at least one of the first recess 4C and the second recess 4D.
  • a second semi-finished product 202 including a conductor block 48 is prepared, and the conductor block 48 is joined to the first wiring layer 41 of the printed circuit board 4 with a joining material such as solder.
  • the manufacturing cost of the printed circuit board 4 including the through vias 45 tends to be higher than the total manufacturing cost of the printed circuit board 4 not including the through vias 45 and the manufacturing cost of the conductor block 48.
  • the manufacturing cost of the printed circuit board 4 including the through vias 45 tends to be much higher than that of a printed circuit board not including the through vias 45, and further tends to be higher than the total manufacturing cost of a printed circuit board not including a typical conductor via and the conductor block. Therefore, the manufacturing cost of the power module 101 shown in FIG. 5 can be reduced compared to the power modules 101 shown in FIGS. 1 to 3.
  • the wiring inductance associated with high-speed switching operation is reduced and the size is made smaller than that of the power module 300, and the wiring inductance associated with high-speed switching operation is reduced and the thickness is made smaller than that of the power modules 310 to 330.
  • the power module 102 according to the second embodiment basically has the same configuration as the power module 101 according to the first embodiment, but Power module 102 differs from power module 101 in that second surface 1B1 of second insulating substrate 1B faces the side opposite to first surface 1A1 of first insulating substrate 1A.
  • the following mainly describes the differences between power module 102 and power module 101.
  • the first recess 4C faces the first surface 1A1.
  • the second recess 4D faces the second surface 1B1.
  • the first protective layer 46 of the printed circuit board 4 is not included in the second opposing portion 4B that faces the second insulating substrate 1B.
  • the first protective layer 46 is arranged side by side with the second insulating substrate 1B in the second direction Y and the third direction X.
  • the second protective layer 47 is not included in the first opposing portion 4A that faces the first insulating substrate 1A.
  • the second protective layer 47 is arranged side by side with the first insulating substrate 1A in the second direction Y and the third direction X.
  • the conductor layer 11 of the second insulating substrate 1B is joined to the first wiring layer 41 by a bonding material such as solder.
  • a bonding material such as solder.
  • Each of the main electrodes 21B and control electrodes 22B of the second power semiconductor element 2B is electrically connected to each pattern of the second wiring layer 42 via the second conductor post 3B.
  • a part of the second wiring layer 42 forms an external connection terminal 42C.
  • Another part of the second wiring layer 42 forms an external connection terminal 42D as a control external terminal.
  • Each of the first wiring layers 41 is not electrically connected to the second wiring layer 42.
  • the printed circuit board 4 does not include a through via 45 for electrically connecting at least one of the first wiring layers 41 to the second wiring layer 42.
  • each of the first wiring layers 41 and the second wiring layer 42 is electrically connected only via the first power semiconductor element 2A or the second power semiconductor element 2B.
  • the main electrode 21B of the second power semiconductor element 2B is electrically connected to the second wiring layer 42 via the second conductor post 3B.
  • the power module 102 has, for example, two-fold rotational symmetry around the center of a cross section perpendicular to the third direction X.
  • the center of the power module 102 is disposed within the insulating layer 44 of the printed circuit board 4.
  • a signal input to the third external connection terminal 42A passes through the second wiring layer 42 and the conductor layer 11 of the first insulating substrate 1A, reaches the back electrode of the first power semiconductor element 2A, and is output from the main electrode 21A of the first power semiconductor element 2A.
  • a signal output from the main electrode 21A of the first power semiconductor element 2A passes through the first conductor post 3A, the first wiring layer 41, and the conductor layer 11 of the second insulating substrate 1B, reaches the back electrode of the second power semiconductor element 2B, and is output from the main electrode 21B of the second power semiconductor element 2B.
  • a signal output from the main electrode 21B of the second power semiconductor element 2B passes through the second conductor post 3B and the second wiring layer 42, reaches the external connection terminal 42C, and is output to an external device.
  • the manufacturing method of the power module 102 has a basically similar configuration to the manufacturing method of the power module 101, but differs from the manufacturing method of the power module 101 in that the first semi-finished product 201 and the second semi-finished product 202 are arranged facing in opposite directions to each other on the printed circuit board 4, as shown in FIG. 10.
  • the manufacturing method of the power module 102 is also the same as the manufacturing method of the power module 101 in that the first opposing portion 4A is arranged to overlap the first surface 1A1 of the first insulating substrate 1A in the first direction Z, and the second opposing portion 4B is arranged to overlap the second surface 1B1 of the second insulating substrate 1B in the first direction Z.
  • the power module 102 can achieve the same effects as the power module 101. Furthermore, the manufacturing cost of the power module 102, which includes a printed circuit board 4 that does not include a through via 45, can be reduced compared to the manufacturing cost of the power module 101, which includes a printed circuit board 4 that includes a through via 45. In other words, the manufacturing cost of the power module 102 can be significantly reduced compared to the power modules 310 to 330.
  • the power module 103 according to the third embodiment has a configuration basically similar to that of the power module 102 according to the second embodiment, but differs from the power module 102 in that the first power semiconductor element 2A is embedded in the resin 6. The following mainly describes the differences between the power module 103 and the power module 102.
  • the second power semiconductor element 2B may also be embedded in a resin 6 different from the resin 6 in which the first power semiconductor element 2A is embedded.
  • the first conductor post 3A has an exposed portion 31A exposed from the resin 6 formed to cover the first power semiconductor element 2A.
  • the second conductor post 3B has an exposed portion 31B exposed from the resin 6 formed to cover the second power semiconductor element 2B.
  • the exposed portions 31A, 31B include, for example, the upper surfaces of the first conductor post 3A and the second conductor post 3B.
  • the exposed portion 31A is electrically connected to the first wiring layer 41 of the first opposing portion 4A via a bonding material (not shown).
  • the exposed portion 31B is electrically connected to the second wiring layer 42 of the second opposing portion 4B via a bonding material (not shown).
  • the bonding material (not shown) is not embedded in the resin 6.
  • At least one of the first power semiconductor element 2A and the second power semiconductor element 2B may be embedded in the resin.
  • the entire first conductor post 3A and the entire second conductor post 3B may be exposed from the resin 6.
  • the material constituting the resin 6 may be any resin material having electrical insulation properties.
  • the resin 6 formed to cover the first power semiconductor element 2A is not in contact with, for example, the first wiring layer 41 of the first opposing portion 4A.
  • the resin 6 formed to cover the second power semiconductor element 2B is not in contact with, for example, the second wiring layer 42 of the second opposing portion 4B.
  • the manufacturing method of the power module 103 has a structure basically similar to that of the power module 102, but differs from it in that a semi-finished product 203 shown in FIG. 12 is prepared in place of each of the semi-finished products 201, 202.
  • the resin 6 is formed so as to embed the entire first power semiconductor element 2A or the second power semiconductor element 2B and the other parts of the first conductor post 3A or the second conductor post 3B except for the exposed parts 31A, 31B.
  • the semi-finished product 203 may include a plurality of first power semiconductor elements 2A or a plurality of second power semiconductor elements 2B.
  • a process is performed in which the characteristics of the power semiconductor elements embedded in the resin 6 for each semi-finished product 203 are inspected, and the power module 103 is assembled using only the semi-finished products 203 that are judged to be good in this process. In this way, the power module 103 is not judged to be defective due to poor characteristics of some of the power semiconductor elements among the multiple semi-finished products 203.
  • any inspection may be performed, for example, a voltage test is performed. In the voltage test on the semi-finished products 203, a high voltage is applied to the power semiconductor elements embedded in the resin 6, so that appropriate inspection can be performed without generating discharge in the air.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are each embedded in the resin 6, so that the first power semiconductor element 2A and the second power semiconductor element 2B are less susceptible to the effects of the external environment (humidity and contamination). Therefore, the reliability of the power module 103 is high.
  • the power module 103 can be manufactured to include only semi-finished products 203 that have been confirmed to be non-defective through inspection. Therefore, the reliability and production efficiency of the power module 103 can be improved at the same time.
  • the semiconductor material of each of the first power semiconductor element 2A and the second power semiconductor element 2B of the power module 103 is not particularly limited, but may be silicon carbide (SiC). Although SiC is more expensive than silicon (Si), as described above, the production efficiency of the power module 103 is high, and therefore, the increase in manufacturing costs associated with the disposal of other good products due to the fact that some of the power semiconductor elements incorporated in the power module 103 are defective is suppressed.
  • the power module 103 may have a configuration similar to that of the power module 101 according to the first embodiment, except that the first power semiconductor element 2A is embedded in the resin 6.
  • the power module 104 according to the fourth embodiment has a basically similar configuration to the power module 102 according to the second embodiment, but differs from the power module 102 in that it includes a first conductor plate 1E as the first substrate instead of the first insulating substrate.
  • the following mainly describes the differences between the power module 104 and the power module 102.
  • the material constituting the first conductor plate 1E is, for example, a metal material with high thermal conductivity.
  • the first conductor 1E is, for example, a metal plate that acts as a heat spreader.
  • the first conductor plate 1E has a first surface 1E1 that faces the first opposing portion 4A.
  • the first power semiconductor element 2A is mounted on the first surface 1E1.
  • the power module 104 further includes, for example, a second conductor plate 1F as a second substrate.
  • the material constituting the second conductor plate 1F may be any metal material, for example a metal material with high thermal conductivity.
  • the second conductor plate 1F acts as a heat spreader.
  • the second conductor plate 1F has a second surface 1F1 facing the second opposing portion 4B.
  • the second power semiconductor element 2B is mounted on the second surface 1F1.
  • the thickness of the first conductor plate 1E is equal to the thickness of the first wiring layer 41 that faces it across the first power semiconductor element 2A, for example.
  • the thickness of the second conductor plate 1F is equal to the thickness of the second wiring layer 42 that faces it across the second power semiconductor element 2B, for example. In this way, warping of the power module 104 is reduced. Since each of the first conductor plate 1E and the second conductor plate 1F is a single metal plate, it is easy to adjust the thickness of each.
  • the manufacturing cost of the power module 104 is lower than that of the power modules 101 to 103.
  • the power module 104 may have a second insulating substrate 1B as the second substrate.
  • the power module 104 may have a similar configuration to the power module 101 according to the first embodiment, except that the power module 104 has a first conductive plate 1E instead of the first insulating substrate as the first substrate.
  • the first conductor plate 1E may include a thick portion 13 and a thin portion 14.
  • the thick portion 13 protrudes toward the printed circuit board 4 in the first direction Z more than the thin portion 14.
  • the first surface 1E1 is disposed as the top surface of the thick portion 13 at a position closest to the first opposing portion 4A on the surface of the first conductor plate 1E.
  • the thin portion 14 is disposed so as to surround the entire periphery of the thick portion 13 in a plan view.
  • the thick portion 13 is disposed inside the first recess 4C.
  • the thick portion 13 is formed so as to fit into the first recess 4C.
  • the second conductor plate 1F may also include a thick portion and a thin portion. In the power module 104 shown in FIG. 14, it is easier to align the first recess 4C of the printed circuit board 4 with the first conductor plate 1E than in the power module 103 shown in FIG. 13.
  • the power module 105 according to the fifth embodiment has a basically similar configuration to the power module 102 according to the second embodiment, but differs from the power module 105 in that the first power semiconductor element 2A, the plurality of first conductor posts 3A, and the portion of the first opposing portion 4A connected to the first conductor post 3A are embedded in resin 7.
  • the following mainly describes the differences between the power module 105 and the power module 102.
  • the first power semiconductor element 2A, the multiple first conductor posts 3A, the portion of the first opposing portion 4A that is connected to the first conductor post 3A via a bonding material (not shown), and the bonding material are embedded in the resin 7.
  • the second power semiconductor element 2B, the multiple second conductor posts 3B, the portion of the second opposing portion 4B that is connected to the second conductor post 3B via a bonding material (not shown), and the bonding material may also be embedded in a resin 7 that is different from the resin 7 in which the first power semiconductor element 2A is embedded.
  • the material that constitutes the resin 7 may be any resin material that has electrical insulation properties, such as an underfill resin.
  • a first power semiconductor element 2A having a plurality of first conductor posts 3A bonded to each of the main electrode 21A and the control electrode 22A, a second power semiconductor element 2B having a plurality of second conductor posts 3B bonded to each of the main electrode 21B and the control electrode 22B, and a printed circuit board 4 are prepared.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are not mounted on the first insulating substrate 1A or the second insulating substrate 1B.
  • first wiring layer 41 of the printed circuit board 4 and each of the first conductor posts 3A are joined by a bonding material (not shown), and the second wiring layer 42 and each of the first conductor posts 3A are joined by a bonding material (not shown).
  • resin 7 is formed to cover the first power semiconductor element 2A, the multiple first conductor posts 3A, and the portion of the first opposing portion 4A that is connected to the first conductor post 3A via a bonding material (not shown), which have been integrated in the previous process, as well as the bonding material.
  • resin 7 is formed to cover the second power semiconductor element 2B, the multiple second conductor posts 3B, and the portion of the second opposing portion 4B that is connected to the second conductor post 3B via a bonding material (not shown), as well as the bonding material.
  • Resin 7 is formed so as to expose the back electrodes of each of the first power semiconductor element 2A and the second power semiconductor element 2B.
  • the back electrode of the first power semiconductor element 2A exposed from the resin 7 is bonded to the conductor layer 11 of the first insulating substrate 1A by the bonding material 5, and the back electrode of the second power semiconductor element 2B exposed from the resin 7 is bonded to the second insulating substrate 1B by the bonding material 5.
  • the power module 105 is manufactured.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are each embedded in the resin 6, so that the first power semiconductor element 2A and the second power semiconductor element 2B are less susceptible to the effects of the external environment (humidity and contamination). Therefore, the reliability of the power module 105 is high.
  • the power module 105 may have a configuration similar to any of the power modules 101, 103, and 104 according to embodiments 1, 3, and 4, except that the first power semiconductor element 2A, the multiple first conductor posts 3A, and the portion of the first opposing portion 4A connected to the first conductor post 3A are embedded in the resin 7.
  • the power module 106 according to the sixth embodiment has a basically similar configuration to the power module 102 according to the second embodiment, but differs from the power module 102 in that the space between the first insulating substrate 1A and the first opposing portion 4A facing the first power semiconductor element 2A and the first conductor post 3A is filled with resin 8.
  • the following mainly describes the differences between the power module 106 and the power module 102.
  • the resin 8 fills the space formed around the first insulating substrate 1A, the first power semiconductor element 2A, the first conductor posts 3A, and the bonding material within the first recess 4C.
  • the space formed around the second insulating substrate 1B, the second power semiconductor element 2B, the multiple second conductor posts 3B, and the bonding material may also be filled with resin 8.
  • the material constituting the resin 8 is, for example, an underfill resin.
  • the material constituting the resin 8 has, for example, thermosetting or ultraviolet curing properties.
  • a first through hole 50A is formed in the first opposing portion 4A, which is connected to the inside of the first recess 4C.
  • the first through hole 50A is formed so as to penetrate the first wiring layer 41 and the first protective layer 46 that face the bottom surface of the first recess 4C.
  • a second through hole 50B that is connected to the inside of the second recess 4D is formed in the second opposing portion 4B.
  • the second through hole 50B is formed so as to penetrate the second wiring layer 42 and the second protective layer 47 that face the bottom surface of the second recess 4D.
  • the first through hole 50A and the second through hole 50B are formed as passages for introducing the resin 8 into the first recess 4C or the second recess 4D.
  • a printed circuit board 4 is prepared in which a first through hole 50A and a second through hole 50B are formed. Then, similar to the method for manufacturing the power module 102, the printed circuit board 4, the first semi-finished product 201, and the second semi-finished product 202 are assembled, and then a liquid curable resin material is introduced into the first recess 4C and the second recess 4D from the first through hole 50A and the second through hole 50B, respectively. The liquid curable resin material then hardens to form the resin 8, and the power module 106 is manufactured.
  • the first power semiconductor element 2A and the second power semiconductor element 2B are each embedded in the resin 6, so that the first power semiconductor element 2A and the second power semiconductor element 2B are less susceptible to the effects of the external environment (humidity and contamination). Therefore, the reliability of the power module 106 is high.
  • the first through hole 50A and the second through hole 50B are formed for introducing the material constituting the resin 8 into the first recess 4C and the second recess 4D, so that the resin 8 can be formed after assembling the printed circuit board 4, the first semi-finished product 201, and the second semi-finished product 202 in a similar procedure to the manufacturing method of the power module 102. Therefore, the power module 106 can be manufactured more easily than the power module 105.
  • the bonding material 5 that bonds the first insulating substrate 1A and the first power semiconductor element 2A is covered with resin 8, so that the bonding material 5 is prevented from breaking even when the power module 106 is placed in a temperature cycle environment. Therefore, the reliability of the power module 106 is high.
  • the power module 106 may have a configuration similar to any of the power modules 101, 103, and 104 according to the first, third, and fourth embodiments, except that the space between the first insulating substrate 1A and the first opposing portion 4A facing the first power semiconductor element 2A and the first conductor post 3A is filled with resin 8.
  • the power module 107 according to the seventh embodiment has a configuration basically similar to that of the power module 102 according to the second embodiment, but differs from the power module 106 in that the printed circuit board 4 is a ceramic board. The following mainly describes the differences between the power module 107 and the power module 102.
  • the printed circuit board 4 is a ceramic board and includes a substrate 49A made of ceramic, and a first wiring layer 41 and a second wiring layer 42 (conductor layers) laminated on the substrate 49A.
  • the first wiring layer 41 is disposed on one surface of the substrate 49A.
  • the second wiring layer 42 is disposed on the other surface of the substrate 49A.
  • the printed circuit board 4 may further include a substrate 49B and a substrate 49C, for example, sandwiching the substrate 49A, the first wiring layer 41, and the second wiring layer 42 in the first direction Z.
  • the material constituting the base materials 49A, 49B , and 49C includes at least one selected from the group consisting of alumina ( Al2O3 ), aluminum nitride (AlN), and silicon nitride ( Si3N4 ).
  • the thermal conductivity of such a ceramic material is higher than that of the resin material constituting the insulator layer 44.
  • the first recess 4C is formed by a through hole formed in the substrate 49A and a substrate 49B that closes the through hole.
  • the second recess 4D is formed by a through hole formed in the substrate 49A and a substrate 49C that closes the through hole.
  • the thermal conductivity of the printed circuit board 4 of the power module 107 is higher than that of the printed circuit board 4 of the power module 102, heat generated in the first power semiconductor element 2A is easily dissipated to the outside via the printed circuit board 4. As a result, the reliability of the power module 107 is high. Furthermore, since the earthquake resistance and impact resistance of the printed circuit board 4 of the power module 107 are higher than those of the printed circuit board 4 of the power module 102, the reliability of the power module 107 is high even in harsher environments where high earthquake resistance and impact resistance are required. The range of application of the power module 107 is wider than that of the power module 102.
  • the power module 107 may have a configuration similar to the power module 101 according to the first embodiment or any of the power modules 103 to 106 according to the third to sixth embodiments, except that the printed circuit board 4 is a ceramic board.
  • Embodiment 8. 19 has a configuration basically similar to that of the power module 106 of the sixth embodiment, but differs from the power module 106 in that it further includes a cooler 9A connected to the first insulating substrate 1A and a cooler 9B connected to the first opposing portion 4A. The following mainly describes the differences between the power module 108 and the power module 106.
  • the first insulating substrate 1A further has a third surface 1A2 located on the opposite side to the first surface 1A1.
  • the first opposing portion 4A further has a fourth surface 4A2 located on the opposite side to the surface on which the first recess 4C is formed.
  • the fourth surface 4A2 is the surface of the first protective layer 46.
  • the second insulating substrate 1B further has a fifth surface 1B2 located on the opposite side to the second surface 1B1.
  • the second opposing portion 4B further has a sixth surface 4B2 located on the opposite side to the surface on which the second recess 4D is formed.
  • the sixth surface 4B2 is the surface of the second protective layer 47.
  • the fifth surface 1B2 is disposed, for example, on the same plane as the fourth surface 4A2.
  • the sixth surface 4B2 is disposed, for example, on the same plane as the third surface 1A2.
  • the cooler 9A is connected, for example, to the third surface 1A2 of the first insulating substrate 1A and the sixth surface 4B2 of the second opposing portion 4B.
  • the cooler 9A is bonded to the third surface 1A2 and the sixth surface 4B2 by, for example, a bonding material 90.
  • the cooler 9B is connected, for example, to the fifth surface 1B2 of the second insulating substrate 1B and the fourth surface 4A2 of the first opposing portion 4A.
  • the cooler 9B is bonded to the fifth surface 1B2 and the fourth surface 4A2 by, for example, a bonding material 90.
  • Each of the coolers 9A and 9B may have any structure as long as it can dissipate heat generated in the first power semiconductor element 2A and the second power semiconductor element 2B to the outside, and may be, for example, a heat sink including a base portion 91 and a number of fins 92 connected to the base portion 91.
  • the material constituting the coolers 9A and 9B may be any material with high thermal conductivity, and may include, for example, copper (Cu) or aluminum (Al).
  • the material constituting the bonding material 90 may be any bonding material having a higher thermal conductivity than the material constituting the insulating layer 44 of the printed circuit board 4.
  • the material constituting the bonding material 90 may be a conductive adhesive.
  • the base material 10 of the first insulating substrate 1A which is made of an electrically insulating material, is interposed between the first power semiconductor element 2A and the cooler 9A, so that the first power semiconductor element 2A can be electrically insulated from the cooler 9A.
  • the power module 108 may include at least one of the coolers 9A and 9B.
  • the cooler 9A may be connected to at least a portion of the first insulating substrate 1A
  • the cooler 9B may be connected to at least a portion of the second insulating substrate 1B.
  • the power module 108 may have a configuration similar to any of the power modules 101 to 105 according to the first to fifth embodiments and the power module 107 according to the seventh embodiment, except that the power module 108 includes at least one of the coolers 9A and 9B. If the power module 107 includes the first conductor plate 1E as the first substrate like the power module 104, the material constituting the bonding material 90 may be selected from materials that have electrical insulation properties and a higher thermal conductivity than the material constituting the insulator layer 44 of the printed circuit board 4.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/JP2023/000401 2023-01-11 2023-01-11 パワーモジュール Ceased WO2024150303A1 (ja)

Priority Applications (4)

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PCT/JP2023/000401 WO2024150303A1 (ja) 2023-01-11 2023-01-11 パワーモジュール
DE112023005535.1T DE112023005535T5 (de) 2023-01-11 2023-01-11 Leistungsmodul
JP2024522041A JP7520273B1 (ja) 2023-01-11 2023-01-11 パワーモジュール

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064852A (ja) * 2007-09-05 2009-03-26 Okutekku:Kk 半導体装置及び半導体装置の製造方法
JP2009260318A (ja) * 2008-03-24 2009-11-05 Ngk Spark Plug Co Ltd 部品内蔵配線基板
JP2013197258A (ja) * 2012-03-19 2013-09-30 Ngk Spark Plug Co Ltd 回路基板、半導体モジュールの製造方法
US20160005684A1 (en) * 2014-07-07 2016-01-07 Infineon Technologies Austria Ag Electronic component and method for electrically coupling a semiconductor die to a contact pad
JP2016162977A (ja) * 2015-03-04 2016-09-05 株式会社イースタン 配線基板およびその製造方法
WO2017187559A1 (ja) * 2016-04-27 2017-11-02 三菱電機株式会社 高周波回路
JP2018011005A (ja) * 2016-07-15 2018-01-18 三菱電機株式会社 半導体装置
JP2019067949A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013070018A (ja) * 2011-09-09 2013-04-18 Ngk Spark Plug Co Ltd 半導体モジュール及びその製造方法
JP7021854B2 (ja) * 2017-01-24 2022-02-17 ゼネラル・エレクトリック・カンパニイ 電力用電子回路パッケージおよびその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064852A (ja) * 2007-09-05 2009-03-26 Okutekku:Kk 半導体装置及び半導体装置の製造方法
JP2009260318A (ja) * 2008-03-24 2009-11-05 Ngk Spark Plug Co Ltd 部品内蔵配線基板
JP2013197258A (ja) * 2012-03-19 2013-09-30 Ngk Spark Plug Co Ltd 回路基板、半導体モジュールの製造方法
US20160005684A1 (en) * 2014-07-07 2016-01-07 Infineon Technologies Austria Ag Electronic component and method for electrically coupling a semiconductor die to a contact pad
JP2016162977A (ja) * 2015-03-04 2016-09-05 株式会社イースタン 配線基板およびその製造方法
WO2017187559A1 (ja) * 2016-04-27 2017-11-02 三菱電機株式会社 高周波回路
JP2018011005A (ja) * 2016-07-15 2018-01-18 三菱電機株式会社 半導体装置
JP2019067949A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置

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JPWO2024150303A1 (https=) 2024-07-18
JP7520273B1 (ja) 2024-07-22
DE112023005535T5 (de) 2025-11-20

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