WO2024148798A1 - 一种存储器 - Google Patents

一种存储器 Download PDF

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Publication number
WO2024148798A1
WO2024148798A1 PCT/CN2023/111093 CN2023111093W WO2024148798A1 WO 2024148798 A1 WO2024148798 A1 WO 2024148798A1 CN 2023111093 W CN2023111093 W CN 2023111093W WO 2024148798 A1 WO2024148798 A1 WO 2024148798A1
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Prior art keywords
transistor
temperature coefficient
power supply
coupled
supply voltage
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PCT/CN2023/111093
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English (en)
French (fr)
Inventor
季汝敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular, to a memory.
  • the size of its on-resistance Ron will affect the sharing speed of the charge stored on the capacitor in the memory, thereby affecting the read and write speed of the memory.
  • the size of the on-resistance Ron of the MOSFET will be affected by the threshold voltage of the MOSFET, and the threshold voltage of the MOSFET is affected by the ambient temperature. Therefore, the ambient temperature affects the read and write speed of the memory.
  • the threshold voltage of MOSFET when the ambient temperature is low temperature will increase compared with the threshold voltage under normal temperature conditions, thereby causing its on-resistance Ron to increase under low temperature conditions, causing the reading and writing speed of the memory to slow down under low temperature conditions. Therefore, how to offset the increase in the threshold voltage of MOSFET caused by the decrease in ambient temperature is a technical problem that needs to be solved urgently.
  • An embodiment of the present disclosure provides a memory, including: a first voltage follower branch, used to generate a first voltage signal with a negative temperature coefficient; a first current generating branch, used to generate a first current signal with a negative temperature coefficient based on the first voltage signal with a negative temperature coefficient; a voltage generating branch, used to generate a reference power supply voltage signal with a negative temperature coefficient based on the first current signal with a negative temperature coefficient; a charge pump circuit, used to generate a word line start-up power supply voltage with a negative temperature coefficient based on the reference power supply voltage signal; a word line driving circuit, receiving the word line start-up power supply voltage, and used to provide the word line start-up power supply voltage to the driven word line when driving the word line.
  • the memory in the disclosed embodiment generates a first voltage signal with a negative temperature coefficient through a first voltage follower branch, generates a first current signal with a negative temperature coefficient according to the first voltage signal with a negative temperature coefficient through a first current generating branch, and then generates a reference power supply voltage signal with a negative temperature coefficient according to the first current signal with a negative temperature coefficient through a voltage generating branch to obtain a reference power supply voltage signal with a negative temperature coefficient, and finally generates a word line start-up power supply voltage with a negative temperature coefficient according to the reference power supply voltage signal with a negative temperature coefficient through a charge pump circuit, and provides a word line start-up power supply voltage with a negative temperature coefficient to the driven word line through a word line driving circuit when driving the word line, so that as the ambient temperature decreases, the word line start-up power supply voltage also increases, thereby ensuring that the reading and writing speeds of the memory are not affected by the ambient temperature.
  • FIG. 1a is a schematic diagram of the composition structure of a storage unit in a memory in the related art
  • FIG. 1b is a schematic diagram of the structure of a sub-word line driving circuit in the related art
  • FIG. 1c is a schematic diagram of the architecture of a memory in the related art
  • FIG2 is a schematic diagram of a memory structure in an exemplary embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the composition structure of a first voltage follower branch in an exemplary embodiment of the present disclosure
  • FIG4 is a schematic diagram of the composition structure of a first voltage follower branch in another exemplary embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the composition structure of a first voltage follower branch in another exemplary embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the composition structure of a first voltage follower branch in yet another exemplary embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the composition structure of a first current generating branch in an exemplary embodiment of the present disclosure
  • FIG8 is a schematic diagram of the composition structure of a first current generating branch in another exemplary embodiment of the present disclosure.
  • FIG9 is a schematic diagram of a composition structure of a memory in another exemplary embodiment of the present disclosure.
  • FIG10 is a schematic diagram of the composition structure of a second voltage follower branch in an exemplary embodiment of the present disclosure
  • FIG11 is a schematic diagram of the composition structure of a second current generating branch in an exemplary embodiment of the present disclosure.
  • FIG12 is a schematic diagram of the composition structure of a second current generating branch in another exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the composition structure of a reference power supply voltage circuit including a total current generating circuit and a voltage generating branch in an exemplary embodiment of the present disclosure
  • FIG14 is a schematic diagram of the composition structure of a charge pump circuit in an exemplary embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram showing changes in a compensated word line start-up power supply voltage in an exemplary embodiment of the present disclosure.
  • the memory in the embodiments of the present disclosure may be understood to be a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM).
  • the semiconductor memory device may be a dual data rate SDRAM (DDR SDRAM) or a low power dual data rate SDRAM (LPDDR SDRAM).
  • DDR SDRAM dual data rate SDRAM
  • LPDDR SDRAM low power dual data rate SDRAM
  • the semiconductor memory device may be DDR3, DDR4, DDR5, etc.
  • FIG. 1c is a schematic diagram of the architecture of a memory in the related art.
  • the memory includes a plurality of memory arrays 101, a plurality of sub-word line drive circuits (SWD) 102 disposed on the right side of the memory array 101, and a plurality of sense amplifiers (SA) 103 disposed below the memory array 101.
  • the sub-word line drive circuit 102 is used to provide a drive voltage to the word line in the memory array 101 so as to perform a read or write operation on the memory array 101.
  • FIG. 1 b is a schematic diagram of the structure of a sub-word line driving circuit in the related art.
  • the sub-word line driving circuit 102 includes: a PMOS transistor P13 , a first NMOS transistor N13 , and a second NMOS transistor N23 .
  • the source of the PMOS transistor P13 is coupled to the word line driving power supply voltage PXID (equivalent to the word line start-up power supply voltage vwlp); the drain of the PMOS transistor P13 is coupled to the word line WL of the storage array 101; the gate of the PMOS transistor P13 is used to receive the main word line driving signal WMLa, so as to turn on or off the PMOS transistor P13 according to the main word line driving signal WMLa, so that the word line start-up power supply voltage vwlp is transmitted to the word line WL of the storage array 101.
  • PXID equivalent to the word line start-up power supply voltage vwlp
  • the drain of the PMOS transistor P13 is coupled to the word line WL of the storage array 101
  • the gate of the PMOS transistor P13 is used to receive the main word line driving signal WMLa, so as to turn on or off the PMOS transistor P13 according to the main word line driving signal WMLa, so that the word line start-up power supply voltage vwlp
  • the drain of the first NMOS transistor N13 is coupled to the word line WL of the memory array 101; the source of the first NMOS transistor N13 is coupled to the ground power supply voltage VSS; the gate of the first NMOS transistor N13 is coupled to the gate of the PMOS transistor P13, and is used to receive the main word line drive signal WMLa, so as to turn on or off the first NMOS transistor N13 according to the main word line drive signal WMLa, so that the ground power supply voltage VSS is transmitted to the word line WL of the memory array 101.
  • the drain of the second NMOS transistor N23 is coupled to the word line WL of the memory array 101; the source of the second NMOS transistor N23 is coupled to the ground power supply voltage VSS; the gate of the second NMOS transistor N23 is used to receive the inverted signal PXIB of the word line driving power supply voltage PXID, so as to turn on or off the second NMOS transistor N23 according to the inverted signal PXIB, so that the ground power supply voltage VSS is transmitted to the word line WL of the memory array 101.
  • the operation of the sub-word line driving circuit 102 may be in the following situations:
  • Case 1 when the main word line drive signal WMLa is at a high level, the word line drive power supply voltage PXID is at a high level, and the corresponding inverting signal PXIB is at a low level, the PMOS transistor P13 is turned off, the first NMOS transistor N13 is turned on, and the second NMOS transistor N23 is turned off, and the ground power supply voltage VSS is transmitted to the word line WL of the memory array 101 through the first NMOS transistor N13;
  • Case 2 when the main word line drive signal WMLa is at a high level, the word line drive power supply voltage PXID is at a low level, and the corresponding inverting signal PXIB is at a high level, the PMOS transistor P13 is turned off, the first NMOS transistor N13 is turned on, and the second NMOS transistor N23 is turned on. At the same time, the ground power supply voltage VSS is transmitted to the word line WL of the memory array 101 through the first NMOS transistor N13 and the second NMOS transistor N23;
  • Case 3 When the main word line drive signal WMLa is at a low level, the word line drive power supply voltage PXID is at a high level, and the corresponding inverting signal PXIB is at a low level, the PMOS transistor P13 is turned on, the first NMOS transistor N13 is turned off, and the second NMOS transistor N23 is turned off, and the word line drive power supply voltage PXID (high level) is transmitted to the word line WL of the storage array 101 through the PMOS transistor P13.
  • FIG. 1a is a schematic diagram of the composition structure of a storage unit in a memory in the related art.
  • a storage unit in a memory includes an Access MOSFET and a storage capacitor Cmbit, wherein the control electrode (gate) of the MOSFET is coupled to the word line, the first electrode (drain or source) of the MOSFET is coupled to the bit line, the second electrode (source or drain) of the MOSFET is coupled to the ground power supply voltage, and Ccol array is the coupling capacitor of the bit line.
  • the size of its on-resistance Ron will affect the sharing speed of the charge stored in Cmbit; when the ambient temperature is low, the threshold voltage of the MOSFET will increase, causing its Ron to increase under low temperature conditions, thus affecting the speed of reading and writing a storage unit in the DRAM under low temperature conditions; in order to offset the problem of the increase in the threshold voltage of the MOSFET due to the decrease in temperature, the voltage value of vwlp can be appropriately increased under low temperature conditions.
  • FIG. 2 is a schematic diagram of a memory structure in an exemplary embodiment of the present disclosure.
  • the memory 20 may include: a first voltage following branch 201, which may generate a first voltage signal with a negative temperature coefficient; a first current generating branch 202, which may be used to generate a first current signal with a negative temperature coefficient according to the first voltage signal with a negative temperature coefficient; a voltage generating branch
  • the circuit 203 can be used to generate a reference power supply voltage signal with a negative temperature coefficient according to a first current signal with a negative temperature coefficient;
  • the charge pump circuit 204 can be used to generate a word line start-up power supply voltage with a negative temperature coefficient according to the reference power supply voltage;
  • the word line driving circuit 205 can receive the word line start-up power supply voltage and can be used to provide the word line start-up power supply voltage to the driven word line when driving the word line.
  • the first voltage signal with a negative temperature coefficient refers to a voltage signal whose voltage value increases as the temperature decreases, or whose voltage value decreases as the temperature increases.
  • the first voltage follower branch 201 may be a circuit including a device with a negative temperature coefficient.
  • the device with a negative temperature coefficient may be a device with a PN junction such as a transistor or a diode, or may be other devices with a negative temperature coefficient, which are not specifically limited here.
  • the first voltage signal with a negative temperature coefficient and the first current signal with a negative temperature coefficient may be in a linear proportional relationship, or other known relationships.
  • the voltage value of the first voltage signal with a negative temperature coefficient may be N times the current value of the first current signal with a negative temperature coefficient; N is a number greater than 1.
  • the voltage value of the reference power supply voltage signal with a negative temperature coefficient and the current value of the first current signal with a negative temperature coefficient may also be in a linear proportional relationship, or other known relationships.
  • the voltage value of the reference power supply voltage signal with a negative temperature coefficient may be M times the current value of the first current signal with a negative temperature coefficient; M is a number greater than 1.
  • the voltage value of the word line start-up power supply voltage with a negative temperature coefficient and the voltage value of the reference power supply voltage signal with a negative temperature coefficient may also be in a linear proportional relationship, or other known relationships.
  • the voltage value of the word line start-up power supply voltage with a negative temperature coefficient may be Q times the voltage value of the reference power supply voltage signal; Q is a number greater than 1.
  • the word line driving circuit 205 can provide the word line start power supply voltage to the driven word line when driving the word line. It can be understood that the memory includes multiple word line driving circuits 205, and the circuit structure of the word line driving circuit 205 is not limited to the structure shown in FIG. 1b. Each word line driving circuit 205 includes a word line start power supply voltage input terminal, but not every word line driving circuit 205 in the memory The word line start power supply voltage input terminal will receive the word line start power supply voltage, but needs to be determined according to the row address.
  • the composition of the sub-line driving circuit 205 can be seen in FIG. 1 b , where the word line start-up power supply voltage input terminal is coupled to the source of the PMOS transistor P13 to receive the word line start-up power supply voltage.
  • a first voltage signal with a negative temperature coefficient is generated through a first voltage follower branch, a first current signal with a negative temperature coefficient is generated through a first current generating branch according to the first voltage signal with a negative temperature coefficient, and then a reference power supply voltage signal with a negative temperature coefficient is generated through a voltage generating branch according to the first current signal with a negative temperature coefficient to obtain a reference power supply voltage signal with a negative temperature coefficient, and finally a word line start-up power supply voltage with a negative temperature coefficient is generated through a charge pump circuit according to the reference power supply voltage signal with a negative temperature coefficient, and when driving the word line, a word line start-up power supply voltage with a negative temperature coefficient is provided to the driven word line through a word line driving circuit, so that as the ambient temperature decreases, the word line start-up power supply voltage also increases, thereby ensuring that the read and write speeds of the memory are not affected by the ambient temperature.
  • FIG. 3 is a schematic diagram of the composition structure of a first voltage follower branch in an exemplary embodiment of the present disclosure.
  • the first voltage follower branch 201 may include: a constant current source Is, the input end of the constant current source Is is used to receive a first power supply voltage VDD; a first transistor Q1, the control electrode and the first electrode of the first transistor Q1 are both coupled to the ground power supply voltage VSS, and the second electrode of the first transistor Q1 is coupled to the output end of the constant current source Is to generate a first voltage signal with a negative temperature coefficient; a first operational amplifier AP1, the positive input end of the first operational amplifier AP1 is respectively coupled to the output end of the constant current source Is and the second electrode of the first transistor Q1, and the negative input end of the first operational amplifier AP1 is coupled to the first current generating branch 202 to provide the first current generating branch 202 with a first voltage signal with a negative temperature coefficient; the output end of the first operational amplifier AP1 is also coupled to the first current generating branch 202.
  • the first transistor Q1 can be a PNP-type triode, and the control electrode, the first electrode, and the second electrode of the first transistor Q1 are respectively the base, the collector, and the emitter of the PNP-type triode.
  • the first transistor Q1 since the control electrode and the first electrode of the first transistor Q1 are both coupled to the ground power supply voltage, the first transistor Q1 is equivalent to a diode, the emitter of the first transistor Q1 is equivalent to the anode of the diode, and the base and the collector of the first transistor Q1 are both equivalent to the cathode of the diode. In this way, when the anode of the diode is coupled to the output end of the constant current source and the cathode is coupled to the ground power supply voltage, the diode is subjected to a forward voltage drop and is in a conducting state.
  • VBE voltage difference between the emitter and the base of the first transistor Q1 (equal to the voltage VE on the emitter) and the negative temperature characteristics of the conduction of the diode or PN junction (-2mV/°C), it can be known that under normal temperature conditions, VBE is approximately 0.7V, and under low temperature conditions, VBE is approximately 0.77V.
  • the first transistor Q1 is turned on, VBE (VE) is generated on the emitter of the first transistor Q1 , and then the first operational amplifier AP follows and outputs a first voltage signal having a negative temperature coefficient that is the same as the VBE voltage value.
  • VBE VBE
  • a diode is connected to the first transistor so that the equivalent diode of the first transistor is forward biased, causing the diode to be turned on, thereby generating a first voltage signal with a negative temperature coefficient. Then, the first operational amplifier follows the output of the first voltage signal with a negative temperature coefficient, so as to subsequently generate a reference power supply voltage signal with a negative temperature coefficient based on the first voltage signal with a negative temperature coefficient.
  • FIG. 4 is a schematic diagram of the composition structure of a first voltage follower branch in another exemplary embodiment of the present disclosure.
  • the first voltage follower branch 201 includes: a constant current source Is, the input end of the constant current source Is is used to receive a first power supply voltage VDD; a first transistor Q1, the control electrode and the first electrode of the first transistor Q1 are both coupled to the output end of the constant current source Is, and the second electrode of the first transistor Q1 is coupled to the ground power supply voltage VSS to generate a first voltage signal with a negative temperature coefficient; a first operational amplifier AP1, the positive input end of the first operational amplifier AP1 is respectively coupled to the output end of the constant current source Is and the first electrode of the first transistor Q1, and the negative input end of the first operational amplifier AP1 is coupled to the first current generating branch 202 to provide the first current generating branch 202 with a first voltage signal with a negative temperature coefficient; the output end of the first operational amplifier AP1 is also coupled to the first current generating branch 202.
  • the first transistor Q1 can be an NPN transistor, and the control electrode, the first electrode, and the second electrode of the first transistor Q1 are respectively the base, the collector, and the emitter of the PNP transistor.
  • the first transistor Q1 since the control electrode and the first electrode of the first transistor Q1 are both coupled to the output end of the constant current source Is, the first transistor Q1 is equivalent to a diode, the collector and the base of the first transistor Q1 can be equivalent to the anode of the diode, and the emitter of the first transistor Q1 is equivalent to the cathode of the diode.
  • the diode when the anode of the diode is coupled to the output end of the constant current source and the cathode is coupled to the ground power supply voltage, the diode is subjected to a forward voltage drop and is in a conducting state.
  • VBE voltage difference between the emitter and the base of the first transistor Q1 (equal to the voltage VC on the collector of the first transistor Q1) and the negative temperature characteristics of the conduction of the diode or PN junction (-2mV/°C), it can be known that under normal temperature conditions, VBE is approximately 0.7V, and under low temperature conditions, VBE is approximately 0.77V.
  • the first transistor Q1 is turned on, VBE (VC) is generated on the collector of the first transistor Q1 , and then the first operational amplifier AP follows and outputs a first voltage signal having a negative temperature coefficient that is the same as the VBE voltage value.
  • a diode is connected to the first transistor so that the equivalent diode of the first transistor is forward biased, causing the diode to be turned on, thereby generating a first voltage signal with a negative temperature coefficient. Then, the first operational amplifier follows the output of the first voltage signal with a negative temperature coefficient, so as to subsequently generate a reference power supply voltage signal with a negative temperature coefficient based on the first voltage signal with a negative temperature coefficient.
  • FIG. 5 is a schematic diagram of the composition structure of a first voltage follower branch in yet another exemplary embodiment of the present disclosure.
  • the first transistor Q1 is also a PNP type triode, but the first The diode connection method of transistor Q1 is different from that in FIG3 .
  • the emitter and collector (as the anode of the equivalent diode) of the first transistor Q1 in FIG5 are both coupled to the output end of the constant current source Is, and the base of the first transistor Q1 (as the cathode of the equivalent diode) is coupled to the ground power supply voltage VSS.
  • the diode equivalent to the first transistor Q1 is subjected to a forward voltage drop and is in a conducting state, thereby generating a first voltage signal with a negative temperature coefficient at the emitter (output end) of the first transistor Q1.
  • FIG. 6 is a schematic diagram of the composition structure of a first voltage follower branch in yet another exemplary embodiment of the present disclosure.
  • the first transistor Q1 is also an NPN-type triode, but the diode connection method of the first transistor Q1 in FIG6 is different from that in FIG4 .
  • the emitter and collector (as the cathode of the equivalent diode) of the first transistor Q1 in FIG4 are both coupled to the ground power supply voltage VSS, and the base of the first transistor Q1 (as the anode of the equivalent diode) is coupled to the output end of the constant current source Is.
  • the equivalent diode of the first transistor Q1 is subjected to a forward voltage drop and is in a conducting state, thereby generating a first voltage signal with a negative temperature coefficient at the base (output end) of the first transistor Q1.
  • the diode connection method of the first transistor Q1 can also be that the collector of the first transistor Q1 is coupled to the output end of the constant current source Is, the base of the first transistor Q1 is coupled to the ground power supply voltage VSS, and the emitter of the first transistor Q1 is suspended, or the emitter of the first transistor Q1 is coupled to the output end of the constant current source Is, the base of the first transistor Q1 is coupled to the ground power supply voltage VSS, and the collector of the first transistor Q1 is suspended; when the first transistor Q1 is an NPN-type transistor, the diode connection method of the first transistor Q1 can also be that the base of the first transistor Q1 is coupled to the output end of the constant current source Is, the collector of the first transistor Q1 is coupled to the ground power supply voltage VSS, and the emitter of the first transistor Q1 is suspended, or the base of the first transistor Q1 is coupled to
  • the first transistor Q1 in the first voltage follower branch 201 may be replaced by a diode D1 , the anode of D1 being coupled to the output end of the constant current source Is, and the cathode of D1 being coupled to the ground power supply voltage VSS.
  • FIG. 7 is a schematic diagram of the composition structure of a first current generating branch in an exemplary embodiment of the present disclosure.
  • the first current generating branch 202 includes: a second transistor Q2, wherein the control terminal of the second transistor Q2 is coupled to the output terminal of the first operational amplifier AP1; a first resistor R1, wherein the first terminal of the first resistor R1 is respectively coupled to the second terminal of the second transistor Q2 and the negative input terminal of the first operational amplifier AP1, and the second terminal of the first resistor R1 is coupled to the ground power supply voltage VSS, so as to generate a first current signal with a negative temperature coefficient at the first resistor according to the first voltage signal with a negative temperature coefficient and the first resistor; a third transistor Q3, wherein the control terminal and the first terminal of the third transistor Q3 are both coupled to the first terminal of the second transistor Q2; the second terminal of the third transistor Q3 is coupled to the first power supply voltage VDD; a fourth transistor Q4, wherein the control terminal of the fourth transistor Q4 is coupled to the first terminal of the second transistor Q2, the first terminal of the fourth transistor Q4
  • the second transistor Q2 can be an NMOS transistor; the third transistor Q3 and the fourth transistor Q4 can both be PMOS transistors; the first ends of the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are all drains, the second ends are all sources, and the control electrodes are all gates.
  • the first end of the first resistor R1 is coupled to the negative input end of the first operational amplifier AP1, and the input at the positive input end of the first operational amplifier AP1 is a first voltage signal with a negative temperature coefficient, according to the "virtual short" and “virtual open” characteristics of the amplifier, it can be known that the negative input end of the first operational amplifier AP1 and the first end of the first resistor R1 are also first voltage signals with a negative temperature coefficient. In this way, a first current signal with a negative temperature coefficient can be generated on the first resistor R1.
  • the first voltage signal having a negative temperature coefficient may be VBE
  • the current value I1 of the first current signal having a negative temperature coefficient may be equal to a quotient of VBE divided by a resistance value of the first resistor R1.
  • the gate of the third transistor Q3, the gate of the fourth transistor Q4, and the drain of the third transistor Q3 are all coupled to the drain of the second transistor Q2, the source of the third transistor Q3 and the source of the fourth transistor Q4 are all coupled to the first power supply voltage VDD, a current mirror structure is formed.
  • the current on the drain of the third transistor Q3 can be mirrored to the drain of the fourth transistor Q4, and the current on the drain of the third transistor Q3 is the same as the current on the first resistor R1, both of which are first current signals with negative temperature coefficients.
  • the drain of the fourth transistor Q4 is coupled to the voltage generating branch 203, and the first current signal with a negative temperature coefficient can be output to the voltage generating branch 203.
  • the output terminal of the first operational amplifier AP1 is coupled via the control terminal of the second transistor Q2; the first terminal of the first resistor R1 is respectively coupled to the second terminal of the second transistor Q2 and the negative input terminal of the first operational amplifier AP1, and the second terminal of the first resistor R1 is coupled to the ground power supply voltage VSS, so as to generate a first current signal with a negative temperature coefficient at the first resistor according to the first voltage signal with a negative temperature coefficient and the first resistor; the control terminal and the first terminal of the third transistor Q3 are both coupled to the first terminal of the second transistor Q2; the second terminal of the third transistor Q3 is coupled to the first power supply voltage VDD; the control terminal of the fourth transistor Q4 is coupled to the first terminal of the second transistor Q2, the first terminal of the fourth transistor Q4 is coupled to the voltage generating branch, and the second terminal of the fourth transistor Q4 is coupled to the first power supply voltage VDD, so as to mirror the first current signal with a negative temperature coefficient to the voltage generating branch, so that
  • FIG. 8 is a schematic diagram of the composition structure of a first current generating branch in another exemplary embodiment of the present disclosure.
  • the first current generating branch 202 includes: an eighth transistor Q8, wherein the control end of the eighth transistor Q8 is coupled to the output end of the first operational amplifier AP1; the first end of the eighth transistor Q8 is coupled to the first power supply voltage VDD; a fourth resistor R4, wherein the first end of the fourth resistor R4 is respectively coupled to the second end of the eighth transistor Q8 and the negative input end of the first operational amplifier AP1, and the second end of the fourth resistor R4 is coupled to the ground power supply voltage VSS, so as to generate a first current signal with a negative temperature coefficient at the fourth resistor R4 according to the first voltage signal with a negative temperature coefficient and the fourth resistor R4; a ninth transistor Q9, wherein the control end of the ninth transistor Q9 is coupled to the output end of the first operational amplifier AP1; the first end of the ninth transistor Q9 is coupled to the first power supply voltage VDD, so as to mirror the first current signal with a negative temperature coefficient to the voltage
  • the eighth transistor Q8 and the ninth transistor Q9 may both be PMOS transistors; the first ends of the eighth transistor Q8 and the ninth transistor Q9 are both drains, the second ends are both sources, and the control electrodes are both gates.
  • the implementation method of generating the first current signal with a negative temperature coefficient on the fourth resistor R4 in the embodiment of the present disclosure is the same as the implementation method of forming the first current signal with a negative temperature coefficient on the first resistor R1 in Figure 7, which is not elaborated here.
  • the control end of the eighth transistor Q8 and the control end of the ninth transistor Q9 are both coupled to the output end of the first operational amplifier AP1; the first end of the eighth transistor Q8 and the first end of the ninth transistor Q9 are both coupled to the first power supply voltage VDD, a current mirror structure is formed, and the current at the second end of the eighth transistor Q8 can be mirrored to the second end of the ninth transistor Q9.
  • the second end of the ninth transistor Q9 is coupled to the voltage generating branch 203, and the first current signal with a negative temperature coefficient can be output to the voltage generating branch 203.
  • FIG. 9 is a schematic diagram of a composition structure of a memory in another exemplary embodiment of the present disclosure.
  • the memory 20 provided in the embodiment of the present disclosure may also include: a second voltage following branch 206, used to obtain a second voltage signal with a zero temperature coefficient; a second current generating branch 207, used to generate a second current signal with a zero temperature coefficient based on the second voltage signal with a zero temperature coefficient; the voltage generating branch 203 is also used to generate a reference power supply voltage signal with a negative temperature coefficient based on the first current signal with a negative temperature coefficient and the second current signal with a zero temperature coefficient.
  • the second voltage signal with zero temperature coefficient is a voltage signal whose voltage value does not change with temperature changes.
  • a second voltage signal with a zero temperature coefficient is obtained through a second voltage following branch, a second current signal with a zero temperature coefficient is generated based on the second voltage signal with a zero temperature coefficient through a second current generating branch, and then a reference power supply voltage signal with a negative temperature coefficient is generated based on a first current signal with a negative temperature coefficient and a second current signal with a zero temperature coefficient through a voltage generating branch. Since the reference power supply voltage signal with a negative temperature coefficient is generated based on the second current signal with a zero temperature coefficient and the first current signal with a negative temperature coefficient, the size of the reference power supply voltage signal can be changed without changing the negative temperature coefficient of the reference power supply voltage signal.
  • FIG. 10 is a schematic diagram of the composition structure of a second voltage follower branch in an exemplary embodiment of the present disclosure.
  • the second voltage follower branch 206 may include: a second operational amplifier AP2, the positive input terminal of the second operational amplifier AP2 is used to receive a second power supply voltage VBGR with a zero temperature coefficient; the negative input terminal of the second operational amplifier AP2 is coupled to the second current generating branch 207 to provide the second current generating branch 207 with a second power supply voltage with a zero temperature coefficient; the output terminal of the second operational amplifier AP2 is also coupled to the second current generating branch 207.
  • a second operational amplifier follows the input second power supply voltage with zero temperature coefficient and outputs a second current generating branch, so that the second current generating branch generates a second current signal with zero temperature coefficient according to the second power supply voltage with zero temperature coefficient.
  • FIG. 11 is a schematic diagram of the composition structure of a second current generating branch in an exemplary embodiment of the present disclosure.
  • the second current generating branch 207 may include: a fifth transistor Q5, wherein the control end of the fifth transistor Q5 is coupled to the output end of the second operational amplifier AP2, and the second end of the fifth transistor Q5 is coupled to the negative input end of the second operational amplifier AP2, so that the second power supply voltage with a zero temperature coefficient is provided at the second end of the fifth transistor Q5; a second resistor R2, wherein the first end of the second resistor R2 is respectively coupled to the second end of the fifth transistor Q5 and the negative input end of the second operational amplifier AP2, and the second end of the second resistor R2 is coupled to the ground power supply voltage, so that the second power supply voltage with a zero temperature coefficient is provided at the second end of the fifth transistor Q5.
  • the second power supply voltage and the second resistor R2 generate a second current signal with a zero temperature coefficient at the second resistor R2; a sixth transistor Q6, the control end and the first end of the sixth transistor Q6 are both coupled to the first end of the fifth transistor Q5; the second end of the sixth transistor Q6 is coupled to the first power supply voltage; a seventh transistor Q7, the control end of the seventh transistor Q7 is coupled to the first end of the fifth transistor Q5, the first end of the seventh transistor Q7 is coupled to the voltage generating branch 103, and the second end of the seventh transistor Q7 is coupled to the first power supply voltage to mirror the second current signal with a zero temperature coefficient to the voltage generating branch 203.
  • the fifth transistor Q5 can be an NMOS transistor; the sixth transistor Q6 and the seventh transistor Q7 can both be PMOS transistors; the first ends of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are all drains, the second ends are all sources, and the control electrodes are all gates.
  • the negative input end of the second operational amplifier AP2 and the first end of the second resistor R2 are also second voltage signals with a zero temperature coefficient. In this way, a second current signal with a zero temperature coefficient can be generated on the second resistor R2. Without changing the negative temperature coefficient of the reference power supply voltage signal, the size of the reference power supply voltage signal can be changed only by changing the resistance value of R2.
  • the second voltage signal with a zero temperature coefficient may be VBGR
  • the current value I2 of the second current signal with a zero temperature coefficient may be equal to the quotient of VBGR divided by the impedance value of the second resistor R2.
  • the gate of the sixth transistor Q6, the gate of the seventh transistor Q7, and the drain of the sixth transistor Q6 are all coupled to the drain of the fifth transistor Q5, the source of the sixth transistor Q6 and the gate of the seventh transistor Q7 are connected to the drain of the fifth transistor Q5.
  • the source of the body transistor Q7 is coupled to the first power supply voltage VDD, forming a current mirror structure. In this way, the current on the drain of the sixth transistor Q6 can be mirrored to the drain of the seventh transistor Q7, and the current on the drain of the sixth transistor Q6 is the same as the current on the second resistor R2, both of which are second current signals with zero temperature coefficient.
  • the drain of the seventh transistor Q7 is coupled to the voltage generating branch 203, and the second current signal with zero temperature coefficient can be output to the voltage generating branch 203.
  • the control terminal of the fifth transistor Q5 is coupled to the output terminal of the second operational amplifier AP2, and the second terminal of the fifth transistor Q5 is coupled to the negative input terminal of the second operational amplifier AP2, so that the second terminal of the fifth transistor Q5 has a second power supply voltage with a zero temperature coefficient;
  • the first terminal of the second resistor R2 is respectively coupled to the second terminal of the fifth transistor Q5 and the negative input terminal of the second operational amplifier AP2, and the second terminal of the second resistor R2 is coupled to the ground power supply voltage, so that a second current signal with a zero temperature coefficient is generated at the second resistor R2 according to the second power supply voltage with a zero temperature coefficient and the second resistor R2;
  • the control terminal and the first terminal of the sixth transistor Q6 are both coupled to the fifth transistor Q5.
  • the second end of the sixth transistor Q6 is coupled to the first power supply voltage; the control end of the seventh transistor Q7 is coupled to the first end of the fifth transistor Q5, the first end of the seventh transistor Q7 is coupled to the voltage generating branch, and the second end of the seventh transistor Q7 is coupled to the first power supply voltage, so as to mirror-output the second current signal with a zero temperature coefficient to the voltage generating branch, so that the voltage generating branch generates a reference power supply voltage signal with a negative temperature coefficient according to the second current signal with a zero temperature coefficient and the first current signal with a negative temperature coefficient.
  • the size of the reference power supply voltage signal can be changed only by changing the resistance value of R2.
  • FIG. 12 is a schematic diagram of the composition structure of a second current generating branch in another exemplary embodiment of the present disclosure.
  • the second current generating branch 207 includes: a tenth transistor Q10, wherein the control end of the tenth transistor Q10 is coupled to the output end of the second operational amplifier AP2; a first end of the tenth transistor Q10 is coupled to the first power supply voltage VDD; a fifth resistor R5, wherein the first end of the fifth resistor R5 is respectively coupled to the second end of the tenth transistor Q10 and the negative input end of the second operational amplifier AP2, and the second end of the fifth resistor R5 is coupled to the ground power supply voltage VSS, so as to generate a second current signal with a zero temperature coefficient in the fifth resistor R5 according to the second voltage signal with a zero temperature coefficient and the fifth resistor R5; an eleventh transistor Q11, wherein the control end of the eleventh transistor Q11 is coupled to the output end of the second operational amplifier AP2; and a first end of the eleventh transistor Q11 is coupled to the first power supply voltage VDD, so as
  • the tenth transistor Q10 and the eleventh transistor Q11 may both be PMOS transistors; the first terminals of the tenth transistor Q10 and the eleventh transistor Q11 are both drains, the second terminals are both sources, and the control terminals are both gates.
  • the implementation method of generating a second current signal with a zero temperature coefficient on the fifth resistor R5 in the embodiment of the present disclosure is the same as the implementation method of forming a first current signal with a negative temperature coefficient on the fourth resistor R4 in Figure 8 (or the first resistor R1 in Figure 7), which will not be elaborated here.
  • the connection method of the tenth transistor Q10 and the eleventh transistor Q11 is the same as the connection method of the control end of the eighth transistor Q8 and the ninth transistor Q9 in Figure 8, the current mirror structure formed is also the same. Based on the same working principle, the second current signal with a zero temperature coefficient can be output to the voltage generating branch 203.
  • FIG. 13 is a schematic diagram of the composition structure of a reference power supply voltage circuit including a total current generating circuit and a voltage generating branch in an exemplary embodiment of the present disclosure.
  • the reference power supply voltage circuit 130 includes a total current generating circuit 1300 and a voltage generating branch 203.
  • the total current generating circuit 1300 includes: a first current generating circuit 1301, the first current generating circuit 1301 includes a first voltage following branch 201 and a first current generating branch 202; a second current generating circuit 1302, the second current generating circuit 1302 includes a second voltage following branch 206 and a second current generating branch 207.
  • the first voltage following branch 201 is shown in FIG. 3
  • the first current generating branch 202 is shown in FIG. 7
  • the second voltage following branch 206 is shown in FIG. 10
  • the second current generating branch 207 is shown in FIG. 11 .
  • the current signal generated at the output end of the total current generating circuit 1300 is (VBE/R1+VBGR/R2), that is, the sum of I1 and I2.
  • the voltage generating branch 203 includes a third resistor R3, a first end of the third resistor R3 is coupled to the output end of the first current generating branch 202 and the output end of the second current generating branch 207 respectively, and a second end of the third resistor R3 is coupled to the ground power supply voltage VSS, so as to receive and generate a reference power supply voltage signal with a negative temperature coefficient according to the first current signal with a negative temperature coefficient, the second current signal with a zero temperature coefficient and the third resistor R3, and then the negative temperature coefficient of the reference power supply voltage signal can be changed by adjusting the resistance values of R1 and R3, so that the slope of the reference power supply voltage signal changing with temperature can be controlled.
  • the first end of the third resistor is coupled to the output end of the first current generating branch and the output end of the second current generating branch respectively, and the second end is coupled to the ground power supply voltage, to receive and generate a reference power supply voltage signal with a negative temperature coefficient based on the first current signal with a negative temperature coefficient, the second current signal with a zero temperature coefficient and the third resistor, so that a subsequent charge pump circuit generates a word line start-up power supply voltage with a negative temperature coefficient based on the reference power supply voltage signal with a negative temperature coefficient.
  • FIG. 14 is a schematic diagram of the composition structure of a charge pump circuit in an exemplary embodiment of the present disclosure.
  • the charge pump circuit 140 includes: a pull-up resistor Rup, the first end of the pull-up resistor Rup is coupled to the output end of the charge pump circuit 140, and the output end of the charge pump circuit 140 is used to output a word line start-up power supply voltage vwlp with a negative temperature coefficient; a pull-down resistor Rdn, the first end of the pull-down resistor Rdn is coupled to the second end of the pull-up resistor Rup, and the second end of the pull-down resistor Rdn is coupled to the ground power supply voltage VSS; a comparator Comp, the negative input end of the comparator Comp is respectively coupled to the second end of the pull-up resistor Rup and the first end of the pull-down resistor Rdn, the positive input end of the comparator Comp is used to receive a reference power supply voltage signal vref with a negative temperature coefficient, and the output end of the comparator Comp outputs an oscillation enable signal Enable; a crystal oscillator OSC, used to receive
  • the comparator Comp when the reference power supply voltage signal vref with a negative temperature coefficient and the word line start power supply voltage vwlp at the connection point between the pull-up resistor Rup and the pull-down resistor Rdn are not equal in voltage division, the comparator Comp outputs the oscillation enable signal Enable, enables the crystal oscillator OSC to oscillate, and outputs the clock signal CLK to the charge pump PUMP chip to adjust the output voltage of the charge pump PUMP chip; when the reference power supply voltage signal vref with a negative temperature coefficient and the word line start power supply voltage vwlp at the connection point between the pull-up resistor Rup and the pull-down resistor Rdn are equal in voltage division, the output oscillation enable signal Enable is zero, the crystal oscillator OSC stops working, and stops adjusting the output voltage of the charge pump PUMP chip.
  • the output end of the charge pump PUMP chip can be the output end of the charge pump circuit 130, and the charge pump PUMP chip is also coupled to the power supply voltage VDD’ to provide working power to the charge pump PUMP chip.
  • the charge pump circuit 140 also includes a capacitor C connected across the ground power supply voltage VSS and the output end of the charge pump PUMP chip (the output end of the charge pump circuit 130), which is used to remove the electromagnetic interference of the word line start-up power supply voltage vwlp output by the charge pump PUMP chip and stabilize the word line start-up power supply voltage vwlp.
  • Vwlp represents the voltage value of the word line start-up power supply voltage vwlp
  • VREF represents the voltage value of the reference power supply voltage signal vref with a negative temperature coefficient
  • Rup also represents the impedance value of the pull-up resistor Rup
  • Rdn also represents the impedance value of the pull-down resistor Rdn.
  • a word line start-up power supply voltage with a negative temperature coefficient can be generated based on a reference power supply voltage signal with a negative temperature coefficient through a charge pump circuit.
  • the word line start-up power supply voltage can be changed based on the reference power supply voltage signal with a negative temperature coefficient, thereby achieving temperature compensation for the word line start-up power supply voltage.
  • FIG. 15 is a schematic diagram showing changes in a compensated word line start-up power supply voltage in an exemplary embodiment of the present disclosure.
  • Line 1501 is a curve showing the voltage value obtained after compensating the word line start power supply voltage in the memory with temperature.

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Abstract

提供一种存储器。该存储器包括第一电压跟随支路（201）、第一电流生成支路（202）、电压生成支路（203）、电荷泵电路（204）和字线驱动电路（205）。第一电压跟随支路（201）生成具有负温度系数的第一电压信号。第一电流生成支路（202）根据具有负温度系数的第一电压信号生成具有负温度系数的第一电流信号。电压生成支路（203）根据具有负温度系数的第一电流信号生成具有负温度系数的参考电源电压信号。电荷泵电路（204）根据参考电源电压信号生成具有负温度系数的字线开启电源电压。字线驱动电路（205）接收字线开启电源电压，用于在驱动字线时向被驱动的字线提供字线开启电源电压。

Description

一种存储器
交叉引用
本公开要求于2023年1月11日提交的申请号为202310063560.0名称为“一种存储器”的中国发明专利申请的优先权，该中国发明专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种存储器。
背景技术
相关技术中，由于存储器中的金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)在开启状态下，其导通电阻Ron的大小会影响存储器中电容上存储的电荷的分享速度，进而影响存储器的读写速度。而MOSFET的导通电阻Ron的大小会受到MOSFET的阈值电压的影响，MOSFET的阈值电压又受环境温度的影响，因此，环境温度影响存储器的读写速度。
进一步地，MOSFET在环境温度为低温条件时的阈值电压，和常温条件下的阈值电压相比会增加，从而导致其导通电阻Ron在低温条件下也有所增加，导致存储器在低温条件下的读写速度也变慢，如此，如何抵消环境温度减小所导致的MOSFET的阈值电压增加是亟待解决的技术问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开实施例提供了一种存储器，包括：第一电压跟随支路，用于生成具有负温度系数的第一电压信号；第一电流生成支路，用于根据具有负温度系数的所述第一电压信号生成具有负温度系数的第一电流信号；电压生成支路，用于根据具有负温度系数的所述第一电流信号生成具有负温度系数的参考电源电压信号；电荷泵电路，用于根据所述参考电源电压信号生成具有负温度系数的字线开启电源电压；字线驱动电路，接收所述字线开启电源电压，用于在驱动字线时向被驱动的所述字线提供所述字线开启电源电压。
本公开实施例中的存储器，通过第一电压跟随支路生成具有负温度系数的第一电压信号，通过第一电流生成支路根据具有负温度系数的第一电压信号生成具有负温度系数的第一电流信号，然后通过电压生成支路根据具有负温度系数的第一电流信号生成负温度系数的参考电源电压信号，得到具有负温度系数的参考电源电压信号，最后通过电荷泵电路根据具有负温度系数的参考电源电压信号生成具有负温度系数的字线开启电源电压，并在驱动字线时通过字线驱动电路向被驱动的字线提供负温度系数的字线开启电源电压，使得随着环境温度的降低，字线开启电源电压也随之增大，从而保证存储器的读写速度不受环境温度的影响。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a是相关技术中存储器中一个存储单元的组成结构示意图；
图1b是相关技术中子字线驱动电路的组成结构示意图；
图1c是相关技术中存储器的构架示意图；
图2是本公开一示例性实施例中的存储器的组成结构示意图；
图3是本公开一示例性实施例中的第一电压跟随支路的组成结构示意图；
图4是本公开另一示例性实施例中的第一电压跟随支路的组成结构示意图；
图5是本公开又一示例性实施例中的第一电压跟随支路的组成结构示意图；
图6是本公开再一示例性实施例中的第一电压跟随支路的组成结构示意图；
图7是本公开一示例性实施例中的第一电流生成支路的组成结构示意图；
图8是本公开另一示例性实施例中的第一电流生成支路的组成结构示意图；
图9是本公开另一示例性实施例中的存储器的组成结构示意图；
图10是本公开一示例性实施例中的第二电压跟随支路的组成结构示意图；
图11是本公开一示例性实施例中的第二电流生成支路的组成结构示意图；
图12是本公开另一示例性实施例中的第二电流生成支路的组成结构示意图；
图13是本公开一示例性实施例中的包括总电流生成电路和电压生成支路的参考电源电压电路的组成结构示意图；
图14是本公开一示例性实施例中的电荷泵电路的组成结构示意图；
图15是本公开一示例性实施例中的补偿后的字线开启电源电压的变化示意图。
具体实施方式
附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。下面结合附图对本公开实施方式提供的存储器进行详细说明。
本公开实施例中的存储器可以理解的是可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)或同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)，例如，半导体存储装置可以是双倍速率同步动态随机存储器(Dual Data Rate SDRAM，DDR SDRAM)或低功耗双倍速率同步动态随机存储器(Low Power Dual Data Rate SDRAM，LPDDR SDRAM)。例如，半导体存储装置可以是DDR3、DDR4、DDR5等。
图1c是相关技术中存储器的构架示意图。
如图1c所示，存储器中包括多个存储阵列101、多个设置在存储阵列101右侧的子字线驱动电路(SWD)102和多个设置在存储阵列101下方的灵敏放大器(Sense Amplifier，SA)103。其中，子字线驱动电路102用于向存储阵列101中的字线提供驱动电压，以对存储阵列101进行读或写操作。
图1b是相关技术中子字线驱动电路的组成结构示意图。
如图1b所示，该子字线驱动电路102包括：PMOS晶体管P13、第一NMOS晶体管N13和第二NMOS晶体管N23。
其中，PMOS晶体管P13的源极耦接字线驱动电源电压PXID(相当于字线开启电源电压vwlp)；PMOS晶体管P13的漏极耦接存储阵列101的字线WL；PMOS晶体管P13的栅极用于接收主字线驱动信号WMLa，以根据主字线驱动信号WMLa导通或关断PMOS晶体管P13，使得字线开启电源电压vwlp传递至存储阵列101的字线WL。
第一NMOS晶体管N13的漏极耦接存储阵列101的字线WL；第一NMOS晶体管N13的源极耦接接地电源电压VSS；第一NMOS晶体管N13的栅极与PMOS晶体管P13的栅极耦接，用于接收主字线驱动信号WMLa，以根据主字线驱动信号WMLa导通或关断第一NMOS晶体管N13，使得接地电源电压VSS传递至存储阵列101的字线WL。
第二NMOS晶体管N23的漏极耦接存储阵列101的字线WL；第二NMOS晶体管N23的源极耦接接地电源电压VSS；第二NMOS晶体管N23的栅极，用于接收字线驱动电源电压PXID的反相信号PXIB，以根据反相信号PXIB导通或关断第二NMOS晶体管N23，使得接地电源电压VSS传递至存储阵列101的字线WL。
可以理解的是，子字线驱动电路102的工作可以存在以下多种情况：
情况1：在主字线驱动信号WMLa为高电平，字线驱动电源电压PXID为高电平，对应反相信号PXIB为低电平时，PMOS晶体管P13断开，第一NMOS晶体管N13导通，第二NMOS晶体管N23断开，通过第一NMOS晶体管N13将接地电源电压VSS传递至存储阵列101的字线WL；
情况2：在主字线驱动信号WMLa为高电平，字线驱动电源电压PXID为低电平，对应反相信号PXIB为高电平时，PMOS晶体管P13断开，第一NMOS晶体管N13导通，第二NMOS晶体管N23导通，同时通过第一NMOS晶体管N13和第二NMOS晶体管N23将接地电源电压VSS传递至存储阵列101的字线WL；
情况3：在主字线驱动信号WMLa为低电平，字线驱动电源电压PXID为高电平，对应反相信号PXIB为低电平时，PMOS晶体管P13导通，第一NMOS晶体管N13断开，第二NMOS晶体管N23断开，通过PMOS晶体管P13将字线驱动电源电压PXID(高电平)传递至存储阵列101的字线WL。
图1a是相关技术中存储器中一个存储单元的组成结构示意图。
如图1a所示，存储器(DRAM)中一个存储单元包括一个Access(接入)MOSFET和一个存储电容Cmbit，其中，MOSFET的控制极(栅极)与字线耦接，MOSFET的第一极(漏极或源极)与位线耦接，MOSFET的第二极(源极或漏极)与接地电源电压耦接，Ccol array是位线的耦合电容。
可以理解的是，在对DRAM中如图1a所示的一个存储单元进行读操作的时候，通常需要将字线置高，即，将向字线提供电源电压的vwlp设置在3V(伏)左右，在将MOSFET开启的情况下，将Cmbit中存储的电荷和位线进行分享，产生电压差ΔV后，提供给后面的灵敏放大器(Sense Amplifier，SA)进行放大。
MOSFET在开启状态下，其导通电阻Ron的大小会影响Cmbit中存储的电荷的分享速度；在环境温度为低温条件下，由于MOSFET的阈值电压会增加，从而导致其Ron在低温条件下也有所增加，如此，导致在低温条件下读写DRAM中一个存储单元的速度受到影响；为了抵消温度降低导致MOSFET的阈值电压增加的问题，可以在低温条件下将vwlp的电压值适当增加。
图2是本公开一示例性实施例中的存储器的组成结构示意图。
如图2所示，本公开实施例提供的存储器20可以包括：第一电压跟随支路201，可以生成具有负温度系数的第一电压信号；第一电流生成支路202，可以用于根据具有负温度系数的第一电压信号生成具有负温度系数的第一电流信号；电压生成支 路203，可以用于根据具有负温度系数的第一电流信号生成具有负温度系数的参考电源电压信号；电荷泵电路204，可以用于根据参考电源电压生成具有负温度系数的字线开启电源电压；字线驱动电路205，可以接收字线开启电源电压，可以用于在驱动字线时向被驱动的所述字线提供所述字线开启电源电压。
可以理解的是，负温度系数的第一电压信号是指随着温度的降低电压值增加，或随着温度的增加电压值减小的电压信号。
本公开实施例中，第一电压跟随支路201可以是包括具有负温度系数的器件的电路。该具有负温度系数的器件可以是三极管、二极管等具有PN结的器件，也可以是其它具有负温度系数的器件，这里不进行具体限定。
在一些可能的实施方式中，具有负温度系数的第一电压信号和具有负温度系数的第一电流信号可以呈线性比例关系，或其它已知的关系。例如，具有负温度系数的第一电压信号的电压值可以是具有负温度系数的第一电流信号的电流值的N倍；N为大于1的数。
在一种可能的实施方式中，具有负温度系数的参考电源电压信号的电压值和具有负温度系数的第一电流信号的电流值也可以是呈线性比例关系，或其它已知的关系。例如，具有负温度系数的参考电源电压信号的电压值可以是具有负温度系数的第一电流信号的电流值的M倍；M为大于1的数。
在一种可能的实施方式中，具有负温度系数的字线开启电源电压的电压值和具有负温度系数的参考电源电压信号的电压值也可以是呈线性比例关系，或其它已知的关系。例如，具有负温度系数的字线开启电源电压的电压值可以是具有参考电源电压信号的电压值的Q倍；Q为大于1的数。
在本公开实施例中，字线驱动电路205可以在驱动字线时将字线开启电源电压提供给被驱动的字线。可以理解的是，存储器中包括多个字线驱动电路205，字线驱动电路205的电路结构并不限于如图1b所示的结构，每一字线驱动电路205中包括字线开启电源电压输入端，但并不是存储器中的每一字线驱动电路205中的字线开启电源电压输入端都会接收到字线开启电源电压，而是需要根据行地址确定。
子线驱动电路205的组成可以参见图1b所示，字线开启电源电压输入端与PMOS晶体管P13的源极耦接，以接收字线开启电源电压。
本公开实施例中，通过第一电压跟随支路生成具有负温度系数的第一电压信号，通过第一电流生成支路根据具有负温度系数的第一电压信号生成具有负温度系数的第一电流信号，然后通过电压生成支路根据具有负温度系数的第一电流信号生成负温度系数的参考电源电压信号，得到具有负温度系数的参考电源电压信号，最后通过电荷泵电路根据具有负温度系数的参考电源电压信号生成具有负温度系数的字线开启电源电压，并在驱动字线时通过字线驱动电路向被驱动的字线提供负温度系数的字线开启电源电压，使得随着环境温度的降低，字线开启电源电压也随之增大，从而保证存储器的读写速度不受环境温度的影响。
图3为本公开一示例性实施例中的第一电压跟随支路的组成结构示意图。
如图3所示，本公开实施例提供的第一电压跟随支路201可以包括：恒流源Is，恒流源Is的输入端用于接收第一电源电压VDD；第一晶体管Q1，第一晶体管Q1的控制极和第一极均耦接接地电源电压VSS，第一晶体管Q1的第二极耦接恒流源Is的输出端以生成具有负温度系数的第一电压信号；第一运算放大器AP1，第一运算放大器AP1的正向输入端分别耦接恒流源Is的输出端和第一晶体管Q1的第二极，第一运算放大器AP1的负向输入端耦接第一电流生成支路202以向所述第一电流生成支路202提供具有负温度系数的第一电压信号；第一运算放大器AP1的输出端也耦接第一电流生成支路202。
可以理解的是，第一晶体管Q1可以是PNP型三极管，第一晶体管Q1的控制极、第一极和第二极分别为PNP型三极管的基极、集电极和发射极。
本公开实施例中，由于第一晶体管Q1的控制极和第一极均耦接接地电源电压，因此，第一晶体管Q1等效为一个二极管，第一晶体管Q1的发射极等效于二极管的阳极，第一晶体管Q1的基极和集电极均等效于二极管的阴极，如此，二极管的阳极耦接恒流源的输出端，阴极耦接接地电源电压的情况下，二极管承受正向压降，处于导通状态。
根据第一晶体管Q1的发射极和基极之间的电压差VBE(等于发射极上的电压VE)、二极管或PN结的导通的负温度特性(-2mV/℃)可知，在常温条件下VBE约为0.7V，在低温条件下，VBE约为0.77V。
通过图3可以看出，第一晶体管Q1导通，在第一晶体管Q1的发射极上生成VBE(VE)，然后通过第一运算放大器AP跟随输出与VBE电压值相同的具有负温度系数的第一电压信号。
本申请实施例中，通过对第一晶体管采用二极管接法，使得第一晶体管等效的二极管正向偏置，使得二极管导通，如此生成具有负温度系数的第一电压信号，然后，通过第一运算放大器跟随具有负温度系数的第一电压信号输出，以便于后续根据具有负温度系数的第一电压信号生成具有负温度系数的参考电源电压信号。
图4为本公开另一示例性实施例中的第一电压跟随支路的组成结构示意图。
如图4所示，本公开实施例提供的第一电压跟随支路201包括：恒流源Is，恒流源Is的输入端用于接收第一电源电压VDD；第一晶体管Q1，第一晶体管Q1的控制极和第一极均耦接恒流源Is的输出端，第一晶体管Q1的第二极耦接接地电源电压VSS，以生成具有负温度系数的第一电压信号；第一运算放大器AP1，第一运算放大器AP1的正向输入端分别耦接恒流源Is的输出端和第一晶体管Q1的第一极，第一运算放大器AP1的负向输入端耦接第一电流生成支路202以向所述第一电流生成支路202提供具有负温度系数的第一电压信号；第一运算放大器AP1的输出端也耦接第一电流生成支路202。
可以理解的是，第一晶体管Q1可以是NPN型三极管，第一晶体管Q1的控制极、第一极和第二极分别为PNP型三极管的基极、集电极和发射极。
本公开实施例中，由于第一晶体管Q1的控制极和第一极均耦接恒流源Is的输出端，因此，第一晶体管Q1等效为一个二极管，第一晶体管Q1的集电极和基极均可以等效于二极管的阳极，第一晶体管Q1的发射极等效于二极管的阴极，如此，二极管的阳极耦接恒流源的输出端，阴极耦接接地电源电压的情况下，二极管承受正向压降，处于导通状态。
根据第一晶体管Q1的发射极和基极之间的电压差VBE(等于第一晶体管Q1的集电极上的电压VC)、二极管或PN结的导通的负温度特性(-2mV/℃)可知，在常温条件下VBE约为0.7V，在低温条件下，VBE约为0.77V。
通过图4可以看出，第一晶体管Q1导通，在第一晶体管Q1的集电极上生成VBE(VC)，然后通过第一运算放大器AP跟随输出与VBE电压值相同的具有负温度系数的第一电压信号。
本申请实施例中，通过对第一晶体管采用二极管接法，使得第一晶体管等效的二极管正向偏置，使得二极管导通，如此生成具有负温度系数的第一电压信号，然后，通过第一运算放大器跟随具有负温度系数的第一电压信号输出，以便于后续根据具有负温度系数的第一电压信号生成具有负温度系数的参考电源电压信号。
图5为本公开又一示例性实施例中的第一电压跟随支路的组成结构示意图。
如图5所示，和图3相比，第一晶体管Q1也为PNP型三极管，但图5中第一 晶体管Q1的二极管接法与图3不同，图5中的第一晶体管Q1的发射极和集电极(作为等效的二极管的阳极)均耦接恒流源Is的输出端，第一晶体管Q1的基极(作为等效的二极管的阴极)耦接接地电源电压VSS，如此，第一晶体管Q1等效的二极管承受正向压降，处于导通状态，进而在第一晶体管Q1的发射极(输出端)生成具有负温度系数的第一电压信号。
图6为本公开再一示例性实施例中的第一电压跟随支路的组成结构示意图。
如图6所示，和图4相比，第一晶体管Q1也为NPN型三极管，但图6中第一晶体管Q1的二极管接法与图4不同，图4中的第一晶体管Q1的发射极和集电极(作为等效的二极管的阴极)均耦接接地电源压VSS，第一晶体管Q1的基极(作为等效的二极管的阳极)耦接恒流源Is的输出端，如此，第一晶体管Q1等效的二极管承受正向压降，处于导通状态，进而在第一晶体管Q1的基极(输出端)生成具有负温度系数的第一电压信号。
在本公开的一些实施例中，第一电压跟随支路201中，在第一晶体管Q1为PNP型三极管时，第一晶体管Q1的二极管接法也可以是第一晶体管Q1的集电极耦接恒流源Is的输出端，第一晶体管Q1的基极耦接接地电源电压VSS，第一晶体管Q1的发射极悬浮，或第一晶体管Q1的发射极耦接恒流源Is的输出端，第一晶体管Q1的基极耦接接地电源电压VSS，第一晶体管Q1的集电极悬浮；在第一晶体管Q1为NPN型三极管时，第一晶体管Q1的二极管接法也可以是第一晶体管Q1的基极耦接恒流源Is的输出端，第一晶体管Q1的集电极耦接接地电源电压VSS，第一晶体管Q1的发射极悬浮，或第一晶体管Q1的基极耦接恒流源Is的输出端，第一晶体管Q1的发射极耦接接地电源电压VSS，第一晶体管Q1的集电极悬浮。
在本公开的一些实施例中，第一电压跟随支路201中的第一晶体管Q1可以通过二极管D1代替，D1的阳极耦接恒流源Is的输出端，D1的阴极耦接接地电源电压VSS。
图7是本公开一示例性实施例中的第一电流生成支路的组成结构示意图。
如图7所示，本公开实施例提供的第一电流生成支路202包括：第二晶体管Q2，第二晶体管Q2的控制端耦接第一运算放大器AP1的输出端；第一电阻R1，第一电阻R1的第一端分别耦接第二晶体管Q2的第二端和第一运算放大器AP1的负向输入端，第一电阻R1的第二端耦接接地电源电压VSS，以根据具有负温度系数的第一电压信号和第一电阻在所述第一电阻生成具有负温度系数的第一电流信号；第三晶体管Q3，第三晶体管Q3的控制端和第一端均与第二晶体管Q2的第一端耦接；第三晶体管Q3的第二端与第一电源电压VDD耦接；第四晶体管Q4，第四晶体管Q4的控制端耦接第二晶体管Q2的第一端，第四晶体管Q4的第一端与电压生成支路203耦接，第四晶体管Q4的第二端与第一电源电压VDD耦接，以将具有负温度系数的第一电流信号镜像输出至电压生成支路203。
在本公开的实施例中，第二晶体管Q2可以为NMOS管；第三晶体管Q3和第四晶体管Q4可以均为PMOS管；第二晶体管Q2、第三晶体管Q3和第四晶体管Q4的第一端均为漏极，第二端均为源极，控制极均为栅极。
本公开的一些实施例中，由于第一电阻R1的第一端耦接第一运算放大器AP1的负向输入端，而第一运算放大器AP1的正向输入端上的输入为具有负温度系数的第一电压信号，根据放大器“虚短”和“虚断”特性，可知第一运算放大器AP1的负向输入端和第一电阻R1的第一端上也是具有负温度系数的第一电压信号，如此，可以在第一电阻R1上生成具有负温度系数的第一电流信号。
这里，具有负温度系数的第一电压信号可以是VBE，具有负温度系数的第一电流信号的电流值I1可以等于VBE除以第一电阻R1的阻抗值的商。
同时，可以理解的是，由于第三晶体管Q3的栅极、第四晶体管Q4的栅极、第三晶体管Q3的漏极均耦接第二晶体管Q2的漏极，第三晶体管Q3的源极和第四晶体管Q4的源极均耦接第一电源电压VDD，形成了电流镜结构，如此，可以将第三晶体管Q3的漏极上的电流镜像到第四晶体管Q4的漏极，而第三晶体管Q3的漏极上的电流与第一电阻R1上的电流相同，均为具有负温度系数的第一电流信号，第四晶体管Q4的漏极与电压生成支路203耦接，进而可以将具有负温度系数的第一电流信号输出至电压生成支路203。
本公开实施例中，通过第二晶体管Q2的控制端耦接第一运算放大器AP1的输出端；第一电阻R1的第一端分别耦接第二晶体管Q2的第二端和第一运算放大器AP1的负向输入端，第一电阻R1的第二端耦接接地电源电压VSS，以根据具有负温度系数的第一电压信号和第一电阻在所述第一电阻生成具有负温度系数的第一电流信号；通过第三晶体管Q3的控制端和第一端均与第二晶体管Q2的第一端耦接；第三晶体管Q3的第二端与第一电源电压VDD耦接；第四晶体管Q4的控制端耦接第二晶体管Q2的第一端，第四晶体管Q4的第一端与电压生成支路耦接，第四晶体管Q4的第二端与第一电源电压VDD耦接，以将具有负温度系数的第一电流信号镜像输出至电压生成支路，以便于电压生成支路203根据具有负温度系数的第一电流信号生成具有负温度系数的参考电源电压信号。
图8是本公开另一示例性实施例中的第一电流生成支路的组成结构示意图。
如图8所示，本公开实施例提供的第一电流生成支路202包括：第八晶体管Q8，第八晶体管Q8的控制端耦接第一运算放大器AP1的输出端；第八晶体管Q8的第一端耦接第一电源电压VDD；第四电阻R4，第四电阻R4的第一端分别耦接第八晶体管Q8的第二端和第一运算放大器AP1的负向输入端，第四电阻R4的第二端耦接接地电源电压VSS，以根据具有负温度系数的第一电压信号和第四电阻R4在第四电阻R4生成具有负温度系数的第一电流信号；第九晶体管Q9，第九晶体管Q9的控制端耦接第一运算放大器AP1的输出端；第九晶体管Q9的第一端耦接第一电源电压VDD，以将具有负温度系数的第一电流信号镜像输出至电压生成支路203。
在本公开的实施例中，第八晶体管Q8和第九晶体管Q9可以均为PMOS管；第八晶体管Q8和第九晶体管Q9的第一端均为漏极，第二端均为源极，控制极均为栅极。
可以理解的是，本公开实施例中在第四电阻R4上生成具有负温度系数的第一电流信号的实现方式和图7中在第一电阻R1上形成具有负温度系数的第一电流信号的实现方式相同，这里不进行阐述。
同时，由于第八晶体管Q8的控制端和第九晶体管Q9的控制端均耦接第一运算放大器AP1的输出端；第八晶体管Q8的第一端和第九晶体管Q9的第一端均耦接第一电源电压VDD，如此形成电流镜结构，可以将第八晶体管Q8的第二端上的电流镜像到第九晶体管Q9的第二端，在第八晶体管Q8的第二端上的电流与第四电阻R4上的电流相同均为具有负温度系数的第一电流信号，第九晶体管Q9的第二端与电压生成支路203耦接的情况下，进而可以将具有负温度系数的第一电流信号输出至电压生成支路203。
图9是本公开另一示例性实施例中的存储器的组成结构示意图。
如图9所示，本公开实施例提供的存储器20还可以包括：第二电压跟随支路206，用于获取具有零温度系数的第二电压信号；第二电流生成支路207，用于根据具有零温度系数的第二电压信号生成具有零温度系数的第二电流信号；电压生成支路203，还用于根据具有负温度系数的第一电流信号和具有零温度系数的第二电流信号生成具有负温度系数的参考电源电压信号。
可以理解的是，零温度系数的第二电压信号是电压值随温度变化不发生变化的电压信号。
本公开实施例中，通过第二电压跟随支路获取具有零温度系数的第二电压信号，通过第二电流生成支路根据具有零温度系数的第二电压信号生成具有零温度系数的第二电流信号，然后通过电压生成支路根据具有负温度系数的第一电流信号和具有零温度系数的第二电流信号生成具有负温度系数的参考电源电压信号，由于具有负温度系数的参考电源电压信号是根据具有零温度系数的第二电流信号和具有负温度系数的第一电流信号生成的，因此在不改变参考电源电压信号的负温度系数的前提下能够改变参考电源电压信号大小。
图10是本公开一示例性实施例中的第二电压跟随支路的组成结构示意图。
如图10所示，本公开实施例提供的第二电压跟随支路206可以包括：第二运算放大器AP2，第二运算放大器AP2的正向输入端用于接收具有零温度系数的第二电源电压VBGR；第二运算放大器AP2的负向输入端耦接第二电流生成支路207以向所述第二电流生成支路207提供具有零温度系数的第二电源电压；第二运算放大器AP2的输出端也耦接第二电流生成支路207。
本申请实施例中，通过第二运算放大器跟随输入的具有零温度系数的第二电源电压并输出值第二电流生成支路，以便于第二电流生成支路根据具有零温度系数的第二电源电压生成具有零温度系数的第二电流信号。
图11是本公开一示例性实施例中的第二电流生成支路的组成结构示意图。
如图11所示，本公开实施例提供的第二电流生成支路207可以包括：第五晶体管Q5，第五晶体管Q5的控制端耦接第二运算放大器AP2的输出端，第五晶体管Q5的第二端耦接第二运算放大器AP2的负向输入端，以在第五晶体管Q5的第二端具有零温度系数的第二电源电压；第二电阻R2，第二电阻R2的第一端分别耦接第五晶体管Q5的第二端和第二运算放大器AP2的负向输入端，第二电阻R2的第二端耦接接地电源电压，以根据具有零温度系数的第二电源电压和第二电阻R2在第二电阻R2生成具有零温度系数的第二电流信号；第六晶体管Q6，第六晶体管Q6的控制端和第一端均与第五晶体管Q5的第一端耦接；第六晶体管Q6的第二端与第一电源电压耦接；第七晶体管Q7，第七晶体管Q7的控制端耦接第五晶体管Q5的第一端，第七晶体管Q7的第一端与电压生成支路103耦接，第七晶体管Q7的第二端与述第一电源电压耦接，以将具有零温度系数的第二电流信号镜像输出至电压生成支路203。
在本公开的实施例中，第五晶体管Q5可以为NMOS管；第六晶体管Q6和第七晶体管Q7可以均为PMOS管；第五晶体管Q5、第六晶体管Q6和第七晶体管Q7的第一端均为漏极，第二端均为源极，控制极均为栅极。
本公开的一些实施例中，由于第二电阻R2的第一端耦接第二运算放大器AP2的负向输入端，而第二运算放大器AP2的正向输入端上的输入为具有零温度系数的第二电压信号，根据放大器“虚短”和“虚断”特性，可知第二运算放大器AP2的负向输入端和第二电阻R2的第一端上也是具有零温度系数的第二电压信号，如此，可以在第二电阻R2上生成具有零温度系数的第二电流信号，在不改变参考电源电压信号的负温度系数的前提下，仅通过改变R2的电阻值便能改变参考电源电压信号的大小。
这里，具有零温度系数的第二电压信号可以是VBGR，具有零温度系数的第二电流信号的电流值I2可以等于VBGR除以第二电阻R2的阻抗值的商。
同时，可以理解的是，由于第六晶体管Q6的栅极、第七晶体管Q7的栅极、第六晶体管Q6的漏极均耦接第五晶体管Q5的漏极，第六晶体管Q6的源极和第七晶 体管Q7的源极均耦接第一电源电压VDD，形成了电流镜结构，如此，可以将第六晶体管Q6的漏极上的电流镜像到第七晶体管Q7的漏极，而第六晶体管Q6的漏极上的电流与第二电阻R2上的电流相同均为具有零温度系数的第二电流信号，第七晶体管Q7的漏极与电压生成支路203耦接，进而可以将具有零温度系数的第二电流信号输出至电压生成支路203。
本公开实施例中，通过第五晶体管Q5的控制端耦接第二运算放大器AP2的输出端，第五晶体管Q5的第二端耦接第二运算放大器AP2的负向输入端，以在第五晶体管Q5的第二端具有零温度系数的第二电源电压；通过第二电阻R2的第一端分别耦接第五晶体管Q5的第二端和第二运算放大器AP2的负向输入端，第二电阻R2的第二端耦接接地电源电压，以根据具有零温度系数的第二电源电压和第二电阻R2在第二电阻R2生成具有零温度系数的第二电流信号；通过第六晶体管Q6的控制端和第一端均与第五晶体管Q5的第一端耦接；第六晶体管Q6的第二端与第一电源电压耦接；第七晶体管Q7的控制端耦接第五晶体管Q5的第一端，第七晶体管Q7的第一端与电压生成支路耦接，第七晶体管Q7的第二端与述第一电源电压耦接，以将具有零温度系数的第二电流信号镜像输出至电压生成支路，以便于电压生成支路根据具有零温度系数的第二电流信号和具有负温度系数的第一电流信号生成具有负温度系数的参考电源电压信号，在不改变参考电源电压信号的负温度系数的前提下，仅通过改变R2的电阻值便能改变参考电源电压信号的大小。
图12是本公开另一示例性实施例中的第二电流生成支路的组成结构示意图。
如图12所示，本公开实施例提供的第二电流生成支路207包括：第十晶体管Q10，第十晶体管Q10的控制端耦接第二运算放大器AP2的输出端；第十晶体管Q10的第一端耦接第一电源电压VDD；第五电阻R5，第五电阻R5的第一端分别耦接第十晶体管Q10的第二端和第二运算放大器AP2的负向输入端，第五电阻R5的第二端耦接接地电源电压VSS，以根据具有零温度系数的第二电压信号和第五电阻R5在第五电阻R5生成具有零温度系数的第二电流信号；第十一晶体管Q11，第十一晶体管Q11的控制端耦接第二运算放大器AP2的输出端；第十一晶体管Q11的第一端耦接第一电源电压VDD，以将具有零温度系数的第二电流信号镜像输出至电压生成支路203。
在本公开的实施例中，第十晶体管Q10和第十一晶体管Q11可以均为PMOS管；第十晶体管Q10和第十一晶体管Q11的第一端均为漏极，第二端均为源极，控制极均为栅极。
可以看出，图12中的第二电流生成支路207和图8中的第一电流生成支路202的组成结构相同。
可以理解的是，本公开实施例中在第五电阻R5上生成具有零温度系数的第二电流信号的实现方式和图8中在第四电阻R4(或图7中在第一电阻R1)上形成具有负温度系数的第一电流信号的实现方式相同，这里不进行阐述。
同时，由于第十晶体管Q10和第十一晶体管Q11的接法和图8中第八晶体管Q8的控制端和第九晶体管Q9的接法相同，形成的电流镜结构也相同，基于相同的工作原理，可以将具有零温度系数的第二电流信号输出至电压生成支路203。
图13是本公开一示例性实施例中的包括总电流生成电路和电压生成支路的参考电源电压电路的组成结构示意图。
如图13所示，该参考电源电压电路130包括总电流生成电路1300和电压生成支路203。总电流生成电路1300包括：第一电流生成电路1301，第一电流生成电路1301包括第一电压跟随支路201和第一电流生成支路202；第二电流生成电路1302，第二电流生成电路1302包括第二电压跟随支路206和第二电流生成支路207。
其中，第一电压跟随支路201参见图3所示，第一电流生成支路202参见图7所示；第二电压跟随支路206参见图10所示和第二电流生成支路207参见图11所示。
基于对图3、图7、图10和图11的分析可知，总电流生成电路1300输出端生成的电流信号为(VBE/R1+VBGR/R2)，即I1和I2的和。
电压生成支路203包括第三电阻R3，第三电阻R3的第一端分别与第一电流生成支路202的输出端和第二电流生成支路207的输出端耦接，第三电阻R3的第二端耦接接地电源电压VSS，以用于接收并根据具有负温度系数的第一电流信号、具有零温度系数的第二电流信号和第三电阻R3生成具有负温度系数的参考电源电压信号，进而可以通过调节R1和R3的电阻值来改变参考电源电压信号的负温度系数，使得参考电源电压信号随温度变化的斜率可控。
本公开实施例中，通过将第三电阻的第一端分别与第一电流生成支路的输出端和第二电流生成支路的输出端耦接，第二端耦接接地电源电压，接收并根据具有负温度系数的第一电流信号、具有零温度系数的第二电流信号和第三电阻生成具有负温度系数的参考电源电压信号，以便后续电荷泵电路根据具有负温度系数的参考电源电压信号生成具有负温度系数的字线开启电源电压。
图14是本公开一示例性实施例中的电荷泵电路的组成结构示意图。
如图14所示，该电荷泵电路140包括：上拉电阻Rup，上拉电阻Rup的第一端耦接电荷泵电路140的输出端，电荷泵电路140的输出端用于输出具有负温度系数的字线开启电源电压vwlp；下拉电阻Rdn，下拉电阻Rdn的第一端耦接上拉电阻Rup的第二端，下拉电阻Rdn的第二端耦接接地电源电压VSS；比较器Comp，比较器Comp的负向输入端分别耦接上拉电阻Rup的第二端和下拉电阻Rdn的第一端，比较器Comp的正向输入端用于接收具有负温度系数的参考电源电压信号vref，比较器Comp的输出端输出振荡使能信号Enable；晶体振荡器OSC，用于接收并根据振荡使能信号Enable生成时钟信号CLK；电荷泵PUMP芯片，接收时钟信号CLK并用于根据时钟信号CLK生成字线开启电源电压vwlp。
可以理解是，当具有负温度系数的所述参考电源电压信号vref与字线开启电源电压vwlp在上拉电阻Rup与下拉电阻Rdn之间的连接点上的分压不相等时，比较器Comp输出的振荡使能信号Enable，使能晶体振荡器OSC震荡，输出时钟信号CLK给电荷泵PUMP芯片，调节电荷泵PUMP芯片的输出电压；当具有负温度系数的所述参考电源电压信号vref与字线开启电源电压vwlp在上拉电阻Rup与下拉电阻Rdn之间的连接点上的分压相等的情况下，输出的振荡使能信号Enable为零，晶体振荡器OSC停止工作，停止调节电荷泵PUMP芯片的输出电压。
本公开实施例中，电荷泵PUMP芯片输出端可以是电荷泵电路130的输出端，电荷泵PUMP芯片还与电源电压VDD’耦接，以向电荷泵PUMP芯片提供工作电源。
本公开实施例中,电荷泵电路140还包括跨接在接地电源电压VSS与电荷泵PUMP芯片的输出端(电荷泵电路130的输出端)之间的电容C，用于去除电荷泵PUMP芯片输出的字线开启电源电压vwlp的电磁干扰，稳定字线开启电源电压vwlp。
本公开实施例中，电荷泵PUMP芯片输出的字线开启电源电压vwlp表示参见公式(1)：
Vwlp＝(VREF/Rdn)*(Rup+Rdn)      (1)
其中，Vwlp表示字线开启电源电压vwlp的电压值，VREF表示具有负温度系数的参考电源电压信号vref的电压值；Rup也同时表示上拉电阻Rup的阻抗值；Rdn也同时表示下拉电阻Rdn的阻抗值。
本公开实施例中，通过电荷泵电路可以基于具有负温度系数的参考电源电压信号生成具有负温度系数的字线开启电源电压，如此，当环境温度降低时，可以基于负温度系数的参考电源电压信号，改变字线开启电源电压，从而实现对字线开启电源电压的温度补偿。
图15是本公开一示例性实施例中的补偿后的字线开启电源电压的变化示意图。
如图15所示，横坐标为温度，单位为℃(摄氏度)；纵坐标为字线开启电源电压vwlp的电压值，单位为V。直线1501为对存储器中的字线开启电源电压进行补偿后得到的电压值随温度变化的曲线。
通过图15可以看出，随着温度的增加字线开启电源电压vwlp的电压值从3.5V以一定的斜率下降直至3.0V。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。

Claims (13)

  1. 一种存储器(20)，其特征在于，包括：
    第一电压跟随支路(201)，用于生成具有负温度系数的第一电压信号；
    第一电流生成支路(202)，用于根据具有负温度系数的所述第一电压信号生成具有负温度系数的第一电流信号；
    电压生成支路(203)，用于根据具有负温度系数的所述第一电流信号生成具有负温度系数的参考电源电压信号(vref)；
    电荷泵电路(204)，用于根据所述参考电源电压信号(vref)生成具有负温度系数的字线开启电源电压(vwlp)；
    字线驱动电路(205)，接收所述字线开启电源电压(vwlp)，用于在驱动字线(WL)时向被驱动的所述字线(WL)提供所述字线开启电源电压(vwlp)。
  2. 如权利要求1所述的存储器(20)，其特征在于，所述第一电压跟随支路(201)包括：
    恒流源(Is)，所述恒流源(Is)的输入端用于接收第一电源电压(VDD)；
    第一晶体管(Q1)，所述第一晶体管(Q1)的控制极和第一极均耦接接地电源电压(VSS)，所述第一晶体管(Q1)的第二极耦接所述恒流源(Is)的输出端以生成具有负温度系数的所述第一电压信号；
    第一运算放大器(AP1)，所述第一运算放大器(AP1)的正向输入端分别耦接所述恒流源(Is)的输出端和所述第一晶体管(Q1)的第二极，所述第一运算放大器(AP1)的负向输入端耦接所述第一电流生成支路(202)以向所述第一电流生成支路(202)提供具有负温度系数的所述第一电压信号。
  3. 如权利要求2所述的存储器(20)，其特征在于，所述第一晶体管(Q1)包括PNP型三极管，所述第一晶体管(Q1)的控制极、第一极和第二极分别为所述PNP型三极管的基极、集电极和发射极。
  4. 如权利要求1所述的存储器(20)，其特征在于，所述第一电压跟随支路(201)包括：
    恒流源(Is)，所述恒流源(Is)的输入端用于接收第一电源电压(VDD)；
    第一晶体管(Q1)，所述第一晶体管(Q1)的控制极和第一极均耦接所述恒流源(Is)的输出端，所述第一晶体管(Q1)的第二极耦接接地电源电压(VSS)，以生成具有负温度系数的所述第一电压信号；
    第一运算放大器(AP1)，所述第一运算放大器(AP1)的正向输入端分别耦接所述恒流源(Is)的输出端和所述第一晶体管(Q1)的第一极，所述第一运算放大器(AP1)的负向输入端耦接所述第一电流生成支路(202)以向所述第一电流生成支路(202)提供具有负温度系数的所述第一电压信号。
  5. 如权利要求4所述的存储器(20)，其特征在于，所述第一晶体管(Q1)包括NPN型三极管，所述第一晶体管(Q1)的控制极、第一极和第二极分别为所述NPN型三极管的基极、集电极和发射极。
  6. 如权利要求2至5任一项所述的存储器(20)，其特征在于，所述第一电流生成支路(202)包括：
    第二晶体管(Q2)，所述第二晶体管(Q2)的控制端耦接所述第一运算放大器(AP1)的输出端；
    第一电阻(R1)，所述第一电阻(R1)的第一端分别耦接所述第二晶体管(Q2)的第二端和所述第一运算放大器(AP1)的负向输入端，所述第一电阻(R1)的第二端耦接接地电源电压(VSS)，以根据具有负温度系数的所述第一电压信号和所述第一电阻(R1)在所述第一电阻(R1)生成具有负温度系数的所述第一电流信号；
    第三晶体管(Q3)，所述第三晶体管(Q3)的控制端和第一端均与所述第二晶体管(Q2)的第一端耦接；所述第三晶体管(Q3)的第二端与所述第一电源电压(VDD)耦接；
    第四晶体管(Q4)，所述第四晶体管(Q4)的控制端耦接所述第二晶体管(Q2)的第一端，所述第四晶体管(Q4)的第一端与所述电压生成支路(203)耦接，所述第四晶体管(Q4)的第二端与所述第一电源电压(VDD)耦接，以将具有负温度系数的所述第一电流信号镜像输出至所述电压生成支路(203)。
  7. 如权利要求6所述的存储器(20)，其特征在于，所述第二晶体管(Q2)为NMOS管；所述第三晶体管(Q3)和所述第四晶体管(Q4)均为PMOS管；所述二晶体管(Q2)、所述第三晶体管(Q3)和所述第四晶体管(Q4)的第一端均为漏极，第二端均为源极。
  8. 如权利要求1至7任一项所述的存储器(20)，其特征在于，还包括：
    第二电压跟随支路(206)，用于获取具有零温度系数的第二电压信号；
    第二电流生成支路(207)，用于根据具有零温度系数的所述第二电压信号生成具有零温度系数的第二电流信号；
    所述电压生成支路(203)还用于根据具有负温度系数的所述第一电流信号和具有零温度系数的所述第二电流信号生成具有负温度系数的所述参考电源电压信号(vref)。
  9. 如权利要求8所述的存储器(20)，其特征在于，所述第二电压跟随支路(206)包括：
    第二运算放大器(AP2)，所述第二运算放大器(AP2)的正向输入端用于接收具有零温度系数的第二电源电压(VBGR)；所述第二运算放大器(AP2)的负向输入端耦接所述第二电流生成支路(207)以向所述第二电流生成支路(207)提供具有零温度系数的所述第二电源电压(VBGR)。
  10. 如权利要求9所述的存储器(20)，其特征在于，所述第二电流生成支路(207)包括：
    第五晶体管(Q5)，所述第五晶体管(Q5)的控制端耦接所述第二运算放大器(AP2)的输出端，所述第五晶体管(Q5)的第二端耦接所述第二运算放大器(AP2)的负向输入端，以在所述第五晶体管(Q5)的第二端具有零温度系数的所述第二电源电压(VBGR)；
    第二电阻(R2)，所述第二电阻(R2)的第一端分别耦接所述第五晶体管(Q5)的第二端和所述第二运算放大器(AP2)的负向输入端，所述第二电阻(R2)的第二端耦接接地电源电压(VSS)，以根据具有零温度系数的所述第二电源电压(VBGR)和所述第二电阻(R2)在所述第二电阻(R2)生成具有零温度系数的所述第二电流信号；
    第六晶体管(Q6)，所述第六晶体管(Q6)的控制端和第一端均与所述第五晶体管(Q5)的第一端耦接；所述第六晶体管(Q6)的第二端与所述第一电源电压(VDD)耦接；
    第七晶体管(Q7)，所述第七晶体管(Q7)的控制端耦接所述第五晶体管(Q5)的第一端，所述第七晶体管(Q7)的第一端与所述电压生成支路(203)耦接，所述第七晶体管(Q7)的第二端与所述第一电源电压(VDD)耦接，以将具有零温度系数的所述第二电流信号镜像输出至所述电压生成支路(203)。
  11. 如权利要求10所述的存储器(20)，其特征在于，所述第五晶体管(Q5)为NMOS管；所述第六晶体管(Q6)和所述第七晶体管(Q7)均为PMOS管；所述第五晶体管(Q5)、所述第六晶体管(Q6)和所述第七晶体管(Q7)的第一端均 为漏极，第二端均为源极。
  12. 如权利要求8至11任一项所述的存储器(20)，其特征在于，所述电压生成支路(203)包括：
    第三电阻(R3)，所述第三电阻(R3)的第一端分别与所述第一电流生成支路的输出端(202)和所述第二电流生成支路(207)的输出端耦接，第二端耦接接地电源电压(VSS)，以用于接收并根据具有负温度系数的所述第一电流信号、具有零温度系数的所述第二电流信号和所述第三电阻生成具有负温度系数的所述参考电源电压信号(vref)。
  13. 如权利要求1至12任一项所述的存储器(20)，其特征在于，所述电荷泵电路(140)包括：
    上拉电阻(Rup)，所述上拉电阻(Rup)的第一端耦接所述电荷泵电路(140)的输出端，所述电荷泵电路(140)的输出端用于输出具有负温度系数的所述字线开启电源电压(vwlp)；
    下拉电阻(Rdn)，所述下拉电阻(Rdn)的第一端耦接所述上拉电阻(Rup)的第二端，所述下拉电阻(Rdn)的第二端藕接接地电源电压(VSS)；
    比较器(Comp)，所述比较器(Comp)的负向输入端分别耦接所述上拉电阻(Rup)的第二端和所述下拉电阻(Rdn)的第一端，所述比较器(Comp)的正向输入端用于接收具有负温度系数的所述参考电源电压信号(vref)，所述比较器(Comp)的输出端输出振荡使能信号(Enable)；
    晶体振荡器(OSC)，用于接收并根据所述振荡使能信号(Enable)生成时钟信号(CLK)；
    电荷泵(PUMP芯片)，接收所述时钟信号(CLK)，用于根据所述时钟信号(CLK)生成并输出所述字线开启电源电压(vwlp)。
PCT/CN2023/111093 2023-01-11 2023-08-03 一种存储器 Ceased WO2024148798A1 (zh)

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