WO2024113095A1 - Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication Download PDF

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WO2024113095A1
WO2024113095A1 PCT/CN2022/134702 CN2022134702W WO2024113095A1 WO 2024113095 A1 WO2024113095 A1 WO 2024113095A1 CN 2022134702 W CN2022134702 W CN 2022134702W WO 2024113095 A1 WO2024113095 A1 WO 2024113095A1
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nitride
semiconductor device
layer
transistor
buffer layer
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PCT/CN2022/134702
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English (en)
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Jianfa Zhang
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Innoscience (suzhou) Semiconductor Co., Ltd.
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Priority to CN202280086106.0A priority Critical patent/CN118476031A/zh
Priority to PCT/CN2022/134702 priority patent/WO2024113095A1/fr
Publication of WO2024113095A1 publication Critical patent/WO2024113095A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having GaN-based transistors integrated into the same substrate.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • the first nitride-based transistor and the second nitride-based transistor are adjacent to the first nitride-based transistor.
  • the first nitride-based transistor and the second nitride-based transistor share the 2DEG region.
  • the STI can extend into the nitride-based buffer layer.
  • the STI vertically aligns with a position between the first nitride-based transistor and the second nitride-based transistor.
  • a method for manufacturing a nitride-based semiconductor device includes steps as follows: forming a nitride-based buffer layer over a substrate; forming a first nitride-based transistor and a second nitride-based transistor over the nitride-based buffer layer; forming a trench in the nitride-based buffer layer and the substrate, wherein the trench aligns with a position between the first nitride- based transistor and the second nitride-based transistor; filling shallow trench isolation (STI) into the trench; removing a portion of the nitride-based buffer to form an opening; and disposing a conductor in the opening of the nitride-based buffer such that a pad is formed.
  • STI shallow trench isolation
  • a nitride-based semiconductor device in accordance with one aspect of the present disclosure, includes a substrate, a nitride-based buffer layer, a barrier layer and a channel layer, a first nitride-based transistor and a second nitride-based transistor, and at least one shallow trench isolation (STI) .
  • the nitride-based buffer layer is connected to the substrate.
  • the barrier layer and the channel layer are between the nitride-based buffer layer and the barrier layer.
  • the barrier layer and has a bandgap greater than a bandgap of the channel layer, so as to from a two-dimensional electron gas (2DEG) region.
  • 2DEG two-dimensional electron gas
  • the first nitride-based transistor and the second nitride-based transistor are adjacent to the first nitride-based transistor.
  • the first nitride-based transistor and the second nitride-based transistor share the 2DEG region.
  • the STI penetrate the substrate to extend into the nitride-based buffer layer.
  • the nitride-based semiconductor device with the STIs is provided so how to demonstrate specifically structure with the integration of multiple nitride-based transistors together.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H show different stages of a method for manufacturing the nitride-based semiconductor device 1A according to some embodiments of the present disclosure
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1A includes a substrate 10, a nitride-based buffer layer 12, nitride-based semiconductor layers 14, 16, nitride-based transistors 20, 30, conductive bridges 40, conductive layer 42, a contact via 44, an isolation layer 46, a conductive pad 48, a passivation layer 50, a bonding wafer 52, and shallow trench isolations (STIs) 60.
  • STIs shallow trench isolations
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the nitride-based buffer layer 12 is connected to the substrate 10.
  • the nitride-based buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14.
  • the nitride-based buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference.
  • the nitride-based buffer layer 12 may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the nitride-based buffer layer 12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the semiconductor device 1A may further include a nucleation layer (not shown) .
  • the nucleation layer may be formed between the substrate 10 and the nitride-based buffer layer 12.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the nitride-based buffer layer 12.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the nitride-based semiconductor layer 14 is connected to the nitride-based buffer layer 12.
  • the nitride-based semiconductor layer 16 is connected to the nitride-based semiconductor layer 14.
  • the nitride-based semiconductor layer 14 is located between the nitride-based buffer layer 12 and the nitride-based semiconductor layer 14.
  • the exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the nitride-based transistor 20 is disposed at the nitride-based semiconductor layers 14 and 16, so as to apply the 2DEG region.
  • the nitride-based transistor 20 includes electrodes 202 and 204, a doped nitride-based semiconductor layer 206, a gate electrode 208, and contact vias 210.
  • the electrodes 202 and 204 and the gate electrode 208 can collectively constitute a nitride-based transistor using the 2DEG region.
  • the electrodes 202 and 204 are connected to the nitride-based semiconductor layer 16.
  • the electrode 202 can make contact with the nitride-based semiconductor layer 16.
  • the electrode 204 can make contact with the nitride-based semiconductor layer 16.
  • Each of the electrodes 202 and 204 can serve as a source electrode or a drain electrode.
  • the electrodes 202 and 204 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 202 and 204 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the electrodes 202 and 204 may be a single layer, or plural layers of the same or different composition. In some embodiments, the electrodes 202 and 204 form ohmic contact with the nitride-based semiconductor layer 16. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes 202 and 204.
  • each of the electrodes 202 and 204 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • the doped nitride-based semiconductor layer 208 is connected to the nitride-based semiconductor layer 16.
  • the doped nitride-based semiconductor layer 208 is located between the electrodes 202 and 204.
  • the doped nitride-based semiconductor layer 208 may be p-type.
  • the doped nitride-based semiconductor layer 208 is configured to bring the nitride-based transistor 20 into enhancement mode.
  • the doped nitride-based semiconductor layer 208 can be a p-type doped III-V semiconductor layer.
  • the doped nitride-based semiconductor layer 208 can be omitted so the nitride-based transistor 20 is operated in depletion mode.
  • the exemplary materials of the doped nitride-based semiconductor layer 208 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
  • the gate electrode 208 is connected to the doped nitride-based semiconductor layer 208.
  • the gate electrode 208 is located between the electrodes 202 and 204.
  • the doped nitride-based semiconductor layer 208 is located between the nitride-based semiconductor layer 16 and the gate electrode 208.
  • the exemplary materials of the gate electrode 208 may include metals or metal compounds.
  • the gate electrode 208 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • the contact vias 210 are connected to the electrodes 202 and 204.
  • the contact vias 210 can connect to external components with respect to the nitride-based transistor 20.
  • the nitride-based transistor 30 is disposed at the nitride-based semiconductor layers 14 and 16, so as to apply the 2DEG region.
  • the nitride-based transistor 30 includes electrodes 302 and 304, a doped nitride-based semiconductor layer 306, a gate electrode 308, and contact vias 310.
  • the electrodes 302 and 304 and the gate electrode 308 can collectively constitute a nitride-based transistor using the 2DEG region.
  • the nitride-based transistors 20 and 30 can share the 2DEG region.
  • the configuration of the nitride-based transistor 30 can be identical with or similar to the nitride-based transistor 20.
  • the conductive bridges 40 can be electrically connected to the nitride-based transistors 20 and 30.
  • at least one of the conductive bridges 40 is located between the nitride-based transistors 20 and 30 and electrically connects the nitride-based transistor 20 to the nitride-based transistor 30.
  • the conductive bridges 40 can electrically connected to the nitride-based transistors 20 and 30 through the contact vias 210 and 310.
  • the conductive bridges 40 can extend to the thickness range of the nitride-based buffer layer 12.
  • the conductive bridges 40 can extend to the thickness range of the substrate 10.
  • the conductive bridges 40 can be grounded due to the extending thereof.
  • the passivation layer 50 covers the nitride-based semiconductor layers 14, the nitride-based transistors 20 and 30, and the conductive bridges 40.
  • the passivation layer 50 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 50 to remove the excess portions, thereby forming a level top surface.
  • CMP chemical mechanical polish
  • the material of the passivation layer 50 can include, for example but are not limited to, dielectric materials.
  • the passivation layer 50 can include SiN x , SiO x , SiON, SiC, SiBN, SiCBN, oxides, nitrides, PEOX, or combinations thereof.
  • the bonding wafer 52 is bonded to the passivation layer 50.
  • the bonding wafer 52 can carry the structure during the process so it is convenient to process the back side of the structure.
  • the STIs 60 can extend into the nitride-based buffer layer 12 from the substrate 10. At least one of the STIs 60 vertically aligns with a position between the nitride-based transistors 20 and 30.
  • the STIs 60 can be configured to isolate electrical disturbance from the nitride-based transistor 20 to the nitride-based transistor 30, such as body effect.
  • the STIs 60 penetrate the substrate 10.
  • the STIs 60 have end surfaces terminated within a thickness range of the nitride-based buffer layer 12.
  • Each of the STIs 60 has an end surface facing the nitride-based semiconductor layers 14 and another end surface which faces away the nitride-based semiconductor layers and is wider than the former end surface.
  • the material of the STIs 60 can be selected to isolate electrical disturbance from the nitride-based transistor 20 to the nitride-based transistor 30.
  • the exemplary materials of the STIs 60 can include, for example but are not limited to, an oxide compound, nitride compound, carbide compound, or combinations thereof. Since the STIs 60 can isolate electrical disturbance among different nitride-based transistors, it is convenient to integrating different nitride-based transistors into the same wafer.
  • the profile of the STIs 60 can be modified to further adjust the isolation demand, including modification to width, depth, or distribution density of the STIs 60.
  • the nitride-based semiconductor device 1A with the STIs 60 is provided so how to demonstrate specifically structure with the integration of multiple nitride-based transistors together.
  • the nitride-based semiconductor device 1A can serve as a half-bridge device, such as half-bridge converter or half-bridge driver, which applies GaN HEMT integration.
  • the conductive layer 42 is disposed within the passivation layer 50.
  • the conductive layer 42 is electrically connected to the nitride-based transistor 30.
  • the contact via 44 is disposed within the passivation layer 50.
  • the contact via 44 is electrically connected to the conductive layer 42.
  • the contact via 44 can extend out of the passivation layer 50.
  • the isolation layer 46 covers the substrate 10.
  • the isolation layer 46 covers the end surfaces of the STIs 60 which face away from the nitride-based buffer layer 12.
  • the substrate 10, the nitride-based buffer layer 12, and the nitride-based semiconductor layers 14 and 16 can collectively have a trench which can be defined by inner sidewalls thereof.
  • the isolation layer 46 covers the inner sidewalls of the substrate 10, the nitride-based buffer layer 12, and the nitride-based semiconductor layers 14 and 16.
  • the isolation layer 46 can extend into the trench and make contact with the passivation layer 50.
  • the contact via 44 can penetrate the isolation layer 46.
  • the contact via 44 and the isolation layer 46 may coplanar with each other.
  • the conductive pad 48 is connected to the contact via 44.
  • the conductive pad 48 is located within the trench.
  • the conductive pad 48 is adjacent to the inner sidewalls of the substrate 10, the nitride-based buffer layer 12, and the nitride-based semiconductor layers 14 and 16.
  • the conductive pad 48 overlaps with a thickness range of the substrate 10, the nitride-based buffer layer 12, and the nitride-based semiconductor layer 14.
  • the conductive pad 48 can serve as a conductor that can receive an external signal such that the nitride-based transistors 20 and 30 can be biased.
  • the material of the conductor can include, for example but are not limited to, Al, AlCu, Cu, TiN, Ti, Ta, TaN, W, or combinations thereof.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a substrate 10 is provided.
  • a nitride-based buffer layer 12 is formed over the substrate 10.
  • the nitride-based semiconductor layers 14 and 16 i.e., a channel layer and a barrier layer
  • Nitride-based transistors 20 and 30 are formed over the nitride-based semiconductor layers 14 and 16.
  • conductive bridges 40 and a conductive layer 42 are formed to connected the corresponding nitride-based transistor 20 or 30.
  • the conductive bridges 40 are formed such that the nitride-based transistor 20 can be electrically coupled to the nitride-based transistor 30.
  • a passivation layer 50 is formed to cover the nitride-based transistors 20 and 30, the conductive bridges 40, and the conductive layer 42.
  • a bonding wafer 52 is bonded to the passivation layer 50, and then the structure is reversed by using the bonding wafer 52 as a bottom of the structure. After the revers, the substrate 10 is thinned so the substrate 10 of FIG. 2D is thinner than the substrate 10 of FIG. 2C.
  • trenches 62 are formed in the nitride-based buffer layer 12 and the substrate 10.
  • the trenches 62 can be formed by using an etching stage, such as a dry or wet etch process. At least one of the trenches 62 aligns with a position between the nitride-based transistors 20 and 30.
  • the trenches 62 have bottom located within a thickness range of the nitride-based buffer 12.
  • the trenches 62 are filled with isolation material, such as an oxide compound, nitride compound, carbide compound, or combinations thereof. Such the filling can serve as filling STIs 60 into the trenches62.
  • the isolation material is in contact with the nitride-based buffer layer 12 and the substrate 10.
  • portions of the substrate 10, the nitride-based buffer layer 12, and the nitride-based semiconductor layers 14 and 16 are removed to form an opening 64.
  • the passivation layer 50 can be exposed form the opening 64.
  • an isolation layer 46 is formed.
  • the isolation layer 46 can extend into the opening 64.
  • the isolation layer 46 can make contact with the passivation layer 50.
  • the isolation layer 46 can cover the STIs 60.
  • portion of the isolation layer 46 and the passivation layer 50 can be removed so as to expose conductive layer 42.
  • a contact via and a conductor can be disposed in the opening 64 so as to obtain the structure with a conductive pad configured to receive an external signal, as afore described.
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the STIs 60 are replaced by STIs 60B.
  • more than one STI 60B is arranged.
  • the STIs 60B still vertically aligns with a position between the nitride-based transistors 20 and 30 so the STIs 60B are confined in the region.
  • the conductive bridge 40 has an end surface (i.e., a top surface thereof) between the STIs 60B. Such the configuration is made to further improve the isolation effect between the nitride-based transistors 20 and 30
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the STIs 60 are replaced by STIs 60C.
  • the STIs 60C further extend in the nitride-based buffer layer 12.
  • the STIs 60C can extend to penetrate the substrate 10 and nitride-based buffer layer 12.
  • the STIs 60C can extend to make contact with the nitride-based semiconductor layer 14.
  • through GaN via technique is applied to achieve the formation of the STIs 60. Such the configuration is made to further improve the isolation effect between the nitride-based transistors 20 and 30.
  • FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the STIs 60 are replaced by STIs 60D.
  • the STIs 60D vertically aligns with the conductive bridges 40. More specifically, the STIs 60D can vertically align with top surface of the conductive bridges 40.
  • the STIs 60D are confined in the substrate 10 so the STIs 60D are out of the nitride-based buffer layer 12.
  • the STIs 60D can make contact with the conductive bridges 40.
  • the STIs 60D have end surfaces abutting against the conductive bridges 40.
  • the conductive bridges 40 can serve as etch stop during an etching stage for the STIs 60D so overetching can be avoided.
  • connection in the present disclosure may include “indirect connection” , “direct connection” , or combinations thereof.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Un dispositif à semi-conducteur à base de nitrure comprend une couche tampon à base de nitrure, une couche barrière et une couche de canal, un premier transistor à base de nitrure et un second transistor à base de nitrure, et au moins une STI. La couche barrière et la couche de canal se trouvent entre la couche tampon à base de nitrure et la couche barrière. La couche barrière comprend une bande interdite supérieure à une bande interdite de la couche de canal, de façon à former une région 2DEG. Le premier transistor à base de nitrure et le second transistor à base de nitrure sont adjacents au premier transistor à base de nitrure. Le premier transistor à base de nitrure et le second transistor à base de nitrure partagent la région 2DEG. Le STI peut s'étendre dans la couche tampon à base de nitrure. Le STI s'aligne verticalement avec une position entre le premier transistor à base de nitrure et le second transistor à base de nitrure.
PCT/CN2022/134702 2022-11-28 2022-11-28 Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication WO2024113095A1 (fr)

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CN202280086106.0A CN118476031A (zh) 2022-11-28 2022-11-28 氮化物基半导体器件及其制造方法
PCT/CN2022/134702 WO2024113095A1 (fr) 2022-11-28 2022-11-28 Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035704A (zh) * 2011-09-29 2013-04-10 富士通株式会社 半导体器件及其制造方法
CN103367424A (zh) * 2012-03-29 2013-10-23 富士通株式会社 化合物半导体器件及其制造方法
CN103765592A (zh) * 2011-07-18 2014-04-30 埃皮根股份有限公司 用于生长iii-v外延层的方法
JP2014197644A (ja) * 2013-03-29 2014-10-16 トランスフォーム・ジャパン株式会社 化合物半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103765592A (zh) * 2011-07-18 2014-04-30 埃皮根股份有限公司 用于生长iii-v外延层的方法
CN103035704A (zh) * 2011-09-29 2013-04-10 富士通株式会社 半导体器件及其制造方法
CN103367424A (zh) * 2012-03-29 2013-10-23 富士通株式会社 化合物半导体器件及其制造方法
JP2014197644A (ja) * 2013-03-29 2014-10-16 トランスフォーム・ジャパン株式会社 化合物半導体装置及びその製造方法

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