WO2023240491A1 - Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication Download PDF

Info

Publication number
WO2023240491A1
WO2023240491A1 PCT/CN2022/098966 CN2022098966W WO2023240491A1 WO 2023240491 A1 WO2023240491 A1 WO 2023240491A1 CN 2022098966 W CN2022098966 W CN 2022098966W WO 2023240491 A1 WO2023240491 A1 WO 2023240491A1
Authority
WO
WIPO (PCT)
Prior art keywords
nitride
based semiconductor
layer
semiconductor layer
gate electrode
Prior art date
Application number
PCT/CN2022/098966
Other languages
English (en)
Inventor
Keping Wu
Qiyue Zhao
Xiao Zhang
Tinglin YOU
Xiaoqi Li
Original Assignee
Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innoscience (suzhou) Semiconductor Co., Ltd. filed Critical Innoscience (suzhou) Semiconductor Co., Ltd.
Priority to PCT/CN2022/098966 priority Critical patent/WO2023240491A1/fr
Priority to CN202280058436.9A priority patent/CN117916866A/zh
Publication of WO2023240491A1 publication Critical patent/WO2023240491A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention generally relates to a semiconductor device. More specifically, the present invention relates to a high electron mobility transistor (HEMT) semiconductor device having multi field plates over a gate electrode thereof for improving the performance thereof.
  • HEMT high electron mobility transistor
  • HEMT high-electron-mobility transistors
  • 2DEG two-dimensional electron gas
  • examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • HBT heterojunction bipolar transistors
  • HFET heterojunction field effect transistor
  • MODFET modulation-doped FET
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, a passivation layer, and a field plate.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the first electrode and the second electrode are disposed over the second nitride-based semiconductor layer.
  • the gate electrode is disposed over the second nitride-based semiconductor layer and between the first and second electrodes.
  • the passivation layer covers the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode.
  • the field plate is disposed over the second nitride-based semiconductor layer and located between the gate electrode and the first electrode. The field plate abuts against a sidewall of the projection portion of the passivation layer and is free from overlapping with the gate electrode along a vertical direction.
  • a method for manufacturing a semiconductor device includes steps as follows.
  • a first nitride-based semiconductor layer is formed.
  • a second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer.
  • a gate electrode is formed over the second nitride-based semiconductor layer.
  • a first passivation layer is formed to cover the gate electrode.
  • a conductive layer is formed on the first passivation layer.
  • a second passivation layer is formed on the conductive layer.
  • a first etching process is performed to thin down the second passivation layer so as to expose a portion of the conductive layer which is located above the gate electrode.
  • a second etching process is performed to remove the exposed portion of the conductive layer so as to expose the first passivation layer.
  • the conductive layer is patterned after performing the first etching process.
  • the gate electrode is disposed over the second nitride-based semiconductor layer and between the first and second electrodes.
  • the passivation layer covers the second nitride-based semiconductor layer and the gate electrode to form a projection portion conformal with a profile of the gate electrode.
  • the field plate is disposed over the second nitride-based semiconductor layer and located between the gate electrode and the first electrode. The field plate laterally extends to have an uniform thickness.
  • the field plate is free from overlapping with the gate electrode so the field plate has no portion directly above or over the gate electrode.
  • the reason for such the configuration is to reduce parasitic capacitance between the field plate and the gate electrode.
  • Such the configuration is advantageous to formation of the field plate by applying a self-alignment process.
  • FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I illustrate different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure
  • FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
  • FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1A is a cross-sectional view of the semiconductor device 1A according to some embodiments of the present disclosure.
  • the semiconductor device 1A is a dual-gate device.
  • the semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 14 and 16, electrodes 20, 22, 24, doped nitride-based semiconductor layers 30, 40, gate electrodes 32, 42, passivation layers 50, 52, 70, 76, field plates 60, 62, contact vias 72, 78, patterned conductive layers 74, 80, and a protection layer 82.
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable semiconductor materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the bidirectional switching device 1A may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated) .
  • the buffer layer can be disposed between the substrate 10 and the nitride-based semiconductor layer 14.
  • the buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the doped nitride-based semiconductor layer 30 and the gate electrode 32 are stacked on the nitride-based semiconductor layer 16.
  • the doped nitride-based semiconductor layer 30 are between the nitride-based semiconductor layer 16 and the gate electrode 32.
  • the gate electrode 32 is narrower than the doped nitride-based semiconductor layer 30.
  • the doped nitride-based semiconductor layer 40 and the gate electrode 42 are stacked on the nitride-based semiconductor layer 16.
  • the doped nitride-based semiconductor layer 40 are between the nitride-based semiconductor layer 16 and the gate electrode 42.
  • the gate electrode 42 is narrower than the doped nitride-based semiconductor layer 40.
  • the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrodes 32 and 42 are at approximately zero bias.
  • the doped nitride-based semiconductor layers 30 and 40 may create at least one p-n junction with the nitride-based semiconductor layer 16 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure 110 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the semiconductor device 100A has a normally-off characteristic.
  • the exemplary materials of the doped nitride-based semiconductor layers 30 and 40 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
  • the electrodes 20, 22, 24 are disposed on the nitride-based semiconductor layer 16. Each of the electrodes 20, 22, 24 can serve as a source electrode or a drain electrode. In some embodiments, each of the electrodes 20, 22, 24 can be called a source/drain (S/D) electrode, which means they can serve as a source electrode or a drain electrode, depending on the device design.
  • S/D source/drain
  • the electrodes 20 and 22 can be located at two opposite sides of the gate electrode 32.
  • the doped nitride-based semiconductor layers 30 and the gate electrode 32 are located between the electrodes 20 and 22.
  • the electrodes 22 and 24 can be located at two opposite sides of the gate electrode 42.
  • the doped nitride-based semiconductor layers 40 and the gate electrode 42 are located between the electrodes 22 and 24.
  • the electrodes 20, 22, 24 and the gate electrodes 32 and 42 can collectively act as at least one nitride-based/GaN-based dual-gate HEMT with the 2DEG region, which can be called a nitride-based/GaN-based dual-gate semiconductor device.
  • the electrodes 20, 22, 24 are symmetrical about the gate electrode 32 or 42 therebetween.
  • the electrodes 20, 22, 24 can be optionally asymmetrical about the gate electrode 32 or 42 therebetween.
  • the electrodes 20, 22, 24 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 20, 22, 24 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the electrodes 20, 22, 24 may be a single layer, or plural layers of the same or different composition.
  • the electrodes 20, 22, 24 form ohmic contact with the nitride-based semiconductor layer 16. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes 20, 22, 24.
  • the passivation layer 52 is disposed over the passivation layer 50.
  • the passivation layer 52 covers the passivation layer 50.
  • the passivation layer 52 can form projection portions conformal with profiles of the passivation layer 50.
  • the electrodes 20, 22, 24 can penetrate the passivation layers 50 and 52 to make contact with the nitride-based semiconductor layer 16.
  • the exemplary materials of the passivation layers 50 and 52 can include, for example but are not limited to, SiNx, SiOx, Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof.
  • the passivation layers 50 or 52 is a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • the passivation layer 70 is disposed above the electrodes 20, 22, 24 and the passivation layer 52.
  • the passivation layer 70 covers the electrodes 20, 22, 24 and the passivation layer 52.
  • the passivation layer 70 can serve as a planarization layer which has a level top surface to support other layers/elements.
  • the passivation layer 70 can be formed as being thicker, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 70 to remove the excess portions, thereby forming a level top surface.
  • CMP chemical mechanical polish
  • the field plate 60 is in a position higher than the doped nitride-based semiconductor layer 30.
  • the field plate 60 at least vertically overlaps with the doped nitride-based semiconductor layer 30. As such, the field plate 60 can still modulate electric field distribution near the edge side of the doped nitride-based semiconductor layer 30 and the gate electrode 32.
  • the exemplary materials of the field plate 60 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.
  • the contact vias 72 are disposed within the passivation layer 70.
  • the contact vias 72 penetrate the passivation layer 70.
  • the contact vias 72 extend longitudinally to electrically couple with the electrodes 20, 22, 24, respectively.
  • the upper surfaces of the contact vias 72 are free from coverage of the passivation layer 70.
  • the exemplary materials of the contact vias 72 can include, for example but are not limited to, conductive materials, such as metals or alloys.
  • a patterned conductive layer 74 is disposed on the passivation layer 70 and the contact vias 72.
  • the patterned conductive layer 74 is in contact with the contact vias 72.
  • the patterned conductive layer 74 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 74 can form at least one circuit.
  • the exemplary materials of the patterned conductive layer 74 can include, for example but are not limited to, conductive materials.
  • the patterned conductive layer 74 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • the passivation layer 76 is disposed above the passivation layer 70 and the patterned conductive layer 74.
  • the passivation layer 76 covers the passivation layer 70 and the patterned conductive layer 74.
  • the exemplary materials of the passivation layer 76 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof.
  • the passivation layer 76 is a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • a patterned conductive layer 80 is disposed on the passivation layer 76 and the contact vias 78.
  • the patterned conductive layer 80 is in contact with the contact vias 78.
  • the patterned conductive layer 80 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 80 can form at least one circuit.
  • the exemplary materials of the patterned conductive layer 80 can include, for example but are not limited to, conductive materials.
  • the patterned conductive layer 80 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • the circuit of the patterned conductive layer 74 or 80 can connect different layers/elements, making these layers or elements have the same electrical potential.
  • the protection layer 82 is disposed above the passivation layer 76 and the patterned conductive layer 80.
  • the protection layer 82 covers the passivation layer 76 and the patterned conductive layer 80.
  • the protection layer 82 can prevent the patterned conductive layer 80 from oxidizing. Some portions of the patterned conductive layer 80 can be exposed through openings in the protection layer 82, which are configured to electrically connect to external elements (e.g., an external circuit) .
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • Nitride-based semiconductor layers 14 and 16 can be formed over the substrate 10 in sequence by using the above-mentioned deposition techniques.
  • a doped nitride-based semiconductor layer 30 and a gate electrode 32 can be formed and patterned over the nitride-based semiconductor layer 14.
  • a doped nitride-based semiconductor layer 40 and a gate electrode 42 can be formed and patterned over the nitride-based semiconductor layer 14.
  • a passivation layer can be formed over the nitride-based semiconductor layer 14 to cover the doped nitride-based semiconductor layer 30 and the gate electrode 32.
  • the passivation layer can be formed over the nitride-based semiconductor layer 14 to cover the doped nitride-based semiconductor layer 40 and the gate electrode 42.
  • a conductive layer 84 can be formed on the passivation layer 50.
  • a passivation layer 86 can be formed on the conductive layer 84.
  • the passivation layer 86 is in contact with conductive layer 84.
  • the conductive layer 84 is entirely covered by the passivation layer 86.
  • the passivation layer 86 is conformal with the conductive layer 84 and thus has projections.
  • an etching process is performed to thin down the passivation layer 86.
  • the thinning down includes make the passivation layer 86 have flat top surface.
  • the etching process is still performed to thin down the passivation layer 86 until a portion of the conductive layer 84 which is located above the gate electrode is exposed.
  • the etching process is performed for exposing the conductive layer 84 from the passivation layer 86.
  • the conductive layer 84 and the passivation layer 86 have different etching rates with respect to the same etchant used in the etching process.
  • the etching rate of the conductive layer 84 can be less than the etching rate of the passivation layer 86 in the etching process as mentioned with respect to FIGS. 2C and 2D.
  • the etching process has a high etching selectivity between the conductive layer 84 and the passivation layer 86.
  • the etching stage with respect to FIGS. 2C and 2D is applied/performed by using an etching back process. Since the removal of the conductive layer 84 can be performed by the etching back process which results from the high etching selectivity, such the etching stage serve as a self-alignment process.
  • another etching process means the etching process in this stage may apply a different etchant as the previous one.
  • the conductive layer 84 and the passivation layer 86 have different etching rates with respect to the same etchant as well.
  • the etching rate of the conductive layer 84 can be greater than the etching rate of the passivation layer 86 in this etching stage. Accordingly, during the etching process, the exposed portions of the conductive layer 84 are removed and then the passivation layer 50 is exposed from the conductive layer 84 and the passivation layer 86.
  • the conductive layer 84 is in a position lower than the passivation 50.
  • the conductive layer can be divided into a plurality of sub-conductive layers. That is, the conductive layer 84 can become discontinuous from a continuous profile.
  • the passivation layer 86 is removed. Then, a mask layer 88 is formed over the conductive layer 84 and the passivation layer 50. Some portions of the conductive layer 84 are exposed from the mask layer 88. The mask layer 88 can define the profile of the conductive layer 84 in a subsequent etching process.
  • electrodes 20, 22, and 24 and passivation layer 52 and 70 are formed. Accordingly, a self-alignment process for field plates is achieved. Such the self-alignment process can be applied for obtaining desired profiles of field plates.
  • FIG. 3 is a cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure.
  • the semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the field plate 60 is replaced by a field plate 60B.
  • the field plate 60B plate has a left end portion 602B in a position higher than the gate electrode 32.
  • the left end portion 602B of the field plate 60B is adjacent to the projection portion of the passivation layer 50.
  • the left end portion 602B of the field plate 60B is in contact with the projection portion of the passivation layer 50.
  • the left end portion 602B of the field plate 60B has a curved end surface facing upward.
  • the curved end surface of the field plate 60B can receive a portion of the passivation layer 52.
  • the curved end surface of the field plate 60B can distribute the stress from the portion of the passivation layer 52 well so as to avoid void or crack therebetween.
  • the curved end surface of the field plate 60B can be formed by tuning recipes in the etching stage.
  • FIG. 4 is a cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure.
  • the semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the field plate 60 is replaced by a field plate 60C.
  • An entirety of the field plate 60C is in within a thickness of the gate electrode. More specifically, opposite end portions 602C and 604C of the field plate 60C are located beneath top surfaces of the gate electrode 32 and the projection portion of the passivation layer 50. The left end portion 602C of the field plate 60C is in contact with the projection portion of the passivation layer 50. The left end portion 602C of the field plate 60C abuts against the projection portion of the passivation layer 50. The right end portion 604C of the field plate 60C is covered by the passivation layer 52. An entirety of the field plate 60C is in a linear shaped profile. In some embodiments, the field plate 60C laterally extends to have an uniform thickness. As such, parasitic capacitance between the gate electrode 32 and the field plate 60C can be further reduce.
  • FIG. 5 is a cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure.
  • the semiconductor device 1D is similar to the semiconductor device 1C as described and illustrated with reference to FIG. 4, except that the field plate 60C is replaced by a field plate 60D.
  • FIG. 6 is a cross-sectional view of a semiconductor device 1E according to some embodiments of the present disclosure.
  • the semiconductor device 1E is similar to the semiconductor device 1 as described and illustrated with reference to FIGS. 1A and 1B, except that the field plate 60 is replaced by a field plate 60E.
  • the embodiments show that the self-alignment process applied to formation of field plates is flexible, which means various profiles of field plates can be achieved, so as to satisfy different device requirements.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteurs à base de nitrure qui comprend une première couche semi-conductrice à base de nitrure, une seconde couche semi-conductrice à base de nitrure, une première électrode et une seconde électrode, une électrode de grille, une couche de passivation et une plaque de champ. La seconde couche semi-conductrice à base de nitrure est disposée sur la première couche semi-conductrice à base de nitrure et présente une bande interdite supérieure à celle de la première couche semi-conductrice à base de nitrure. La première électrode et la seconde électrode sont disposées sur la seconde couche semi-conductrice à base de nitrure. L'électrode de grille est disposée sur la seconde couche semi-conductrice à base de nitrure et entre les première et seconde électrodes. La couche de passivation recouvre la seconde couche semi-conductrice à base de nitrure et l'électrode de grille pour former une partie de projection conforme à un profil de l'électrode de grille. La plaque de champ est disposée sur la seconde couche semi-conductrice à base de nitrure. La plaque de champ est ne chevauche pas l'électrode de grille le long d'une direction verticale.
PCT/CN2022/098966 2022-06-15 2022-06-15 Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication WO2023240491A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/098966 WO2023240491A1 (fr) 2022-06-15 2022-06-15 Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication
CN202280058436.9A CN117916866A (zh) 2022-06-15 2022-06-15 基于氮化物的半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/098966 WO2023240491A1 (fr) 2022-06-15 2022-06-15 Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2023240491A1 true WO2023240491A1 (fr) 2023-12-21

Family

ID=89193015

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/098966 WO2023240491A1 (fr) 2022-06-15 2022-06-15 Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN117916866A (fr)
WO (1) WO2023240491A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113601A1 (en) * 2004-11-30 2006-06-01 Shibib Muhammed A Dual-gate metal-oxide semiconductor device
CN101976686A (zh) * 2005-06-10 2011-02-16 日本电气株式会社 场效应晶体管
US20150144953A1 (en) * 2013-11-26 2015-05-28 Darrell G. Hill Transistors with field plates resistant to field plate material migration and methods of their fabrication
US20150279722A1 (en) * 2014-03-31 2015-10-01 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method of manufacturing the same
CN108604596A (zh) * 2015-07-17 2018-09-28 剑桥电子有限公司 用于半导体装置的场板结构
CN112204753A (zh) * 2020-07-07 2021-01-08 英诺赛科（珠海）科技有限公司 半导体装置和其制作方法
CN114270533A (zh) * 2021-02-19 2022-04-01 英诺赛科(苏州)科技有限公司 半导体器件及其制造方法
US20220130965A1 (en) * 2020-10-27 2022-04-28 Cree, Inc. Field effect transistor with source-connected field plate

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113601A1 (en) * 2004-11-30 2006-06-01 Shibib Muhammed A Dual-gate metal-oxide semiconductor device
CN101976686A (zh) * 2005-06-10 2011-02-16 日本电气株式会社 场效应晶体管
US20150144953A1 (en) * 2013-11-26 2015-05-28 Darrell G. Hill Transistors with field plates resistant to field plate material migration and methods of their fabrication
US20150279722A1 (en) * 2014-03-31 2015-10-01 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method of manufacturing the same
CN108604596A (zh) * 2015-07-17 2018-09-28 剑桥电子有限公司 用于半导体装置的场板结构
CN112204753A (zh) * 2020-07-07 2021-01-08 英诺赛科（珠海）科技有限公司 半导体装置和其制作方法
US20220130965A1 (en) * 2020-10-27 2022-04-28 Cree, Inc. Field effect transistor with source-connected field plate
CN114270533A (zh) * 2021-02-19 2022-04-01 英诺赛科(苏州)科技有限公司 半导体器件及其制造方法

Also Published As

Publication number Publication date
CN117916866A (zh) 2024-04-19

Similar Documents

Publication Publication Date Title
US11929406B2 (en) Semiconductor device and method for manufacturing the same
US20240047540A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2023283954A1 (fr) Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication
US20240038886A1 (en) Semiconductor device and method for manufacturing the same
US20230075628A1 (en) Semiconductor device and method for manufacturing the same
US20220376074A1 (en) Nitride-based semiconductor device and method for manufacturing the same
US20230095367A1 (en) Semiconductor device and method for manufacturing the same
US20240038852A1 (en) Semiconductor device and method for manufacturing the same
US20240030309A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2023019436A1 (fr) Dispositif à semi-conducteurs et son procédé de fabrication
WO2023082058A1 (fr) Dispositif semi-conducteur à base de nitrure et son procédé de fabrication
US20240038883A1 (en) Semiconductor device and method for manufacturing the same
WO2023102744A1 (fr) Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication
US20240047567A1 (en) Semiconductor device and method for manufacturing the same
US20240030331A1 (en) Semiconductor device and method for manufacturing the same
US20240030327A1 (en) Semiconductor device and method for manufacturing the same
US20230369423A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2023240491A1 (fr) Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication
CN115440811B (zh) 半导体器件及其制造方法
WO2024040600A1 (fr) Dispositif à semi-conducteur et son procédé de fabrication
WO2024108491A1 (fr) Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication
WO2024108490A1 (fr) Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication
WO2024092720A1 (fr) Dispositif à semi-conducteur et son procédé de fabrication
WO2024016216A1 (fr) Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication
WO2024016219A1 (fr) Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22946185

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202280058436.9

Country of ref document: CN