WO2024108422A1 - Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication Download PDF

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WO2024108422A1
WO2024108422A1 PCT/CN2022/133708 CN2022133708W WO2024108422A1 WO 2024108422 A1 WO2024108422 A1 WO 2024108422A1 CN 2022133708 W CN2022133708 W CN 2022133708W WO 2024108422 A1 WO2024108422 A1 WO 2024108422A1
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based semiconductor
nitride
semiconductor layer
type doped
doped nitride
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PCT/CN2022/133708
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English (en)
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King Yuen Wong
Yang Liu
Yi-Lun Chou
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Innoscience (Zhuhai) Technology Co., Ltd.
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Priority to PCT/CN2022/133708 priority Critical patent/WO2024108422A1/fr
Priority to CN202280074917.9A priority patent/CN118302863A/zh
Publication of WO2024108422A1 publication Critical patent/WO2024108422A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a n+doped GaN layer for low contact resistance.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a n-type doped nitride-based semiconductor layer, a p-type doped nitride-based semiconductor layer, and an electrode.
  • the first nitride-based semiconductor layer has a first portion and a second portion, in which the first portion has a thickness greater than that of the second portion and is surrounded by the second portion.
  • the second nitride-based semiconductor layer is disposed over the first portion and has a bandgap greater than that of the first nitride-based semiconductor layer.
  • the n-type doped nitride-based semiconductor layer is disposed over the second portion of the first nitride-based semiconductor layer.
  • the p-type doped nitride-based semiconductor layer is disposed over and makes contact with the n-type doped nitride-based semiconductor layer.
  • the electrode penetrates the p-type doped nitride-based semiconductor layer to make contact with the n-type doped nitride-based semiconductor layer.
  • a method for manufacturing a nitride-based semiconductor device includes steps as follows: forming a first nitride-based semiconductor layer having a first and a second portions, wherein the first portion has a thickness greater than that of the second portion and is surrounded by the second portion; forming a second nitride-based semiconductor layer over the first portion of the first nitride-based semiconductor layer; forming an n-type doped nitride-based semiconductor layer on the second portion of the first nitride-based semiconductor layer; forming a blanket p-type doped nitride-based semiconductor layer to cover the n-type doped nitride-based semiconductor layer and the second nitride-based semiconductor layer; performing a patterning process on the blanket p-type doped nitride-based semiconductor layer, such that some portions of the blanket p-type doped nitride-based semiconductor layer are remained on the
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an n-type doped nitride-based semiconductor layer, and a p-type doped nitride-based semiconductor layer.
  • the first nitride-based semiconductor layer has a first and a second portions, in which the first portion has a thickness greater than that of the second portion and is surrounded by the second portion.
  • the second nitride-based semiconductor layer is disposed over the first portion and has a bandgap greater than that of the first nitride-based semiconductor layer.
  • the n-type doped nitride-based semiconductor layer is disposed over the second portion of the first nitride-based semiconductor layer and vertically extends from the second portion of the first nitride-based semiconductor layer to a position over an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.
  • the p-type doped nitride-based semiconductor layer is disposed over and makes contact with the n-type doped nitride-based semiconductor layer.
  • the sidewall of the electrode adjacent to the top surface of the n-type doped nitride-based semiconductor layer is covered by the p-type doped nitride-based semiconductor layer.
  • the resistance of the p-type doped nitride-based semiconductor layer can block leakage current from the electrodes.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing the nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, a doped III-V semiconductor layer 20, a gate electrode 22, n-type doped nitride-based semiconductor layers 30 and 32, p-type doped nitride-based semiconductor layers 34 and 36, electrodes 40 and 42, and a passivation layer 50.
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 16.
  • the buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference.
  • the buffer layer 12 may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer 12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the semiconductor device 1A may further include a nucleation layer (not shown) .
  • the nucleation layer may be formed between the substrate 10 and the buffer layer 12.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer 12.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12.
  • the nitride-based semiconductor layer 16 can be disposed on/over/above the nitride-based semiconductor layer 14.
  • the exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region 15 adjacent to or along the heterojunction.
  • the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the nitride-based semiconductor layer 14 has a portion 142 and a portion 144 connected to the portion 142.
  • the portion 142 is surrounded by the portion 144.
  • the portion 142 has a thickness T1 greater than a thickness T2 of the portion 144.
  • the nitride-based semiconductor layer 16 over the nitride-based semiconductor layer 14 can be confined within the portion 144 of the nitride-based semiconductor layer 14.
  • the doped III-V semiconductor layer 20 is disposed over the nitride-based semiconductor layer 16.
  • the doped III-V semiconductor layer 20 can make contact with the nitride-based semiconductor layer 16.
  • the doped III-V semiconductor layer 20 can bring the nitride-based semiconductor device 1A into an enhancement mode.
  • the doped III-V semiconductor layer 20 can be a p-type doped III-V semiconductor layer.
  • the exemplary materials of the doped p-type doped III-V semiconductor layer can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.
  • the gate electrode 22 is disposed over the doped III-V semiconductor layer 20.
  • the gate electrode 22 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • the n-type doped nitride-based semiconductor layers 30 and 32 are disposed over the portion 144 of the nitride-based semiconductor layer 14.
  • the portion 142 of the nitride-based semiconductor layer 14 is located between the type doped nitride-based semiconductor layers 30 and 32.
  • the conductive type of the n-type doped nitride-based semiconductor layers 30 and 32 includes “n + ” , “n - ” , and “n” .
  • An n + doping portion has a doping concentration higher/heavier than an n-doping portion; and an n-doping portion has a doping concentration than higher an n - -doping portion.
  • the n-type doped nitride-based semiconductor layers 30 and 32 can be n + doped III-V semiconductor layers.
  • the exemplary materials of the n-type doped nitride-based semiconductor layers 30 and 32 can include, for example but are not limited to, n-doped group III-V nitride semiconductor materials, such as n-type GaN, n-type AlGaN, n-type InN, n-type AlInN, n-type InGaN, n-type AlInGaN, or combinations thereof.
  • the n-doped materials are achieved by using a n-type impurity, such as, Si, C, Ge, Se, and Te.
  • the n-type doped nitride-based semiconductor layers 30 and 32 can be configured to improve contact resistance for conductor with respect to semiconductor.
  • the n-type doped nitride-based semiconductor layers 30 and 32 can abut against the nitride-based semiconductor layers 14 and 16.
  • the portion 142 of the nitride-based semiconductor layer 14 can extends horizontally to abut against side surfaces of the n-type doped nitride-based semiconductor layers 30 and 32.
  • the n-type doped nitride-based semiconductor layers 30 and 32 are connected to the nitride-based semiconductor layers 14 and 16.
  • the n-type doped nitride-based semiconductor layers 30 and 32 can vertically extend from the portion 144 of the nitride-based semiconductor layer 14 to a position over an interface between the nitride-based semiconductor layers 14 and 16.
  • the p-type doped nitride-based semiconductor layers 34 and 36 are disposed over the n-type doped nitride-based semiconductor layers 30 and 32, respectively.
  • the p-type doped nitride-based semiconductor layers 34 and 36 can make contact with the n-type doped nitride-based semiconductor layers 30 and 32, respectively.
  • the p-type doped nitride-based semiconductor layers 34 and 36 are entirely at a position over the nitride-based semiconductor layers 14 and 16.
  • the n-type doped nitride-based semiconductor layers 30 and 32 can form interfaces with the p-type doped nitride-based semiconductor layers 34 and 36, respectively, at a position over the interface between the nitride-based semiconductor layers 14 and 16. In some embodiments, thicknesses of the n-type doped nitride-based semiconductor layers 30 and 32 are greater than that of the p-type doped nitride-based semiconductor layers 34 and 36.
  • each of the n-type doped nitride-based semiconductor layers 30 and 32 has a doping concentration greater than that of each of the p-type doped nitride-based semiconductor layers 34 and 36.
  • the n-type doped nitride-based semiconductor layers 30 and 32 can serve as “n+” nitride-based semiconductor layers
  • the p-type doped nitride-based semiconductor layers 34 and 36 can serve as “p” nitride-based semiconductor layers.
  • the exemplary materials of the p-type doped nitride-based semiconductor layers 34 and 36 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.
  • the doped III-V semiconductor layer 20 and the p-type doped nitride-based semiconductor layers 34 and 36 have the same material.
  • the doped III-V semiconductor layer 20 and the p-type doped nitride-based semiconductor layers 34 and 36 are formed by patterning a single blanket p-type doped nitride-based semiconductor layer.
  • the electrode 40 is disposed over the n-type doped nitride-based semiconductor layer 30 and the p-type doped nitride-based semiconductor layer 34.
  • the electrode 40 can penetrate the p-type doped nitride-based semiconductor layer 34 to make contact with the n-type doped nitride-based semiconductor layer 30.
  • the electrode 40 can extend downward such that a bottom surface of the electrode 40 is lower than a bottom surface of the p-type doped nitride-based semiconductor layer 34.
  • the bottom surface of the electrode 40 is within a thickness range of the n-type doped nitride-based semiconductor layer 30.
  • the bottom surface of the electrode 40 is in a position high than the nitride-based semiconductor layer 16.
  • the electrode 40 can have a side surface making contact with inner side surfaces of the p-type doped semiconductor layer 34 and the n-type doped nitride-based semiconductor layer 30.
  • the electrode 42 is disposed over the n-type doped nitride-based semiconductor layer 32 and the p-type doped nitride-based semiconductor layer 36.
  • the electrode 42 can penetrate the p-type doped nitride-based semiconductor layer 36 to make contact with the n-type doped nitride-based semiconductor layer 32.
  • the electrode 42 can extend downward such that a bottom surface of the electrode 42 is lower than a bottom surface of the p-type doped nitride-based semiconductor layer 36.
  • the bottom surface of the electrode 42 is within a thickness range of the n-type doped nitride-based semiconductor layer 32.
  • the bottom surface of the electrode 42 is in a position high than the nitride-based semiconductor layer 16.
  • the electrode 42 can have a side surface making contact with inner side surfaces of the p-type doped semiconductor layer 36 and the n-type doped nitride-based semiconductor layer 32.
  • Each of the electrodes 40 and 42 can serve as a source electrode or a drain electrode.
  • the electrode 40 is a source electrode and the electrode 42 is the drain electrode.
  • the electrodes 40 and 42 can be called ohmic electrodes.
  • the electrodes 40, 42, and the gate electrode 22 can constitute an enhancement mode HEMT.
  • the electrodes 40 and 42 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 40 and 42 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the electrodes 40 and 42 may be a single layer, or plural layers of the same or different composition.
  • the electrodes 40 and 42 can form ohmic contact with the nitride-based semiconductor layer 16. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes 40 and 42.
  • each of the electrodes 40 and 42 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • the p-type doped nitride-based semiconductor layers 34 and 36 can Define the carrier entrance for the electrodes 40 and 42.
  • the electrodes 40 and 42 passing through the p-type doped nitride-based semiconductor layers 34 and 36 to inject carriers into the n-type doped nitride-based semiconductor layers 30 and 32.
  • the sidewalls of the electrodes 40 and 42 adjacent to the top surfaces of the n-type doped nitride-based semiconductor layers 30 and 32 are covered by the p-type doped nitride-based semiconductor layers 34 and 36.
  • the resistance of the p-type doped nitride-based semiconductor layers 34 and 36 can block leakage current from the electrodes 40 and 42.
  • such the structure is compatible with the process that the formation of the p-type doped nitride-based semiconductor layers 34 and 36 is performed after the formation of the n-type doped nitride-based semiconductor layers 30 and 32.
  • dopants in the of p-type doped nitride-based semiconductor layer may diffuse to the channel layer during the formation of n-type doped nitride-based semiconductor layers, which results in degrading the channel mobility and carrier concentration. 30 and 32.
  • the passivation layer 50 is disposed over the nitride-based semiconductor layer 16.
  • the passivation layer 50 covers the n-type doped nitride-based semiconductor layers 30 and 32 and the p-type doped nitride-based semiconductor layers 34 and 36.
  • the exemplary materials of the passivation layer 50 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma-enhanced oxide (PEOX) , or combinations thereof.
  • the passivation layer 50 can be a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a buffer layer 12 is formed over a substrate 10.
  • Nitride-based semiconductor layers 14 and 16 i.e., a channel layer and a barrier layer
  • the nitride-based semiconductor layer 14 has portions 142 and 144 as afore described.
  • N-type doped nitride-based semiconductor layers 30 and 32 are formed on the portions 144 of the nitride-based semiconductor layer 14.
  • the formation of the n-type doped nitride-based semiconductor layers 30 and 32 includes epitaxial growth. Prior to the epitaxial growth, a mask layer is provided to cover the nitride-based semiconductor layer 16 and expose the portion 144 of the nitride-based semiconductor layer 14. Therefore, the formation of the n-type doped nitride-based semiconductor layers 30 and 32 is a selectively epitaxial growth.
  • a blanket p-type doped nitride-based semiconductor layer 60 is formed to cover the n-type doped nitride-based semiconductor layers 30 and 32 and the nitride-based semiconductor layer 16.
  • a patterning process is performed on the blanket p-type doped nitride-based semiconductor layer 60. Accordingly, at least one portion of the blanket p-type doped nitride-based semiconductor layer 60 is removed.
  • the patterning process may include at least one etching stage. After the patterning process, a doped nitride-based semiconductor layer 20 remains on the nitride-based semiconductor layer 16, and p-type doped nitride-based semiconductor layers 34 and 36 remain on the n-type doped nitride-based semiconductor layers 30 and 32.
  • dopants in the p-type doped nitride-based semiconductor layers 34 and 36 may diffuse to the n-type doped nitride-based semiconductor layers 30 and 32 so the thicknesses of the n-type doped nitride-based semiconductor layers 30 and 32 may be varied. At least one n-type feature in portions of the n-type doped nitride-based semiconductor layers 30 and 32 may get weaken.
  • the risk that dopants in the p-type doped nitride-based semiconductor layers 34 and 36 may diffuse to the channel layer during the formation of the n-type doped nitride-based semiconductor layers 30 and 32 is moot. As such, potential degrading to the channel mobility and carrier concentration is avoided.
  • a passivation layer 50 is formed over the nitride-based semiconductor layer 16. Thereafter, a portion of the passivation layer 50 is removed to expose the p-type doped nitride-based semiconductor layers 34 and 36. A removing process is performed on the p-type doped nitride-based semiconductor layers 34 and 36, so as to make through holes in the p-type doped nitride-based semiconductor layers 34 and 36. The removing process can include at least one etching stage.
  • n-type doped nitride-based semiconductor layers 30 and 32 and the p-type doped nitride-based semiconductor layers 34 and 36 have the identical material or similar materials, it is difficult to terminate the removing process free from removal to the n-type doped nitride-based semiconductor layers 30 and 32. Accordingly, some of the n-type doped nitride-based semiconductor layers 30 and 32 is removed to form recesses in the n-type doped nitride-based semiconductor layers 30 and 32. Then, electrodes and a gate electrode as afore mentioned are formed, in which the electrodes are in the through holes, so as to obtain the structure as shown in FIG. 1.
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the nitride-based semiconductor device 1B applies dual channels to the structure.
  • the nitride-based semiconductor device 1B includes III-V layers 70 and 72 which are alternatively disposed with stacked sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14 along a vertical direction.
  • the III-V layer 70 is located between the sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14.
  • the III-V layer 70 makes contact with the sub-portion SP1 of the nitride-based semiconductor layer 14 to form a heterojunction therebetween with a 2DEG region 15A.
  • the III-V layer 72 is located between the sub-portion SP2 of the nitride-based semiconductor layer 14 and the nitride-based semiconductor layer 16.
  • the III-V layer 72 makes contact with the nitride-based semiconductor layer 16 to form a heterojunction therebetween with a 2DEG region 15B.
  • the III-V layers 70 and 72 overlap with a thickness range of the n-type doped nitride-based semiconductor layers 30 and 32 such that dual channels are generated and entirely located between the n-type doped nitride-based semiconductor layers 30 and 32.
  • each of the III-V layers 70 and 72 includes an aluminum nitride layer. Such the configuration can match requirements for RF devices.
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1B as described and illustrated with reference to FIG. 3, except that there is only one III-V layer 74.
  • the III-V layer 74 is located between the sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14.
  • the III-V layer 74 makes contact with the sub-portion SP1 of the nitride-based semiconductor layer 14 to form a heterojunction therebetween with a 2DEG region 15C.
  • the nitride-based semiconductor layer 16 can make contact with the nitride-based semiconductor layer 14 so as to form a heterojunction therebetween with a 2DEG region 15D.
  • the configuration can be achieved by tuning bandgap of the materials applied to the nitride-based semiconductor layers 14 and 16 and the III-V layer 74.
  • the configuration can be achieved by selecting materials for the nitride-based semiconductor layers 14 and 16 and the III-V layer 74.
  • the configuration is considered since the n-type doped nitride-based semiconductor layer 32D may serve as improvement for drain contact resistance. When high voltage operation is applied, too high resistance may result in heat so the power is lost. Accordingly, the configuration can improve such the defect.
  • the n-type doped nitride-based semiconductor layers 30D and 32D may have different doping concentrations.
  • the doping concentrations of the n-type doped nitride-based semiconductor layer 32D is greater than the doping concentrations of the n-type doped nitride-based semiconductor layer 30D.
  • FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the p-type doped nitride-based semiconductor layers 34 and 36 are replaced by the p-type doped nitride-based semiconductor layers 34D and 36D.
  • the p-type doped nitride-based semiconductor layers 34D and 36D can further cover sidewalls of the n-type doped nitride-based semiconductor layers 30 and 32.
  • the coverage of the p-type doped nitride-based semiconductor layers 34D and 36D to the n-type doped nitride-based semiconductor layers 30 and 32 can protect the n-type doped nitride-based semiconductor layers 30 and 32 from etching damaged during the patterning process to the p-type doped nitride-based semiconductor layers 34D and 36D.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

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Abstract

Le dispositif à semi-conducteur à base de nitrure comprend une première couche semi-conductrice à base de nitrure, une seconde couche semi-conductrice à base de nitrure, une couche semi-conductrice à base de nitrure dopée de type n, une couche semi-conductrice à base de nitrure dopée de type p et une électrode. La première couche semi-conductrice à base de nitrure comporte une première partie et une seconde partie, la première partie présentant une épaisseur supérieure à celle de la seconde partie et étant entourée par la seconde partie. La seconde couche semi-conductrice à base de nitrure est disposée sur la première partie et comporte une bande interdite supérieure à celle de la première couche semi-conductrice à base de nitrure. La couche semi-conductrice à base de nitrure dopée de type n est disposée sur la seconde partie de la première couche semi-conductrice à base de nitrure. La couche semi-conductrice à base de nitrure dopée de type p est disposée sur la couche semi-conductrice à base de nitrure dopée de type n et entre en contact avec celle-ci. L'électrode pénètre dans la couche semi-conductrice à base de nitrure dopée de type p pour entrer en contact avec la couche semi-conductrice à base de nitrure dopée de type n.
PCT/CN2022/133708 2022-11-23 2022-11-23 Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication WO2024108422A1 (fr)

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CN202280074917.9A CN118302863A (zh) 2022-11-23 2022-11-23 氮化物基半导体器件及其制造方法

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579327A (zh) * 2012-08-09 2014-02-12 台湾积体电路制造股份有限公司 高电子迁移率晶体管及其形成方法
US20170092747A1 (en) * 2015-09-30 2017-03-30 Sumitomo Electric Industries, Ltd. Hemt having heavily doped n-type regions and process of forming the same
CN111477682A (zh) * 2020-04-13 2020-07-31 杭州士兰明芯科技有限公司 氮化镓晶体管及其制造方法
US20220199782A1 (en) * 2020-12-19 2022-06-23 Cornell University Integrated electronics on the aluminum nitride platform

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579327A (zh) * 2012-08-09 2014-02-12 台湾积体电路制造股份有限公司 高电子迁移率晶体管及其形成方法
US20170092747A1 (en) * 2015-09-30 2017-03-30 Sumitomo Electric Industries, Ltd. Hemt having heavily doped n-type regions and process of forming the same
CN111477682A (zh) * 2020-04-13 2020-07-31 杭州士兰明芯科技有限公司 氮化镓晶体管及其制造方法
US20220199782A1 (en) * 2020-12-19 2022-06-23 Cornell University Integrated electronics on the aluminum nitride platform

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