WO2024108489A1 - Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication Download PDF

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WO2024108489A1
WO2024108489A1 PCT/CN2022/134082 CN2022134082W WO2024108489A1 WO 2024108489 A1 WO2024108489 A1 WO 2024108489A1 CN 2022134082 W CN2022134082 W CN 2022134082W WO 2024108489 A1 WO2024108489 A1 WO 2024108489A1
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nitride
based semiconductor
semiconductor layer
portions
semiconductor device
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PCT/CN2022/134082
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English (en)
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Ronghui Hao
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Innoscience (suzhou) Semiconductor Co., Ltd.
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Priority to PCT/CN2022/134082 priority Critical patent/WO2024108489A1/fr
Publication of WO2024108489A1 publication Critical patent/WO2024108489A1/fr

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

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  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a doped nitride-based semiconductor layer with different profiles in different vertical cross-sectional views of the nitride-based semiconductor device.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a doped nitride-based semiconductor layer.
  • the second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • 2DEG two-dimensional electron gas
  • the second nitride-based semiconductor layer has a plurality of recessed portions separated from each other and a plurality of flat portions arranged alternatively along a first direction.
  • the doped nitride-based semiconductor layer conformally covers the second nitride-based semiconductor layer and has a plurality of first portions and a plurality of second portions. The first portions cover the recessed portions respectively and the second portions cover the flat portions respectively.
  • the doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view of the nitride-based semiconductor device passing through the first portion thereof.
  • the doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view passing through the second portion thereof. The second profile is different from that of the first profile.
  • a method for manufacturing a semiconductor device includes steps as follows.
  • a first nitride-based semiconductor layer is formed.
  • An intermediate nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer, wherein the intermediate nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer.
  • Portions of the intermediate nitride-based semiconductor layer are removed to form a second nitride-based semiconductor layer having plurality of recessed portions separated from each other and a plurality of flat portions arranged alternatively along a first direction.
  • a doped nitride-based semiconductor layer is formed to at least cover the recessed portions and the flat portions, such that the doped nitride-based semiconductor layer is formed to have a plurality of first portions and a plurality of second portions, wherein the first portions cover the recessed portions respectively and the second portions cover the flat portions respectively.
  • the doped nitride-based semiconductor layer has a first profile in a first vertical cross-sectional view passing through the first portion thereof.
  • the doped nitride-based semiconductor layer has a second profile in a second vertical cross-sectional view passing through the second portion thereof. The first profile is different from the second profile.
  • a semiconductor device in accordance with one aspect of the present disclosure, includes a channel layer, a barrier layer and a doped semiconductor layer.
  • the barrier layer is disposed over the channel layer and having a plurality of recessed portions separated from each other and a plurality of flat portions. Each of the flat portions is located between two of the adjacent recessed portions.
  • the doped semiconductor layer is conformally disposed on the recessed portions and the flat portions, such that the doped semiconductor layer has a plurality of first portions received by the recessed portions respectively and a plurality of second portions disposed over the flat portions respectively.
  • the doped semiconductor layer In a first vertical cross-sectional view of the of the semiconductor device passing through the first portion and the recessed portion thereunder, the doped semiconductor layer has an uneven top surface.
  • the doped semiconductor layer In a second vertical cross-sectional view of the of the semiconductor device passing through the second portion and the flat portion thereunder, the doped semiconductor layer has a flat top surface.
  • the barrier layer is formed to have a plurality of recessed portions and a plurality of flat portions alternatively along a direction. Then, a doped nitride-based semiconductor layer is formed to extend along the direction to cover the recessed portions and the flat portions of the barrier layer. Therefore, the doped nitride-based semiconductor layer can have different profiles in different vertical cross-sectional views of the semiconductor device. Portions of the doped nitride-based semiconductor layer can extend into the recessed portions of the barrier layer; and therefore, top and side surfaces of the flat portion of the barrier layer can make contact with the doped nitride-based semiconductor layer.
  • the contact area between the doped nitride-based semiconductor layer and the barrier layer can be increased.
  • the dopants in the doped nitride-based semiconductor layer can fully deplete a zone of the 2DEG region under the flat portion, and thus a current leakage issue can be avoided.
  • FIG. 1A is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 1B is a vertical cross-sectional view taken along a line A-A’ in the FIG. 1A;
  • FIG. 1C is a vertical cross-sectional view taken along a line B-B’ in the FIG. 1A;
  • FIG. 1D is a vertical cross-sectional view taken along a line C-C’ in the FIG. 1A;
  • FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure
  • FIG. 3 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 4 is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
  • FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1A is a top view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • FIG. 1B is a vertical cross-sectional view taken along a line A-A’ in the FIG. 1A.
  • the nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, electrodes 20, 22, a doped nitride-based semiconductor layer 30, a gate electrode 34, and a dielectric layer 40.
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14.
  • the buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference.
  • the buffer layer 12 may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the semiconductor device 1A may further include a nucleation layer (not shown) .
  • the nucleation layer may be formed between the substrate 10 and the buffer layer 12.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer 12.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12.
  • the nitride-based semiconductor layer 16 can be disposed on/over/above the nitride-based semiconductor layer 14.
  • the exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • HEMT devices In conventional HEMT devices, it is usually to form a p-type doped nitride-based semiconductor layer to deplete a zone of 2DEG region thereunder, so as to achieve an enhancement mode device.
  • the zone of 2DEG under the p-type doped nitride-based semiconductor layer may not be fully depleted, resulting in a current leakage issue as the device is in an off-state.
  • the present disclosure provides a novel structure.
  • the nitride-based semiconductor layer 16 firstly, an intermediate nitride-based semiconductor layer having a flat top surface is formed. Then, a patterning process is performed on the doped intermediate nitride-based semiconductor layer, portions of the intermediate nitride-based semiconductor layer are removed, thereby forming the nitride-based semiconductor layer 16 with a plurality of recessed portions 162A and a plurality of flat portions 164.
  • the recessed portions 162A and the flat portions 164 are arranged alternatively along a direction D1.
  • Recessed portions 162A of the second nitride-based semiconductor layer extend along a direction D2 different from that of the direction D1, for example, the extending direction D2 is vertical to the direction D1.
  • a profile of the recessed portions 162A in the FIG. 1A has a constant width, for example, a rectangular profile with a straight edge.
  • the recessed portions 162A are arranged at equal intervals along the direction D1.
  • the recessed portions 162A are separated from each other.
  • Each of the flat portions 164 is located between two of the adjacent recessed portions 162A.
  • Each of the recessed portions 162A has a top surface lower than that of the flat portion 164.
  • a doped nitride-based semiconductor layer 22 is formed to extend along the direction D1 to form a strip profile, such that the doped nitride-based semiconductor layer 22 is formed to conformally cover the nitride-based semiconductor layer 16.
  • portions 222 of the doped nitride-based semiconductor layer 22 cover the recessed portions 162A, respectively.
  • the portions 222 of the doped nitride-based semiconductor layer 22 are received/confined by the recessed portions 162A, respectively.
  • the recessed portions 162A has a width smaller than that of the formed doped nitride-based semiconductor layer 22. Referring to FIG.
  • each of the recessed portions 162A has a rectangular profile
  • each of the portions 222 of the doped nitride-based semiconductor layer 22 has a rectangular profile by aforesaid configuration.
  • Portions 224 of the doped nitride-based semiconductor layer 22 are disposed on/over/above the flat portions 164, respectively.
  • the portions 224 of the doped nitride-based semiconductor layer 22 cover the flat portions 164, respectively.
  • the portion 222 has a top surface lower than that of the portion 224.
  • the doped nitride-based semiconductor layer 22 formed on the nitride-based semiconductor layer 16 has an undulating structure.
  • the portion 222 of the doped nitride-semiconductor layer 22 makes contact with a top surface of the recessed portion 162A; and therefore, the dopants in the doped nitride-semiconductor layer 22 can deplete a zone of the 2DEG region in the region R1 through the top surface of the recessed portion 162A.
  • the flat portion 164 is surrounded by the portions 222, 224 of the doped nitride-based semiconductor layer 22, such that side and top surfaces of the flat portion 164 make contact with the doped nitride-based semiconductor layer 22. Therefore, the dopants in the doped nitride-semiconductor layer 22 can deplete a zone of the 2DEG region in the region R2 through the top and the side surfaces of the flat portion 164.
  • a zone of the 2DEG region in the region R2 can be fully depleted by the dopants in the doped nitride-based semiconductor layer 22.
  • a current leakage issue can be avoided.
  • a ratio of the width of the region R1 to the width of the region R2 is in a range from 1 to 10. The range is made for improvement to the sensitivity in the off state. A ratio out of such the range may result in at least one leakage current at an off-state.
  • FIG. 1C is a vertical cross-sectional view taken along a line B-B’ in the FIG. 1A.
  • FIG. 1D is a vertical cross-sectional view taken along a line C-C’ in the FIG. 1A.
  • the striped doped nitride-based semiconductor layer 22 is formed to cover the recessed portions 162A and the flat portions 164; and hence, the doped nitride-based semiconductor layer 22 has different profiles in different vertical cross-sectional views as shown in FIGs 1C and 1D, respectively.
  • FIG. 1C is a vertical cross-sectional view taken along a line B-B’ in the FIG. 1A.
  • FIG. 1D is a vertical cross-sectional view taken along a line C-C’ in the FIG. 1A.
  • the striped doped nitride-based semiconductor layer 22 is formed to cover the recessed portions 162A and the flat portions 164; and hence, the doped nitride-based semiconductor layer 22 has different profiles in different vertical
  • the portion 222 of the doped nitride-based semiconductor layer 22 has a profile with a variable width.
  • the portion 222 has an uneven top surface.
  • the portion 224 of the doped nitride-based semiconductor layer 22 has a profile different from that of the portion 222, for example, a rectangular profile.
  • the portion 224 has a flat top surface.
  • the gate electrode 24 is formed to extend along the direction D1 to form a strip profile, such that the gate electrode 24 is formed to disposed/cover on/over/above the doped nitride-based semiconductor layer 22.
  • the gate electrode 24 makes contact with the doped nitride-based semiconductor layer 30.
  • the gate electrode 24 is formed to have a width less than that of the recessed portion 162A.
  • the portion 222 of the doped nitride-based semiconductor layer 22 is spaced apart from the gate electrode 24 in the FIG. 1C.
  • the doped nitride-based semiconductor layer 22 and the gate electrode 24 can collectively serve as a gate structure.
  • the nitride-based semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 24 is at approximately zero bias.
  • the doped nitride-based semiconductor layer 22 may create at least one p-n junction with the nitride-based semiconductor layer 16 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 24 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked.
  • the nitride-based semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 22 or a voltage applied to the gate electrode 22 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 22) , the zone of the 2DEG region below the gate electrode 22 is kept blocked, and thus no current flows therethrough.
  • a threshold voltage i.e., a minimum voltage required to form an inversion layer below the gate electrode 22
  • the doped nitride-based semiconductor layer 22 can be a p-type doped III-V semiconductor layer.
  • the exemplary materials of the doped nitride-based semiconductor layer 22 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.
  • the nitride-based semiconductor layer 14 includes undoped GaN and the nitride-based semiconductor layer 16 includes AlGaN, and the doped nitride-based semiconductor layer 22 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.
  • the exemplary materials of the gate electrode 24 may include metals or metal compounds.
  • the gate electrode 24 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • the electrodes 30, 32 are disposed on/over/above the nitride-based semiconductor layer 16.
  • the electrodes 30, 32 are formed to extend along the direction D1 to form a strip profile.
  • the electrodes 30, 32 make contact with the nitride-based semiconductor layer 16.
  • the gate electrode 22 is located between the electrodes 30, 32.
  • Each of the recessed portions 162A extends along a direction D2 from the electrode 30 toward the electrode 32.
  • the electrodes 30, 32 are disposed over two opposite sides of the recessed portions 162A.
  • the electrode 30 can serve as a source electrode.
  • the electrode 30 can serve as a drain electrode.
  • the electrode 32 can serve as a source electrode.
  • the electrode 32 can serve as a drain electrode.
  • the role of the electrodes 30 and 32 depends on the device design.
  • the electrodes 30 and 32 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 30 and 32 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • Each of the electrodes 30 and 32 may be a single layer, or plural layers of the same or different composition.
  • the electrodes 30 and 32 form ohmic contacts with the nitride-based semiconductor layer 16. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the electrodes 30 and 32.
  • the dielectric layer 40 is disposed on/over/above the nitride-based semiconductor layer 16, the doped nitride-based semiconductor layer 22, the gate electrode 24, and the electrodes 30, 32.
  • the material of the dielectric layer 40 can include, for example but are not limited to, dielectric materials.
  • the dielectric layer 40 can include, for example but are not limited to, SiN x , SiO x , Si 3 N 4 , SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
  • the dielectric layer 40 can include an oxide.
  • the dielectric layer 40 can be a multi-layered structure, such as a composite dielectric layer of Al 2 O 3 /SiN, Al 2 O 3 /SiO 2 , AlN/SiN, AlN/SiO 2 , or combinations thereof.
  • the optional dielectric layer can be formed by a single layer or more layers of dielectric materials.
  • the exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO x layer, a SiN x layer, a high-k dielectric material (e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc) , or combinations thereof.
  • a high-k dielectric material e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a substrate 10 is provided.
  • a nitride-based semiconductor layer is formed on/over/above the substrate 10 by using deposition techniques.
  • An intermediate nitride-based semiconductor layer 16’ is formed on/over/above the first nitride-based semiconductor layer 14.
  • portions of the intermediate nitride-based semiconductor layer 16’ are removed to form nitride-based semiconductor layer 16 having plurality of recessed portions 162A separated from each other and a plurality of flat portions 164 arranged alternatively along a direction D1.
  • an intermediate doped nitride-based semiconductor layer 22’ is formed to at least cover the recessed portions 162A and the flat portions 164, such that the intermediate doped nitride-based semiconductor layer 22’ is formed to have a plurality of portions 222 and a plurality of portions 224.
  • the portions 222 cover the recessed portions 162A respectively and the portions 224 cover the flat portions 164 respectively.
  • a patterning process is performed on the intermediate doped nitride-based semiconductor layer 22’ to remove excess portions thereof, such that an doped nitride-based semiconductor layer 22 with the portions 222 and the portions 224 is formed.
  • the portion 222 is formed to have a profile with a variable width.
  • the portion 224 is formed to have a rectangular profile.
  • a gate electrode 24, the electrodes 30, 32 and the dielectric layer 40 are formed in sequence, obtaining the nitride-based semiconductor device 1A in the FIG. 1A.
  • FIG. 3 is a top view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGs. 1A, 1B, 1C and 1D, except that the recessed portion 162B has an ellipse profile with a curve edge.
  • FIG. 4 is a top view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGs. 1A, 1B and 1C, except that the recessed portion 162C has a profile with a gradually changed width, for example, a trapezoid profile.
  • a width of the recessed portion 162C is gradually decreased along a direction D2 from the electrode 30 toward the electrode 32.
  • nitride-based semiconductor devices 1B and 1C With respect to the nitride-based semiconductor devices 1B and 1C, by changing the profile of the recessed portions 162B and 162C in a top view of the nitride-based semiconductor devices 1B and 1C, a desired electric distribution can be obtained, so as to meet different device requirements.
  • FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the recessed portion 162D has inclined side surfaces.
  • the recessed portion 162D and the flat portion 164D share the same inclined side surfaces. Since the doped nitride-based semiconductor layer 22D is conformally covered with the nitride-based semiconductor layer 16D, each of the portions 222D and 224D can have inclined side surfaces.
  • the contact area between the nitride-based semiconductor layer 16D and the doped nitride-based semiconductor layer 22D can be further increased. More dopants in the doped nitride-based semiconductor layer 22D can assist to deplete zones of the 2DEG region.
  • FIG. 6 is a top view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIGs. 1A, 1B and 1C, except that the recessed portion 162E has a profile with a gradually changed width, for example, a trapezoid profile and an inverted trapezoid profile.
  • the trapezoid profile and the inverted trapezoid profile are arranged alternately along the direction D1.
  • the trapezoid profile and the inverted trapezoid profile have oblique edges/boundaries so more side areas are configured to deplete the 2DEG region for the normally-off state.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

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Abstract

Le présent dispositif à semi-conducteur à base de nitrure comprend une première couche semi-conductrice à base de nitrure, une seconde couche semi-conductrice à base de nitrure et une couche semi-conductrice à base de nitrure dopé. La seconde couche semi-conductrice à base de nitrure comporte une pluralité de parties évidées séparées les unes des autres ainsi qu'une pluralité de parties plates agencées en alternance le long d'une première direction. La couche semi-conductrice à base de nitrure dopé recouvre la seconde couche semi-conductrice à base de nitrure de façon à en épouser la forme, et elle comporte une pluralité de premières parties ainsi qu'une pluralité de secondes parties. Les premières parties recouvrent respectivement les parties évidées, et les secondes parties recouvrent respectivement les parties plates. La couche semi-conductrice à base de nitrure dopé présente un premier profil dans une première vue en coupe transversale verticale du dispositif à semi-conducteur à base de nitrure qui passe à travers la première partie de celle-ci. La couche semi-conductrice à base de nitrure dopé présente un second profil dans une seconde vue en coupe transversale verticale qui passe à travers la seconde partie de celle-ci. Le second profil est différent du premier profil.
PCT/CN2022/134082 2022-11-24 2022-11-24 Dispositif à semi-conducteurs à base de nitrure et son procédé de fabrication WO2024108489A1 (fr)

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