WO2024065148A1 - Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication Download PDF

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WO2024065148A1
WO2024065148A1 PCT/CN2022/121552 CN2022121552W WO2024065148A1 WO 2024065148 A1 WO2024065148 A1 WO 2024065148A1 CN 2022121552 W CN2022121552 W CN 2022121552W WO 2024065148 A1 WO2024065148 A1 WO 2024065148A1
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nitride
based semiconductor
layer
semiconductor layer
semiconductor device
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PCT/CN2022/121552
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English (en)
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Huixin He
Kai Hu
Zhongyu ZHANG
King Yuen Wong
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Innoscience (Zhuhai) Technology Co., Ltd.
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Priority to PCT/CN2022/121552 priority Critical patent/WO2024065148A1/fr
Publication of WO2024065148A1 publication Critical patent/WO2024065148A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a gate electrode with a stepwise profile.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, an etch resistant layer, and a gate electrode.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the source electrode and the drain electrode are disposed on the second nitride-based semiconductor layer.
  • the etch resistant layer is disposed on the second nitride-based semiconductor layer.
  • the etch resistant layer makes contact with the second nitride-based semiconductor layer and extends from the second nitride-based semiconductor layer to a position higher than the source electrode and the drain electrode.
  • the gate electrode is disposed over the second nitride-based semiconductor layer and has a bottom potion and a middle portion over the bottom portion and wider than the bottom portion.
  • a method for manufacturing a nitride-based semiconductor device has steps as follows; forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer to form a heterojunction therebetween; forming a first etch stop layer on the second nitride-based semiconductor layer; forming an opening in the first etch stop layer; forming a second etch stop layer on the second nitride-based semiconductor layer and connecting to the first etch stop layer; forming a first passivation layer to cover the second etch stop layer; forming an opening in the first passivation layer to expose a portion of the second etch stop layer; removing the exposed portion of the second etch stop layer; and forming a gate electrode aligning with the opening of the first passivation layer.
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an etch resistant layer, a passivation layer, and a gate electrode.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the etch resistant layer is disposed on the second nitride-based semiconductor layer and makes contact with the second nitride-based semiconductor layer.
  • the passivation layer is disposed over the second nitride-based semiconductor layer and is separated from the second nitride-based semiconductor layer by the etch resistant layer.
  • the gate electrode is disposed over the second nitride-based semiconductor layer and has a bottom potion and a middle portion over the bottom portion and wider than the bottom portion.
  • the etch stop layers can protect the second nitride-based semiconductor layer from damaged in more than one etching stage so as to avoid generation of unwanted defects in the second nitride-based semiconductor layer.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • FIG. 2A, FIG. 2B, FIG. 2C, FIG 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, and FIG. 2J show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, etch resistant layers 20, 22, 44, 46, electrodes 30 and 32, passivation layers 40, 42, 48, 50, a gate dielectric layer 52, and a gate electrode 54.
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the nitride-based semiconductor device 1A may further include a buffer layer (not illustrated) .
  • the buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12.
  • the buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the semiconductor device 1A may further include a nucleation layer (not shown) .
  • the nucleation layer may be formed between the substrate 10 and a buffer layer.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer.
  • the nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12.
  • the exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the electrodes 30 and 32 are disposed on the nitride-based semiconductor layer 14.
  • the electrode 30 can make contact with the nitride-based semiconductor layer 14.
  • the electrode 32 can make contact with the nitride-based semiconductor layer 14.
  • Each of the electrodes 30 and 32 can serve as a source electrode or a drain electrode. In some embodiments, the electrodes 30 and 32 can be called ohmic electrodes.
  • the electrodes 30 and 32 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 30 and 32 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the electrodes 30 and 32 may be a single layer, or plural layers of the same or different composition.
  • the electrodes 30 and 32 can form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes 30 and 32.
  • each of the electrodes 30 and 32 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • the etch resistant layers 20 and 22 are disposed on the nitride-based semiconductor layer 14.
  • the etch resistant layers 20 and 22 can cover the nitride-based semiconductor layer 14.
  • the etch resistant layers 20 and 22 can make contact with the nitride-based semiconductor layer 14.
  • the etch resistant layer 20 can extend to abut against the electrode 30.
  • the electrode 30 may penetrate the etch resistant layer 20 to make contact with the nitride-based semiconductor layer 14.
  • the etch resistant layer 22 can extend to abut against the electrode 32.
  • the electrode 32 may penetrate the etch resistant layer 22 to make contact with the nitride-based semiconductor layer 14.
  • the passivation layers 40 and 42 are disposed on the etch resistant layers 20 and 22, respectively.
  • the passivation layers 40 and 42 can cover the etch resistant layers 20 and 22, respectively.
  • the passivation layers 40 and 42 can cover the electrodes 30 and 32, respectively.
  • the etch resistant layers 44 and 46 are disposed on the nitride-based semiconductor layer 14.
  • the etch resistant layers 44 and 46 can cover the nitride-based semiconductor layer 14.
  • the etch resistant layers 44 and 46 can make contact with the nitride-based semiconductor layer 14.
  • the etch resistant layers 44 and 46 can laterally extends between the electrodes 30 and 32.
  • the etch resistant layer 44 can laterally extend over the electrode 30.
  • the etch resistant layer 44 may has an upward-extending portion between the electrodes 30 and 32.
  • the etch resistant layer 46 can laterally extend over the electrode 32.
  • the etch resistant layer 46 may has an upward-extending portion between the electrodes 30 and 32.
  • the etch resistant layers 20 and 40 can have a visible interface therebetween. In some embodiments, the etch resistant layers 20 and 40 can be merged with each other so they can collectively serve as a merged etch resistant layer. The merged etch resistant layer formed by the etch resistant layers 20 and 40 can extend from the nitride-based semiconductor layer 14 to a position higher than the electrode 30.
  • the etch resistant layers 22 and 42 can have a visible interface therebetween. In some embodiments, the etch resistant layers 22 and 42 can be merged with each other so can collectively serve as a merged etch resistant layer.
  • the merged etch resistant layer formed by the etch resistant layers 22 and 42 can extend from the nitride-based semiconductor layer 14 to a position higher than the electrode 32.
  • the passivation layer 48 is disposed on the etch resistant layer 44.
  • the passivation layer 48 covers the etch resistant layer 44.
  • the passivation layer 50 is disposed on the etch resistant layer 46.
  • the passivation layer 50 covers the etch resistant layer 46.
  • the materials of the etch resistant layers 20, 22, 44, 46 are different than the materials of the passivation layers 40, 42, 48, 50.
  • the exemplary materials of the etch resistant layers 20, 22, 44, 46 can include, for example but are not limited to, nitride-based dielectric layer.
  • each of the etch resistant layers 20, 22, 44, 46 is an aluminum nitride.
  • the material of the passivation layers 40, 42, 48, 50 can include, for example but are not limited to, dielectric materials.
  • the passivation layers 40, 42, 48, 50 can include SiN x , SiO x , SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
  • the material difference among the etch resistant layers 20, 22, 44, 46 and the passivation layers 40, 42, 48, 50 is to let the etch resistant layers 20, 22, 44, 46 serve as etch stop layer during etching stages of the passivation layers 40, 42, 48, 50.
  • Such the configuration can protect the nitride-based semiconductor layer 14 from accident etching and promote the geometry of the gate dielectric layer 52 and the gate electrode 54.
  • the gate dielectric layer 52 is disposed over the nitride-based semiconductor layer 14.
  • the gate dielectric layer 52 is connected to the etch resistant layer.
  • the gate dielectric layer 52 makes contact with the nitride-based semiconductor layer 14.
  • Sidewalls of the gate dielectric layer 52 can abut against and make contact with the etch resistant layers 44 and 46.
  • the gate dielectric layer 52 can form a stepwise profile along sidewalls of the passivation layers 48 and 50.
  • the gate dielectric layer 52 is a silicon nitride layer, which can serve as a curing layer for improving defects in the surface of the nitride-based semiconductor layer 14.
  • the gate electrode 54 is disposed over the nitride-based semiconductor layer 14 and the gate dielectric layer 52.
  • the gate dielectric layer 52 is disposed between the nitride-based semiconductor layer 14 and the gate electrode 54.
  • the gate electrode 54 can fill up the gap defined by the gate dielectric layer 52.
  • the gate electrode 54 is located between the electrodes 30 and 32.
  • the upward-extending portion of the etch resistant layer 44 is located between the electrode 30 and the gate electrode 54.
  • the upward-extending portion of the etch resistant layer 46 is located between the electrode 32 and the gate electrode 54.
  • the gate electrode 54 has a bottom potion 542, a middle portion 544 over the bottom portion 542, and a top portion 546 over the middle portion 544.
  • the middle portion 544 is wider than the bottom potion 542.
  • the top portion 546 is wider than the middle portion 544.
  • the sidewalls of the gate electrode 54 are in contact with the gate dielectric layer 52.
  • the sidewalls of the gate electrode 54 and the gate dielectric layer 52 can form an interface therebetween in a stepwise shape.
  • the different widths of the gate electrode 54 is able to function as a multiple field plates configuration. For example, ends of the middle portion 544 which are out of the bottom portion 542 can serve as a field plate. Similarly, ends of the top portion 546 which are out of middle portion 544 can serve as a field plate.
  • the gate electrode 54 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • FIG. 1 The structure as shown in FIG. 1 can be achieved by a series of processes with the nitride-based semiconductor layer 14 protected from etching stages. Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, and FIG. 2J, as described below.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a substrate 10 is provided.
  • a nitride-based semiconductor layer 12 is formed on the substrate 10.
  • a nitride-based semiconductor layer 14 is formed on the nitride-based semiconductor layer 12.
  • An etch stop layer 60 is formed on the nitride-based semiconductor layer 14.
  • a passivation layer 62 is formed on the etch stop layer 60. The nitride-based semiconductor layer 14 and the passivation layer 62 are separated from each other by the etch stop layer 60.
  • electrodes 30 and 32 are formed over the nitride-based semiconductor layer 14. The formation of the electrodes 30 and 32 is performed after the formation of the etch stop layer 60.
  • a mask layer 64 is formed on the passivation layer 62.
  • the mask layer 64 has an opening to expose the passivation layer 62.
  • a portion of the passivation layer 62 is removed.
  • the removal of the passivation layer 62 is performed by an etching stage using the mask layer 64.
  • the etch stop layer 60 is exposed from the passivation layer 62. Since the etch stop layer 60 and the passivation layer 62 have different materials so the etch stop layer 60 can serve as etch stop during the etching stage.
  • an opening is formed in the etch stop layer 60 by using an etching stage. The nitride-based semiconductor layer 14 can be exposed from the opening of the etch stop layer 60.
  • an etch stop layer 66 is formed on the nitride-based semiconductor layer 14.
  • the etch stop layer 66 is formed over the etch stop layer 60 and the passivation layer 62 as well.
  • the etch stop layer 66 connects to the etch stop layer 60 so the exposed portion of the nitride-based semiconductor layer 14 as shown in FIG. 2D is entirely covered.
  • a passivation layer 68 is formed to cover the etch stop layer 66.
  • the passivation layer 68 is separated from the nitride-based semiconductor layer 14 by the etch resistant layers 60 and 66.
  • a mask layer 70 is formed on the passivation layer 68.
  • the mask layer 70 has an opening to exposed a portion of the passivation layer 68.
  • the exposed portion of the passivation layer 68 is removed.
  • the removal of the passivation layer 68 is performed by an etching stage using the mask layer 70. After the removal, an opening is formed in the passivation layer 68 to expose a portion of the etch stop layer 66.
  • a gate dielectric layer 52 is formed on the nitride-based semiconductor layer 14.
  • the gate dielectric layer 52 makes contact with the nitride-based semiconductor layer 14.
  • the gate dielectric layer 52 makes contact with the etch stop layer 66 and the passivation layer 68.
  • a gate electrode can be formed, in which the gate electrode aligns with the opening of the passivation layer 68.
  • the etch stop layers 60 and 66 can protect the nitride-based semiconductor layer 14 from damaged in more than one etching stage so as to avoid generation of unwanted defects in the nitride-based semiconductor layer 14.
  • FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the passivation layers 48 and 50, the gate dielectric layer 52, and the gate electrode 54 are replaced by passivation layers 48B and 50B, a gate dielectric layer 52B, and a gate electrode 54B.
  • the passivation layers 48B and 50B have inner sidewalls which are oblique with respect to the nitride-based semiconductor layer 14. Accordingly, the gate dielectric layer 52B formed to cover the passivation layers 48B and 50B can have an oblique profile.
  • the gate electrode 54B has a bottom portion 542B that has oblique sidewalls as well. The oblique profile of the gate dielectric layer 52B and the gate electrode 54B can make deposition thereof smooth.
  • FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the passivation layers 48 and 50, the gate dielectric layer 52, and the gate electrode 54 are replaced by passivation layers 48C and 50C, a gate dielectric layer 52C, and a gate electrode 54C.
  • the passivation layers 48C and 50C have inner sidewalls which are oblique with respect to the nitride-based semiconductor layer 14. Accordingly, the gate dielectric layer 52C formed to cover the passivation layers 48C and 50C can have an oblique profile.
  • the gate electrode 54C has a middle portion 542C that has oblique sidewalls as well. The oblique profile of the gate dielectric layer 52C and the gate electrode 54C can make deposition thereof smooth.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

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Abstract

Dispositif à semi-conducteur à base de nitrure comprenant une première couche semi-conductrice à base de nitrure, une seconde couche semi-conductrice à base de nitrure, une électrode de source et une électrode de drain, une couche résistant à la gravure et une électrode de grille. La seconde couche semi-conductrice à base de nitrure est disposée sur la première couche semi-conductrice à base de nitrure et présente une bande interdite supérieure à celle de la première couche semi-conductrice à base de nitrure. L'électrode de source et l'électrode de drain sont disposées sur la seconde couche semi-conductrice à base de nitrure. La couche résistant à la gravure est disposée sur la seconde couche semi-conductrice à base de nitrure. La couche résistant à la gravure entre en contact avec la seconde couche semi-conductrice à base de nitrure et s'étend de la seconde couche semi-conductrice à base de nitrure à une position plus élevée que l'électrode de source et l'électrode de drain. L'électrode de grille est disposée par-dessus la seconde couche semi-conductrice à base de nitrure et possède une partie inférieure et une partie centrale par-dessus la partie inférieure et plus large que la partie inférieure.
PCT/CN2022/121552 2022-09-27 2022-09-27 Dispositif à semi-conducteur à base de nitrure et son procédé de fabrication WO2024065148A1 (fr)

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CN103582938A (zh) * 2011-06-03 2014-02-12 住友电气工业株式会社 氮化物电子器件、氮化物电子器件的制作方法
US20200357905A1 (en) * 2019-05-08 2020-11-12 Cambridge Electronics Inc. Iii-nitride transistor device with a thin barrier
CN112771677A (zh) * 2020-12-18 2021-05-07 英诺赛科(苏州)科技有限公司 半导体器件以及制造半导体器件的方法
CN114026699A (zh) * 2021-09-07 2022-02-08 英诺赛科(苏州)科技有限公司 半导体装置和其制造方法
CN114127951A (zh) * 2021-09-15 2022-03-01 英诺赛科(苏州)科技有限公司 氮化物基半导体装置以及制造其的方法

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CN103582938A (zh) * 2011-06-03 2014-02-12 住友电气工业株式会社 氮化物电子器件、氮化物电子器件的制作方法
US20200357905A1 (en) * 2019-05-08 2020-11-12 Cambridge Electronics Inc. Iii-nitride transistor device with a thin barrier
CN112771677A (zh) * 2020-12-18 2021-05-07 英诺赛科(苏州)科技有限公司 半导体器件以及制造半导体器件的方法
CN114026699A (zh) * 2021-09-07 2022-02-08 英诺赛科(苏州)科技有限公司 半导体装置和其制造方法
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