WO2024109050A1 - 一种倒装芯片封装堆叠方法 - Google Patents

一种倒装芯片封装堆叠方法 Download PDF

Info

Publication number
WO2024109050A1
WO2024109050A1 PCT/CN2023/103877 CN2023103877W WO2024109050A1 WO 2024109050 A1 WO2024109050 A1 WO 2024109050A1 CN 2023103877 W CN2023103877 W CN 2023103877W WO 2024109050 A1 WO2024109050 A1 WO 2024109050A1
Authority
WO
WIPO (PCT)
Prior art keywords
filling material
chip
solder balls
substrate
solder
Prior art date
Application number
PCT/CN2023/103877
Other languages
English (en)
French (fr)
Inventor
冉红雷
张魁
席善斌
彭浩
黄杰
柳华光
赵海龙
Original Assignee
河北北芯半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 河北北芯半导体科技有限公司 filed Critical 河北北芯半导体科技有限公司
Publication of WO2024109050A1 publication Critical patent/WO2024109050A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate

Definitions

  • Flip chip is a packaging technology that plants balls on the chip, then flips the chip, places it on the substrate through surface mounting technology, and uses heating to melt the solder balls so that the chip and the substrate are interconnected, which is conducive to high-density packaging of chips. Due to the differences in the properties of the solder ball materials, chip materials and substrate materials, the solder balls will generate large thermal mechanical stress during the service of the product, resulting in low reliability of the package. Therefore, bottom filler is usually filled in the gap between the solder ball and the substrate to improve the fatigue life and reliability of the solder ball.
  • the embodiment of the present application provides a flip chip packaging stacking method to simultaneously improve the reliability of the semiconductor packaging structure and the electrical performance of the high-frequency signal of the semiconductor packaging structure, and solve the problem that the electrical performance of the semiconductor packaging structure will be reduced when filling the bottom filling material.
  • an embodiment of the present application provides a flip chip packaging stacking method, comprising: placing a filling template on a substrate, the filling template being provided with through holes of a preset pattern; filling the through holes of the filling template with a filling material, and removing the filling template after the filling material is formed; placing a chip with solder balls on the substrate with the formed filling material, so that at least part of the solder balls are covered by the filling material; connecting the chip and the substrate through the solder balls and curing the filling material, with gaps between the solder balls covered with the filling material.
  • all solder balls on the chip are covered with a filling material; and the thickness of the filling material of the solder balls decreases evenly from the periphery to the middle of the chip.
  • the thickness of the filling material of the solder balls located at the periphery of the chip is greater than the thickness of the filling material of the solder balls located in the middle of the chip.
  • solder balls on the periphery of the chip are covered by the filling material, and solder balls in the middle of the chip are not covered by the filling material.
  • the flip chip packaging stacking method also includes: filling a preset area between the chip and the substrate with filling material to form an air cavity in the middle between the chip and the substrate, and the preset area is the area between the outermost solder balls and the boundary of the chip.
  • the filling material and the solder ball fit tightly together without any gap.
  • the filling material is a polymer composite material including an epoxy resin matrix, a curing agent, and an accelerator.
  • an embodiment of the present application provides a flip chip packaging stacking method, comprising: placing a dam of a preset shape on a substrate; connecting the chip and the substrate through solder balls on the chip, the solder balls on the periphery of the chip are located outside the area surrounded by the dam, and the solder balls in the middle of the chip are located within the area surrounded by the dam, and there are gaps between the solder balls on the chip; filling a filling material into a preset area between the chip and the substrate, the preset area being the area outside the dam; and heating and curing the filling material.
  • the filling material is a polymer composite material including an epoxy resin matrix, a curing agent, and an accelerator.
  • an embodiment of the present application provides a flip chip packaging stacking method, comprising: welding solder joints for bonding with solder balls at preset positions on a substrate; uniformly applying filling material around at least part of the solder balls on the chip and around at least part of the solder joints on the substrate; bonding the solder joints and solder balls so that at least part of the solder balls are covered with the filling material, and there are gaps between the solder balls covered with the filling material; heating and curing the filling material; after heating and curing the filling material, the flip chip packaging stacking method also comprises: filling a preset area between the chip and the substrate with the filling material to form an air cavity in the middle between the chip and the substrate, the preset area being the area between the outermost solder balls and the boundary of the chip.
  • all solder balls on the chip and all solder joints on the substrate are evenly coated with the filling material.
  • the outermost solder balls on the chip and the outermost solder joints on the substrate are evenly coated with filling material, and the solder balls in the middle of the chip and the solder joints in the middle of the substrate are not coated with filling material.
  • the thickness of the filling material of the solder ball decreases evenly from the periphery to the middle of the chip, and the thickness of the filling material around the solder point on the substrate is the same as the thickness of the filling material of the corresponding solder ball.
  • the thickness of the filling material of the solder balls located at the periphery of the chip is greater than the thickness of the filling material of the solder balls located in the middle of the chip, and the thickness of the filling material around the solder joints on the substrate is the same as the thickness of the filling material of the corresponding solder balls.
  • the thickness of the filling material is less than or equal to half of the difference between the distance between the centers of two adjacent solder balls and the diameter of the solder balls.
  • the filling material is a polymer composite material including an epoxy resin matrix, a curing agent, and an accelerator.
  • the beneficial effects of the first aspect are: filling the solder balls with filling material through the filling template so that at least part of the solder balls are covered with the filling material, and the solder balls are surrounded by the filling material so that air can circulate, thereby improving the heat dissipation of the middle solder balls. At least part of the solder balls are covered with the filling material and the setting of the thickness of the filling material improves the reliability of the semiconductor packaging structure while improving the electrical performance of the high-frequency signals of the semiconductor packaging structure.
  • the beneficial effects of the second aspect are: through the preset shape of the dam, the filling material can only be filled outside the dam, thereby improving the reliability of the semiconductor packaging structure; an air cavity is formed in the middle, and the existence of the air cavity improves the electrical performance of the high-frequency signal of the semiconductor packaging structure.
  • the beneficial effect of the third aspect is: filling material is coated around at least part of the solder joints on the substrate and at least part of the solder balls on the chip, and the solder balls and solder joints are connected by bonding, so that air around the middle solder balls can circulate, thereby improving the heat dissipation of the middle solder balls, and improving the reliability of the semiconductor packaging structure while improving the electrical performance of the high-frequency signals of the semiconductor packaging structure.
  • FIG1 is a schematic diagram of a process of a flip chip packaging stacking method provided in one embodiment of the present application.
  • FIG2 is a schematic diagram of some steps of a flip chip packaging stacking method provided by an embodiment of the present application.
  • FIG3 is a schematic diagram of some steps of a flip chip packaging stacking method provided by an embodiment of the present application.
  • FIG4 is a schematic diagram of some steps of a flip chip packaging stacking method provided by an embodiment of the present application.
  • FIG5 is a schematic diagram of a chip front side solder ball coating state provided by an embodiment of the present application.
  • FIG7 is a schematic diagram of a chip front side solder ball coating state provided by another embodiment of the present application.
  • FIG8 is a schematic diagram of a chip front side solder ball coating state provided by another embodiment of the present application.
  • FIG9 is a schematic diagram of a chip front side solder ball coating state provided by another embodiment of the present application.
  • FIG10 is a schematic diagram of a chip front side solder ball coating state provided by another embodiment of the present application.
  • FIG11 is a schematic flow chart of a flip chip packaging stacking method provided in another embodiment of the present application.
  • FIG12 is a schematic diagram of a chip front side solder ball coating state provided by another embodiment of the present application.
  • FIG13 is a schematic flow chart of a flip chip packaging stacking method provided in another embodiment of the present application.
  • FIG14 is a schematic diagram of the steps of a flip chip packaging stacking method provided by another embodiment of the present application.
  • 15 is a schematic diagram of a chip front solder ball coating state and a substrate solder point coating state provided by another embodiment of the present application;
  • 16 is a schematic diagram of a chip front solder ball coating state and a substrate solder point coating state provided by another embodiment of the present application;
  • 17 is a schematic diagram of a chip front solder ball coating state and a substrate solder point coating state provided by another embodiment of the present application;
  • FIG19 is a schematic diagram of the thickness of the filling material between two adjacent solder balls provided in one embodiment of the present application.
  • FIG20 is a schematic diagram of solder ball coating provided by an embodiment of the present application.
  • FIG21 is a schematic diagram of solder ball encapsulation provided by another embodiment of the present application.
  • FIG. 22 is a schematic diagram of a multi-layer packaging stacking structure provided in another embodiment of the present application.
  • the term “if” can be interpreted as “when” or “uponce” or “in response to determining” or “in response to detecting”, depending on the context.
  • the phrase “if it is determined” or “if [described condition or event] is detected” can be interpreted as meaning “uponce it is determined” or “in response to determining” or “uponce [described condition or event] is detected” or “in response to detecting [described condition or event]", depending on the context.
  • references to "one embodiment” or “some embodiments” etc. described in the specification of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean “one or more but not all embodiments", unless otherwise specifically emphasized in other ways.
  • the terms “including”, “comprising”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized in other ways.
  • “Multiple” refers to two or more quantities, and “several” refers to one or more quantities.
  • FIG. 1 is a schematic flow chart of a flip chip package stacking method provided by an embodiment of the present application. Referring to FIG. 1 , the flip chip package stacking method is described in detail as follows:
  • Step A1 placing a filling template on a substrate, wherein the filling template is provided with through holes of a preset pattern.
  • a through hole 202 of a preset pattern is provided on the filling template 201, and the cross-sectional shape of the through hole 202 is set as required.
  • the filling template 201 is placed on the substrate 100, that is, the filling template 201 and the substrate 100 are stacked.
  • Step A2 filling the filling material into the through holes of the filling template, and after the filling material is formed, removing the filling template.
  • the filling material 103 is filled into the through hole 202 of the filling template 201 ; after the filling material 103 is formed, the filling template 201 is removed, and as shown in the lower figure in FIG. 3 , a substrate 100 with the filling material 103 is obtained.
  • Step A3 placing the chip with solder balls on the substrate with the formed filling material, so that at least part of the solder balls are covered by the filling material.
  • a chip 101 with a solder ball 10 is placed on a substrate 100 with a filling material 103, as shown in the lower figure in FIG4 , to obtain a placed chip 101 and substrate 100, that is, the chip 101 and substrate 100 are made to present a stacked posture. At this time, there is still a gap between the filling material 103 and the solder ball 10.
  • the filling material 103 will fit tightly with the solder ball 10.
  • there are multiple solder balls 10 there are multiple solder balls 10, and the filling material 103 forms multiple first filling bodies.
  • solder ball 10 is surrounded by one first filling body, wherein, in one case, each solder ball 10 is configured with a first filling body, and in another case, a part of the number of solder balls 10 is configured with a first filling body.
  • each solder ball 10 on the chip 101 is covered by the filling material 103 .
  • each solder ball 10 is surrounded by a first filling body formed by the filling material 103 .
  • the thickness of the filling material 103 of the solder ball 10 decreases uniformly from the periphery to the middle of the chip 101. It can be understood that the thickness of the filling material 103 of each several turns of the solder ball 10 can be gradually reduced from the outside to the inside, that is, there is a situation where the thickness of the filling material 103 of the solder ball 10 of two or more adjacent turns is unchanged.
  • solder balls 10 of the chip 101 can be arranged in an array or in a circular arrangement from the center to the outside. Based on this, the outermost solder balls 10 refer to multiple solder balls 10 in the outermost circle, and the middlemost solder balls 10 refer to one solder ball 10 or multiple solder balls 10 in the innermost circle, and the number of solder balls 10 in the outermost circle is greater than the number of solder balls 10 in the middle.
  • the thickness of the filling material 103 of the solder balls 10 located at the periphery of the chip 101 is greater than the thickness of the filling material 103 of the solder balls 10 located at the middle of the chip 101.
  • the thickness of the filling material 103 of two or more adjacent circles of solder balls 10 at the periphery can be a constant value, and the thickness of the filling material 103 of two or more adjacent circles of solder balls 10 in the middle can also be a constant value. From the periphery to the middle, the thickness of the filling material 103 of the solder balls 10 at the outer circle is greater than the thickness of the filling material 103 of the solder balls 10 in the middle.
  • the solder balls 10 on the periphery of the chip 101 are covered by the filling material 103 , while the solder balls 10 in the middle are not covered by the filling material 103 .
  • Step A4 connecting the chip and the substrate through solder balls and curing the filling material, and there are spaces between the solder balls coated with the filling material.
  • the flip chip packaging stacking method further includes:
  • the filling material 103 is filled in the predetermined area 104 between the chip 101 and the substrate 100, so that an air cavity 105 is formed in the middle between the chip 101 and the substrate 100.
  • the predetermined area 104 is the area between the outermost solder ball 10 and the boundary of the chip 101. In this way, the filling material 103 forms a second filling body in the predetermined area 104.
  • the substrate 100 may be a hard packaging substrate, such as any one of a polymer substrate, a metal substrate, a composite substrate or a ceramic substrate.
  • the substrate 100 may also be a flexible packaging substrate, and the material of the flexible packaging substrate may be any one of PI (polyimide) resin or PE (polyester) resin.
  • the filling material 103 can disperse the thermomechanical stress on the solder ball 10 to the surface of the filling material 103 , thereby reducing the thermomechanical stress concentrated on the solder ball 10 , and at the same time provide additional protection for the solder ball 10 , thereby increasing the reliability of the solder ball 10 .
  • the material of the filling material 103 can be a polymer composite material composed of epoxy resin matrix mixed with reinforcing particles (the particle material is silicon dioxide, aluminum oxide, etc.), curing agent, accelerator and other additives; the material of the solder ball 10 can be tin-lead alloy, copper-zinc alloy, tin-silver-copper alloy, etc.
  • the filling material 103 can be made of different materials on the same product according to different needs.
  • the curing agent is a substance used to promote or control the curing reaction, such as anhydride-type substances, polythiol, phenolic-type substances, polyamines, etc.
  • Accelerators are substances used to improve reaction efficiency, such as imidazole, DMP-30 (i.e., 2, 4, 6-tris (dimethylaminomethyl) phenol, with a molecular formula of C 15 H 27 N 3 O), N, N-dimethylbenzylamine, etc.
  • the proportions between the components of the filling material 103 will affect the high-frequency characteristics of the device to a certain extent. Therefore, in actual production, when designing a flip-chip packaging structure that is partially filled with bottom filling material, the amount, shape and ratio of each filling material 103 are fixed, which facilitates the production of products with a frequency band corresponding to the design.
  • the filling material 103 can cover each solder ball 10, and there is a gap between the filling materials 103 corresponding to adjacent solder balls 10.
  • the filling material 103 can protect each solder ball 10, reduce the risk of the solder ball 10 falling off or breaking, and thus improve the overall reliability of the solder ball 10 located between the chip 101 and the substrate 100.
  • RC delay refers to the signal delay caused by the charging and discharging process of the capacitor C controlled by the resistor R in the integrated circuit. It is understandable that when the air cavity 105 is not formed, the air between the chip 101 and the substrate 100 can be connected to the external environment. When the air cavity 105 is formed, due to the porosity of the filling material 103 itself, the air between the chip 101 and the substrate 100 can still be connected to the external environment.
  • the difference between the two is that when the air cavity 105 is formed, the peripheral solder balls 10 are surrounded by the filling material 103, so that the forces generated by various collisions, impacts, and extrusions in the outside world are difficult to cause the solder balls 10 to fall off or break, etc., thereby improving the structural strength of the semiconductor packaging structure.
  • the filling material 103 can be filled in a suitable position according to the comprehensive requirements of factors such as dielectric properties, heat dissipation properties, and structural strength.
  • the solder balls 10 in the middle can be directly in contact with the air. Since the solder balls 10 in the middle are not provided with the filling material 103, the solder balls 10 in the middle can achieve high-frequency communication better. Therefore, in some embodiments, the solder balls 10 with higher requirements for high-frequency transmission performance can be arranged in the middle, so that the solder balls 10 in the middle can achieve better high-frequency communication effects.
  • the cross-sectional shape of the filling material 103 may be circular, and the cross-sectional shape of the filling material 103 specifically refers to the projected cross-sectional shape of the filling material 103 on the substrate 100, so that when the semiconductor package structure is in a thermal environment, the thermal mechanical stress of the solder ball 10 can be evenly dispersed to the edge of the filling material 103, reducing the influence of stress concentration on the solder ball 10. It can be understood that in other embodiments, the cross-sectional shape of the filling material 103 may also be other shapes, such as a rectangle or other polygon.
  • FIG. 11 is a schematic flow chart of a flip chip package stacking method provided by another embodiment of the present application. Referring to FIG. 11 , the flip chip package stacking method is described in detail as follows:
  • Step B1 placing a dam of a preset shape on a substrate.
  • Step B2 connecting the chip to the substrate through the solder balls on the chip, the solder balls on the periphery of the chip are located outside the area surrounded by the dam, the solder balls in the middle of the chip are located within the area surrounded by the dam, and there are gaps between the solder balls on the chip.
  • Step B3 filling the filling material into a preset area between the chip and the substrate, where the preset area is the area outside the dam.
  • Step B4 heating and curing the filling material.
  • the dam is removed, and the filling material 103 is solidified to form a third filling body.
  • the filling material 103 with good fluidity when used for filling, the filling material 103 will fill the area outside the dam 106 to form an air cavity 105 .
  • the specific description of the substrate 100, the filling material 103 and the solder ball 10 in the flip chip packaging stacking method shown in Figure 11 can refer to the specific description of the substrate 100, the filling material 103 and the solder ball 10 in the flip chip packaging stacking method shown in Figure 1. The contents of the two are the same and will not be repeated here.
  • FIG. 13 is a schematic flow chart of a flip chip package stacking method provided by another embodiment of the present application. Referring to FIG. 13 , the flip chip package stacking method is described in detail as follows:
  • Step C1 welding solder joints for bonding with solder balls at preset positions of the substrate.
  • Step C2 uniformly coating a filling material around at least a portion of the solder balls on the chip and around at least a portion of the solder joints on the substrate.
  • a filling material 103 is uniformly applied around at least some of the solder balls 10 on the chip 101 and around at least some of the solder joints 20 on the substrate 100.
  • the at least some of the solder balls 10 may be a part of the number of solder balls 10 or all of the number of solder balls 10; the at least some of the solder joints 20 may be a part of the number of solder joints 20 or all of the number of solder joints 20.
  • all solder balls 10 on the chip 101 and all solder joints 20 on the substrate 100 are uniformly coated with the filling material 103 .
  • the outermost solder balls 10 on the chip 101 and the outermost solder joints 20 on the substrate 100 are uniformly coated with the filling material 103, and the solder balls 10 in the middle of the chip 101 and the solder joints 20 in the middle of the substrate 100 are not coated with the filling material 103.
  • the flip chip packaging stacking method further includes: filling the filling material 103 in the preset area 104 between the chip 101 and the substrate 100, so that an air cavity 105 is formed in the middle between the chip 101 and the substrate 100, and the preset area 104 is the area between the outermost solder ball 10 and the boundary of the chip 101.
  • the filling material 103 forms a fourth filling body in the preset area 104.
  • Step C3 bonding the solder joints and solder balls, so that at least a portion of the solder balls are covered by the filling material, and there are spaces between the solder balls covered by the filling material.
  • the solder joint 20 and the solder ball 10 are bonded to obtain the structure shown in the lower figure in FIG14 .
  • the filling material 103 fills the gap between the solder ball 10 and the filling material 103 , so that the filling material 103 and the solder ball 10 fit tightly.
  • the filling material 103 forms a plurality of fifth filling bodies around the plurality of solder balls 10 .
  • Step C4 heating and curing the filling material.
  • the thickness of the filling material 103 of the solder ball 10 decreases uniformly from the periphery to the middle of the chip 101 , and the thickness of the filling material 103 around the solder joint 20 on the substrate 100 is the same as the thickness of the filling material 103 of the corresponding solder ball 10 .
  • the thickness of the filling material 103 of the solder ball 10 located at the periphery of the chip 101 is greater than the thickness of the filling material 103 of the solder ball 10 located in the middle of the chip 101, and the thickness of the filling material 103 around the solder joint 20 on the substrate 100 is the same as the thickness of the filling material 103 of the corresponding solder ball 10.
  • the specific description of the substrate 100, the filling material 103 and the solder ball 10 in the flip chip packaging stacking method shown in Figure 13 can refer to the specific description of the substrate 100, the filling material 103 and the solder ball 10 in the flip chip packaging stacking method shown in Figure 1. The contents of the two are the same and will not be repeated here.
  • the above-mentioned flip chip packaging stacking method not only improves the reliability of the semiconductor packaging structure, but also improves the electrical performance of the high-frequency signal of the semiconductor packaging structure, meets the stringent requirements of the semiconductor packaging structure under different environments, achieves a balance between reliability and electrical performance, and enables the semiconductor packaging structure to better withstand the test of use in actual production and life.
  • an embodiment of the present application further provides a flip chip package stacking structure, including: a substrate 100 , a chip 101 and a plurality of solder balls 10 .
  • the substrate 100 and the chip 101 are stacked.
  • a plurality of solder balls 10 are distributed in an array between the substrate 100 and the chip 101.
  • the chip 101 is electrically connected to the substrate 100 through the solder balls 10.
  • At least some of the plurality of solder balls 10 are coated with a filling material 103, and there are intervals between the solder balls 10 coated with the filling material 103.
  • all solder balls 10 among the plurality of solder balls 10 are covered by the filling material 103 .
  • peripheral solder balls 10 among the plurality of solder balls 10 are covered by the filling material 103 .
  • a preset area 104 between the chip 101 and the substrate 100 is filled with a filling material 103 so that an air cavity 105 is formed in the middle between the chip 101 and the substrate 100 , and the preset area 104 is the area between the outermost solder ball 10 and the boundary of the chip 101 .
  • the thickness of the filling material 103 is less than or equal to half of the difference between the distance between the centers of two adjacent solder balls and the diameter of the solder balls.
  • the thickness of the filling material 103 is W
  • the distance between the centers of two adjacent solder balls 10, namely O 1 and O 2 is O 1 O 2
  • the diameter of the solder ball is D, that is, .
  • the thickness W of the filling material 103 the larger the gap between adjacent filling materials 103, that is, the larger the air circulation space, which can improve the signal transmission performance of the solder ball 10.
  • the smaller the thickness W of the filling material 103 the smaller the protective effect on the solder ball 10.
  • the thickness W of the filling material 103 can be appropriately adjusted according to the specific application scenario of the semiconductor packaging structure, so that the use effect of the semiconductor packaging structure is better.
  • the filling material 103 completely covers the solder ball 10, or as shown in Figures 20 and 21, according to the needs of actual production and life, the filling material 103 covers part of the surface of the solder ball 10, thereby improving the reliability of the semiconductor packaging structure and the electrical performance of the high-frequency signal of the semiconductor packaging structure.
  • the filling material 103 coated around the solder ball 10 may be partially coated on the surface in some cases.
  • the solder ball 10 is located in the middle of the chip 101; and in the coating situation shown in FIG. 21 , the solder ball 10 is located at the outermost periphery of the chip 101, and the portion of the solder ball 10 not coated with the filling material 103 is away from the edge of the chip 101.
  • the filling material 103 and the solder ball 10 fit tightly together without any gaps.
  • the filling material 103 will fill the small space between the filling material 103 and the solder ball 10, so that the filling material 103 and the solder ball 10 fit tightly together.
  • the three methods mentioned above only obtain a packaging structure with a layer of substrate 100 and a layer of chip 101.
  • a packaging structure with multiple layers of chips 101 stacked on a layer of substrate 100 can be obtained according to any one of the three methods mentioned above, that is, the bottom layer is the substrate 100, and the upper layer of the substrate 100 is the multiple layers of stacked chips 101.
  • the packaging structure includes a bottom substrate 100, a middle chip 101, and a top chip 1011.
  • the top chip 1011 can also be connected to the middle chip 101 using any one of the above three methods on the middle chip 101, that is, the substrate 100 in the above three methods is replaced by the middle chip 101, and the chip 101 in the above three methods is replaced by the top chip 1011.
  • steps B1 to B4 are generally selected to connect the top chip 1011 to the middle chip 101.
  • any one of the above three methods can also be referred to.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本申请适用于半导体技术领域，提供了一种倒装芯片封装堆叠方法，该方法包括：将填充模板放置于基板上，填充模板上设置有预设图案的通孔；将填充材料填充至填充模板的通孔中，当填充材料成型后，取下填充模板；将带有焊球的芯片放置到成型好填充材料的基板上，使焊球中的至少部分焊球被填充材料包覆；将芯片与基板通过焊球连接并固化填充材料，且被包覆填充材料的焊球之间具有间隔。本申请有利于实现在提高半导体封装结构的可靠性的同时，提高半导体封装结构的高频信号的电气性能。

Description

一种倒装芯片封装堆叠方法
本专利申请要求于2022年11月24日提交的中国专利申请No.CN202211478794.3的优先权。在先申请的公开内容通过整体引用并入本申请。
技术领域
本申请属于半导体技术领域，尤其涉及一种倒装芯片封装堆叠方法。
 背景技术
倒装芯片是在芯片上植球，然后将芯片翻转，通过表面安装技术放置于基板上，利用加热过程熔融焊球，使芯片与基板形成互连的封装技术，有利于实现芯片的高密度封装。由于焊球的材料、芯片的材料与基板的材料存在特性差异，产品服役过程中，焊球处会产生较大的热机械应力，导致封装的可靠性较低，因此，通常会在焊球和基板之间的空隙中填充底部填充料，用于提高焊球的疲劳寿命和可靠性。
然而，一些特殊应用场合，如具有高频通讯要求的器件，在采用倒装芯片技术对半导体结构进行封装时，存在在填充底部填充料，即提高半导体封装结构的可靠性的同时，会降低半导体封装结构的电性能的问题。
 技术问题
本申请实施例提供了一种倒装芯片封装堆叠方法，以同时提高半导体封装结构的可靠性和半导体封装结构的高频信号的电气性能，解决在填充底部填充料时会降低半导体封装结构的电性能的问题。
 技术解决方案
本申请是通过如下技术方案实现的：
第一方面，本申请实施例提供了一种倒装芯片封装堆叠方法，包括：将填充模板放置于基板上，填充模板上设置有预设图案的通孔；将填充材料填充至填充模板的通孔中，当填充材料成型后，取下填充模板；将带有焊球的芯片放置到成型好填充材料的基板上，使焊球中的至少部分焊球被填充材料包覆；将芯片与基板通过焊球连接并固化填充材料，且被包覆填充材料的焊球之间具有间隔。
结合第一方面，在一些可能的实现方式中，芯片上的所有焊球均被填充材料包覆；由芯片的外围到中部，焊球的填充材料的厚度均匀变小。
结合第一方面，在一些可能的实现方式中，位于芯片外围的焊球的填充材料的厚度，大于位于芯片中部的焊球的填充材料的厚度。
结合第一方面，在一些可能的实现方式中，芯片上外围的焊球被填充材料包覆，芯片上中部的焊球不被填充材料包覆。
结合第一方面，在一些可能的实现方式中，在芯片与基板通过焊球完成连接之后，倒装芯片封装堆叠方法还包括：对芯片和基板之间的预设区域填充填充材料，使芯片和基板之间的中部形成空气腔体，预设区域为最外围的焊球与芯片的边界之间的区域。
结合第一方面，在一些可能的实现方式中，填充材料的厚度小于等于两相邻焊球球心之间的距离与焊球直径差值的一半。
结合第一方面，在一些可能的实现方式中，填充材料和焊球紧密贴合无缝隙。
结合第一方面，在一些可能的实现方式中，填充材料为包括环氧树脂基体与固化剂、促进剂的聚合物复合材料。
第二方面，本申请实施例提供了一种倒装芯片封装堆叠方法，包括：将预设形状的堤坝放置于基板上；将芯片与基板通过芯片上的焊球连接，芯片上外围的焊球位于堤坝围成的区域之外，芯片上中部的焊球位于堤坝围成的区域之内，芯片上的各个焊球之间具有间隔；将填充材料填充到芯片和基板之间的预设区域，预设区域为堤坝外部的区域；加热固化填充材料。
结合第二方面，在一些可能的实现方式中，填充材料为包括环氧树脂基体与固化剂、促进剂的聚合物复合材料。
第三方面，本申请实施例提供了一种倒装芯片封装堆叠方法，包括：在基板的预设位置焊接用于与焊球键合的焊点；在芯片上的至少部分焊球周围和基板上的至少部分焊点周围均匀涂敷填充材料；将焊点和焊球键合，使得至少部分焊球被填充材料包覆，且被包覆填充材料的焊球之间具有间隔；加热固化填充材料；在加热固化填充材料之后，倒装芯片封装堆叠方法，还包括：对芯片和基板之间的预设区域填充填充材料，使芯片和基板之间的中部形成空气腔体，预设区域为最外围的焊球与芯片的边界之间的区域。
结合第三方面，在一些可能的实现方式中，芯片上的所有焊球以及基板上的所有焊点均匀涂敷填充材料。
结合第三方面，在一些可能的实现方式中，芯片上的最外围的焊球和基板上的最外围的焊点均匀涂敷填充材料，芯片上中部的焊球和基板上中部的焊点不涂敷填充材料。
结合第三方面，在一些可能的实现方式中，由芯片的外围到中部，焊球的填充材料的厚度均匀变小，基板上焊点周围的填充材料的厚度与对应焊球的填充材料的厚度相同。
结合第三方面，在一些可能的实现方式中，位于芯片外围的焊球的填充材料的厚度，大于位于芯片中部的焊球的填充材料的厚度，基板上焊点周围的填充材料的厚度与对应焊球的填充材料的厚度相同。
结合第三方面，在一些可能的实现方式中，所述填充材料的厚度小于等于两相邻焊球球心之间的距离与焊球直径差值的一半。
结合第三方面，在一些可能的实现方式中，所述填充材料为包括环氧树脂基体与固化剂、促进剂的聚合物复合材料。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本说明书。
 有益效果
第一方面的有益效果为：通过填充模板为焊球包覆填充填充材料，使焊球中的至少部分焊球被填充材料包覆，焊球四周被填充材料包覆使得空气得以流通，提高了中部焊球的散热性，至少部分焊球被填充材料包覆和填充材料厚度的设置均在提高半导体封装结构的可靠性的同时，提高了半导体封装结构的高频信号的电气性能。
第二方面的有益效果为：通过预设形状的堤坝，使得填充材料只能填充在堤坝外部，提高了半导体封装结构的可靠性；在中部形成了空气腔体，空气腔体的存在提高了半导体封装结构的高频信号的电气性能。
第三方面的有益效果为：在基板上的至少部分焊点和芯片上的至少部分焊球周围均涂敷填充材料，再通过键合的方式连接焊球和焊点的方式，使得中部焊球周围的空气得以流通，提高了中部焊球的散热性，在提高半导体封装结构的可靠性的同时，提高了半导体封装结构的高频信号的电气性能。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例提供的一种倒装芯片封装堆叠方法的流程示意图；
图2是本申请一实施例提供的一种倒装芯片封装堆叠方法的部分步骤示意图；
图3是本申请一实施例提供的一种倒装芯片封装堆叠方法的部分步骤示意图；
图4是本申请一实施例提供的一种倒装芯片封装堆叠方法的部分步骤示意图；
图5是本申请一实施例提供的芯片正面焊球包覆状态的示意图；
图6是本申请另一实施例提供的芯片正面焊球包覆状态的示意图；
图7是本申请另一实施例提供的芯片正面焊球包覆状态的示意图；
图8是本申请另一实施例提供的芯片正面焊球包覆状态的示意图；
图9是本申请另一实施例提供的芯片正面焊球包覆状态的示意图；
图10是本申请另一实施例提供的芯片正面焊球包覆状态的示意图；
图11是本申请另一实施例提供的一种倒装芯片封装堆叠方法的流程示意图；
图12是本申请另一实施例提供的芯片正面焊球包覆状态的示意图；
图13是本申请另一实施例提供的一种倒装芯片封装堆叠方法的流程示意图；
图14是本申请另一实施例提供的一种倒装芯片封装堆叠方法的步骤示意图；
图15是本申请另一实施例提供的芯片正面焊球包覆状态和基板上焊点包覆状态的示意图；
图16是本申请另一实施例提供的芯片正面焊球包覆状态和基板上焊点包覆状态的示意图；
图17是本申请另一实施例提供的芯片正面焊球包覆状态和基板上焊点包覆状态的示意图；
图18是本申请另一实施例提供的芯片正面焊球包覆状态和基板上焊点包覆状态的示意图；
图19是本申请一实施例提供的两相邻焊球之间填充材料厚度示意图；
图20是本申请一实施例提供的焊球包覆的示意图；
图21是本申请另一实施例提供的焊球包覆的示意图；
图22是本申请另一实施例提供的多层封装堆叠结构示意图。
 本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
应当理解，当在本申请说明书和所附权利要求书中使用时，术语“包括”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本申请说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
另外，在本申请说明书和所附权利要求书的描述中，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。“多个”指的是两个及以上数量，“若干个”指的是一个及以上数量。
图1是本申请一实施例提供的倒装芯片封装堆叠方法的示意性流程图，参照图1，对该倒装芯片封装堆叠方法的详述如下：
步骤A1，将填充模板放置于基板上，填充模板上设置有预设图案的通孔。
如图2所示，填充模板201上设置有预设图案的通孔202，通孔202的截面形状根据需要设定。将填充模板201放置于基板100上，也就是说，使填充模板201与基板100呈现出层叠的姿态。
步骤A2，将填充材料填充至填充模板的通孔中，当填充材料成型后，取下填充模板。
如图3中的上图所示，将填充材料103填充至填充模板201的通孔202中；当填充材料103成型后，取下填充模板201，如图3中的下图所示，得到带有填充材料103的基板100。
步骤A3，将带有焊球的芯片放置到成型好填充材料的基板上，使焊球中的至少部分焊球被填充材料包覆。
如图4中的上图所示，将带有焊球10的芯片101放置到带有填充材料103的基板100上，如图4中的下图所示，得到放置好的芯片101和基板100，也就是说，使芯片101和基板100呈现出层叠的姿态。此时填充材料103与焊球10之间还有空隙，使用回流焊工艺焊接基板100和焊球10时，填充材料103将会和焊球10紧密贴合。如图4所示，焊球10的数量为多个，填充材料103形成多个第一填充体，焊球10与填充材料103的对应关系是一个焊球10被一个第一填充体包围，其中，一种情况下，每个焊球10均被配置有第一填充体，另一种情况下，部分数量的焊球10被配置有第一填充体。
示例性的，在一些可能的实现方式中，如图5所示，芯片101上的所有焊球10均被填充材料103包覆。也就是说，每个焊球10均被填充材料103所形成的第一填充体包围。
示例性的，在一些可能的实现方式中，如图6所示，由芯片101的外围到中部，焊球10的填充材料103的厚度均匀变小。可以理解的是，每若干圈的焊球10的填充材料103的厚度可以由外向内逐渐减小，即，存在相邻两圈或更多圈的焊球10的填充材料103的厚度不变的情况。
可以理解的是，芯片101的所有焊球10可以是阵列式排列，也可以是自中心向外呈圆周式排列，基于此，最外围的焊球10指的是最外圈的多个焊球10，最中部的焊球10指的是最内圈的一个焊球10或者多个焊球10，且最外围的焊球10的数量大于最中部的焊球10的数量。由于所有焊球10排列成多圈形状，因此，当本文中提到外围时，外围指的是由外向内的一圈或多圈，但并非是最内圈；当本文中提到中部时，中部指的是由内向外的一圈或多圈，但并非是最外圈。在此解释之后，本文出现“最外围”、“外围”和“中部”时，均沿用此处的解释。
示例性的，在一些可能的实现方式中，如图7所示，位于芯片101外围的焊球10的填充材料103的厚度，大于位于芯片101中部的焊球10的填充材料103的厚度。可以理解的是，本实现方式中，外围的相邻两圈或更多圈的焊球10的填充材料103的厚度可以为恒定值，中部的相邻两圈或更多圈的焊球10的填充材料103的厚度也可以为恒定值，从外围向中部，外圈的焊球10的填充材料103的厚度大于中部的焊球10的填充材料103的厚度。
示例性的，在一些可能的实现方式中，如图8所示，芯片101上外围的焊球10被填充材料103包覆，中部的焊球10不被填充材料103包覆。
步骤A4，将芯片与基板通过焊球连接并固化填充材料，且被包覆填充材料的焊球之间具有间隔。
示例性的，如图9和图10所示，在芯片101与基板100通过焊球10完成连接之后，上述倒装芯片封装堆叠方法还包括：
对芯片101和基板100之间的预设区域104填充填充材料103，使芯片101和基板100之间的中部形成空气腔体105，预设区域104为最外围的焊球10与芯片101的边界之间的区域。如此使得填充材料103在预设区域104形成第二填充体。
可选的，上述基板100可以是硬质封装基板，如聚合物基板、金属基板、复合基板或者陶瓷基板中的任一种。在另一些实施例中，基板100也可以是柔性封装基板，柔性封装基板的材料可以是PI（聚酰亚胺）树脂或者PE（聚酯）树脂中的任一者。
可选的，填充材料103能够把焊球10所承受的热机械应力分散到填充材料103的表面，从而降低了集中在焊球10上的热机械应力，同时为焊球10提供了额外的保护，从而增加了焊球10的可靠性。
具体的，在一些实施例中，填充材料103的材料可以为环氧树脂基体混合增强颗粒（颗粒材料为二氧化硅、氧化铝等）、固化剂、促进剂等其他添加剂组成的聚合物复合材料；焊球10的材料可以为锡铅合金、铜锌合金、锡银铜合金等，除此之外，填充材料103可以根据不同的需求，在同一产品上使用不同材质的填充材料103。其中，固化剂是用于增进或控制固化反应的物质，例如，酸酐型物质、聚硫醇、酚醛型物质、多胺类等。促进剂是用于提高反应效率的物质，例如，咪唑、DMP-30（即2, 4, 6-三(二甲胺基甲基)苯酚，分子式为C 15H 27N 3O）、N,N-二甲基苄胺等。
具体的，填充材料103的组成成分之间的占比会在一定程度上影响器件的高频特性，所以在实际生产中，在设计部分填充底部填充料的倒装芯片封装结构的同时，每一种填充材料103的多少、形状以及各成分之间的配比就已经固定，便于生产得到与设计相对应的频段的产品。
具体的，填充材料103可以包覆每一个焊球10，且相邻的焊球10对应的填充材料103之间具有间隔。通过设置填充材料103包覆每一个焊球10，可以使得填充材料103对每一个焊球10进行保护，降低焊球10脱落或断裂的风险，从而可以改善位于芯片101与基板100之间的焊球10的整体可靠性。同时，位于相邻的焊球10的填充材料103之间留有一定的空气间隙，即相邻的焊球10的填充材料103之间不存在连续的填充材料103，使得芯片101与基板100之间的空气与外界环境相连通，不仅可以降低每一个焊球10在传输信号时的RC延迟，即对每一个焊球10传输信号的性能进行改善，从而可以满足所有焊球10都需要进行高频通信的通信需求，同时，还有利于半导体封装结构整体在热环境下运行时的热量散发，具有良好的散热性。其中，RC延迟指的是集成电路中由电阻R控制电容C充放电过程引起的信号延迟。可以理解的是，在没有形成空气腔体105时，芯片101与基板100之间的空气与外界环境可以连通，在形成空气腔体105时，由于填充材料103本身存在的孔隙问题，芯片101与基板100之间的空气依然可以与外界环境连通，二者的区别在于，当形成有空气腔体105时，由于外围的焊球10被填充材料103包围，使得外界各种碰撞、冲击、挤压等产生的力难以使焊球10脱落或断裂等，提高了半导体封装结构的结构强度。在实际生产中，可以根据介电性能、散热性能、结构强度等因素的综合要求，在合适的位置填充填充材料103。
具体的，对于具有较低失效风险的中部的焊球10而言，可以使焊球10直接与空气相接触。由于位于中部的焊球10不设置填充材料103，可以使得位于中部的焊球10可以较好的实现高频通信，因此，在一些实施例中，可以将对高频传输性能要求较高的焊球10设置在中部，从而使得中部的焊球10可以发挥较好的高频通信效果。
具体的，填充材料103的截面形状可以为圆形，填充材料103的截面具体是指填充材料103在基板100上的投影截面，这样使得半导体封装结构处于热环境下时，焊球10的热机械应力可以均匀分散至填充材料103的边缘，降低了应力集中对焊球10的影响。可以理解的是，在另一些实施例中，填充材料103的截面形状也可以为其它形状，例如可以为矩形或者其它多边形。
图11是本申请另一实施例提供的倒装芯片封装堆叠方法的示意性流程图，参照图11，对该倒装芯片封装堆叠方法的详述如下：
步骤B1，将预设形状的堤坝放置于基板上。
步骤B2，将芯片与基板通过芯片上的焊球连接，芯片上外围的焊球位于堤坝围成的区域之外，芯片上中部的焊球位于堤坝围成的区域之内，芯片上的各个焊球之间具有间隔。
步骤B3，将填充材料填充到芯片和基板之间的预设区域，预设区域为堤坝外部的区域。
步骤B4，加热固化填充材料。
可以理解的是，当填充材料103固化之后，取下堤坝，填充材料103固化之后形成第三填充体。
示例性的，如图12所示，因为存在堤坝106，在使用流动性好的填充材料103进行填充时，填充材料103会充满堤坝106外部的区域，形成空气腔体105。
需要说明的是，图11所示的倒装芯片封装堆叠方法中关于基板100、填充材料103和焊球10的具体描述可以参考图1所示的倒装芯片封装堆叠方法中关于基板100、填充材料103和焊球10的具体描述，二者内容相同，在此不再赘述。
图13是本申请另一实施例提供的倒装芯片封装堆叠方法的示意性流程图，参照图13，对该倒装芯片封装堆叠方法的详述如下：
步骤C1，在基板的预设位置焊接用于与焊球键合的焊点。
步骤C2，在芯片上的至少部分焊球周围和基板上的至少部分焊点周围均匀涂敷填充材料。
如图14中的上图所示，芯片101上的至少部分焊球10周围和基板100上的至少部分焊点20周围均匀涂敷填充材料103。其中，至少部分焊球10可以是部分数量的焊球10，也可以是全部数量的焊球10；至少部分焊点20可以是部分数量的焊点20，也可以是全部数量的焊点20。
示例性的，在一些可能的实现方式中，如图15所示，芯片101上的所有焊球10以及基板100上的所有焊点20均匀涂敷填充材料103。
示例性的，在一些可能的实现方式中，如图16所示，芯片101上的最外围的焊球10和基板100上的最外围的焊点20均匀涂敷填充材料103，芯片101上中部的焊球10和基板100上中部的焊点20不涂敷填充材料103。
示例性的，如图17和图18所示，在加热固化填充材料103之后，倒装芯片封装堆叠方法，还包括：对芯片101和基板100之间的预设区域104填充填充材料103，使芯片101和基板100之间的中部形成空气腔体105，预设区域104为最外围的焊球10与芯片101的边界之间的区域。其中，填充材料103在预设区域104形成第四填充体。
步骤C3，将焊点和焊球键合，使得至少部分焊球被填充材料包覆，且被包覆填充材料的焊球之间具有间隔。
如图14中的下图所示，焊点20和焊球10键合，得到如图14中的下图的结构。在键合过程中，填充材料103会将焊球10与填充材料103之间的空隙填满，使填充材料103和焊球10紧紧贴合。其中，填充材料103在若干个焊球10周围对应地形成若干个第五填充体。
步骤C4，加热固化填充材料。
示例性的，在一些可能的实现方式中，由芯片101的外围到中部，焊球10的填充材料103的厚度均匀变小，基板100上焊点20周围的填充材料103的厚度与对应焊球10的填充材料103的厚度相同。
示例性的，在一些可能的实现方式中，位于芯片101外围的焊球10的填充材料103的厚度，大于位于芯片101中部的焊球10的填充材料103的厚度，基板100上焊点20周围的填充材料103的厚度与对应焊球10的填充材料103的厚度相同。
需要说明的是，图13所示的倒装芯片封装堆叠方法中关于基板100、填充材料103和焊球10的具体描述可以参考图1所示的倒装芯片封装堆叠方法中关于基板100、填充材料103和焊球10的具体描述，二者内容相同，在此不再赘述。
上述倒装芯片封装堆叠方法，均在提高半导体封装结构的可靠性的同时，提高了半导体封装结构的高频信号的电气性能，满足了不同环境下对半导体封装结构的苛刻要求，实现了可靠性和电气性能的平衡，使半导体封装结构更能经受住实际生产生活中使用的考验。
结合以上内容，本申请的实施例还提供了一种倒装芯片封装堆叠结构，包括：基板100、芯片101和多个焊球10。
基板100和芯片101为层叠结构。多个焊球10呈阵列分布在基板100和芯片101之间，通过焊球10使得芯片101与基板100电连接，且多个焊球10中的至少部分焊球10被填充材料103包覆，且被包覆填充材料103的焊球10之间具有间隔。
示例性的，在一些可能的实现方式中，多个焊球10中的所有焊球10被填充材料103包覆。
示例性的，在一些可能的实现方式中，多个焊球10中的外围焊球10被填充材料103包覆。
示例性的，在一些可能的实现方式中，芯片101和基板100之间的预设区域104填充有填充材料103，使芯片101和基板100之间的中部形成空气腔体105，预设区域104为最外围的焊球10与芯片101的边界之间的区域。
示例性的，在一些可能的实现方式中，填充材料103的厚度小于等于两相邻焊球球心之间的距离与焊球直径差值的一半。
具体的，如图19所示，填充材料103的厚度为W，两相邻焊球10球心即O 1和O 2之间的距离为O 1O 2，焊球直径为D，即 。
具体的，填充材料103的厚度W越小，则相邻填充材料103之间的间隙越大，即空气流通空间较大，可以提高焊球10的信号传输性能。填充材料103的厚度W越小，对焊球10的保护效果也随之对应的减小，在实际生产生活中，可以根据半导体封装结构的具体应用场景对填充材料103的厚度W进行适当的调整，以便半导体封装结构的使用效果更好。
示例性的，在一些可能的实现方式中，填充材料103全包覆焊球10，或者如图20和图21所示，根据实际生产生活的需要，填充材料103包覆焊球10的部分表面，同时提高半导体封装结构的可靠性和半导体封装结构的高频信号的电气性能。
示例性的，在一些可能的实现方式中，如图20和图21所示，包覆在焊球10周围的填充材料103在某些情况下可以进行部分表面包覆，如图20所示的包覆情况，该焊球10位于芯片101的中部；如图21所示的包覆情况，该焊球10位于芯片101的最外围，焊球10上未包覆填充材料103的部分远离芯片101的边缘。
示例性的，在一些可能的实现方式中，填充材料103和焊球10紧密贴合无缝隙，在实际生产过程中，在填充材料103的加热固化过程中，填充材料103会将填充材料103与焊球10之间的细小间隔填满，使得填充材料103和焊球10紧密贴合。
示例性的，上述的三种方法得到的仅为一层基板100和一层芯片101的封装结构，在实际的生产生活中，可以根据上述三种方法中的任意一种方法得到多层的芯片101与一层基板100层叠的封装结构，即最下层为基板100，基板100的上层为多层层叠的芯片101。
具体的，如图22所示，封装结构包括底层的基板100、中间层的芯片101和顶层的芯片1011，中间层的芯片101在使用上述三种方法中的任意一种方法与底层的基板100连接以后，还可以在中间层的芯片101上同样使用上述三种方法中的任意一种方法将顶层的芯片1011与中间层的芯片101连接，也就是将上述三种方法中的基板100用中间层的芯片101替代，上述三种方法中的芯片101用顶层的芯片1011替代，但在实际生产中考虑实现的难易程度，一般选择B1至B4的步骤将顶层的芯片1011与中间层的芯片101连接。当芯片101的数量更多时，同样可以参考上述三种方法中的任意一种。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种倒装芯片封装堆叠方法，其特征在于，包括：
    将填充模板放置于基板上，所述填充模板上设置有预设图案的通孔；
    将填充材料填充至所述填充模板的通孔中，当所述填充材料成型后，取下所述填充模板；
    将带有焊球的芯片放置到成型好所述填充材料的所述基板上，使所述焊球中的至少部分焊球被所述填充材料包覆；
    将所述芯片与所述基板通过所述焊球连接并固化所述填充材料，且被包覆所述填充材料的焊球之间具有间隔。
  2. 如权利要求1所述的倒装芯片封装堆叠方法，其特征在于，所述芯片上的所有焊球均被所述填充材料包覆；由所述芯片的外围到中部，所述焊球的填充材料的厚度均匀变小。
  3. 如权利要求2所述的倒装芯片封装堆叠方法，其特征在于，位于所述芯片外围的焊球的填充材料的厚度，大于位于所述芯片中部的焊球的填充材料的厚度。
  4. 如权利要求1所述的倒装芯片封装堆叠方法，其特征在于，所述芯片上外围的焊球被所述填充材料包覆，所述芯片上中部的焊球不被所述填充材料包覆。
  5. 如权利要求1至4任一项所述的倒装芯片封装堆叠方法，其特征在于，在所述芯片与所述基板通过焊球完成连接之后，所述倒装芯片封装堆叠方法还包括：
    对所述芯片和所述基板之间的预设区域填充所述填充材料，使所述芯片和所述基板之间的中部形成空气腔体，所述预设区域为最外围的焊球与所述芯片的边界之间的区域。
  6. 如权利要求1所述的倒装芯片封装堆叠方法，其特征在于，所述填充材料的厚度小于等于两相邻焊球球心之间的距离与焊球直径差值的一半。
  7. 如权利要求1所述的倒装芯片封装堆叠方法，其特征在于，所述填充材料为包括环氧树脂基体与固化剂、促进剂的聚合物复合材料。
  8. 一种倒装芯片封装堆叠方法，其特征在于，包括：
    将预设形状的堤坝放置于基板上；
    将芯片与所述基板通过所述芯片上的焊球连接，所述芯片上外围的焊球位于所述堤坝围成的区域之外，所述芯片上中部的焊球位于所述堤坝围成的区域之内，所述芯片上的各个焊球之间具有间隔；
    将填充材料填充到所述芯片和所述基板之间的预设区域，所述预设区域为所述堤坝外部的区域；
    加热固化所述填充材料。
  9. 如权利要求8所述的倒装芯片封装堆叠方法，其特征在于，所述填充材料为包括环氧树脂基体与固化剂、促进剂的聚合物复合材料。
  10. 一种倒装芯片封装堆叠方法，其特征在于，包括：
    在基板的预设位置焊接用于与焊球键合的焊点；
    在芯片上的至少部分焊球周围和所述基板上的至少部分焊点周围均匀涂敷填充材料；
    将所述焊点和所述焊球键合，使得所述至少部分焊球被所述填充材料包覆，且被包覆所述填充材料的焊球之间具有间隔；
    加热固化所述填充材料；在所述加热固化所述填充材料之后，所述倒装芯片封装堆叠方法，还包括：
    对所述芯片和所述基板之间的预设区域填充所述填充材料，使所述芯片和所述基板之间的中部形成空气腔体，所述预设区域为最外围的焊球与所述芯片的边界之间的区域。
  11. 如权利要求10所述的倒装芯片封装堆叠方法，其特征在于，所述芯片上的所有焊球以及所述基板上的所有焊点均匀涂敷所述填充材料。
  12. 如权利要求10所述的倒装芯片封装堆叠方法，其特征在于，所述芯片上的最外围的焊球和所述基板上的最外围的焊点均匀涂敷填充材料，所述芯片上中部的焊球和所述基板上中部的焊点不涂敷所述填充材料。
  13. 如权利要求10所述的倒装芯片封装堆叠方法，其特征在于，由所述芯片的外围到中部，所述焊球的填充材料的厚度均匀变小，所述基板上焊点周围的填充材料的厚度与对应焊球的填充材料的厚度相同。
  14. 如权利要求13所述的倒装芯片封装堆叠方法，其特征在于，位于所述芯片外围的焊球的填充材料的厚度，大于位于所述芯片中部的焊球的填充材料的厚度，所述基板上焊点周围的填充材料的厚度与对应焊球的填充材料的厚度相同。
  15. 如权利要求10所述的倒装芯片封装堆叠方法，其特征在于，所述填充材料的厚度小于等于两相邻焊球球心之间的距离与焊球直径差值的一半。
  16. 如权利要求10所述的倒装芯片封装堆叠方法，其特征在于，所述填充材料为包括环氧树脂基体与固化剂、促进剂的聚合物复合材料。
PCT/CN2023/103877 2022-11-24 2023-06-29 一种倒装芯片封装堆叠方法 WO2024109050A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211478794.3A CN115579300B (zh) 2022-11-24 2022-11-24 一种倒装芯片封装堆叠方法
CN202211478794.3 2022-11-24

Publications (1)

Publication Number Publication Date
WO2024109050A1 true WO2024109050A1 (zh) 2024-05-30

Family

ID=84590622

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103877 WO2024109050A1 (zh) 2022-11-24 2023-06-29 一种倒装芯片封装堆叠方法

Country Status (2)

Country Link
CN (1) CN115579300B (zh)
WO (1) WO2024109050A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115579300B (zh) * 2022-11-24 2023-03-28 河北北芯半导体科技有限公司 一种倒装芯片封装堆叠方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040169275A1 (en) * 2003-02-27 2004-09-02 Motorola, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
JP2004254068A (ja) * 2003-02-20 2004-09-09 Mitsubishi Electric Corp 高周波送受信モジュール
US20050287705A1 (en) * 2004-06-25 2005-12-29 Advanced Semiconductor Engineering, Inc. Flip chip on leadframe package and method for manufacturing the same
CN101038898A (zh) * 2006-03-18 2007-09-19 新光电气工业株式会社 半导体器件及其制造方法
JP2011061175A (ja) * 2009-09-14 2011-03-24 Samsung Electro-Mechanics Co Ltd 半田ボール及び半導体パッケージ
US8193624B1 (en) * 2008-02-25 2012-06-05 Amkor Technology, Inc. Semiconductor device having improved contact interface reliability and method therefor
US20160086902A1 (en) * 2014-09-24 2016-03-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
CN115513147A (zh) * 2022-11-24 2022-12-23 河北北芯半导体科技有限公司 一种部分填充底填料的倒装芯片封装结构
CN115579300A (zh) * 2022-11-24 2023-01-06 河北北芯半导体科技有限公司 一种倒装芯片封装堆叠方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677228A (ja) * 1992-08-25 1994-03-18 Tanaka Kikinzoku Kogyo Kk 高周波用シールド型バンプ
JP2758115B2 (ja) * 1992-12-28 1998-05-28 ローム株式会社 半導体装置
JP3559013B2 (ja) * 2001-10-16 2004-08-25 株式会社ルネサステクノロジ 半導体装置
JP2003142523A (ja) * 2001-10-31 2003-05-16 Toshiba Corp 電子部品装置およびその製造方法
WO2007015683A1 (en) * 2005-08-04 2007-02-08 Infineon Technologies Ag An integrated circuit package and a method for forming an integrated circuit package
JP2008112835A (ja) * 2006-10-30 2008-05-15 Sony Corp Ｗｌｐ（ウェハレベルパッケージ）およびその製造方法、ｗｌｐを内蔵した電子機器、ならびに気密封止方法
JP4670851B2 (ja) * 2007-09-25 2011-04-13 セイコーエプソン株式会社 モジュールおよび電子機器
JP4943312B2 (ja) * 2007-12-19 2012-05-30 新光電気工業株式会社 導電性ボールの搭載方法及び余剰ボール除去装置
US8451620B2 (en) * 2009-11-30 2013-05-28 Micron Technology, Inc. Package including an underfill material in a portion of an area between the package and a substrate or another package
JP2012027644A (ja) * 2010-07-22 2012-02-09 Toppan Forms Co Ltd 電子回路基板の製造方法及びこれにより製造された電子回路基板
CN110660891A (zh) * 2018-06-29 2020-01-07 合肥彩虹蓝光科技有限公司 一种倒装器件封装方法及结构

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004254068A (ja) * 2003-02-20 2004-09-09 Mitsubishi Electric Corp 高周波送受信モジュール
US20040169275A1 (en) * 2003-02-27 2004-09-02 Motorola, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US20050287705A1 (en) * 2004-06-25 2005-12-29 Advanced Semiconductor Engineering, Inc. Flip chip on leadframe package and method for manufacturing the same
CN101038898A (zh) * 2006-03-18 2007-09-19 新光电气工业株式会社 半导体器件及其制造方法
US8193624B1 (en) * 2008-02-25 2012-06-05 Amkor Technology, Inc. Semiconductor device having improved contact interface reliability and method therefor
JP2011061175A (ja) * 2009-09-14 2011-03-24 Samsung Electro-Mechanics Co Ltd 半田ボール及び半導体パッケージ
US20160086902A1 (en) * 2014-09-24 2016-03-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
CN115513147A (zh) * 2022-11-24 2022-12-23 河北北芯半导体科技有限公司 一种部分填充底填料的倒装芯片封装结构
CN115579300A (zh) * 2022-11-24 2023-01-06 河北北芯半导体科技有限公司 一种倒装芯片封装堆叠方法

Also Published As

Publication number Publication date
CN115579300B (zh) 2023-03-28
CN115579300A (zh) 2023-01-06

Similar Documents

Publication Publication Date Title
US6049122A (en) Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US6756685B2 (en) Semiconductor device
TWI278046B (en) Structure and process for reducing die corner and edge stresses in microelectronic packages
US8324740B2 (en) Semiconductor device, and method of manufacturing multilayer wiring board and semiconductor device
US8022532B2 (en) Interposer and semiconductor device
US7018866B2 (en) Circuit component built-in module with embedded semiconductor chip and method of manufacturing
JP3118187B2 (ja) 再加工可能な電子デバイス及び形成方法
JP2848357B2 (ja) 半導体装置の実装方法およびその実装構造
JP3598060B2 (ja) 回路部品内蔵モジュール及びその製造方法並びに無線装置
CN115513147B (zh) 一种部分填充底填料的倒装芯片封装结构
US20100096747A1 (en) Semiconductor device and method of manufacturing the same
US8378482B2 (en) Wiring board
WO2024109050A1 (zh) 一种倒装芯片封装堆叠方法
US7482200B2 (en) Process for fabricating chip package structure
WO2002103793A1 (fr) Dispositif a semi-conducteurs et procede de fabrication associe
US20050214971A1 (en) Bumping process, bump structure, packaging process and package structure
US20230260891A1 (en) Semiconductor package including an interposer and method of fabricating the same
JPH11186322A (ja) フリップチップ実装用基板及びフリップチップ実装構造
WO2000052739A2 (en) A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material
US20090017582A1 (en) Method for manufacturing semiconductor device
US5895976A (en) Microelectronic assembly including polymeric reinforcement on an integrated circuit die, and method for forming same
US6331446B1 (en) Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US5698904A (en) Packaging material for electronic components
JPH1187424A (ja) 半導体装置およびその製造方法
US20060175702A1 (en) Ball grid array package

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23893150

Country of ref document: EP

Kind code of ref document: A1