WO2024109030A1 - 一种环栅晶体管、其制备方法及电子设备 - Google Patents

一种环栅晶体管、其制备方法及电子设备 Download PDF

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Publication number
WO2024109030A1
WO2024109030A1 PCT/CN2023/102928 CN2023102928W WO2024109030A1 WO 2024109030 A1 WO2024109030 A1 WO 2024109030A1 CN 2023102928 W CN2023102928 W CN 2023102928W WO 2024109030 A1 WO2024109030 A1 WO 2024109030A1
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layer
epitaxial
substrate
doped
doped layer
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PCT/CN2023/102928
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English (en)
French (fr)
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王巍霖
侯朝昭
贝尼斯坦特弗朗西斯•莱昂内尔
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华为技术有限公司
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Publication of WO2024109030A1 publication Critical patent/WO2024109030A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a ring-gate transistor, a preparation method thereof, and an electronic device.
  • CMOS complementary metal oxide semiconductor
  • Gate-all-around (GAA) transistors have better subthreshold swing and better gate control capabilities than Fin FETs, thereby achieving better electrical performance.
  • GAA Gate-all-around
  • substrate parasitic leakage there is a parasitic leakage path from the source to the drain under the stacked channel layer in the GAA transistor, which is called substrate parasitic leakage.
  • Substrate parasitic leakage is one of the main challenges facing GAA transistors. As the channel length of GAA transistors continues to shrink, the problem of substrate parasitic leakage will become more and more serious.
  • the present application provides a GAA transistor, a preparation method thereof, and an electronic device, which are used to reduce the substrate parasitic leakage of the GAA transistor.
  • the present application provides a GAA transistor, which mainly includes a substrate, a fin located on the substrate, a source and a drain located on both sides of the fin, and a gate structure located between the source and the drain and covering the fin.
  • the GAA transistor may also include a first epitaxial doping layer and a second epitaxial doping layer located on both sides of the fin.
  • the first epitaxial doping layer is located between the substrate and the source
  • the second epitaxial doping layer is located between the substrate and the drain.
  • the conductivity type of the doped impurities in the first epitaxial doping layer and the second epitaxial doping layer is the same as the conductivity type of the doped impurities in the substrate, and the conductivity type of the doped impurities in the first epitaxial doping layer and the second epitaxial doping layer is opposite to the conductivity type of the doped impurities in the source and the drain.
  • the conductivity type of the doped impurities in the source and the drain is N-type, then the conductivity type of the doped impurities in the first epitaxial doping layer, the second epitaxial doping layer and the substrate are all P-type; if the conductivity type of the doped impurities in the source and the drain is P-type, then the conductivity type of the doped impurities in the first epitaxial doping layer, the second epitaxial doping layer and the substrate are all N-type.
  • the doping concentrations of the first epitaxial doping layer and the second epitaxial doping layer are both greater than the doping concentration of the substrate.
  • the conductivity type of the doped impurities in the first epitaxial doping layer and the second epitaxial doping layer is opposite to the conductivity type of the doped impurities in the source and the drain
  • the inversely doped first epitaxial doping layer and the second epitaxial doping layer can be used to cut off the substrate leakage channel between the source and the drain.
  • the depletion region formed by the first epitaxial doping layer and the source is confined to the first epitaxial doping layer, and the depletion region formed by the second epitaxial doping layer and the drain is confined to the second epitaxial doping layer, and will not diffuse into the substrate.
  • the depletion region formed by the first epitaxial doping layer and the source is separated from the depletion region formed by the second epitaxial doping layer and the drain in a direction parallel to the substrate, so the substrate leakage can be greatly suppressed.
  • the doping concentration of the first epitaxial doping layer and the second epitaxial doping layer can be maintained at a low level, thereby not causing greater BTBT leakage.
  • the GAA transistor provided in the present application can obtain a better subthreshold swing, and as the channel length continues to shrink, the operating voltage can also be continuously reduced while ensuring the device performance.
  • the fin may include a plurality of channel layers stacked in a direction perpendicular to the substrate;
  • the gate structure may include two sidewalls disposed opposite to each other, a gate oxide layer wrapping each channel layer, and a gate layer filling the gap between the two sidewalls.
  • the channel layer is isolated from the source and the drain, and two internal isolation parts are arranged on the side facing the substrate of each channel layer, and the two internal isolation parts are isolated by the gate layer, wherein one internal isolation part is located between the gate layer and the source, and the other is located between the gate layer and the drain.
  • the doping concentrations of the first epitaxial doping layer and the second epitaxial doping layer can be maintained at a relatively low level.
  • the doping concentration of the first epitaxial doping layer can be set to be less than or equal to 5*10 18 /cm 3
  • the doping concentration of the second epitaxial doping layer can be set to be less than or equal to 5*10 18 /cm 3 .
  • the doping concentration of the first epitaxial doping layer may be controlled to be less than 10 18 /cm 3
  • the doping concentration of the second epitaxial doping layer may be controlled to be less than 10 18 /cm 3 .
  • the present application does not limit the thickness of the first epitaxial doping layer and the second epitaxial doping layer.
  • the thickness of the first epitaxial doping layer can be set to 5-25nm, such as 5nm, 7nm, 10nm, 15nm, 20nm, 25nm, etc.
  • the thickness of the second epitaxial doping layer can be set to 5-25nm, such as 5nm, 7nm, 10nm, 15nm, 20nm, 25nm, etc.
  • the first epitaxial doping layer and the second epitaxial doping layer can be formed simultaneously, so the doping concentrations of the first epitaxial doping layer and the second epitaxial doping layer can be set to be the same, and the thicknesses of the first epitaxial doping layer and the second epitaxial doping layer can be set to be the same.
  • the present application provides a method for preparing a GAA transistor, which may include the following steps: forming an initial fin and a sacrificial gate and two side walls across the initial fin on a substrate; wherein the initial fin includes a sacrificial layer and a channel layer that are stacked and alternately arranged, and the two side walls are respectively located on both sides of the sacrificial gate; then removing the initial fin exposed on the outside of the two side walls, and forming an internal isolation portion on both sides of each sacrificial layer, and the internal isolation portion is located below the side wall; then epitaxially growing a first epitaxial doping layer and a second epitaxial doping layer on the substrate, and the first epitaxial doping layer and the second epitaxial doping layer are respectively located on the outside of the internal isolation portion; epitaxially growing a source in a region corresponding to the first epitaxial doping layer, and epitaxially growing a drain in a region corresponding to the second epit
  • the conductivity type of the doped impurities in the first epitaxial doped layer and the second epitaxial doped layer is the same as the conductivity type of the doped impurities in the substrate, and is opposite to the conductivity type of the doped impurities in the source and the drain, and the doping concentration of the first epitaxial doped layer and the second epitaxial doped layer is greater than the doping concentration of the substrate.
  • the first epitaxial doped layer and the second epitaxial doped layer can be epitaxially grown on the substrate in the following manner: at least the first doped layer and the second doped layer are epitaxially grown on the substrate; and then the first doped layer and the second doped layer are etched to remove the first doped layer and the second doped layer located on the side walls of the channel layer, thereby forming the first epitaxial doped layer and the second epitaxial doped layer.
  • the first doped layer and the second doped layer are epitaxially grown on the substrate at least multiple times; after each epitaxial growth of the first doped layer and the second doped layer, the first doped layer and the second doped layer are etched to remove the first doped layer and the second doped layer located on the side walls of the channel layer; until the first doped layer and the second doped layer are etched for the last time, the first epitaxial doped layer and the second epitaxial doped layer can be formed.
  • a feasible implementation method is to make the growth rate of the first doping layer and the second doping layer in the direction perpendicular to the substrate greater than the growth rate in the direction parallel to the substrate when epitaxially growing the first doping layer and the second doping layer. That is, the thickness of the first doping layer and the second doping layer in the direction perpendicular to the substrate is greater than the thickness in the direction parallel to the substrate.
  • a growth rate of the first doping layer and the second doping layer in a direction perpendicular to the substrate is 20% greater than a growth rate in a direction parallel to the substrate.
  • the etching rate in the direction parallel to the substrate is greater than the etching rate in the direction perpendicular to the substrate. In this way, when etching is performed, it can be ensured that when the first doped layer and the second doped layer on the sidewalls of the channel layer are completely etched, there are still the first doped layer and the second doped layer of a certain thickness on the substrate.
  • the etching rate in the direction parallel to the substrate is 2 times greater than the etching rate in the direction perpendicular to the substrate.
  • the etching rate in the direction parallel to the substrate is 3 times, 4 times, or 5 times the etching rate in the direction perpendicular to the substrate.
  • the sidewalls of the channel layer do not have the first doped layer and the second doped layer.
  • the growth rate of the first doped layer and the second doped layer in a direction perpendicular to the substrate is greater than the growth rate in a direction parallel to the substrate.
  • the etching rate in a direction parallel to the substrate is greater than the etching rate in a direction perpendicular to the substrate.
  • an isolation portion may be first formed on the side wall of the channel layer, and then the first epitaxial doping layer and the second epitaxial doping layer are epitaxially grown. After the first epitaxial doping layer and the second epitaxial doping layer are formed, the isolation portion on the side wall of the channel layer is removed.
  • forming an internal isolation portion on both sides of each sacrificial layer and epitaxially growing a first epitaxial doped layer and a second epitaxial doped layer on a substrate may include: removing the sacrificial layer under the two side walls; forming an internal isolation portion on both sides of each sacrificial layer and on both sides of each channel layer; epitaxially growing a first epitaxial doped layer and a second epitaxial doped layer on the substrate, and the first epitaxial doped layer and the second epitaxial doped layer are respectively located on the outside of the internal isolation portion; removing the internal isolation portion located on the outside of each channel layer, and retaining the internal isolation portion located on both sides of each sacrificial layer.
  • the GAA transistor provided in the embodiment of the present application on the basis of the traditional GAA transistor, epitaxially grows a first epitaxial doping layer and a second epitaxial doping layer between the substrate and the source and drain to cut off the substrate leakage channel between the source and the drain.
  • the present application can be integrated into the traditional GAA device process steps in two feasible ways, and the doping concentration of the first epitaxial doping layer and the second epitaxial doping layer can be maintained below 10 18 /cm 3 , which can suppress the substrate parasitic leakage while limiting the BTBT leakage.
  • the present application provides an electronic device, the electronic device comprising a circuit board, and a GAA transistor as described in the first aspect or various embodiments of the first aspect disposed on the circuit board. Since the principle of solving the problem by the electronic device is similar to that of the aforementioned GAA transistor, the implementation of the electronic device can refer to the implementation of the aforementioned GAA transistor, and the repeated parts will not be repeated.
  • FIG1 is a schematic diagram of a cross-sectional structure of a conventional GAA transistor
  • FIG2 is a schematic cross-sectional structure diagram of a GAA transistor provided by the related art
  • FIG3 is a schematic diagram of the structure of a GAA transistor provided in an embodiment of the present application.
  • FIG4 is a flow chart of a method for preparing a GAA transistor provided in one embodiment of the present application.
  • 5a to 5e are partial structural schematic diagrams of a manufacturing process of a GAA transistor in an embodiment of the present application.
  • FIG6 is a schematic diagram of simulation results using TCAD in one embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • the GAA transistor provided in the embodiment of the present application can be widely used in various scenarios as a component of an electronic device.
  • the electronic device can be a logic device, a processor, etc.
  • the GAA transistor proposed in the embodiment of the present application is intended to include but is not limited to application in these and any other suitable types of electronic devices.
  • FIG. 1 is a schematic diagram of the structure of a conventional GAA transistor.
  • the GAA transistor 1 mainly includes a substrate 01, a fin 02 located on the substrate 01, a source and a drain located on both sides of the fin 02, and a gate structure 06 located between the source and the drain and covering the fin 02.
  • the fin 02 includes a plurality of channel layers 021 stacked at intervals in a direction perpendicular to the substrate 01.
  • the gate structure 06 includes: two sidewalls 061 arranged opposite to each other, a gate oxide layer 062 wrapping each channel layer 021, and a gate layer 063 filling the gap between the two sidewalls 061.
  • Two internal isolation parts 05 are also provided on the side of each channel layer 021 facing the substrate 01, and the internal isolation part 05 is used to isolate the gate layer 063 from the source 031 and the drain 032.
  • substrate parasitic leakage path from the source 031 to the drain 032 under the stacked channel layer 021 in the GAA transistor 1, which is called substrate parasitic leakage.
  • Substrate parasitic leakage is one of the main challenges faced by the GAA transistor 1. As the channel length of the GAA transistor 1 continues to shrink, the problem of substrate parasitic leakage will become more and more serious.
  • the inversion ion implantation region 08 is formed by performing inversion ion implantation in the region corresponding to the source 031 and the drain 032 in the substrate 01, thereby increasing the substrate 01 barrier at the junction position below the source 031 and the drain 032, thereby suppressing the substrate parasitic leakage.
  • the channel length decreases, the short channel effect is enhanced, so a higher concentration of inversion ion implantation is required. This will make the junction morphology steeper, thereby increasing the band-to-band tunneling (BTBT) leakage between the drain end and the substrate 01.
  • BBT band-to-band tunneling
  • the present application provides a GAA transistor, a method for manufacturing the same, and an electronic device, which can reduce the parasitic leakage of the substrate.
  • FIG. 3 is a schematic diagram of the structure of a GAA transistor 1 provided in an embodiment of the present application.
  • the GAA transistor 1 mainly includes a substrate 01, a fin 02 located on the substrate 01, a source 031 and a drain 032 located on both sides of the fin 02, and a gate structure 06 located between the source 031 and the drain 032 and covering the fin 02.
  • the GAA transistor 1 may also include a first epitaxial doping layer 041 and a second epitaxial doping layer 042 located on both sides of the fin 02.
  • the first epitaxial doping layer 041 is located between the substrate 01 and the source 031, and the second epitaxial doping layer 042 is located between the substrate 01 and the drain 032.
  • the conductivity type of the doped impurities in the first epitaxial doping layer 041 and the second epitaxial doping layer 042 is the same as the conductivity type of the doped impurities in the substrate 01
  • the conductivity type of the doped impurities in the first epitaxial doping layer 041 and the second epitaxial doping layer 042 is opposite to the conductivity type of the doped impurities in the source 031 and the drain 032
  • the doping concentration of the first epitaxial doping layer 041 and the second epitaxial doping layer 042 is greater than the doping concentration of the substrate 01.
  • the conductivity type of the doped impurities in the first epitaxial doping layer 041 and the second epitaxial doping layer 042 is opposite to the conductivity type of the doped impurities in the source 031 and the drain 032, the inversely doped first epitaxial doping layer 041 and the second epitaxial doping layer 042 can be used to cut off the substrate 01 leakage channel between the source 031 and the drain 032.
  • the depletion region formed by the first epitaxial doping layer 041 and the source 031 is confined to the first epitaxial doping layer 041
  • the depletion region formed by the second epitaxial doping layer 042 and the drain 032 is confined to the second epitaxial doping layer 042, and will not diffuse into the substrate 01.
  • the depletion region formed by the first epitaxial doping layer 041 and the source 031 and the depletion region formed by the second epitaxial doping layer 042 and the drain 032 are separated in a direction parallel to the substrate 01 , thereby greatly suppressing leakage of the substrate 01 .
  • the doping concentration of the first epitaxial doping layer 041 and the second epitaxial doping layer 042 can be maintained at a low level, thereby not causing greater BTBT leakage.
  • the GAA transistor 1 provided in the present application can obtain a better subthreshold swing, and as the channel length continues to shrink, The operating voltage can also be continuously reduced while ensuring device performance.
  • the present application does not limit the specific implementation of the fin 02 and the gate structure 06 in the GAA transistor 1, which can be any structure that can realize the function of the GAA transistor 1.
  • the fin 02 may include a plurality of channel layers 021 stacked at intervals in a direction perpendicular to the substrate 01; the gate structure 06 may include two sidewalls 061 arranged opposite to each other, a gate oxide layer 062 wrapping each channel layer 021, and a gate layer 063 filling the gap between the two sidewalls 061.
  • the GAA transistor 1 provided in the embodiment of the present application is further described below in combination with the preparation method. It should be noted that the following embodiment is only used to illustrate the feasibility of the GAA transistor 1 of the present application and does not limit the scope of the application.
  • FIG. 4 shows a schematic flow chart of a method for manufacturing a GAA transistor 1 provided in an embodiment of the present application.
  • the method may include the following steps:
  • Step S101 forming an initial fin, a sacrificial gate and two sidewalls spanning the initial fin on a substrate; wherein the initial fin includes a sacrificial layer and a channel layer stacked and alternately arranged, and the two sidewalls are respectively located on both sides of the sacrificial gate.
  • an initial fin is first formed on the substrate 01, and then a sacrificial gate 07 is formed across the initial fin, and then sidewalls 061 are formed on both sides of the sacrificial gate 07.
  • the drawings of the present application illustrate the GAA transistor 1 including three sacrificial layers 022 and three channel layers 021 as an example. It can be understood that in the GAA transistor 1, the number of layers of the sacrificial layer 022 and the channel layer 021 can be determined according to the actual needs of the device, and is not limited here. For example, the number of layers of the sacrificial layer 022 and the channel layer 021 can be set according to the conductive properties of the GAA transistor 1.
  • a gate oxide layer 062 covering the initial fin may be formed before forming the sacrificial gate 07 .
  • STI shallow trench isolation
  • the present application does not limit the thickness of the sacrificial layer and the channel layer, and the thickness of the sacrificial layer and the channel layer can be set according to the actual requirements of the GAA transistor.
  • the substrate may be a semiconductor material, for example, the substrate may be made of silicon.
  • the sacrificial layer can be formed of a material having a similar lattice constant to the channel layer, and in the same etching process, the sacrificial layer and the channel layer have a higher etching selectivity ratio, so that the sacrificial layer can be etched away during subsequent selective etching, while the channel layer is retained, thereby forming a suspended channel layer.
  • the channel layer may be formed of Si semiconductor material, and the sacrificial layer may be formed of SiGe semiconductor material.
  • the bottom layer in the initial fin is a sacrificial layer
  • the top layer is a channel layer.
  • the sacrificial layer and the channel layer can be epitaxially grown on the substrate in sequence, and the epitaxial growth can be repeated multiple times to form multiple sacrificial layers and multiple channel layers stacked in sequence. Then, the sacrificial layer and the channel layer are patterned using a composition process to form the initial fin.
  • the extension direction of the sacrificial gate may be set to be perpendicular to the extension direction of the initial fin.
  • the spacer may be formed of a material with a low dielectric constant, such as but not limited to silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and combinations thereof.
  • Step S102 removing the initial fins exposed on the outer sides of the two side walls.
  • Step S103 forming internal isolation portions on both sides of each sacrificial layer, and the internal isolation portions are located below the sidewalls.
  • the internal isolation portion can be formed by using a material with a low dielectric constant, and the internal isolation portion can physically isolate the source, the drain, and a gate layer subsequently formed in the suspended region, thereby reducing parasitic capacitance.
  • Step S104 epitaxially growing a first epitaxial doping layer and a second epitaxial doping layer on the substrate, wherein the first epitaxial doping layer and the second epitaxial doping layer are respectively located outside the internal isolation portion.
  • the conductivity type of the doped impurities in the first epitaxial doping layer and the second epitaxial doping layer is the same as the conductivity type of the doped impurities in the substrate, and is opposite to the conductivity type of the doped impurities in the source and the drain, and the doping concentration of the first epitaxial doping layer and the second epitaxial doping layer is greater than the doping concentration of the substrate.
  • the conductivity type of the doped impurities in the source and drain is N-type
  • the first epitaxial doped layer and the second epitaxial doped layer are The conductivity types of the doped impurities in the source and drain are all P-type; if the conductivity types of the doped impurities in the source and drain are P-type, then the conductivity types of the doped impurities in the first epitaxial doped layer, the second epitaxial doped layer and the substrate are all N-type.
  • the doping concentrations of the first epitaxial doping layer and the second epitaxial doping layer can be maintained at a relatively low level.
  • the doping concentration of the first epitaxial doping layer is less than or equal to 5*10 18 /cm 3
  • the doping concentration of the second epitaxial doping layer is less than or equal to 5*10 18 /cm 3 .
  • the doping concentration of the first epitaxial doping layer may be controlled to be less than 10 18 /cm 3
  • the doping concentration of the second epitaxial doping layer may be controlled to be less than 10 18 /cm 3 .
  • the present application does not limit the thickness of the first epitaxial doping layer and the second epitaxial doping layer.
  • the thickness of the first epitaxial doping layer can be set to 5-25nm, such as 5nm, 7nm, 10nm, 15nm, 20nm, 25nm, etc.
  • the thickness of the second epitaxial doping layer can be set to 5-25nm, such as 5nm, 7nm, 10nm, 15nm, 20nm, 25nm, etc.
  • the first epitaxial doping layer and the second epitaxial doping layer can be formed simultaneously, so the doping concentrations of the first epitaxial doping layer and the second epitaxial doping layer can be set to be the same, and the thicknesses of the first epitaxial doping layer and the second epitaxial doping layer can be set to be the same.
  • Step S105 epitaxially growing a source electrode in a region corresponding to the first epitaxial doping layer, and epitaxially growing a drain electrode in a region corresponding to the second epitaxial doping layer.
  • the source electrode and the drain electrode are made of the same material, and the material of the source electrode and the drain electrode can be set according to the structure of the device.
  • the source and drain materials may be P-type doped semiconductors, such as P-type doped germanium silicon semiconductors, wherein the doped P-type ions may be trivalent ions, such as boron, aluminum, gallium, etc. ions.
  • the source and drain materials may be N-type doped semiconductors, such as N-type doped semiconductors, where the doped N-type ions may be pentavalent ions, such as nitrogen, phosphorus, arsenic, etc. ions.
  • Step S106 removing the sacrificial gate and the sacrificial layer to form a plurality of suspended channel layers.
  • the sacrificial gate may be removed by dry etching, wet etching or a combination of the two, which is not limited here.
  • the sacrificial layer may be removed by dry etching or wet etching, which is not limited here.
  • an etching method with a significantly higher etching rate than the channel layer can be used to selectively etch away the sacrificial layer in the initial fin, so that the remaining channel layer is suspended.
  • the suspended channel layer can be referred to as a nanowire channel.
  • Step S107 forming a gate oxide layer and a gate layer between the two sidewall spacers.
  • a gate oxide layer wrapping each channel layer may be formed first, and then a gate layer may be formed between two sidewalls.
  • an atomic layer deposition method or a low pressure chemical vapor deposition method may be used to form a fully surrounding gate oxide layer on the surface of each channel layer.
  • the gate oxide layer may be formed of a material with a high dielectric constant, such as an oxide or oxynitride of Si, titanium (Ti), zirconium (Zr), or hafnium (Hf).
  • the gate oxide layer may be a dielectric layer formed of any one of SiO 2 , HfON, HfO 2 , ZrO, and TiO 2 , or a stack thereof.
  • an atomic layer deposition method can be used to form a gate layer on the surface of the gate oxide layer until the gate layer completely fills the gap between the two sidewalls.
  • the gate layer can be formed of titanium, titanium nitride, aluminum, tungsten, tantalum nitride, or a stack of the above materials.
  • the present application does not limit the execution order of the above steps, and the execution order of the above steps can be adjusted according to actual conditions.
  • the first epitaxial doping layer 041 and the second epitaxial doping layer 042 are epitaxially grown on the substrate 01 below the source 031 and the drain 032, respectively. Since the conductivity type of the doped impurities in the first epitaxial doping layer 041 and the second epitaxial doping layer 042 is opposite to the conductivity type of the doped impurities in the source 031 and the drain 032, the first epitaxial doping layer 041 and the second epitaxial doping layer 042 with inverse doping are used to cut off the leakage channel of the substrate 01 between the source 031 and the drain 032.
  • the depletion region formed by the first epitaxial doping layer 041 and the source 031 is confined in the first epitaxial doping layer 041
  • the depletion region formed by the second epitaxial doping layer 042 and the drain 032 is confined in the second epitaxial doping layer 042, and will not diffuse into the substrate 01.
  • the depletion region formed by the first epitaxial doping layer 041 and the source 031 and the depletion region formed by the second epitaxial doping layer 042 and the drain 032 are separated in a direction parallel to the substrate 01 , thereby greatly suppressing leakage of the substrate 01 .
  • the first epitaxial doping layer and the second epitaxial doping layer can be epitaxially grown on the substrate in the following manner, that is, after completing step S103, at least the first doping layer and the second doping layer are epitaxially grown on the substrate; then the first doping layer and the second doping layer are etched to remove the first doping layer and the second doping layer located on the side walls of the channel layer, thereby forming the first epitaxial doping layer and the second epitaxial doping layer.
  • the sidewalls of the initial fins will also grow, and when the first doped layer and the second doped layer located on the sidewalls of the channel layer are etched, the first doped layer perpendicular to the substrate direction will also be etched away.
  • multiple growth and multiple etching can be performed.
  • the first doped layer and the second doped layer are epitaxially grown on the substrate at least multiple times; after each epitaxial growth of the first doped layer and the second doped layer, the first doped layer and the second doped layer are etched to remove the first doped layer and the second doped layer located on the side walls of the channel layer; until the first doped layer and the second doped layer are etched for the last time, the first epitaxial doped layer and the second epitaxial doped layer can be formed.
  • a feasible implementation method is to make the growth rate of the first doping layer and the second doping layer in the direction perpendicular to the substrate greater than the growth rate in the direction parallel to the substrate when epitaxially growing the first doping layer and the second doping layer. That is, the thickness of the first doping layer and the second doping layer in the direction perpendicular to the substrate is greater than the thickness in the direction parallel to the substrate.
  • a growth rate of the first doping layer and the second doping layer in a direction perpendicular to the substrate is 20% greater than a growth rate in a direction parallel to the substrate.
  • the etching rate in the direction parallel to the substrate is greater than the etching rate in the direction perpendicular to the substrate. In this way, when etching is performed, it can be ensured that when the first doped layer and the second doped layer on the sidewalls of the channel layer are completely etched, there are still the first doped layer and the second doped layer of a certain thickness on the substrate.
  • the etching rate in the direction parallel to the substrate is 2 times greater than the etching rate in the direction perpendicular to the substrate.
  • the etching rate in the direction parallel to the substrate is 3 times, 4 times, or 5 times the etching rate in the direction perpendicular to the substrate.
  • the sidewalls of the channel layer do not have the first doped layer and the second doped layer.
  • the growth rate of the first doped layer and the second doped layer in a direction perpendicular to the substrate is greater than the growth rate in a direction parallel to the substrate.
  • the etching rate in a direction parallel to the substrate is greater than the etching rate in a direction perpendicular to the substrate.
  • an isolation portion may be first formed on the side wall of the channel layer, and then the first epitaxial doping layer and the second epitaxial doping layer are epitaxially grown. After the first epitaxial doping layer and the second epitaxial doping layer are formed, the isolation portion on the side wall of the channel layer is removed.
  • forming internal isolation portions on both sides of each sacrificial layer and epitaxially growing a first epitaxial doped layer and a second epitaxial doped layer on a substrate may include:
  • the sacrificial layer 022 under the two sidewalls 061 is removed;
  • internal isolation portions 05 are formed on both sides of each sacrificial layer 022 and on both sides of each channel layer 021 ;
  • a first epitaxial doped layer 041 and a second epitaxial doped layer 042 are epitaxially grown on the substrate 01 , and the first epitaxial doped layer 041 and the second epitaxial doped layer 042 are respectively located outside the internal isolation portion 05 ;
  • the internal isolation portions 05 located outside each channel layer 021 are removed, and the internal isolation portions 05 located on both sides of each sacrificial layer 022 are retained.
  • FIG5e After the first epitaxial doping layer 041 and the second epitaxial doping layer 042 are epitaxially grown on the substrate 01, as shown in FIG5e, the source 031 is epitaxially grown in the region corresponding to the first epitaxial doping layer 041, and the drain 032 is epitaxially grown in the region corresponding to the second epitaxial doping layer 042.
  • FIG5a to FIG5e only show the drain 032 side of the GAA transistor 1, and the source 031 side is generally symmetrical with the drain 032 side.
  • the GAA transistor 1 provided in the embodiment of the present application, on the basis of the conventional GAA transistor 1, epitaxially grows a first epitaxial doping layer 041 and a second epitaxial doping layer 042 between the substrate 01 and the source 031 and the drain 032, for cutting off the leakage channel of the substrate 01 between the source and the drain.
  • the present application can be integrated into the conventional GAA device process steps in two feasible ways.
  • the doping concentration of the first epitaxial doping layer 041 and the second epitaxial doping layer 042 can be maintained below 10 18 /cm 3 , which can suppress the parasitic leakage of the substrate 01 while limiting the BTBT leakage.
  • the present application uses semiconductor process simulation and device simulation tools (Technology Computer Aided Design, TCAD) to simulate and verify the effects of epitaxial doping layers (the first epitaxial doping layer and the second epitaxial doping layer) of different thicknesses (5nm/10nm) on the
  • TCAD Technicalnology Computer Aided Design
  • the simulation results shown in FIG6 show that a 10 nm thick epitaxial doping layer with a concentration of 10 18 /cm3 can reduce the substrate parasitic leakage by 60% while ensuring the same turn-on current. Therefore, the present application can perform process-device coordinated optimization by adjusting the thickness of the epitaxial doping layer.
  • an embodiment of the present application further provides an electronic device 10, including a circuit board 11, and a GAA transistor 1 disposed on the circuit board 11.
  • the electronic device 10 further includes a housing 12, and the circuit board 11 is disposed in the housing 12. Since the principle of solving the problem by the electronic device 10 is similar to that of the aforementioned GAA transistor 1, the implementation of the electronic device 10 can refer to the implementation of the aforementioned GAA transistor 1, and the repeated parts will not be repeated.

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Abstract

提供一种环栅晶体管、其制备方法及电子设备，属于半导体技术领域。环栅晶体管（1），在衬底（01）和源极（031）、漏极（032）之间外延生长第一外延掺杂层（041）和第二外延掺杂层（042），用于切断源极（031）和漏极（032）之间的衬底漏电通道。第一外延掺杂层（041）和第二外延掺杂层（042）均是外延生长在衬底（01）之上，因此第一外延掺杂层（041）和源极（031）形成的耗尽区被限制在第一外延掺杂层（041）里，第二外延掺杂层（042）和漏极（032）形成的耗尽区被限制在第二外延掺杂层（042）里，而不会延伸到衬底（01）中。第一外延掺杂层（041）和源极（031）形成的耗尽区与第二外延掺杂层（042）和漏极（032）形成的耗尽区在平行于衬底（01）的方向上被分隔开，因此可以抑制衬底漏电。

Description

一种环栅晶体管、其制备方法及电子设备
相关申请的交叉引用
本申请要求在2022年11月22日提交中国专利局、申请号为202211468805.X、申请名称为“一种环栅晶体管、其制备方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及到一种环栅晶体管、其制备方法及电子设备。
背景技术
随着摩尔定律的持续推进，芯片中晶体管的尺寸持续微缩，集成度不断提高，工作电压不断减小，以此来满足芯片高性能，低功耗的需求。从第一个晶体管的发明到目前的主流5nm技术节点，经历了半个多世纪，在每一个技术节点，创新的工艺技术被提出来进一步推动晶体管的发展。传统的晶体管特征尺寸的持续微缩已经达到了物理极限，导致芯片功耗，性能和成本的矛盾，因此互补金属氧化物半导体(Complementary metal oxide semiconductor，CMOS)器件从二维平面结构进入到了3D鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)时代，并且已经延续到了5nm工艺节点。为了进一步延伸摩尔定律，微电子学术界和工业界纷纷布局基于新材料和新架构的下一代器件的研发。环栅(Gate-all-around，GAA)晶体管比Fin FET具有更好的亚阈值摆幅和更好的栅控制能力，从而能够获得更加优异的电学性能。然而，在GAA晶体管中堆叠的沟道层下方有着从源极到漏极的寄生漏电途径，被称为衬底寄生漏电。衬底寄生漏电是GAA晶体管面临的主要挑战之一，随着GAA晶体管的沟道长度不断微缩，衬底寄生漏电的问题会愈发严峻。
发明内容
本申请提供了一种GAA晶体管、其制备方法及电子设备，用于减小GAA晶体管的衬底寄生漏电。
第一方面，本申请提供了一种GAA晶体管，该GAA晶体管主要包括衬底，位于衬底上的鳍部，分别位于鳍部两侧的源极和漏极，位于源极和漏极之间且覆盖该鳍部的栅极结构。为了减小衬底的寄生漏电，该GAA晶体管中还可以包括分别位于鳍部两侧的第一外延掺杂层和第二外延掺杂层。其中，第一外延掺杂层位于衬底与源极之间，第二外延掺杂层位于衬底与漏极之间。第一外延掺杂层和第二外延掺杂层中掺杂杂质的导电类型均与衬底中掺杂杂质的导电类型相同，第一外延掺杂层和第二外延掺杂层中掺杂杂质的导电类型均与源极和漏极中掺杂杂质的导电类型相反，例如，如果源极和漏极中掺杂杂质的导电类型为N型，那么第一外延掺杂层、第二外延掺杂层以及衬底中掺杂杂质的导电类型均为P型；如果源极和漏极中掺杂杂质的导电类型为P型，那么第一外延掺杂层、第二外延掺杂层以及衬底中掺杂杂质的导电类型均为N型。但是第一外延掺杂层和第二外延掺杂层的掺杂浓度均大于衬底的掺杂浓度。
在本申请中，由于第一外延掺杂层和第二外延掺杂层中掺杂杂质的导电类型均与源极和漏极中掺杂杂质的导电类型相反，因此可以利用反型掺杂的第一外延掺杂层和第二外延掺杂层截断源极和漏极之间的衬底漏电通道。并且，由于第一外延掺杂层和第二外延掺杂层均是外延生长在衬底之上的，因此第一外延掺杂层和源极形成的耗尽区被限制在第一外延掺杂层里，第二外延掺杂层和漏极形成的耗尽区被限制在第二外延掺杂层里，而不会扩散到衬底里。且第一外延掺杂层和源极形成的耗尽区与第二外延掺杂层和漏极形成的耗尽区在平行于衬底的方向上是被分隔开的，因此可以极大的抑制衬底漏电。
另外，随着沟道长度的微缩，由于第一外延掺杂层和源极形成的耗尽区与第二外延掺杂层和漏极形成的耗尽区在平行于衬底的方向上是被分隔开的，因此第一外延掺杂层和第二外延掺杂层的掺杂浓度可以保持在较低的水平，从而不会造成更大的BTBT漏电。
因此，本申请提供的GAA晶体管可以获得更好的亚阈值摆幅，并且随着沟道长度不断微缩，在保证器件性能的情况下工作电压也可以不断减小。
示例性的，鳍部可以包括沿垂直于衬底方向间隔堆叠的多个沟道层；栅极结构可以包括相对设置的两个侧墙、包裹各沟道层的栅氧化层以及填充于该两个侧墙之间的间隙的栅极层。为了使栅极层与源极 和漏极隔离，每一沟道层面向衬底一侧均设置有两个内部隔离部，且该两个内部隔离部被栅极层隔离，其中一个内部隔离部位于栅极层与源极之间，另一个位于栅极层与漏极之间。
在本申请中，由于第一外延掺杂层和源极形成的耗尽区与第二外延掺杂层和漏极形成的耗尽区在平行于衬底的方向上是被分隔开的，因此第一外延掺杂层和第二外延掺杂层的掺杂浓度可以保持在较低的水平。示例性的，第一外延掺杂层的掺杂浓度可以设置为小于或等于5*1018/cm3，第二外延掺杂层的掺杂浓度可以设置为小于或等于5*1018/cm3。
在一种实施例中，第一外延掺杂层的掺杂浓度可以控制在1018/cm3以下，第二外延掺杂层的掺杂浓度可以控制在1018/cm3以下。
本申请对第一外延掺杂层和第二外延掺杂层的厚度不作限定。示例性的，第一外延掺杂层的厚度可以设置为5-25nm，例如5nm、7nm、10nm、15nm、20nm、25nm等。第二外延掺杂层的厚度可以设置为5-25nm，例如5nm、7nm、10nm、15nm、20nm、25nm等。
示例性的，在本申请中第一外延掺杂层和第二外延掺杂层可以同时形成，因此第一外延掺杂层和第二外延掺杂层的掺杂浓度可以设置为相同，第一外延掺杂层和第二外延掺杂层的厚度可以设置为相同。
第二方面，本申请提供了一种GAA晶体管的制备方法，该制备方法可以包括以下步骤：在衬底上形成初始鳍部以及横跨该初始鳍部的牺牲栅极和两个侧墙；其中，初始鳍部包括层叠且交替重复设置的牺牲层和沟道层，两个侧墙分别位于牺牲栅极的两侧；然后去除两个侧墙外侧裸露的初始鳍部，并在各牺牲层两侧形成内部隔离部，且内部隔离部位于侧墙下方；接着在衬底上外延生长第一外延掺杂层和第二外延掺杂层，且第一外延掺杂层和第二外延掺杂层分别位于内部隔离部的外侧；在第一外延掺杂层对应的区域外延生长源极，在第二外延掺杂层对应的区域外延生长漏极；去除牺牲栅极和牺牲层，形成多个悬空的沟道层；在两个侧墙之间形成栅氧化层和栅极层。本申请中，第一外延掺杂层和第二外延掺杂层中掺杂杂质的导电类型均与衬底中掺杂杂质的导电类型相同，与源极和漏极中掺杂杂质的导电类型相反，且第一外延掺杂层和第二外延掺杂层的掺杂浓度均大于衬底的掺杂浓度。
在一种可行的实现方式中，可以通过以下方式在衬底上外延生长第一外延掺杂层和第二外延掺杂层：在衬底上至少外延生长第一掺杂层和第二掺杂层；然后对该第一掺杂层和该第二掺杂层进行刻蚀，以去除位于沟道层侧壁的第一掺杂层和第二掺杂层，从而形成第一外延掺杂层和第二外延掺杂层。
但是考虑到，在具体实施时，在衬底上外延生长第一掺杂层和第二掺杂层时，初始鳍部的侧壁上也会生长，在刻蚀位于沟道层侧壁的第一掺杂层和第二掺杂层时，也会刻蚀掉垂直于衬底方向的第一掺杂层和第二掺杂层，为了保证最终形成的第一外延掺杂层和第二外延掺杂层能够满足一定的厚度，可以进行多次生长，多次刻蚀。
示例性的，在衬底上至少外延生长多次第一掺杂层和第二掺杂层；在每一外延生长第一掺杂层和第二掺杂层后对该第一掺杂层和该第二掺杂层进行刻蚀，以去除位于沟道层侧壁的第一掺杂层和第二掺杂层；直到最后一次对第一掺杂层和第二掺杂层进行刻蚀后，就可以形成第一外延掺杂层和第二外延掺杂层。
为了保证形成的第一外延掺杂层和第二外延掺杂层既有一定的厚度，且沟道层的侧壁又不会有第一掺杂层和第二掺杂层的存在。一种可行的实现方式是，在外延生长第一掺杂层和第二掺杂层时，使第一掺杂层和第二掺杂层在垂直于衬底的方向上的生长速率大于在平行于衬底的方向上的生长速率。即第一掺杂层和第二掺杂层在垂直衬底方向的厚度要大于平行于衬底方向的厚度，这样在进行刻蚀时，可以保证当沟道层侧壁的第一掺杂层和第二掺杂层刻蚀完成时，衬底上还有一定厚度的第一掺杂层和第二掺杂层。
示例性的，第一掺杂层和第二掺杂层在垂直于衬底的方向上的生长速率比在平行于衬底的方向上的生长速率大20％。
为了保证形成的第一外延掺杂层和第二外延掺杂层既有一定的厚度，且沟道层的侧壁又不会有第一掺杂层和第二掺杂层的存在。另一种可行的实现方式是，对第一掺杂层和第二掺杂层进行刻蚀时，在平行于衬底的方向上的刻蚀速率大于在垂直于衬底的方向上的刻蚀速率。这样在进行刻蚀时，可以保证当沟道层侧壁的第一掺杂层和第二掺杂层刻蚀完成时，衬底上还有一定厚度的第一掺杂层和第二掺杂层。
示例性的，对第一掺杂层和第二掺杂层进行刻蚀时，在平行于衬底的方向上的刻蚀速率比在垂直于衬底的方向上的刻蚀速率大2倍。例如在平行于衬底的方向上的刻蚀速率是在垂直于衬底的方向上的刻蚀速率的3倍、4倍或5倍等。
可选的，在本申请中，为了保证形成的第一外延掺杂层和第二外延掺杂层既有一定的厚度，且沟道层的侧壁又不会有第一掺杂层和第二掺杂层的存在。在外延生长第一掺杂层和第二掺杂层时，使第一掺杂层和第二掺杂层在垂直于衬底的方向上的生长速率大于在平行于衬底的方向上的生长速率。对第一掺杂层和第二掺杂层进行刻蚀时，在平行于衬底的方向上的刻蚀速率大于在垂直于衬底的方向上的刻蚀速率。
为了避免在沟道层侧壁形成第一外延掺杂层和第二外延掺杂层，还可以先在沟道层的侧壁形成隔离部，然后再外延生长第一外延掺杂层和第二外延掺杂层，当第一外延掺杂层和第二外延掺杂层形成后再去除沟道层侧壁的隔离部。
在一种可行的实现方式中，在各牺牲层两侧形成内部隔离部和在衬底上外延生长第一外延掺杂层和第二外延掺杂层，可以包括：去除两个侧墙下方的牺牲层；在各牺牲层两侧以及各沟道层两侧形成内部隔离部；在衬底上外延生长第一外延掺杂层和第二外延掺杂层，且第一外延掺杂层和第二外延掺杂层分别位于内部隔离部的外侧；去除位于各沟道层外侧的内部隔离部，保留位于各牺牲层两侧的内部隔离部。
本申请实施例提供的GAA晶体管，在传统GAA晶体管的基础上，在衬底和源极、漏极漏之间外延生长第一外延掺杂层和第二外延掺杂层，用于切断源和漏之间的衬底漏电通道。相比现有GAA器件衬底漏电抑制技术，本申请可以通过两种可行的方式集成进传统的GAA器件工艺步骤，并且第一外延掺杂层和第二外延掺杂层的掺杂浓度可以保持在1018/cm3以下，可以在抑制衬底寄生漏电的同时限制BTBT漏电。
第三方面，本申请提供了一种电子设备，该电子设备包括电路板，设置在所述电路板上的如第一方面或第一方面的各种实施方式所述的GAA晶体管。由于该电子设备解决问题的原理与前述一种GAA晶体管相似，因此该电子设备的实施可以参见前述GAA晶体管的实施，重复之处不再赘述。
上述第三方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1为传统GAA晶体管的剖面结构示意图；
图2为相关技术提供的GAA晶体管的剖面结构示意图；
图3为本申请实施例提供的一种GAA晶体管的结构示意图；
图4为本申请一种实施例提供的GAA晶体管的制备方法的流程图；
图5a至图5e为本申请实施例中GAA晶体管的制备过程的局部结构示意图；
图6为本申请一种实施例中采用TCAD进行仿真的仿真结果示意图；
图7为本申请实施例提供的一种电子设备的结构示意图。
附图标记说明：
1      GAA晶体管；                01    衬底；
02     鳍部；                     021    沟道层；
022    牺牲层；                   031    源极；
032    漏极；                     041    第一外延掺杂层；
042    第二外延掺杂层；           05     内部隔离部；
06     栅极结构；                 061    侧墙；
062    栅氧化层；                 063    栅极层；
07     牺牲栅极；                 08     反型离子注入区；
09     浅槽隔离部；               10     电子设备；
11      电路板；                  12     壳体。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与 方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
为了方便理解本申请实施例提供的技术方案，下面首先介绍一下其应用场景。
GAA晶体管由于栅极结构可以围绕沟道设置而能实现对沟道的理想控制，因此，本申请实施例提供的GAA晶体管可以作为电子设备的元器件被广泛应用在各种场景中，例如该电子设备可以为逻辑器件、处理器等，应注意的是，本申请实施例提出的GAA晶体管旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。
参见图1，图1为传统GAA晶体管的结构示意图，GAA晶体管1主要包括衬底01，位于衬底01上的鳍部02，分别位于鳍部02两侧的源极和漏极；位于源极和漏极之间且覆盖鳍部02的栅极结构06。其中，鳍部02包括沿垂直于衬底01方向间隔堆叠的多个沟道层021。栅极结构06包括：相对设置的两个侧墙061、包裹各沟道层021的栅氧化层062、以及填充于两个侧墙061之间的间隙的栅极层063。在多个沟道层021的每一沟道层021面向衬底01一侧还设置有两个内部隔离部05，内部隔离部05用于隔离栅极层063与源极031和漏极032。
然而，在GAA晶体管1中堆叠的沟道层021下方有着从源极031到漏极032的寄生漏电途径，被称为衬底寄生漏电。衬底寄生漏电是GAA晶体管1面临的主要挑战之一，随着GAA晶体管1的沟道长度不断微缩，衬底寄生漏电的问题会愈发严峻。
参见图2，相关技术中通过在衬底01中与源极031和漏极032对应的区域进行反型离子注入形成反型离子注入区08，从而可以增加源极031和漏极032下方成结位置处的衬底01势垒，进而可以抑制衬底寄生漏电。然而随着沟道长度的减小，会导致短沟道效应增强，因此需要更高浓度的反型离子注入。这会使成结形貌更加陡峭，从而增大了漏端和衬底01之间的带间隧穿(Band to band tunneling，BTBT)漏电。
为此，本申请实施例提供了一种GAA晶体管、其制备方法及电子设备，可以减小衬底的寄生漏电。下面将结合附图对本申请作进一步地详细描述。
参见图3，图3为本申请实施例提供的一种GAA晶体管1的结构示意图。该GAA晶体管1主要包括衬底01，位于衬底01上的鳍部02，分别位于鳍部02两侧的源极031和漏极032，位于源极031和漏极032之间且覆盖该鳍部02的栅极结构06。为了减小衬底01的寄生漏电，该GAA晶体管1中还可以包括分别位于鳍部02两侧的第一外延掺杂层041和第二外延掺杂层042。其中，第一外延掺杂层041位于衬底01与源极031之间，第二外延掺杂层042位于衬底01与漏极032之间。第一外延掺杂层041和第二外延掺杂层042中掺杂杂质的导电类型均与衬底01中掺杂杂质的导电类型相同，第一外延掺杂层041和第二外延掺杂层042中掺杂杂质的导电类型均与源极031和漏极032中掺杂杂质的导电类型相反，且第一外延掺杂层041和第二外延掺杂层042的掺杂浓度均大于衬底01的掺杂浓度。
在本申请中，由于第一外延掺杂层041和第二外延掺杂层042中掺杂杂质的导电类型均与源极031和漏极032中掺杂杂质的导电类型相反，因此可以利用反型掺杂的第一外延掺杂层041和第二外延掺杂层042来截断源极031和漏极032之间的衬底01漏电通道。并且，由于第一外延掺杂层041和第二外延掺杂层042均是外延生长在衬底01之上的，因此第一外延掺杂层041和源极031形成的耗尽区被限制在第一外延掺杂层041里，第二外延掺杂层042和漏极032形成的耗尽区被限制在第二外延掺杂层042里，而不会扩散到衬底01里。且第一外延掺杂层041和源极031形成的耗尽区与第二外延掺杂层042和漏极032形成的耗尽区在平行于衬底01的方向上是被分隔开的，因此可以极大的抑制衬底01漏电。
另外，随着沟道长度的微缩，由于第一外延掺杂层041和源极031形成的耗尽区与第二外延掺杂层042和漏极032形成的耗尽区在平行于衬底01的方向上是被分隔开的，因此第一外延掺杂层041和第二外延掺杂层042的掺杂浓度可以保持在较低的水平，从而不会造成更大的BTBT漏电。
因此，本申请提供的GAA晶体管1可以获得更好的亚阈值摆幅，并且随着沟道长度不断微缩，在 保证器件性能的情况下工作电压也可以不断减小。
本申请对GAA晶体管1中鳍部02以及栅极结构06的具体实施方式不作限定，可以是任意能够实现GAA晶体管1功能的结构。示例性的，如图3所示，鳍部02可以包括沿垂直于衬底01方向间隔堆叠的多个沟道层021；栅极结构06可以包括相对设置的两个侧墙061、包裹各沟道层021的栅氧化层062以及填充于该两个侧墙061之间的间隙的栅极层063。为了使栅极层063与源极031和漏极032隔离，每一沟道层021面向衬底01一侧均设置有两个内部隔离部05，且该两个内部隔离部05被栅极层063隔离，其中一个内部隔离部05位于栅极层063与源极031之间，另一个位于栅极层063与漏极032之间。
为方便理解本申请实施例提供的GAA晶体管1，下面结合制备方法对本申请实施例提供的上述GAA晶体管1进行进一步的说明。需要注意的是，下面实施例仅是用于阐述本申请GAA晶体管1的可行性，不对申请的范围进行限制。
参见图4，图4示出了本申请实施例提供的GAA晶体管1的制备方法的流程示意图，该制备方法可以包括以下步骤：
步骤S101、在衬底上形成初始鳍部以及横跨该初始鳍部的牺牲栅极和两个侧墙；其中，初始鳍部包括层叠且交替重复设置的牺牲层和沟道层，两个侧墙分别位于牺牲栅极的两侧。
在一种可行的实现方式中，参见图5a至图5e，先在衬底01上形成初始鳍部，然后形成横跨该初始鳍部的牺牲栅极07，之后在该牺牲栅极07的两侧分别形成侧墙061。本申请附图中以GAA晶体管1中包括三层牺牲层022和三层沟道层021为例进行示意。可以理解，GAA晶体管1中，牺牲层022和沟道层021的层数可以根据器件的实际需求来确定，在此不作限定。例如，可以根据GAA晶体管1的导电性能来设定牺牲层022和沟道层021的层数。
可选的，参见图5a至图5e，在形成牺牲栅极07之前还可以形成覆盖该初始鳍部的栅氧化层062。
在具体实施时，在制备GAA晶体管时，一般会在衬底上形成很多GAA晶体管，然后再根据需求进行切割。为了在制备过程将不同的GAA晶体管进行隔离，在一种实施例中，参见图5a至图5e，在牺牲栅极07两侧形成侧墙061之前，还会在相邻器件之间形成浅槽隔离部(Shallow trench isolation，STI)09，然后再形成侧墙061。
本申请对牺牲层和沟道层的厚度不作限定，可以根据实际GAA晶体管要求设定牺牲层和沟道层的厚度。
在本申请中，衬底可以是半导体材料，例如，衬底的材质可以为硅。
在本申请中，牺牲层可以选与沟道层具有相近的晶格常数的材料形成，并且在同一刻蚀工艺中，牺牲层与沟道层具有较高的刻蚀选择比，这样，在进行后续的选择性刻蚀时可以将牺牲层刻蚀掉，而保留沟道层，从而形成悬空的沟道层。
示例性的，沟道层可以采用Si半导体材料形成，牺牲层可以采用SiGe半导体材料形成。
在具体实施时，在初始鳍部中最底层为牺牲层，最顶层为沟道层。在制备时，可以在衬底上依次外延生长牺牲层和沟道层，重复外延生长多次，从而形成依次层叠设置的多层牺牲层和多层沟道层。然后采用构图工艺对牺牲层和沟道层进行图形化，从而形成初始鳍部。
在具体实施时，牺牲栅极的延伸方法可以设置为与初始鳍部的延伸方向垂直。
示例性的，侧墙可以采用低介电常数的材料形成，例如包括但不限于氮化硅、氧化硅、氮氧化硅，碳氧化硅及其组合。
步骤S102、去除两个侧墙外侧裸露的初始鳍部。
步骤S103、在各牺牲层两侧形成内部隔离部，且内部隔离部位于侧墙下方。
本申请中，内部隔离部可以采用低介电常数的材料形成，内部隔离部可以物理隔离源极、漏极和后续形成在悬空区域中的栅极层，从而减小寄生电容。
步骤S104、在衬底上外延生长第一外延掺杂层和第二外延掺杂层，且第一外延掺杂层和第二外延掺杂层分别位于内部隔离部的外侧。
其中，第一外延掺杂层和第二外延掺杂层中掺杂杂质的导电类型均与衬底中掺杂杂质的导电类型相同，与源极和漏极中掺杂杂质的导电类型相反，且第一外延掺杂层和第二外延掺杂层的掺杂浓度均大于衬底的掺杂浓度。
例如，如果源极和漏极中掺杂杂质的导电类型为N型，那么第一外延掺杂层、第二外延掺杂层以 及衬底中掺杂杂质的导电类型均为P型；如果源极和漏极中掺杂杂质的导电类型为P型，那么第一外延掺杂层、第二外延掺杂层以及衬底中掺杂杂质的导电类型均为N型。
在本申请中，由于第一外延掺杂层和源极形成的耗尽区与第二外延掺杂层和漏极形成的耗尽区在平行于衬底的方向上是被分隔开的，因此第一外延掺杂层和第二外延掺杂层的掺杂浓度可以保持在较低的水平。示例性的，第一外延掺杂层的掺杂浓度小于或等于5*1018/cm3，第二外延掺杂层的掺杂浓度小于或等于5*1018/cm3。
在一种实施例中，第一外延掺杂层的掺杂浓度可以控制在1018/cm3以下，第二外延掺杂层的掺杂浓度可以控制在1018/cm3以下。
本申请对第一外延掺杂层和第二外延掺杂层的厚度不作限定。示例性的，第一外延掺杂层的厚度可以设置为5-25nm，例如5nm、7nm、10nm、15nm、20nm、25nm等。第二外延掺杂层的厚度可以设置为5-25nm，例如5nm、7nm、10nm、15nm、20nm、25nm等。
示例性的，在本申请中，第一外延掺杂层和第二外延掺杂层可以同时形成，因此第一外延掺杂层和第二外延掺杂层的掺杂浓度可以设置为相同，第一外延掺杂层和第二外延掺杂层的厚度可以设置为相同。
步骤S105、在第一外延掺杂层对应的区域外延生长源极，在第二外延掺杂层对应的区域外延生长漏极。
在具体实施时，源极和漏极的材料相同，源极和漏极的材料可以根据器件的结构设定。
当GAA晶体管为P型晶体管时，源极和漏极的材料可以为P型掺杂半导体，例如P型掺杂半导体为P型掺杂的锗硅半导体。其中，掺杂的P型离子可以为三价离子，例如硼、铝、镓等离子。
当GAA晶体管为N型晶体管时，源极和漏极的材料可以为N型掺杂半导体，例如N型掺杂半导体为N型掺杂的硅半导体。其中，掺杂的N型离子可以为五价离子，例如氮、磷、砷等离子。
步骤S106、去除牺牲栅极和牺牲层，形成多个悬空的沟道层。
在具体实施时，可以采用干法刻蚀法、湿法刻蚀法或者二者组合去除牺牲栅极，在此不作限定。
在具体实施时，可以采用干法刻蚀法或湿法刻蚀法去除牺牲层，在此不作限定。
示例性的，可以采用明显高于沟道层的刻蚀速率的刻蚀方法选择性的刻蚀掉初始鳍部中的牺牲层，使保留下来的沟道层呈悬空设置，这里可以将悬空的沟道层称为纳米线沟道。
步骤S107、在两个侧墙之间形成栅氧化层和栅极层。
在一种可行的实现方式中，可以先形成包裹各沟道层的栅氧化层，然后在两个侧墙之间形成栅极层。
在具体实施时，可以采用原子层沉积法或低压化学气相沉积法等在各沟道层的表面形成全包围式的栅氧化层。示例性的，栅氧化层可以采用高介电常数的材料形成，诸如Si、钛(Ti)、锆(Zr)、铪(Hf)的氧化物或氮氧化物，例如，栅氧化层可以为SiO2、HfON、HfO2、ZrO、TiO2中的任意一种形成的介质层或它们的叠层。
在具体实施时，可以采用原子层沉积法于栅氧化层表面形成栅极层，直至栅极层完全填充两个侧墙之间的空隙。示例性的，栅极层可以为钛、氮化钛、铝、钨、氮化钽或上述材料组成的叠层等形成。
本申请对上述步骤的执行顺序不作限定，具体可以根据实际情况对上述步骤的执行顺序进行调整。
在本申请中，在源极031和漏极032下方的衬底01上分别外延生长第一外延掺杂层041和第二外延掺杂层042，由于第一外延掺杂层041和第二外延掺杂层042中掺杂杂质的导电类型均与源极031和漏极032中掺杂杂质的导电类型相反，利用反型掺杂的第一外延掺杂层041和第二外延掺杂层042从而截断源极031和漏极032之间的衬底01漏电渠道。并且，由于第一外延掺杂层041和第二外延掺杂层042均是外延生长在衬底01之上的，因此第一外延掺杂层041和源极031形成的耗尽区被限制在第一外延掺杂层041里，而第二外延掺杂层042和漏极032形成的耗尽区被限制在第二外延掺杂层042里，而不会扩散到衬底01里。且第一外延掺杂层041和源极031形成的耗尽区与第二外延掺杂层042和漏极032形成的耗尽区在平行于衬底01的方向上是被分隔开的，因此可以极大的抑制衬底01漏电。
在一种可行的实现方式中，可以通过以下方式在衬底上外延生长第一外延掺杂层和第二外延掺杂层，即在完成步骤S103之后，在衬底上至少外延生长第一掺杂层和第二掺杂层；然后对该第一掺杂层和该第二掺杂层进行刻蚀，以去除位于沟道层侧壁的第一掺杂层和第二掺杂层，从而形成第一外延掺杂层和第二外延掺杂层。
但是考虑到，在具体实施时，在衬底上外延生长第一掺杂层和第二掺杂层时，初始鳍部的侧壁上也会生长，在刻蚀位于沟道层侧壁的第一掺杂层和第二掺杂层时，也会刻蚀掉垂直于衬底方向的第一掺杂 层和第二掺杂层，为了保证最终形成的第一外延掺杂层和第二外延掺杂层能够满足一定的厚度，可以进行多次生长，多次刻蚀。
示例性的，在衬底上至少外延生长多次第一掺杂层和第二掺杂层；在每一外延生长第一掺杂层和第二掺杂层后对该第一掺杂层和该第二掺杂层进行刻蚀，以去除位于沟道层侧壁的第一掺杂层和第二掺杂层；直到最后一次对第一掺杂层和第二掺杂层进行刻蚀后，就可以形成第一外延掺杂层和第二外延掺杂层。
为了保证形成的第一外延掺杂层和第二外延掺杂层既有一定的厚度，且沟道层的侧壁又不会有第一掺杂层和第二掺杂层的存在。一种可行的实现方式是，在外延生长第一掺杂层和第二掺杂层时，使第一掺杂层和第二掺杂层在垂直于衬底的方向上的生长速率大于在平行于衬底的方向上的生长速率。即第一掺杂层和第二掺杂层在垂直衬底方向的厚度要大于平行于衬底方向的厚度，这样在进行刻蚀时，可以保证当沟道层侧壁的第一掺杂层和第二掺杂层刻蚀完成时，衬底上还有一定厚度的第一掺杂层和第二掺杂层。
示例性的，第一掺杂层和第二掺杂层在垂直于衬底的方向上的生长速率比在平行于衬底的方向上的生长速率大20％。
为了保证形成的第一外延掺杂层和第二外延掺杂层既有一定的厚度，且沟道层的侧壁又不会有第一掺杂层和第二掺杂层的存在。另一种可行的实现方式是，对第一掺杂层和第二掺杂层进行刻蚀时，在平行于衬底的方向上的刻蚀速率大于在垂直于衬底的方向上的刻蚀速率。这样在进行刻蚀时，可以保证当沟道层侧壁的第一掺杂层和第二掺杂层刻蚀完成时，衬底上还有一定厚度的第一掺杂层和第二掺杂层。
示例性的，对第一掺杂层和第二掺杂层进行刻蚀时，在平行于衬底的方向上的刻蚀速率比在垂直于衬底的方向上的刻蚀速率大2倍。例如在平行于衬底的方向上的刻蚀速率是在垂直于衬底的方向上的刻蚀速率的3倍、4倍或5倍等。
可选的，在本申请中，为了保证形成的第一外延掺杂层和第二外延掺杂层既有一定的厚度，且沟道层的侧壁又不会有第一掺杂层和第二掺杂层的存在。在外延生长第一掺杂层和第二掺杂层时，使第一掺杂层和第二掺杂层在垂直于衬底的方向上的生长速率大于在平行于衬底的方向上的生长速率。对第一掺杂层和第二掺杂层进行刻蚀时，在平行于衬底的方向上的刻蚀速率大于在垂直于衬底的方向上的刻蚀速率。
为了避免在沟道层侧壁形成第一外延掺杂层和第二外延掺杂层，还可以先在沟道层的侧壁形成隔离部，然后再外延生长第一外延掺杂层和第二外延掺杂层，当第一外延掺杂层和第二外延掺杂层形成后再去除沟道层侧壁的隔离部。
在一种可行的实现方式中，在各牺牲层两侧形成内部隔离部和在衬底上外延生长第一外延掺杂层和第二外延掺杂层，可以包括：
如图5a所示，去除两个侧墙061下方的牺牲层022；
如图5b所示，在各牺牲层022两侧以及各沟道层021两侧形成内部隔离部05；
如图5c所示，在衬底01上外延生长第一外延掺杂层041和第二外延掺杂层042，且第一外延掺杂层041和第二外延掺杂层042分别位于内部隔离部05的外侧；
如图5d所示，去除位于各沟道层021外侧的内部隔离部05，保留位于各牺牲层022两侧的内部隔离部05。
当在衬底01上外延生长完第一外延掺杂层041和第二外延掺杂层042后，如图5e所示，在第一外延掺杂层041对应的区域外延生长源极031，在第二外延掺杂层042对应的区域外延生长漏极032。其中，图5a至图5e仅是示出了GAA晶体管1的漏极032一侧，源极031一侧一般与漏极032一侧是对称的。
本申请实施例提供的GAA晶体管1，在传统GAA晶体管1的基础上，在衬底01和源极031、漏极032之间外延生长第一外延掺杂层041和第二外延掺杂层042，用于切断源极和漏极之间的衬底01漏电通道。相比现有GAA器件衬底01漏电抑制技术，本申请可以通过两种可行的方式集成进传统的GAA器件工艺步骤。并且第一外延掺杂层041和第二外延掺杂层042的掺杂浓度可以保持在1018/cm3以下，可以在抑制衬底01寄生漏电的同时限制BTBT漏电。
示例性的，本申请采用半导体工艺模拟以及器件模拟工具(Technology Computer Aided Design，TCAD)仿真验证了不同厚度(5nm/10nm)的外延掺杂层(第一外延掺杂层和第二外延掺杂层的简称)对 衬底寄生漏电的抑制作用。如图6所示的仿真结果显示，10nm厚且浓度为1018/cm3的外延掺杂层可以在保证相同的开启电流的情况下使衬底寄生漏电减小60％。因此本申请通过调整外延掺杂层的厚度，可以进行工艺-器件的协同优化。
相应地，参见图7，本申请实施例还提供了一种电子设备10，包括电路板11，设置在该电路板11上的GAA晶体管1。示例性的，该电子设备10还包括壳体12，电路板11设置在该壳体12内。由于该电子设备10解决问题的原理与前述一种GAA晶体管1相似，因此该电子设备10的实施可以参见前述GAA晶体管1的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种环栅晶体管，其特征在于，包括：
    衬底；
    位于所述衬底上的鳍部；
    分别位于所述鳍部两侧的源极和漏极；
    位于所述源极和所述漏极之间、且覆盖所述鳍部的栅极结构；
    分别位于所述鳍部两侧的第一外延掺杂层和第二外延掺杂层，且所述第一外延掺杂层位于所述衬底与所述源极之间，所述第二外延掺杂层位于所述衬底与所述漏极之间；
    其中，所述第一外延掺杂层和所述第二外延掺杂层中掺杂杂质的导电类型均与所述衬底中掺杂杂质的导电类型相同，所述第一外延掺杂层和所述第二外延掺杂层中掺杂杂质的导电类型均与所述源极和所述漏极中掺杂杂质的导电类型相反，且所述第一外延掺杂层和所述第二外延掺杂层的掺杂浓度均大于所述衬底的掺杂浓度。
  2. 如权利要求1所述的环栅晶体管，其特征在于，所述第一外延掺杂层的掺杂浓度小于或等于5*1018/cm3；
    第二外延掺杂层的掺杂浓度小于或等于5*1018/cm3。
  3. 如权利要求1或2所述的环栅晶体管，其特征在于，所述第一外延掺杂层的厚度为5-25nm；
    所述第二外延掺杂层的厚度为5-25nm。
  4. 如权利要求1-3任一项所述的环栅晶体管，其特征在于，所述鳍部包括沿垂直于所述衬底方向间隔堆叠的多个沟道层；
    所述栅极结构包括：相对设置的两个侧墙、包裹各所述沟道层的栅氧化层以及填充于所述两个侧墙之间的间隙的栅极层；
    所述环栅晶体管还包括位于所述多个沟道层的每一所述沟道层面向所述衬底一侧的两个内部隔离部，且所述两个内部隔离部被所述栅极层隔离。
  5. 一种电子设备，其特征在于，包括电路板，设置在所述电路板上的如权利要求1-4任一项所述的环栅晶体管。
  6. 一种环栅晶体管的制备方法，其特征在于，包括：
    在衬底上形成初始鳍部以及横跨所述初始鳍部的牺牲栅极和两个侧墙；所述初始鳍部包括层叠且交替重复设置的牺牲层和沟道层，所述两个侧墙分别位于所述牺牲栅极的两侧；
    去除所述两个侧墙外侧裸露的所述初始鳍部；
    在各所述牺牲层两侧形成内部隔离部，且所述内部隔离部位于所述侧墙下方；
    在所述衬底上外延生长第一外延掺杂层和第二外延掺杂层，且所述第一外延掺杂层和所述第二外延掺杂层分别位于所述内部隔离部的外侧；
    在所述第一外延掺杂层对应的区域外延生长源极，在所述第二外延掺杂层对应的区域外延生长漏极；
    去除所述牺牲栅极和所述牺牲层，形成多个悬空的所述沟道层；
    在所述两个侧墙之间形成栅氧化层和栅极层；
    其中，所述第一外延掺杂层和所述第二外延掺杂层中掺杂杂质的导电类型均与所述衬底中掺杂杂质的导电类型相同，所述第一外延掺杂层和所述第二外延掺杂层中掺杂杂质的导电类型均与所述源极和所述漏极中掺杂杂质的导电类型相反，且所述第一外延掺杂层和所述第二外延掺杂层的掺杂浓度均大于所述衬底的掺杂浓度。
  7. 如权利要求6所述的制备方法，其特征在于，在所述衬底上外延生长第一外延掺杂层和第二外延掺杂层，包括：
    在所述衬底上至少外延生长一次第一掺杂层和第二掺杂层；
    在每一外延生长所述第一掺杂层和所述第二掺杂层后对所述第一掺杂层和所述第二掺杂层进行刻蚀，以去除位于所述沟道层侧壁的所述第一掺杂层和所述第二掺杂层；
    最后一次对所述第一掺杂层和所述第二掺杂层进行刻蚀后，形成所述第一外延掺杂层和所述第二外延掺杂层。
  8. 如权利要求7所述的制备方法，其特征在于，外延生长所述第一掺杂层和所述第二掺杂层时，所述第一掺杂层和所述第二掺杂层在垂直于所述衬底的方向上的生长速率大于在平行于所述衬底的方向上的生长速率。
  9. 如权利要求8所述的制备方法，其特征在于，所述第一掺杂层和所述第二掺杂层在垂直于所述衬底的方向上的生长速率比在平行于所述衬底的方向上的生长速率大20％。
  10. 如权利要求7所述的制备方法，其特征在于，对所述第一掺杂层和所述第二掺杂层进行刻蚀时，在平行于所述衬底的方向上的刻蚀速率大于在垂直于所述衬底的方向上的刻蚀速率。
  11. 如权利要求10所述的制备方法，其特征在于，对所述第一掺杂层和所述第二掺杂层进行刻蚀时，在平行于所述衬底的方向上的刻蚀速率比在垂直于所述衬底的方向上的刻蚀速率大2倍。
  12. 如权利要求7所述的制备方法，其特征在于，在各所述牺牲层两侧形成内部隔离部和在所述衬底上外延生长第一外延掺杂层和第二外延掺杂层，包括：
    去除所述两个侧墙下方的所述牺牲层；
    在各所述牺牲层两侧以及各所述沟道层两侧形成内部隔离部；
    在所述衬底上外延生长第一外延掺杂层和第二外延掺杂层，且所述第一外延掺杂层和第二外延掺杂层分别位于所述内部隔离部的外侧；
    去除位于各所述沟道层外侧的所述内部隔离部，保留位于各所述牺牲层两侧的所述内部隔离部。
PCT/CN2023/102928 2022-11-22 2023-06-27 一种环栅晶体管、其制备方法及电子设备 WO2024109030A1 (zh)

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