WO2024098708A1 - 三维半导体存储装置及其形成方法 - Google Patents

三维半导体存储装置及其形成方法 Download PDF

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Publication number
WO2024098708A1
WO2024098708A1 PCT/CN2023/094451 CN2023094451W WO2024098708A1 WO 2024098708 A1 WO2024098708 A1 WO 2024098708A1 CN 2023094451 W CN2023094451 W CN 2023094451W WO 2024098708 A1 WO2024098708 A1 WO 2024098708A1
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substrate
capacitor
forming
opening
dimensional semiconductor
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PCT/CN2023/094451
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English (en)
French (fr)
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李晓杰
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长鑫存储技术有限公司
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Publication of WO2024098708A1 publication Critical patent/WO2024098708A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a three-dimensional semiconductor memory device and a method for forming the same.
  • the integration of a two-dimensional semiconductor memory device is mainly determined by the area occupied by the memory cell, and therefore its integration is largely affected by the level of fine pattern formation technology.
  • a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells has been proposed recently.
  • an embodiment of the present disclosure provides a method for forming a three-dimensional semiconductor memory device, the method comprising:
  • the isolation structure separates the storage stack structure into a conductive line region and a storage region
  • Capacitor structures arranged in an array along a first direction and a second direction are formed in the capacitor region; a first electrode of the capacitor structure is exposed in the first opening; and the capacitor structure extends along a third direction;
  • a common terminal lead-out structure electrically connecting the first electrode of the capacitor structure to the substrate is formed in the first opening.
  • the method before forming the capacitor structure arranged in arrays along the first direction and the second direction in the capacitor region, the method further includes:
  • An active structure arranged in an array along the first direction and the second direction is formed in the transistor area in the storage area; the active structure extends along a third direction, and the active structure includes a first source and drain region, a channel region, and a second source and drain region; the second electrode of the capacitor structure is electrically connected to the first source and drain region in the active structure.
  • the method for forming the three-dimensional semiconductor memory device further includes:
  • the isolation structure is etched to form a second opening exposing the channel region; the isolation structure between the bottom of the second opening and the substrate constitutes a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer between the substrate and the storage stack structure;
  • a bit line structure is formed in the conductive line region, arranged along the first direction, extending along the second direction, and electrically connected to the second source and drain region.
  • the method for forming the three-dimensional semiconductor memory device further includes:
  • the isolation structure is etched to form a third opening exposing the second source and drain region; the isolation structure between the bottom of the third opening and the substrate constitutes a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer between the substrate and the storage stack structure;
  • bit line structures extending along the first direction in the third opening, wherein the bit line structures are electrically connected to the second source and drain regions;
  • a word line structure is formed in the conductive line region, which is arranged along the first direction, extends along the second direction, and is located at both sides of the channel region.
  • the capacitor structure is symmetrically distributed on both sides of the bit line structure along the third direction; or, the capacitor structure is distributed on one side of the bit line structure.
  • forming a common terminal lead-out structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate includes:
  • the conductive material is deposited on the adhesion layer to fill the first opening; the conductive material includes polysilicon.
  • forming an isolation structure in the storage stack structure includes:
  • An insulating material is filled in the isolation trench to form the isolation structure.
  • the storage stack structure includes dielectric layers and semiconductor layers alternately stacked along the first direction; the capacitor structure arranged in an array along the first direction and the second direction formed in the capacitor region includes:
  • the second electrode of the capacitor structure, a capacitor dielectric layer and the first electrode are sequentially formed on the surface of the semiconductor layer exposed by the first opening and the fourth opening.
  • forming a common terminal lead-out structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate includes:
  • the conductive material is filled in the first opening and between the capacitor structures to form the common terminal lead-out structure.
  • an embodiment of the present disclosure provides a three-dimensional semiconductor storage device, the three-dimensional semiconductor storage device comprising:
  • the storage structure includes capacitor structures arranged in an array along a first direction and a second direction; the capacitor structures extend along a third direction; the first direction is a thickness direction of the substrate, and the second direction and the third direction are both perpendicular to the first direction;
  • a common terminal lead-out structure wherein the bottom surface of the common terminal lead-out structure is lower than the top surface of the substrate; the common terminal lead-out structure is electrically connected to the first electrode of the capacitor structure and the substrate.
  • the storage structure further includes:
  • An active structure extending along the third direction; the active structure comprises a first source-drain region, a channel region and a second source-drain region sequentially arranged along the third direction; and the second electrode of the capacitor structure is electrically connected to the first source-drain region.
  • the three-dimensional semiconductor memory device further comprises:
  • a word line structure extending along the first direction; the word line structure is located on two opposite sides of the channel region along the second direction;
  • a shallow trench isolation structure is located between the word line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer; the initial oxide layer is located between the substrate and the storage structure;
  • the bit line structure is arranged along the first direction, extends along the second direction, and is electrically connected to the second source and drain region.
  • the three-dimensional semiconductor memory device further comprises:
  • bit line structure extending along the first direction; the bit line structure is electrically connected to the second source and drain region;
  • a shallow trench isolation structure is located between the bottom of the bit line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of the initial oxide layer; the initial oxide layer is located between the substrate and the storage structure;
  • the word line structure is arranged along the first direction, extends along the second direction, and is located at two sides of the channel region.
  • the capacitor structure is symmetrically distributed on both sides of the bit line structure along the third direction; or, the capacitor structure is located on one side of the bit line structure.
  • the three-dimensional semiconductor memory device further comprises:
  • a metal silicide layer located between the common terminal lead-out structure and the substrate;
  • the adhesive layer is located between the common terminal lead-out structure and the metal silicide layer; the material of the common terminal lead-out structure includes polysilicon.
  • the common electrode of the capacitor structure in the three-dimensional semiconductor storage device is electrically connected to the substrate by forming a common terminal lead-out structure, so that a common voltage can be provided to the capacitor structure through the substrate, reducing the number of power supply pads required for the bonding interface, and effectively improving the integration of the three-dimensional semiconductor storage device.
  • FIG1 is a schematic flow chart of a method for forming a three-dimensional semiconductor memory device according to an embodiment of the present disclosure
  • FIGS. 2a-2r are schematic structural diagrams of a process for forming a three-dimensional semiconductor storage device according to an embodiment of the present disclosure
  • FIG3 is a schematic structural diagram of a three-dimensional semiconductor storage device provided by another embodiment of the present disclosure.
  • 4a-4j are schematic structural diagrams of a process for forming a three-dimensional semiconductor memory device according to another embodiment of the present disclosure.
  • spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as “under other elements” or “under it” or “under it” will be oriented as “on” other elements or features. Therefore, the exemplary terms “under” and “under” may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.
  • the storage array and peripheral circuits of the three-dimensional semiconductor storage device can be formed in different wafers respectively, and a wafer bonding structure is formed by wafer bonding technology, thereby effectively improving the integration of the semiconductor storage device.
  • the bonding interface on the storage array wafer includes a plurality of bonding pads for wafer bonding and a plurality of power supply pads for providing a common voltage to the common electrode of the capacitor structure.
  • the density of the pads set on the bonding interface also increases, resulting in a large parasitic capacitance of the bonding interface, which will have a negative impact on the signal transmission between the storage array and the peripheral circuit.
  • the number of pads set on the bonding interface is also limited, which limits the improvement of the integration of the three-dimensional semiconductor storage device.
  • a word line structure or a bit line structure perpendicular to the substrate is usually formed by forming a word line opening or a bit line opening in a stacked structure and then filling it with a conductive material.
  • this formation method since the thickness of the initial oxide layer between the stacked structure and the substrate is relatively small, this formation method has the risk of penetrating the initial oxide layer and causing leakage between the word line structure or the bit line structure and the substrate.
  • the present disclosure proposes the following embodiments.
  • FIG1 is a flow chart of the method for forming a three-dimensional semiconductor storage device provided by the present disclosure. As shown in FIG1, the method for forming a three-dimensional semiconductor storage device includes the following steps:
  • Step 101 forming a storage stack structure on a substrate, and forming an isolation structure in the storage stack structure; the isolation structure separates the storage stack structure into a conductive line region and a storage region;
  • Step 102 etching the isolation structure to form a plurality of first openings exposing the capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate;
  • Step 103 forming capacitor structures arranged in an array along a first direction and a second direction in the capacitor region; a first electrode of the capacitor structure is exposed in the first opening; and the capacitor structure extends along a third direction;
  • Step 104 forming a common terminal lead-out structure in the first opening to electrically connect the first electrode of the capacitor structure to the substrate.
  • FIG. 2a to 2r are schematic diagrams of the structure of the process of forming a three-dimensional semiconductor storage device according to an embodiment of the present disclosure. Next, the method of forming a three-dimensional semiconductor storage device according to an embodiment of the present disclosure will be described in detail in conjunction with FIG. 1 and FIG. 2a to FIG. 2r.
  • a method for forming a three-dimensional semiconductor memory device includes: forming an initial stacking structure on a substrate 201 .
  • the substrate 201 can be a single semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, etc.
  • a single semiconductor material substrate for example, a silicon substrate, a germanium substrate, etc.
  • a compound semiconductor material substrate for example, a germanium silicon substrate, etc.
  • SOI silicon on insulator
  • GeOI germanium on insulator
  • the substrate 201 is a P-type substrate or an N-type substrate.
  • an initial oxide layer 202 is first formed on the substrate 201, and then an initial stack structure is formed on the initial oxide layer 202.
  • the initial stack structure includes semiconductor layers 203 and sacrificial layers 204 alternately stacked in a first direction.
  • the semiconductor layer 203 can be formed of a semiconductor material such as silicon, germanium, or indium gallium zinc oxide, and the sacrificial layer 204 can be formed of a material having a higher etching selectivity ratio relative to the semiconductor layer 203, for example, the sacrificial layer 203 can be formed of silicon germanium.
  • the initial stack structure includes semiconductor layers 203 and sacrificial layers 204 alternately stacked in a first direction
  • the method further includes removing the sacrificial layer 204 to expose a surface of the substrate 201 , and then forming an initial oxide layer 202 on the surface of the substrate 201 .
  • the first direction is the thickness direction of the substrate 201, that is, the Z direction
  • the second direction is the Y direction
  • the third direction is the The direction is the X direction
  • the second direction and the third direction are both perpendicular to the first direction
  • the second direction and the third direction are parallel to the top surface of the substrate 201 .
  • the method for forming a three-dimensional semiconductor memory device further includes: etching the initial stacking structure and the substrate 201 in a first direction to form a plurality of isolation trenches 205 that penetrate the initial stacking structure and extend into the substrate 201 .
  • FIG2b only takes the formation of four isolation trenches 205 in the initial stacking structure as an example, but the embodiments of the present disclosure are not limited thereto. For example, multiple isolation trenches 205 on only one side may also be formed.
  • the structure in FIG2c is a portion of the structure in FIG2b. In order to facilitate observation of the structure formed by subsequent steps, the subsequent steps are described below based on the structure in FIG2c.
  • the method for forming a three-dimensional semiconductor storage device further includes: after forming a plurality of isolation trenches 205 in the initial stacking structure, replacing the sacrificial layer 204 with a dielectric material to form a storage stacking structure in which semiconductor layers 203 and dielectric layers 206 are alternately stacked in a first direction.
  • the isolation trenches 205 separate the storage stacking structure into a conductive line region and a storage region, the conductive line region extends along the second direction, and the storage region is located on opposite sides of the conductive line region along the third direction.
  • the conductive line region is a formation region of a bit line structure
  • the storage region is a formation region of a storage unit
  • the storage unit includes a transistor structure and a capacitor structure
  • the storage region includes two parts symmetrically distributed relative to the conductive line region, each part includes a transistor region connected to the conductive line region and a capacitor region away from the conductive line region.
  • the method for forming a three-dimensional semiconductor memory device further includes: forming an active structure in the semiconductor layer 203 extending along the third direction in the transistor region by ion implantation, each active structure including a first source-drain region 207, a channel region 208, and a second source-drain region 209.
  • the first source-drain region 207 is used as one of the source region or the drain region
  • the second source-drain region 209 is used as the other of the source region or the drain region. As shown in FIG.
  • the active structures are arranged symmetrically relative to the conductive line region extending along the second direction, wherein the active structure located on one side of the conductive line region includes the first source-drain region 207, the channel region 208, and the second source-drain region 209 arranged in sequence along the third direction, and the active structure located on the other side of the conductive line region includes the second source-drain region 209, the channel region 208, and the first source-drain region 207 arranged in sequence along the third direction.
  • the first source-drain region 207 and the second source-drain region 209 in the active structure are N-type doped, and the channel region 208 is P-type doped.
  • the first source-drain region 207 and the second source-drain region 209 in the active structure are P-type doped, and the channel region 208 is N-type doped.
  • the method for forming a three-dimensional semiconductor memory device further includes: filling the plurality of isolation trenches 205 with an insulating material to form a plurality of isolation structures 210 .
  • the substrate exposed by the isolation trench 205 may be oxidized by a thermal oxidation process first, and then the remaining portion of the isolation trench 205 may be filled with an insulating material to form a plurality of isolation structures 210 .
  • one of the four isolation structures 210 shown in the figure is a perspective effect, which is convenient for observing the structure formed in subsequent steps.
  • an insulating material may be deposited in the isolation trench 205 by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to form the isolation structure 210, and the insulating material includes silicon oxide.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the remaining portion of the isolation trench 205 may be filled with an insulating material to form the isolation structure 210.
  • the method for forming a three-dimensional semiconductor memory device further includes: etching each isolation structure 210 in the first direction and stopping in the isolation structure 210 to form a second opening 211 exposing a plurality of channel regions 208 in the transistor region, the bottom surface of the second opening 211 may be lower than the bottom surface of the bottommost semiconductor layer 203, and the bottom surface of the second opening 211 may also be higher than the top surface of the substrate 201.
  • two columns of active structures arranged in the first direction are formed in the three-dimensional semiconductor memory device, and in the second direction, the second openings 211 are located on both sides of the channel region 208 in each column of active structures.
  • FIG2g is a cross-sectional view of FIG2f along line AA'. As shown in FIG2g, after etching the isolation structure 210 in the first direction, the remaining isolation structure 210 between the bottom of the second opening 211 and the substrate 201 forms a shallow trench isolation structure 212. The thickness T1 of the substrate 212 in the first direction is greater than the thickness T2 of the initial oxide layer 202 between the substrate 201 and the memory stack structure.
  • the method for forming a three-dimensional semiconductor memory device further includes: filling the second opening 211 with a conductive material to form a word line structure 213 extending along the first direction on the shallow trench isolation structure 212.
  • FIG. 2i is a cross-sectional view of FIG. 2h along line AA'. As shown in FIG. 2i, in a specific example, a gate dielectric layer 214 is first formed on one side of the second opening 211 close to the channel region 208, and then a conductive material is filled in the second opening 211 to form the word line structure 213.
  • a shallow trench isolation structure 212 is formed between the bottom of the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202.
  • the thickness T1 of the shallow trench isolation structure 212 in the first direction is 3 times the thickness T2 of the initial oxide layer 202.
  • the thickness T1 of the shallow trench isolation structure 212 in the first direction is 6 times the thickness T2 of the initial oxide layer 202.
  • the method for forming a three-dimensional semiconductor storage device also includes: removing the dielectric layer 206 exposed by the second opening 211 to obtain a suspended semiconductor layer 203, forming a gate dielectric layer 214 on the periphery of the channel region 208 exposed by the semiconductor layer 203, and then filling with conductive material to form a word line structure 213.
  • the word line structure 213 may also be located between the semiconductor layers 203 in the first direction.
  • an active structure is formed in the semiconductor layer 203 in the transistor area, and the active structure includes a first source and drain region 207, a channel region 208 and a second source and drain region 209.
  • a word line structure 213 extending along a first direction is formed next to the channel region 208 as a gate of the transistor structure.
  • a transistor structure is formed in the transistor area, and multiple transistor structures with the same word line structure 213 as a gate are arranged along the first direction.
  • word line openings are usually formed by etching a stacked structure.
  • the initial oxide layer on the substrate is relatively small, the initial oxide layer may be penetrated during the etching of the stacked structure, thereby causing leakage between the word line structure and the substrate.
  • an isolation structure 210 extending into the substrate 201 is first formed in the storage stack structure, and then the isolation structure 210 is etched in the first direction to form a second opening 211.
  • the isolation structure 210 between the bottom of the second opening 211 and the substrate 201 constitutes a shallow trench isolation structure 212.
  • the thickness T1 of the shallow trench isolation structure 212 in the first direction is greater than the thickness T2 of the initial oxide layer 202.
  • a conductive material is used to fill the second opening 211 to form a word line structure 213 on the shallow trench isolation structure 212.
  • the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 has a greater thickness, thereby preventing leakage between the word line structure 213 and the substrate 201, thereby effectively improving the reliability of the three-dimensional semiconductor storage device.
  • the conductive material forming the word line structure 213 may be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).
  • a doped semiconductor material e.g., doped silicon, doped germanium, etc.
  • a conductive metal nitride e.g., titanium nitride, tantalum nitride, etc.
  • a metal material e.g., tungsten, titanium, tantalum, etc.
  • a metal semiconductor compound e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.
  • the gate dielectric layer 214 may be formed of at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride, or include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride.
  • the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • the method for forming a three-dimensional semiconductor memory device further includes: forming a plurality of bit line structures 220 in the conductive line region extending along the second direction.
  • the bit line structures 220 extend along the second direction, are alternately arranged with the dielectric layer 206 in the first direction, and are electrically connected to the second source and drain regions 209 on both sides of the conductive line region.
  • the extending directions of the bit line structures 220 and the word line structures 213 are perpendicular to each other.
  • its channel region 208 is connected to a word line structure 213 extending along the first direction
  • its second source and drain region 209 is connected to a bit line structure 220 extending along the second direction.
  • the step of forming the bit line structure 220 includes: etching the conductive line region along the second direction to remove the semiconductor layer 203 extending along the second direction in the conductive line region, and filling the openings produced by the etching with a conductive material to form a plurality of bit line structures 220 extending along the second direction.
  • an isotropic etching process is used to form an opening extending along a certain direction in the isolation structure 210 or the stacked structure.
  • the method for forming a three-dimensional semiconductor memory device further includes: in a first The isolation structure 210 is etched in a third direction to form a plurality of first openings 240 exposing the capacitor region in the storage region and the substrate 201, wherein the bottom surface of the first opening 240 is lower than the top surface of the substrate 201 below the isolation structure 210; and the dielectric layer 206 extending along the third direction in the capacitor region is etched through the first openings 240 to form a plurality of fourth openings 230, wherein the fourth openings 230 are connected to the first openings 240.
  • the method for forming a three-dimensional semiconductor storage device also includes: after forming the fourth opening 230 and the first opening 240, forming a capacitor structure 231 on the surface of the semiconductor layer 203 exposed by the fourth opening 230 and the first opening 240, the capacitor structure 231 is symmetrically distributed on both sides of the bit line structure 220 along the third direction.
  • the embodiment of the present disclosure is only described by taking the example that the capacitor structure 231 is electrically connected to the first source and drain region 207, and the bit line structure 220 is electrically connected to the second source and drain region 209.
  • the second source and drain region 209 can also be electrically connected to the capacitor structure 231, and the first source and drain region 207 can be electrically connected to the bit line structure 220.
  • the cross section of the capacitor structure 231 shown in FIG. 21 is shown in FIG. 2m, and the step of forming the capacitor structure 231 includes: forming the second electrode 2311, the capacitor dielectric layer 2312 and the first electrode 2313 of the capacitor structure 231 in sequence around the end of the semiconductor layer 203.
  • the second electrode 2311 is electrically connected to the first source and drain region 207.
  • the cross section of the capacitor structure 231 is shown in FIG.
  • the step of forming the capacitor structure 231 includes: etching the semiconductor material layer 203 extending along the third direction in the capacitor region to form a plurality of capacitor openings; forming the second electrode 2314, the capacitor dielectric layer 2315 and the first electrode 2316 of the capacitor structure 231 in sequence in the capacitor openings; and the second electrode 2314 is electrically connected to the first source and drain region 207.
  • the isolation structure 210 is etched in the first direction to form a first opening 240 exposing the capacitor structure 231 and the substrate 201.
  • the fourth opening 230 and the first opening 240 may be formed first, and then the capacitor structure 231 as shown in FIG. 2m may be formed, or the capacitor opening and the capacitor structure 231 as shown in FIG. 2n may be formed first, and then the first opening 240 may be formed, and the present disclosure does not limit this.
  • the subsequent steps are described by taking the formation of the capacitor structure 231 as shown in FIG. 2m as an example.
  • a capacitor structure 231 is formed in the capacitor region in the storage region, and the second electrode 2311 of the capacitor structure 231 is electrically connected to the first source and drain region 207 of the transistor structure located in the same semiconductor layer 203, so that one capacitor structure 231 corresponds to one transistor structure electrically connected thereto, thereby forming a storage unit.
  • the storage units are arranged in an array along the first direction and the second direction, and together form a storage structure in a three-dimensional semiconductor storage device.
  • the method for forming a three-dimensional semiconductor memory device further includes: filling a plurality of first openings 240 with a conductive material to form a common terminal lead-out structure 241, wherein the common terminal lead-out structure 241 electrically connects the first electrode 2313 of the capacitor structure 231 to the substrate 201.
  • the bottom surface of the common terminal lead-out structure 241 may be flush with the bottom surfaces of the isolation structure 210 and the shallow trench isolation structure 212.
  • Figure 2p is a cross-sectional view of Figure 2o along line BB’.
  • the step of forming a common terminal lead-out structure 241 also includes: while filling the plurality of first openings 240 with a conductive material, filling the remaining portions of the plurality of fourth openings 230 with a conductive material, thereby, the common terminal lead-out structure 241 also includes a portion 241’ located between the two capacitor structures 231 in the first direction and extending along the third direction.
  • the step of forming the common terminal lead-out structure 241 further includes: sequentially forming a metal silicide layer 242 and an adhesive layer 243 on the surface of the substrate 201 exposed by the first opening 240, and depositing a conductive material on the adhesive layer 243 to fill the first opening 240.
  • the metal silicide layer 242 and the adhesive layer 243 can effectively reduce the contact resistance between the common terminal lead-out structure 241 and the substrate 201.
  • the bottom surface of the metal silicide layer 242 can be flush with the bottom surfaces of the isolation structure 210 and the shallow trench isolation structure 212.
  • the conductive material forming the common terminal lead-out structure 241 may be a doped semiconductor material (for example, doped polysilicon, doped germanium silicon, etc.); the material of the metal silicide layer 242 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesion layer 243 may be a conductive metal nitride (for example, titanium nitride, tantalum nitride, etc.).
  • the common electrode of the capacitor structure 231 is electrically connected to the substrate 201 by forming the common terminal lead-out structure 241, so that the common voltage can be provided to the common electrode of the capacitor structure 231 through the substrate 201. Therefore, in the process of forming the back-end interconnection layer, it is not necessary to provide a common voltage for the common electrode of the capacitor structure 231 in the bonding interface on the memory array wafer.
  • the power supply pads of the common voltage can reduce the density of the pads in the bonding interface and reduce the parasitic capacitance between the pads. In addition, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the storage array can be further increased, thereby improving the integration of the three-dimensional semiconductor storage device.
  • the common voltage may be half the power supply voltage, that is, the power supply voltage (VCC)/2.
  • a three-dimensional semiconductor storage device finally formed by the above method is shown in Figure 2r, and the three-dimensional semiconductor storage device includes multiple three-dimensional structures as shown in Figure 2o, and the storage structures are symmetrically distributed on both sides of the bit line structure 220.
  • the storage structure includes a storage unit composed of a transistor structure and a capacitor structure 231, and the storage unit is arranged in an array along a first direction and a second direction; a shallow trench isolation structure 212 is formed between the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202; the common terminal lead-out structure 241 electrically connects the first electrodes 2313 of the multiple capacitor structures 231 to the substrate 201.
  • the thickness T1 of the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 in the first direction is greater than the maximum distance between the storage structure and the substrate 201.
  • the maximum distance between the storage structure and the substrate 201 may be the distance between the bottom of the active structure closest to the substrate 201 and the substrate 201.
  • a three-dimensional semiconductor memory device as shown in FIG3 may also be formed by a method similar to the above-mentioned method for forming a three-dimensional semiconductor memory device.
  • a memory cell including a transistor structure and a capacitor structure 331 is formed on the same side of the bit line structure 320, and the active structure in the transistor structure includes a second source and drain region 309, a channel region 308, and a first source and drain region 307 arranged in sequence along the third direction.
  • the process of forming the three-dimensional semiconductor memory device is similar to the process of forming the three-dimensional semiconductor memory device shown in FIG2q, so the formation process thereof will not be described in detail.
  • FIGS. 4a to 4j are schematic diagrams of a three-dimensional semiconductor memory device forming process according to another embodiment of the present disclosure.
  • the differences between the three-dimensional semiconductor memory device forming method according to another embodiment of the present disclosure and the three-dimensional semiconductor memory device forming method shown in FIGS. 2a to 2r will be described in conjunction with FIGS. 1 and 4a to 4j.
  • FIG. 4 a to FIG. 4 j are only partial structures of the three-dimensional semiconductor memory device.
  • a method for forming a three-dimensional semiconductor storage device includes: forming an initial stacking structure on a substrate 401; forming a plurality of isolation trenches 405 and 405' that penetrate the initial stacking structure and extend into the substrate 401; and replacing the sacrificial layer in the initial stacking structure with a dielectric layer 406 to form a storage stacking structure.
  • the isolation trenches 405 and 405' extend into the substrate 401, separating the storage stacking structure into two mutually symmetrical parts, each of which includes a storage area and a conductive line area.
  • the conductive line area extends in the second direction and is a formation area of a word line structure;
  • the storage area is a formation area of a storage unit, the storage unit includes a transistor structure and a capacitor structure, and the storage area includes a transistor area cross-connected to the conductive line area and a capacitor area away from the conductive line area in a third direction.
  • the first direction is the thickness direction of the substrate 401, that is, the Z direction
  • the second direction is the Y direction
  • the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction.
  • the method for forming a three-dimensional semiconductor storage device also includes: forming an active structure in each semiconductor layer 403 extending along the third direction in the transistor area; the active structure includes a first source and drain region 407, a channel region 408, and a second source and drain region 409 arranged in sequence in the third direction, and the channel region 408 is located at the intersection of the conductive line region and the storage region.
  • the method for forming a three-dimensional semiconductor storage device also includes: filling the plurality of isolation trenches 405 and 405' with insulating material to form a plurality of isolation structures 410 and 410'; or first oxidizing the substrate 401 exposed by the isolation trenches 405 and 405' through a thermal oxidation process, and then filling the remaining portions of the isolation trenches 405 and 405' with insulating material to form a plurality of isolation structures 410 and 410'.
  • isolation structure 410' shown in the figure is a perspective effect, which is convenient for observing the structure formed in subsequent steps.
  • the method for forming a three-dimensional semiconductor memory device further includes: etching the isolation structure 410' in the first direction to form an exposed second source and drain region 409.
  • the third opening 420, the isolation structure 410' between the bottom of the third opening 420 and the substrate 401 constitutes a shallow trench isolation structure 412; the thickness T3 of the shallow trench isolation structure 412 in the first direction is greater than the thickness T4 of the initial oxide layer 402 between the substrate and the storage stack structure.
  • the thickness T3 of the shallow trench isolation structure 412 in the first direction is 3 times the thickness T4 of the initial oxide layer 402. In another specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 6 times the thickness T4 of the initial oxide layer 402.
  • the method for forming a three-dimensional semiconductor memory device further includes: filling the third opening 420 with a conductive material to form a bit line structure 421 extending along the first direction on the shallow trench isolation structure 412. As shown in FIG. 4e, the bit line structure 421 is electrically connected to the second source and drain regions 409 located on opposite sides thereof in the third direction.
  • the conductive material forming the bit line structure 421 may be one of a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).
  • a doped semiconductor material e.g., doped polysilicon, doped germanium, etc.
  • a conductive metal nitride e.g., titanium nitride, tantalum nitride, etc.
  • a metal material e.g., tungsten, titanium, tantalum, etc.
  • a metal semiconductor compound e.g., tungsten silicide, cobalt silicide, titanium silicide, etc
  • the method for forming a three-dimensional semiconductor memory device further includes: forming a plurality of word line structures 413 arranged along the first direction, extending along the second direction, and located on both sides of the channel region 408 in the conductive line region extending along the second direction, and the word line structures 413 and the bit line structures 421 extend in directions perpendicular to each other.
  • the specific structure of the word line structure 413 can be referred to FIG. 4j, in the first direction, a gate dielectric layer 414 is formed between the word line structure 413 and the channel region 408, and an insulating material is filled between two adjacent word line structures 413.
  • an active structure is formed in the semiconductor layer 403 in the transistor area in the storage area, the active structure including a first source and drain area 407, a channel area 408 and a second source and drain area 409, and a word line structure 413 is formed in the conductive line area extending along the second direction and located on opposite sides of the channel area 408 in the active structure along the first direction as a gate of the transistor structure.
  • a transistor structure is formed in the transistor area, and multiple transistor structures with the same word line structure 413 as the gate are arranged along the second direction.
  • the method for forming a three-dimensional semiconductor storage device also includes: etching a plurality of isolation structures 410 in a first direction to form a plurality of first openings 440 exposing the capacitor region and the substrate 401, wherein the bottom surface of the first openings 440 is lower than the top surface of the substrate 401 in the storage region; etching the dielectric layer 406 extending along the third direction of the capacitor region through the first openings 440 to form a plurality of fourth openings 430, and the fourth openings 430 are connected to the first openings 440.
  • the method for forming a three-dimensional semiconductor storage device further includes: forming a capacitor structure 431 on the surface of the semiconductor layer 403 exposed by the fourth opening 430 and the first opening 440, and the capacitor structure 431 is symmetrically distributed on both sides of the bit line structure 421 along the third direction.
  • the capacitor structure 431 is similar to the capacitor structure shown in FIG. 2m, including a second electrode 4311, a capacitor dielectric layer 4312 and a first electrode 4313 formed in sequence around the end of the semiconductor layer 403, wherein the first electrode 4313 is located at the outermost layer.
  • the embodiment of the present disclosure is only described by taking the capacitor structure 431 as an example of being electrically connected to the source region and the bit line structure 421 as an example of being electrically connected to the drain region.
  • the drain region can also be electrically connected to the capacitor structure 431, and the source region can be electrically connected to the bit line structure 421.
  • the step of forming the capacitor structure 431 includes: etching the semiconductor material layer 403 extending along the third direction in the capacitor region to form a plurality of capacitor openings; forming the capacitor structure 431 in the capacitor openings.
  • the capacitor structure 431 is similar to the capacitor structure shown in FIG. 2n. After forming the capacitor structure 431, etching the isolation structure 410 in the first direction to form a first opening 440 exposing the capacitor structure 431 and the substrate 401.
  • the fourth opening 430 and the first opening 440 may be formed first, and then the capacitor structure shown in FIG. 2m may be formed, or the capacitor opening and the capacitor structure shown in FIG. 2n may be formed first, and then the first opening 440 may be formed, and the present disclosure does not limit this.
  • the subsequent steps are described by taking the formation of the capacitor structure shown in FIG. 2m as an example.
  • a capacitor structure 431 is formed in the capacitor region in the storage region, and a second electrode 4311 of the capacitor structure 431 is electrically connected to a first source-drain region 407 of a transistor structure in the same semiconductor layer 403, thereby one capacitor structure 431 corresponds to one transistor structure electrically connected thereto, thereby forming one storage unit.
  • the storage units are arranged in an array along the first direction and the second direction, and together form a storage structure of a three-dimensional semiconductor storage device.
  • the method for forming a three-dimensional semiconductor storage device also includes: filling the remaining portions of the multiple first openings 440 and the fourth openings 430 with a conductive material to form a common terminal lead-out structure 441 that electrically connects the first electrodes 4313 of the multiple capacitor structures 431 to the substrate 401.
  • a three-dimensional semiconductor memory device finally formed by the above method is shown in Figure 4j.
  • the storage structure is symmetrically distributed on both sides of the bit line structure 421 along the third direction, and the storage structure includes a plurality of storage cells composed of a transistor structure and a capacitor structure 431, and arranged in an array along the first direction and the second direction; a shallow trench isolation structure 412 is formed between the bottom of the bit line structure 421 and the substrate 401, and its thickness T3 in the first direction is greater than the thickness T4 of the initial oxide layer 402; the common terminal lead-out structure 441 electrically connects the first electrodes 4313 of the plurality of capacitor structures 431 to the substrate 401.
  • a bit line opening (i.e., a third opening 420) exposing the second source and drain region 409 is formed in the isolation structure 410', and a shallow trench isolation structure 412 is formed between the bottom of the bit line opening and the substrate 401, wherein the thickness T3 of the bit line isolation structure 412 in the first direction is greater than the thickness T4 of the initial oxide layer, and then the bit line opening is filled with a conductive material to form a bit line structure 421 extending along the first direction.
  • this method forms a bit line structure 421 on a shallow trench isolation structure 412 having a larger thickness, which can effectively prevent leakage between the bit line structure 421 and the substrate 401, thereby improving the reliability of the three-dimensional semiconductor memory device.
  • the thickness T3 of the shallow trench isolation structure 412 between the bottom of the bit line structure 421 and the substrate 401 in the first direction is greater than the distance between the bottom of the active structure closest to the substrate 401 and the substrate 401.
  • leakage between the bit line structure 421 and the substrate 401 can be effectively prevented.
  • a common terminal lead-out structure 441 is formed to electrically connect the first electrodes 4313 of the plurality of capacitor structures 431 to the substrate 401, so that a common voltage can be provided to the common electrodes of the capacitor structures 431 through the substrate 401. Therefore, in the process of forming the back-end interconnection layer, it is not necessary to set a power supply pad for providing a common voltage to the common electrode of the capacitor structure 431 in the bonding interface on the memory array wafer, so that the density of the pads in the bonding interface can be reduced, and the parasitic capacitance between the pads can be reduced. Moreover, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the memory array can be further increased, and the integration of the three-dimensional semiconductor memory device can be improved.
  • the common voltage may be half of the power supply voltage, that is, VCC/2.
  • FIG2r is a three-dimensional diagram of a three-dimensional semiconductor storage device provided by an embodiment of the present disclosure.
  • the three-dimensional semiconductor storage device includes: a substrate 201; a storage structure located on the substrate 201; the storage structure includes capacitor structures 231 arranged in an array along a first direction and a second direction; the capacitor structures 231 all extend along a third direction; a common terminal lead-out structure 241, the bottom surface of the common terminal lead-out structure 241 is lower than the top surface of the substrate 201, and the common terminal lead-out structure 241 is electrically connected to the first electrode 2313 of the capacitor structure 231 and the substrate 201.
  • the first direction is the thickness direction of the substrate 201, that is, the Z direction
  • the second direction is the Y direction
  • the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction.
  • a three-dimensional semiconductor memory device includes: a substrate 201; an isolation structure 210 and a common terminal lead-out structure 241 located on the substrate 201; the isolation structure 210 and the common terminal lead-out structure 241 are arranged along a third direction;
  • the storage structure includes a transistor structure located in the isolation structure 210 and a capacitor structure 231 located in the common terminal lead structure 241; the transistor structure and the capacitor structure 231 constitute a storage unit;
  • the storage units are arranged in an array along a first direction and a second direction;
  • the transistor structure and the capacitor structure 231 both extend along the third direction;
  • the common terminal lead-out structure 241 is electrically connected to the first electrode 2313 of the capacitor structure 231 and the substrate 201 .
  • the transistor structure includes an active structure extending along a third direction, the active structure including a first source and drain region 207 , a channel region 208 , and a second source and drain region 209 arranged along the third direction.
  • the second electrode 2311 of the capacitor structure 231 is electrically connected to the first source and drain region 207 .
  • the three-dimensional semiconductor memory device further includes: a word line structure 213 extending along the first direction and located in the trench The channel region 208 is on opposite sides along the second direction; the shallow trench isolation structure 212 is located between the bottom of the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202; the bit line structure 220 extends along the second direction and is alternately arranged with the dielectric layer 206 in the first direction, and the bit line structure 220 is electrically connected to the second source and drain regions 209 on both sides.
  • the word line structure 213 serves as the gate of the transistor structure, and together with the active structure, constitutes a transistor structure, and the transistor structures with the same word line structure 213 as the gate are arranged along the first direction.
  • the first source and drain region 207 of a transistor structure is electrically connected to the second electrode 2311 of a capacitor structure 231, thereby constituting a storage unit.
  • the storage units are arranged in an array along the first direction and the second direction, and together constitute the storage structure of the three-dimensional semiconductor storage device.
  • the thickness T1 of the shallow trench isolation structure 212 in the first direction is 3 times the thickness T2 of the initial oxide layer 202. In another specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is 6 times the thickness T2 of the initial oxide layer 202.
  • the capacitor structures 231 are symmetrically distributed on two sides of the bit line structure 220 along the third direction.
  • the three-dimensional semiconductor memory device further includes: a metal silicide layer 242 and an adhesive layer 243 located between the common terminal lead-out structure 241 and the substrate 201 , wherein the adhesive layer 243 is located between the common terminal lead-out structure 241 and the metal silicide layer 242 .
  • the material of the common terminal lead-out structure 241 includes a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.); the material of the metal silicide layer 242 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 243 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The metal silicide layer 242 and the adhesive layer 243 may effectively reduce the contact resistance between the common terminal lead-out structure 241 and the substrate 201.
  • a doped semiconductor material e.g., doped polysilicon, doped germanium, etc.
  • the material of the metal silicide layer 242 may be tungsten silicide, cobalt silicide, titanium silicide, etc.
  • the material of the adhesive layer 243 may be a conductive metal nitride (e.g., titanium nitride, tant
  • the three-dimensional semiconductor memory device includes a common terminal lead-out structure 241 that electrically connects a plurality of first electrodes 2313 of capacitor structures 231 arrayed in a first direction and a second direction to a substrate 201 at the same time, so that the common electrode (i.e., the first electrode 2313) of the capacitor structure 231 can be connected to a common voltage through the substrate 201.
  • the setting of the power supply pad for providing a common voltage to the common electrode of the capacitor structure 231 can be omitted, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads.
  • the pad density in the bonding interface remains unchanged, the density of the capacitor structure 231 in the storage array can be further increased, thereby improving the integration of the three-dimensional semiconductor memory device.
  • the common voltage may be half of the power supply voltage, that is, VCC/2.
  • a shallow trench isolation structure 212 is formed between the bottom of the word line structure 213 and the substrate 201, and its thickness T1 in the first direction is greater than the thickness T2 of the initial oxide layer 202.
  • the thickness T1 of the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 in the first direction is greater than the maximum distance between the storage structure and the substrate 201.
  • the maximum distance between the storage structure and the substrate 201 may be the distance between the bottom of the active structure closest to the substrate 201 and the substrate 201.
  • FIG. 3 is a perspective view of another three-dimensional semiconductor memory device provided by an embodiment of the present disclosure.
  • the difference between this three-dimensional semiconductor memory device and the three-dimensional semiconductor memory device shown in FIG. 2q is that the capacitor structure 331 of this semiconductor memory device is distributed on the same side of the bit line structure 320.
  • FIG4j is a stereoscopic diagram of a three-dimensional semiconductor storage device provided by another embodiment of the present disclosure.
  • the three-dimensional semiconductor storage device includes: a substrate 401; a storage structure located on the substrate 401; the storage structure includes a plurality of capacitor structures 431 arranged in an array along a first direction and a second direction; the capacitor structures 431 all extend along a third direction, including a second electrode 4311, a capacitor dielectric layer 4312, and a first electrode 4313 that sequentially surround the end of the semiconductor layer 403; a common terminal lead-out structure 441, the bottom surface of the common terminal lead-out structure 441 is lower than the top surface of the substrate 401, and the common terminal lead-out structure 441 is electrically connected to the first electrode 4313 of the capacitor structure 431 and the substrate 401.
  • the first direction is the thickness direction of the substrate 401, that is, the Z direction
  • the second direction is the Y direction
  • the third direction is the X direction. Both the second direction and the third direction are perpendicular to the first direction.
  • the storage structure further includes an active structure extending along the third direction, the active structure including a first source and drain region 407 , a channel region 408 , and a second source and drain region 409 arranged along the third direction.
  • the second electrode 4311 of the capacitor structure 431 is electrically connected to the first source and drain region 407 .
  • the three-dimensional semiconductor storage device further includes: a bit line structure 421 extending along the first direction and electrically connected to the second source and drain region 409; a shallow trench isolation structure 412 located between the bottom of the bit line structure 421 and the substrate 401, and having a thickness T3 in the first direction greater than a thickness T4 of the initial oxide layer 402; and a word line structure 413 extending along the second direction, the word line structure 413 being arranged in the first direction and located on opposite sides of the channel region 408 along the first direction.
  • the word line structure 413 serves as the gate of the transistor structure, and together with the active structure, constitutes a transistor structure, and the transistor structures with the same word line structure 413 as the gate are arranged along the second direction.
  • the first source and drain region 407 of a transistor structure is electrically connected to the second electrode 4311 of a capacitor structure 431, thereby constituting a storage unit.
  • the storage units are arranged in an array along the first direction and the second direction, and together constitute a storage structure of a three-dimensional semiconductor storage device.
  • the thickness T3 of the shallow trench isolation structure 412 in the first direction is 3 times the thickness T4 of the initial oxide layer 402. In another specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 6 times the thickness T4 of the initial oxide layer 402.
  • a thickness T3 of the shallow trench isolation structure 412 in the first direction is greater than a distance between the bottom of the active structure closest to the substrate 401 and the substrate 401 .
  • the three-dimensional semiconductor memory device further includes a gate dielectric layer 414 located between the word line structure 413 and the channel region 408 .
  • the capacitor structures 431 are symmetrically distributed on both sides of the bit line structure 421 along the third direction.
  • the three-dimensional semiconductor memory device further includes: a metal silicide layer 442 and an adhesive layer 443 located between the common terminal lead-out structure 441 and the substrate 401 , wherein the adhesive layer 443 is located between the common terminal lead-out structure 441 and the metal silicide layer 442 .
  • the material of the common terminal lead-out structure 441 includes a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.); the material of the metal silicide layer 442 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 443 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).
  • the metal silicide layer 442 and the adhesive layer 443 may effectively reduce the contact resistance between the common terminal lead-out structure 441 and the substrate 401.
  • the three-dimensional semiconductor storage device includes a first electrode 4313 of a plurality of capacitor structures 431 arrayed along a first direction and a second direction, electrically connected to a common terminal lead-out structure 441 of a substrate 401 at the same time, so that the common electrode of the capacitor structure 431 can be connected to a common voltage through the substrate 401.
  • the setting of a power supply pad for providing a common voltage to the common electrode of the capacitor structure 431 can be omitted, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads.
  • a shallow trench isolation structure 412 is formed between the bottom of the bit line structure 421 and the substrate 401, and its thickness T3 in the first direction is greater than the thickness T4 of the initial oxide layer 402. Therefore, leakage between the bit line structure 421 and the substrate 401 can be prevented, thereby effectively improving the reliability of the three-dimensional semiconductor storage device.
  • the three-dimensional semiconductor memory device is a three-dimensional dynamic random access memory (DRAM).
  • DRAM three-dimensional dynamic random access memory
  • the common voltage may be half the power supply voltage, ie, VCC/2.
  • the common electrode of the arrayed capacitor structure can be electrically connected to the substrate by forming a common terminal lead-out structure, and a common voltage is provided to the capacitor structure through the substrate. Therefore, in the process of forming the back-end interconnection layer, the setting of the power supply pad for providing a common voltage to the common electrode of the capacitor structure can be omitted, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads. In addition, when the pad density in the bonding interface remains unchanged, the density of the capacitor structure in the storage array can be further increased, and the integration of the three-dimensional semiconductor storage device can be improved.
  • the three-dimensional semiconductor memory device has a word line structure or a bit line structure perpendicular to the substrate, and a word line opening or a bit line opening is formed in the isolation structure to form a shallow trench isolation structure between the word line structure and the substrate or between the bit line structure and the substrate, and the thickness of the shallow trench isolation structure is greater than the thickness of the initial oxide layer between the substrate and the stacked structure. Therefore, compared with the method of forming a word line opening or a bit line opening in a stacked structure, the method of forming a three-dimensional semiconductor memory device in the embodiment of the present disclosure can effectively avoid leakage between the word line structure or the bit line structure and the substrate, and significantly improve the reliability of the three-dimensional semiconductor memory device.
  • the method for forming a three-dimensional semiconductor memory device electrically connects the common electrode of the capacitor structure in the three-dimensional semiconductor memory device to the substrate by forming a common terminal lead-out structure, so that a common voltage can be provided to the capacitor structure through the substrate, reducing the number of power supply pads required for the bonding interface, and effectively improving the integration of the three-dimensional semiconductor memory device.

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Abstract

本公开提供了一种三维半导体存储装置及其形成方法，该方法包括：在衬底上形成堆叠结构，并在堆叠结构中形成隔离结构，隔离结构将堆叠结构分隔成导电线区域和存储区域；蚀刻隔离结构，以形成暴露存储区域中的电容区域和衬底的第一开口，第一开口的底面低于衬底的顶面；在电容区域形成电容结构，电容结构的第一电极暴露于第一开口中；在第一开口中形成将电容结构的第一电极电连接至衬底的公共端引出结构。

Description

三维半导体存储装置及其形成方法
相关申请的交叉引用
本公开基于申请号为202211391444.3、申请日为2022年11月07日、发明名称为“三维半导体存储装置及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种三维半导体存储装置及其形成方法。
背景技术
二维半导体存储装置的集成度主要由存储单元占据的面积决定，因此其集成度在很大程度上受精细图案形成技术水平的影响。为了克服精细图案技术水平对半导体存储装置集成度的限制，近来已经提出了包括三维布置的存储单元的三维半导体存储装置。
然而，传统的三维半导体存储装置及其形成方法仍存在一定的缺陷，如何进一步提高三维半导体存储装置的集成度和可靠性，成为了目前亟需解决的问题。
发明内容
本公开实施例的技术方案是这样实现的：
第一方面，本公开实施例提供一种三维半导体存储装置的形成方法，所述方法包括：
在衬底上形成存储堆叠结构，并在所述存储堆叠结构中形成隔离结构；所述隔离结构将所述存储堆叠结构分隔成导电线区域和存储区域；
蚀刻所述隔离结构，以形成暴露所述存储区域中的电容区域和所述衬底的多个第一开口；所述第一开口的底面低于所述衬底的顶面；
在所述电容区域形成沿第一方向和第二方向阵列排布的电容结构；所述电容结构的第一电极暴露于所述第一开口中；所述电容结构沿第三方向延伸；
在所述第一开口中形成将所述电容结构的第一电极电连接至所述衬底的公共端引出结构。
在一些实施例中，所述在所述电容区域形成沿所述第一方向和第二方向阵列排布的电容结构之前，还包括：
在所述存储区域中的晶体管区域形成沿所述第一方向和所述第二方向阵列排布的有源结构；所述有源结构沿第三方向延伸，所述有源结构包括第一源漏区、沟道区和第二源漏区；所述电容结构的第二电极与所述有源结构中的所述第一源漏区电连接。
在一些实施例中，所述三维半导体存储装置的形成方法还包括：
蚀刻所述隔离结构，以形成暴露所述沟道区的第二开口；所述第二开口的底部与所述衬底之间的隔离结构构成浅沟槽隔离结构；所述浅沟槽隔离结构在所述第一方向上的厚度大于所述衬底与所述存储堆叠结构之间的初始氧化层的厚度；
在所述第二开口中形成沿所述第一方向延伸的字线结构；
在所述导电线区域形成沿所述第一方向排布，沿所述第二方向延伸，并与所述第二源漏区电连接的位线结构。
在一些实施例中，所述三维半导体存储装置的形成方法还包括：
蚀刻所述隔离结构，以形成暴露所述第二源漏区的第三开口；所述第三开口的底部与所述衬底之间的隔离结构构成浅沟槽隔离结构；所述浅沟槽隔离结构在所述第一方向上的厚度大于所述衬底与所述存储堆叠结构之间的初始氧化层的厚度；
在所述第三开口中形成多个沿所述第一方向延伸的位线结构，所述位线结构与所述第二源漏区电连接；
在所述导电线区域中形成沿所述第一方向排布，沿所述第二方向延伸，并位于所述沟道区两侧的字线结构。
在一些实施例中，所述电容结构沿所述第三方向对称分布于所述位线结构两侧；或者，所述电容结构分布于所述位线结构一侧。
在一些实施例中，所述在所述第一开口中形成将所述电容结构的第一电极电连接至所述衬底的公共端引出结构，包括：
在所述第一开口暴露的所述衬底表面依次形成金属硅化物层和粘合层；
在所述粘合层上沉积所述导电材料以填充所述第一开口；所述导电材料包括多晶硅。
在一些实施例中，所述在所述存储堆叠结构中形成隔离结构，包括：
在所述第一方向上蚀刻初始堆叠结构，以形成多个贯穿所述初始堆叠结构并暴露所述衬底的隔离沟槽；
在所述隔离沟槽中填充绝缘材料以形成所述隔离结构。
在一些实施例中，所述存储堆叠结构包括沿所述第一方向交替层叠的介质层和半导体层；所述在所述电容区域形成沿所述第一方向和第二方向阵列排布的电容结构，包括：
在所述第三方向上蚀刻所述介质层，以形成暴露所述电容区域的所述半导体层的第四开口，所述第四开口与所述第一开口连通；
在所述第一开口和所述第四开口暴露的所述半导体层表面依次形成所述电容结构的所述第二电极、电容电介质层和所述第一电极。
在一些实施例中，所述在所述第一开口中形成将所述电容结构的第一电极电连接至所述衬底的公共端引出结构，包括：
在所述第一开口中及所述电容结构之间填充所述导电材料，以形成所述公共端引出结构。
第二方面，本公开实施例提供一种三维半导体存储装置，所述三维半导体存储装置包括：
衬底；
位于所述衬底上的存储结构；
所述存储结构包括沿第一方向和第二方向阵列排布的电容结构；所述电容结构沿第三方向延伸；所述第一方向为所述衬底的厚度方向，所述第二方向和所述第三方向均与所述第一方向垂直；
公共端引出结构，所述公共端引出结构的底面低于所述衬底的顶面；所述公共端引出结构与所述电容结构的第一电极和所述衬底电连接。
在一些实施例中，所述存储结构还包括：
沿所述第三方向延伸的有源结构；所述有源结构包括沿所述第三方向依次排列的第一源漏区、沟道区和第二源漏区；所述电容结构的第二电极与所述第一源漏区电连接。
在一些实施例中，所述三维半导体存储装置还包括：
字线结构，沿所述第一方向延伸；所述字线结构位于所述沟道区沿所述第二方向相对的两侧；
浅沟槽隔离结构，位于所述字线结构与所述衬底之间；所述浅沟槽隔离结构在所述第一方向上的厚度大于初始氧化层的厚度；所述初始氧化层位于所述衬底和所述存储结构之间；
位线结构，沿所述第一方向排布，沿所述第二方向延伸，并与所述第二源漏区电连接。
在一些实施例中，所述三维半导体存储装置还包括：
位线结构，沿所述第一方向延伸；所述位线结构与所述第二源漏区电连接；
浅沟槽隔离结构，位于所述位线结构的底部与所述衬底之间；所述浅沟槽隔离结构在所述第一方向上的厚度大于初始氧化层的厚度；所述初始氧化层位于所述衬底和所述存储结构之间；
字线结构，沿所述第一方向排布，沿所述第二方向延伸，并位于所述沟道区的两侧。
在一些实施例中，所述电容结构沿所述第三方向对称分布于所述位线结构的两侧；或者，所述电容结构位于所述位线结构的一侧。
在一些实施例中，所述三维半导体存储装置还包括：
金属硅化物层，位于所述公共端引出结构与所述衬底之间；
粘合层，位于所述公共端引出结构与所述金属硅化物层之间；所述公共端引出结构的材料包括多晶硅。
在本公开所提供的技术方案中，通过形成公共端引出结构将三维半导体存储装置中电容结构的公共电极电连接至衬底，从而可以通过衬底为电容结构提供公共电压，减少键合界面所需供电焊盘的数量，有效提高三维半导体存储装置的集成度。
附图说明
图1为本公开实施例提供的三维半导体存储装置形成方法的流程示意图；
图2a-2r为本公开实施例提供的三维半导体存储装置形成过程的结构示意图；
图3为本公开另一实施例提供的三维半导体存储装置的结构示意图；
图4a-4j为本公开另一实施例提供的三维半导体存储装置形成过程的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述术语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、 元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了提高半导体存储装置的存储容量，目前已提出包括三维布置的存储单元的三维半导体存储装置。三维半导体存储装置的存储阵列和外围电路可以分别形成在不同的晶圆中，并通过晶圆键合技术形成晶圆键合结构，从而有效提高半导体存储装置的集成度。在目前提出的晶圆键合结构中，存储阵列晶圆上的键合界面中包括多个用于晶圆键合的键合焊盘和多个用于为电容结构的公共电极提供公共电压的供电焊盘。随着存储阵列中电容结构数量的增加，键合界面上设置的焊盘的密度也随之增加，导致键合界面的寄生电容较大，从而会对存储阵列与外围电路之间的信号传输产生负面影响。同时，由于键合界面的面积有限，在键合界面上设置焊盘的数量也是有限的，这对三维半导体存储装置的集成度的提高产生了限制。
此外，在目前提出的三维半导体存储装置形成方法中，通常采用在堆叠结构中形成字线开口或位线开口后填充导电材料的方式形成与衬底垂直的字线结构或位线结构，然而，由于堆叠结构与衬底之间的初始氧化层的厚度较小，这种形成方法存在贯穿初始氧化层而导致字线结构或位线结构与衬底之间发生漏电的风险。
因此，需要进一步提高三维半导体存储装置的集成度和可靠性。对此，本公开提出了以下实施方式。
本公开实施例提供了一种三维半导体存储装置的形成方法。图1为本公开实施例提供的三维半导体存储装置形成方法的流程示意图。如图1所示，三维半导体存储装置的形成方法包括以下步骤：
步骤101：在衬底上形成存储堆叠结构，并在所述存储堆叠结构中形成隔离结构；所述隔离结构将所述存储堆叠结构分隔成导电线区域和存储区域；
步骤102：蚀刻所述隔离结构，以形成暴露所述存储区域中的电容区域和所述衬底的多个第一开口；所述第一开口的底面低于所述衬底的顶面；
步骤103：在所述电容区域形成沿第一方向和第二方向阵列排布的电容结构；所述电容结构的第一电极暴露于所述第一开口中；所述电容结构沿第三方向延伸；
步骤104：在所述第一开口中形成将所述电容结构的第一电极电连接至所述衬底的公共端引出结构。
图2a至图2r为本公开实施例提供的三维半导体存储装置形成过程的结构示意图。下面，将结合图1、图2a至图2r对本公开实施例提供的三维半导体存储装置的形成方法进行详细说明。
在一些实施例中，参照图2a，三维半导体存储装置的形成方法包括：在衬底201上形成初始堆叠结构。
在一些实施例中，衬底201可以为单质半导体材料衬底(例如为硅衬底、锗衬底等)、复合半导体材料衬底(例如为锗硅衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。
在一些实施例中，衬底201为P型衬底或者N型衬底。
在本公开实施例中，在衬底201上形成存储堆叠结构之前，先在衬底201上形成初始氧化层202，然后在初始氧化层202上形成初始堆叠结构。初始堆叠结构包括在第一方向上交替层叠的半导体层203和牺牲层204。半导体层203可以由硅、锗或铟镓锌氧化物等半导体材料形成，牺牲层204可以由相对于半导体层203具有较高蚀刻选择比的材料形成，例如，牺牲层203可以由锗化硅形成。
在一些实施例中，在衬底201上形成存储堆叠结构之后，初始堆叠结构包括在第一方向上交替层叠的半导体层203和牺牲层204，方法还包括去除牺牲层204以暴露衬底201表面，然后在衬底201表面形成初始氧化层202。
在本公开实施例中，第一方向为衬底201的厚度方向，即Z方向，第二方向为Y方向，第三 方向为X方向，第二方向和第三方向均与第一方向垂直，且第二方向和第三方向平行于衬底201的顶面。
在一些实施例中，结合图2a和图2b所示，三维半导体存储装置的形成方法还包括：在第一方向上蚀刻初始堆叠结构和衬底201，以形成多个贯穿初始堆叠结构并延伸至衬底201中的隔离沟槽205。
需要说明的是，图2b仅以在初始堆叠结构中形成四个隔离沟槽205为例，但本公开实施例不限于此，例如，还可以仅形成单侧的多个隔离沟槽205。图2c中的结构为图2b中结构的一部分，为了便于观察通过后续步骤形成的结构，下面以图2c中的结构为基础对后续步骤进行描述。
在一些实施例中，结合图2c和图2d所示，三维半导体存储装置的形成方法还包括：在初始堆叠结构中形成多个隔离沟槽205后，使用介质材料替换牺牲层204，以形成半导体层203和介质层206在第一方向上交替层叠的存储堆叠结构。如图2d所示，隔离沟槽205将存储堆叠结构分隔成导电线区域和存储区域，导电线区域沿第二方向延伸，存储区域位于导电线区域沿第三方向的相对两侧。导电线区域为位线结构的形成区域，存储区域为存储单元的形成区域，存储单元包括晶体管结构和电容结构，存储区域包括相对于导电线区域对称分布的两个部分，每个部分包括与导电线区域相连的晶体管区域和远离导电线区域的电容区域。
在一些实施例中，三维半导体存储装置的形成方法还包括：通过离子注入在晶体管区域中沿第三方向延伸的半导体层203中形成有源结构，每个有源结构包括第一源漏区207、沟道区208和第二源漏区209。第一源漏区207用于作为源区或漏区其中的一者，第二源漏区209用于作为源区或漏区中的另一者。如图2d所示，有源结构相对于沿第二方向延伸的导电线区域对称排布，其中，位于导电线区域一侧的有源结构包括沿第三方向依次排列的第一源漏区207、沟道区208和第二源漏区209，位于导电线区域另一侧的有源结构包括沿第三方向依次排列的第二源漏区209、沟道区208和第一源漏区207。
在一具体示例中，有源结构中的第一源漏区207和第二源漏区209为N型掺杂，沟道区208为P型掺杂。在另一具体示例中，有源结构中的第一源漏区207和第二源漏区209为P型掺杂，沟道区208为N型掺杂。
在一些实施例中，结合图2d和图2e所示，三维半导体存储装置的形成方法还包括：使用绝缘材料填充多个隔离沟槽205，以形成多个隔离结构210。
在另一些实施例中，还可以先通过热氧化工艺氧化隔离沟槽205暴露的衬底，然后使用绝缘材料填充隔离沟槽205的剩余部分，以形成多个隔离结构210。
需要说明的是，图中所示的四个隔离结构210中的一个为透视后的效果，便于观察通过后续步骤形成的结构。
在一具体示例中，可以通过低压化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)、等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)或原子层沉积法(Atom Layer Deposition，ALD)在隔离沟槽205中沉积绝缘材料以形成隔离结构210，绝缘材料包括氧化硅。在另一具体示例中，还可以在通过热氧化工艺氧化隔离沟槽205暴露的衬底201后，使用绝缘材料填充隔离沟槽205的剩余部分，以形成隔离结构210。
在一些实施例中，结合图2e和图2f所示，三维半导体存储装置的形成方法还包括：在第一方向上蚀刻每个隔离结构210并停止在隔离结构210中，以形成暴露晶体管区域中多个沟道区208的第二开口211，第二开口211的底面可低于最下层的半导体层203的底面，且第二开口211的底面还可高于衬底201的顶面。参照图2f，三维半导体存储装置中形成有两列在第一方向上排布的有源结构，在第二方向上，第二开口211位于每列有源结构中沟道区208的两侧。
图2g为图2f沿AA’线的截面图，如图2g所示，在第一方向上蚀刻隔离结构210后，第二开口211的底部与衬底201之间剩余的隔离结构210构成浅沟槽隔离结构212，浅沟槽隔离结构 212在第一方向上的厚度T1大于衬底201与存储堆叠结构之间初始氧化层202的厚度T2。
在一些实施例中，结合图2f和图2h所示，三维半导体存储装置的形成方法还包括：使用导电材料填充第二开口211以在浅沟槽隔离结构212上形成沿第一方向延伸的字线结构213。图2i为图2h沿AA’线的截面图，如图2i所示，在一具体示例中，先在第二开口211中靠近沟道区208的一侧形成栅极介质层214，然后在第二开口211中填充导电材料以形成字线结构213。字线结构213的底部与衬底201之间形成有浅沟槽隔离结构212，其在第一方向上的厚度T1大于初始氧化层202的厚度T2。在一具体示例中，浅沟槽隔离结构212的在第一方向上的厚度T1是初始氧化层202厚度T2的3倍。在另一具体示例中，浅沟槽隔离结构212在第一方向上的厚度T1是初始氧化层202厚度T2的6倍。
在一些实施例中，三维半导体存储装置的形成方法还包括：去除第二开口211暴露的介质层206，以得到悬空的半导体层203，在半导体层203暴露的沟道区208的外周形成栅极介质层214，再填充导电材料以形成字线结构213，字线结构213还可位于第一方向上的半导体层203之间。
在本公开实施例中，在晶体管区域中的半导体层203中形成有源结构，有源结构包括第一源漏区207、沟道区208和第二源漏区209，在沟道区208旁形成沿第一方向延伸的字线结构213，作为晶体管结构的栅极，由此，在晶体管区域中形成了晶体管结构，以同一个字线结构213作为栅极的多个晶体管结构沿第一方向排布。
在目前已提出的三维半导体存储装置的形成方法中，通常采用蚀刻堆叠结构的方法形成字线开口，然而，由于衬底上初始氧化层的厚度较小，蚀刻堆叠结构的过程中可能造成初始氧化层被贯穿，从而导致字线结构与衬底之间发生漏电。
在本公开实施例中，先在存储堆叠结构中形成延伸至衬底201中的隔离结构210，然后在第一方向上对隔离结构210进行蚀刻以形成第二开口211，第二开口211的底部与衬底201之间的隔离结构210构成浅沟槽隔离结构212，浅沟槽隔离结构212在第一方向上的厚度T1大于初始氧化层202的厚度T2，接着使用导电材料填充第二开口211以在浅沟槽隔离结构212上形成字线结构213，由此，字线结构213的底部与衬底201之间的浅沟槽隔离结构212具有较大的厚度，从而可以防止字线结构213与衬底201之间发生漏电，有效提高三维半导体存储装置的可靠性。
在一些实施例中，形成字线结构213的导电材料可以是掺杂半导体材料(例如，掺杂硅、掺杂锗等)、导电金属氮化物(例如，氮化钛、氮化钽等)、金属材料(例如，钨、钛、钽等)和金属半导体化合物(例如，硅化钨、硅化钴、硅化钛等)中的一种。栅极介质层214可以由高介电常数材料、氧化硅、氮化硅和氮氧化硅中的至少一种形成，或者包括高介电常数材料、氧化硅、氮化硅和氮氧化硅中的至少一种。其中，高介电常数材料可以包括氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化锂、氧化铝、氧化铅钪钽和铌酸铅锌中的至少一种。
在一些实施例中，如图2j所示，三维半导体存储装置的形成方法还包括：在沿第二方向延伸的导电线区域形成多个位线结构220。位线结构220沿第二方向延伸，与介质层206在第一方向上交替排布，并与导电线区域两侧的第二源漏区209电连接。位线结构220与字线结构213的延伸方向相互垂直，对于一个有源结构，其沟道区208与一个沿第一方向延伸的字线结构213相连，其第二源漏区209与一个沿第二方向延伸的位线结构220相连。
在一具体示例中，结合图2h和图2j所示，形成位线结构220的步骤包括：沿第二方向蚀刻导电线区域以除去导电线区域中沿第二方向延伸的半导体层203，使用导电材料填充蚀刻产生的开口，以形成多个沿第二方向延伸的位线结构220。
在本公开实施例中，采用各向同性的蚀刻工艺，以在隔离结构210或堆叠结构中形成沿某一个方向延伸的开口。
在一些实施例中，结合图2j和图2k所示，三维半导体存储装置的形成方法还包括：在第一 方向上蚀刻隔离结构210，以形成暴露存储区域中电容区域以及衬底201的多个第一开口240，第一开口240的底面低于衬底201在隔离结构210下方的顶面；通过第一开口240蚀刻电容区域中沿第三方向延伸的介质层206，以形成多个第四开口230，第四开口230与第一开口240连通。
在一些实施例中，如图2l所示，三维半导体存储装置的形成方法还包括：在形成第四开口230和第一开口240后，在由第四开口230和第一开口240暴露的半导体层203表面形成电容结构231，电容结构231沿第三方向对称分布于位线结构220的两侧。
需要说明的是，本公开实施例仅以电容结构231与第一源漏区207电连接，位线结构220与第二源漏区209电连接为例进行说明。在一些实施例中，还可以使第二源漏区209与电容结构231电连接，第一源漏区207与位线结构220电连接。
在一具体示例中，图2l所示的电容结构231的截面如图2m所示，形成电容结构231的步骤包括：围绕半导体层203的末端依次形成电容结构231的第二电极2311、电容电介质层2312和第一电极2313。其中，第二电极2311与第一源漏区207电连接。在另一具体示例中，电容结构231的截面如图2n所示，形成电容结构231的步骤包括：蚀刻电容区域中沿第三方向延伸的半导体材料层203，以形成多个电容开口；在电容开口中依次形成电容结构231的第二电极2314、电容介质层2315和第一电极2316；第二电极2314与第一源漏区207电连接。在形成电容结构231后，在第一方向上蚀刻隔离结构210，以形成暴露电容结构231和衬底201的第一开口240。
需要说明的是，在本公开的实施例中，可以先形成第四开口230和第一开口240，再形成如图2m所示的电容结构231，也可以先形成电容开口和如图2n所示的电容结构231，再形成第一开口240，本公开对此不作限制。在以下实施例中，以形成图2m所示的电容结构231为例进行后续步骤的说明。
在本公开实施例中，在存储区域中的电容区域中形成了电容结构231，电容结构231的第二电极2311与位于同一半导体层203的晶体管结构的第一源漏区207电连接，由此，一个电容结构231对应于一个与之电连接的晶体管结构，从而构成一个存储单元。存储单元沿第一方向和第二方向阵列排布，共同构成三维半导体存储装置中的存储结构。
在一些实施例中，结合图2l和图2o所示，三维半导体存储装置的形成方法还包括：使用导电材料填充多个第一开口240以形成公共端引出结构241，公共端引出结构241将电容结构231的第一电极2313电连接至衬底201。公共端引出结构241的底面可与隔离结构210和浅沟槽隔离结构212的底面齐平。
在一具体示例中，图2p为图2o沿BB’线的截面图，如图2p所示，形成公共端引出结构241的步骤还包括：在使用导电材料填充多个第一开口的240的同时，使用导电材料填充多个第四开口230的剩余部分，由此，公共端引出结构241还包括在第一方向上位于两个电容结构231之间，并沿第三方向延伸的部分241’。
在一具体示例中，结合图2l和图2q所示，形成公共端引出结构241的步骤还包括：在第一开口240暴露的衬底201表面依次形成金属硅化物层242和粘合层243，在粘合层243上沉积导电材料以填充第一开口240。金属硅化物层242和粘合层243可以有效降低公共端引出结构241与衬底201之间的接触电阻。金属硅化物层242的底面可与隔离结构210和浅沟槽隔离结构212的底面齐平。
在本公开实施例中，形成公共端引出结构241的导电材料可以是掺杂半导体材料(例如，掺杂多晶硅、掺杂锗硅等)；金属硅化物层242的材料可以是硅化钨、硅化钴、硅化钛等；粘合层243的材料可以是导电金属氮化物(例如，氮化钛、氮化钽等)。
在本公开实施例中，通过形成公共端引出结构241将电容结构231的公共电极电连接至衬底201，从而可以通过衬底201为电容结构231的公共电极提供公共电压。由此，在后端互连层的形成过程中，不需要在存储阵列晶圆上的键合界面中设置用于为电容结构231的公共电极提供公 共电压的供电焊盘，从而可以降低键合界面中焊盘的密度，减小焊盘之间的寄生电容。此外，在键合界面中焊盘密度保持不变的情况下，可以进一步增大存储阵列中电容结构的密度，从而提高三维半导体存储装置的集成度。
在本公开实施例中，公共电压的大小可以为电源电压的一半，即电源电压(VCC)/2。
在一些实施例中，通过上述方法最终形成的三维半导体存储装置如图2r所示，该三维半导体存储装置包括多个图2o所示的立体结构，存储结构对称分布于位线结构220的两侧，存储结构包括由晶体管结构和电容结构231构成的存储单元，存储单元沿第一方向和第二方向阵列排布；字线结构213与衬底201之间形成有浅沟槽隔离结构212，其在第一方向上的厚度T1大于初始氧化层202的厚度T2；公共端引出结构241将多个电容结构231的第一电极2313电连接至衬底201。
在一些实施例中，字线结构213的底部与衬底201之间的浅沟槽隔离结构212在第一方向上的厚度T1大于存储结构与衬底201之间的最大距离。这里，存储结构与衬底201之间的最大距离可以为最接近衬底201的有源结构的底部与衬底201之间的距离。由此，可以有效防止字线结构213与衬底201之间产生漏电。
在一些实施例中，通过与上述三维半导体存储装置的形成方法类似的方法还可以形成如图3所示的三维半导体存储装置。在该三维半导体存储装置的形成过程中，在位线结构320的同一侧形成包括晶体管结构和电容结构331的存储单元，晶体管结构中的有源结构包括沿第三方向依次排列的第二源漏区309、沟道区308和第一源漏区307。该三维半导体存储装置的形成过程与图2q所示的三维半导体存储装置的形成过程类似，因此对其形成过程不再赘述。
图4a至图4j为本公开另一实施例提供的三维半导体存储装置形成过程的结构示意图。下面，将结合图1、图4a至图4j对本公开另一实施例提供的三维半导体存储装置的形成方法中与图2a至图2r所示的三维半导体存储装置形成方法的不同之处进行说明。
需要说明的是，为了便于观察三维半导体存储装置的形成过程，图4a至图4j所示的结构仅为三维半导体存储装置中的部分结构。
在一些实施例中，参照图4a，三维半导体存储装置的形成方法包括：在衬底401上形成初始堆叠结构；形成贯穿初始堆叠结构并延伸至衬底401中的多个隔离沟槽405和405’；使用介质层406替换初始堆叠结构中的牺牲层，以形成存储堆叠结构。隔离沟槽405和405’延伸至衬底401中，将存储堆叠结构分隔为相互对称的两个部分，每个部分包括存储区域和导电线区域。导电线区域延第二方向延伸，为字线结构的形成区域；存储区域为存储单元的形成区域，存储单元包括晶体管结构和电容结构，存储区域包括与导电线区域交叉相连的晶体管区域和在第三方向上远离导电线区域的电容区域。
在本公开实施例中，第一方向为衬底401的厚度方向，即Z方向，第二方向为Y方向，第三方向为X方向，第二方向和第三方向均与第一方向垂直。
在一些实施例中，参照图4a，三维半导体存储装置的形成方法还包括：在晶体管区域中沿第三方向延伸的每个半导体层403中形成有源结构；有源结构包括在第三方向上依次排列的第一源漏区407、沟道区408和第二源漏区409，沟道区408位于导电线区域和存储区域的交叉处。
在一些实施例中，结合图4a和图4b所示，三维半导体存储装置的形成方法还包括：使用绝缘材料填充多个隔离沟槽405和405’，以形成多个隔离结构410和410’；或先通过热氧化工艺氧化隔离沟槽405和405’暴露的衬底401，然后使用绝缘材料填充隔离沟槽405和405’的剩余部分，以形成多个隔离结构410和410’。
需要说明的是，图中所示的隔离结构410’为透视后的效果，便于观察通过后续步骤形成的结构。
在一些实施例中，结合图4b至4d所示，其中，图4d为图4c沿AA’线的截面图，三维半导体存储装置的形成方法还包括：在第一方向上蚀刻隔离结构410’，形成暴露第二源漏区409的 第三开口420，第三开口420的底部与衬底401之间的隔离结构410’构成浅沟槽隔离结构412；浅沟槽隔离结构412在第一方向上的厚度T3大于衬底与存储堆叠结构之间初始氧化层402的厚度T4。在一具体示例中，浅沟槽隔离结构412在第一方向上的厚度T3是初始氧化层402厚度T4的3倍。在另一具体示例中，浅沟槽隔离结构412在第一方向上的厚度T3是初始氧化层402厚度T4的6倍。
在一些实施例中，结合图4c和图4e所示，三维半导体存储装置的形成方法还包括：使用导电材料填充第三开口420，以在浅沟槽隔离结构412上形成沿第一方向延伸的位线结构421。如图4e所示，位线结构421与位于其在第三方向上相对两侧的第二源漏区409电连接。在一些实施例中，形成位线结构421的导电材料可以是掺杂半导体材料(例如，掺杂多晶硅、掺杂锗等)、导电金属氮化物(例如，氮化钛、氮化钽等)、金属材料(例如，钨、钛、钽等)和金属半导体化合物(例如，硅化钨、硅化钴、硅化钛等)中的一种。
在一些实施例中，结合图4e和图4f所示，三维半导体存储装置的形成方法还包括：在沿第二方向延伸的导电线区域形成多个沿第一方向排布，沿第二方向延伸，并位于沟道区408两侧的字线结构413，字线结构413与位线结构421的延伸方向相互垂直。需要说明的是，字线结构413的具体结构可以参照图4j，在第一方向上，字线结构413与沟道区408之间形成有栅极介质层414，且在相邻的两个字线结构413之间填充有绝缘材料。
在本公开实施例中，在存储区域中的晶体管区域中的半导体层403中形成有源结构，有源结构包括第一源漏区407、沟道区408和第二源漏区409，在沿第二方向延伸的导电线区域中形成位于有源结构中沟道区408沿第一方向的相对两侧的字线结构413，作为晶体管结构的栅极，由此，在晶体管区域中形成了晶体管结构，以同一个字线结构413作为栅极的多个晶体管结构沿第二方向排布。
在一些实施例中，结合图4f和图4g所示，三维半导体存储装置的形成方法还包括：在第一方向上蚀刻多个隔离结构410，以形成暴露电容区域和衬底401的多个第一开口440，第一开口440的底面低于衬底401在存储区域的顶面；通过第一开口440蚀刻电容区域沿第三方向延伸的介质层406，以形成多个第四开口430，第四开口430与第一开口440连通。
在一些实施例中，结合图4g和图4h所示，三维半导体存储装置的形成方法还包括：在由第四开口430和第一开口440暴露的半导体层403表面形成电容结构431，电容结构431沿第三方向对称分布于位线结构421的两侧。这里，电容结构431与图2m所示的电容结构类似，包括围绕半导体层403的末端依次形成的第二电极4311、电容电介质层4312和第一电极4313，其中，第一电极4313位于最外层。需要说明的是，本公开实施例仅以电容结构431与源区电连接，位线结构421与漏区电连接为例进行说明。在一些实施例中，还可以使漏区与电容结构431电连接，源区与位线结构421电连接。
在一些实施例中，形成电容结构431的步骤包括：蚀刻电容区域中沿第三方向延伸的半导体材料层403，以形成多个电容开口；在电容开口中形成电容结构431。这里，电容结构431与图2n所示的电容结构类似。在形成电容结构431后，在第一方向上蚀刻隔离结构410，以形成暴露电容结构431和衬底401的第一开口440。
需要说明的是，在本公开的实施例中，可以先形成第四开口430和第一开口440，再形成图2m所示的电容结构，也可以先形成电容开口和图2n所示的电容结构，再形成第一开口440，本公开对此不作限制。在以下实施例中，以形成图2m所示的电容结构为例进行后续步骤的说明。
在本公开实施例中，在存储区域中的电容区域中形成电容结构431，电容结构431的第二电极4311与同一半导体层403中晶体管结构的第一源漏区407电连接，由此，一个电容结构431对应于一个与之电连接的晶体管结构，从而构成一个存储单元。存储单元沿第一方向和第二方向阵列排布，共同构成三维半导体存储装置的存储结构。
在一些实施例中，结合图4h和图4i所示，三维半导体存储装置的形成方法还包括：使用导电材料填充多个第一开口440和第四开口430的剩余部分，以形成将多个电容结构431的第一电极4313电连接至衬底401的公共端引出结构441。
在一些实施例中，通过上述方法最终形成的三维半导体存储装置如图4j所示，在该三维半导体存储装置中，存储结构沿第三方向对称分布于位线结构421的两侧，存储结构包括多个由晶体管结构和电容结构431构成，且沿第一方向和第二方向阵列排布的存储单元；位线结构421的底部与衬底401之间形成有浅沟槽隔离结构412，其在第一方向上的厚度T3大于初始氧化层402的厚度T4；公共端引出结构441将多个电容结构431的第一电极4313电连接至衬底401。
上述三维半导体存储装置的形成过程中，在隔离结构410’中形成暴露第二源漏区409的位线开口(即第三开口420)，在位线开口底部与衬底401之间形成了浅沟槽隔离结构412，其在第一方向上的厚度T3大于初始氧化层的厚度T4，接着使用导电材料填充位线开口，以形成沿第一方向延伸的位线结构421。相较于在堆叠结构中形成位线开口的方法，该方法在具有较大厚度的浅沟槽隔离结构412上形成位线结构421，能够有效防止位线结构421与衬底401之间发生漏电，提高三维半导体存储装置的可靠性。
在一些实施例中，位线结构421的底部与衬底401之间的浅沟槽隔离结构412在第一方向上的厚度T3大于最接近衬底401的有源结构的底部与衬底401之间的距离。由此，可以有效防止位线结构421与衬底401之间产生漏电。
此外，通过上述三维半导体存储装置的形成方法，形成了将多个电容结构431的第一电极4313电连接至衬底401的公共端引出结构441，从而可以通过衬底401为电容结构431的公共电极提供公共电压。由此，在后端互连层的形成过程中，不需要在存储阵列晶圆上的键合界面中设置用于为电容结构431的公共电极提供公共电压的供电焊盘，从而可以降低键合界面中焊盘的密度，减小焊盘之间的寄生电容。并且，在键合界面中焊盘密度保持不变的情况下，可以进一步增大存储阵列中电容结构的密度，提高三维半导体存储装置的集成度。
在本公开实施例中，公共电压的大小可以为电源电压的一半，即VCC/2。
基于前述三维半导体存储装置的形成方法相同的技术构思，本公开实施例提供一种三维半导体存储装置。图2r为本公开实施例提供的三维半导体存储装置的立体图。如图2r所示，三维半导体存储装置包括：衬底201；位于衬底201上的存储结构；存储结构包括沿第一方向和第二方向阵列排布的电容结构231；电容结构231均沿第三方向延伸；公共端引出结构241，公共端引出结构241的底面低于衬底201的顶面，公共端引出结构241与电容结构231的第一电极2313和衬底201电连接。
在本公开实施例中，第一方向为衬底201的厚度方向，即Z方向，第二方向为Y方向，第三方向为X方向，第二方向和第三方向均与第一方向垂直。
在一些实施例中，三维半导体存储装置包括：衬底201；位于衬底201上的隔离结构210和公共端引出结构241；隔离结构210和公共端引出结构241沿第三方向排布；
存储结构；存储结构包括位于隔离结构210中的晶体管结构和位于公共端引出结构241中的电容结构231；晶体管结构和电容结构231构成存储单元；
存储单元沿第一方向和第二方向呈阵列排布；
晶体管结构和电容结构231均沿第三方向延伸；
公共端引出结构241与电容结构231的第一电极2313和衬底201电连接。
在一些实施例中，晶体管结构包括：沿第三方向延伸的有源结构，有源结构包括沿第三方向排列的第一源漏区207、沟道区208和第二源漏区209。电容结构231的第二电极2311与第一源漏区207电连接。
在一些实施例中，三维半导体存储装置还包括：字线结构213，沿第一方向延伸，且位于沟 道区208沿第二方向相对的两侧；浅沟槽隔离结构212，位于字线结构213的底部与衬底201之间，其在第一方向上的厚度T1大于初始氧化层202的厚度T2；位线结构220，沿第二方向延伸，与介质层206在第一方向上交替排布，位线结构220与两侧的第二源漏区209电连接。
在本公开实施例中，字线结构213作为晶体管结构的栅极，与有源结构共同构成晶体管结构，以同一个字线结构213作为栅极的晶体管结构沿第一方向排布。在第三方向上，一个晶体管结构的第一源漏区207与一个电容结构231的第二电极2311电连接，由此，构成一个存储单元。存储单元沿第一方向和第二方向阵列排布，共同构成三维半导体存储装置的存储结构。
在一具体示例中，浅沟槽隔离结构212的在第一方向上的厚度T1是初始氧化层202厚度T2的3倍。在另一具体示例中，浅沟槽隔离结构212在第一方向上的厚度T1是初始氧化层202厚度T2的6倍。
在一些实施例中，电容结构231沿第三方向对称分布于位线结构220的两侧。
在一些实施例中，三维半导体存储装置还包括：位于公共端引出结构241与衬底201之间的金属硅化物层242和粘合层243，其中粘合层243位于公共端引出结构241与金属硅化物层242之间。
在本公开实施例中，公共端引出结构241的材料包括掺杂半导体材料(例如，掺杂多晶硅、掺杂锗等)；金属硅化物层242的材料可以是硅化钨、硅化钴、硅化钛等；粘合层243的材料可以是导电金属氮化物(例如，氮化钛、氮化钽等)。金属硅化物层242和粘合层243可以有效降低公共端引出结构241与衬底201之间的接触电阻。
在本公开实施例中，三维半导体存储装置包括同时将多个沿第一方向和第二方向阵列排布的电容结构231的第一电极2313电连接至衬底201的公共端引出结构241，从而可以通过衬底201将电容结构231的公共电极(即第一电极2313)接至公共电压，在后端互连层的形成过程中，可以省略用于为电容结构231的公共电极提供公共电压的供电焊盘的设置，从而降低键合界面中焊盘的密度，减小焊盘之间的寄生电容。此外，在键合界面中焊盘密度保持不变的情况下，可以进一步增大存储阵列中电容结构231的密度，从而提高三维半导体存储装置的集成度。
在本公开实施例中，公共电压的大小可以为电源电压的一半，即VCC/2。
在图2r所示的三维半导体存储装置中，字线结构213的底部与衬底201之间形成有浅沟槽隔离结构212，其在第一方向上的厚度T1大于初始氧化层202的厚度T2，由此，可以防止字线结构213与衬底201之间发生漏电，有效提高三维半导体存储装置的可靠性。
在一些实施例中，字线结构213的底部与衬底201之间的浅沟槽隔离结构212在第一方向上的厚度T1大于存储结构与衬底201之间的最大距离。这里，存储结构与衬底201之间的最大距离可以为最接近衬底201的有源结构的底部与衬底201之间的距离。由此，可以有效防止字线结构213与衬底201之间产生漏电。
图3为本公开实施例提供的另一种三维半导体存储装置的立体图。该三维半导体存储装置与图2q所示的三维半导体存储装置的差别在于，该半导体存储装置的电容结构331分布于位线结构320的同一侧。
图4j为本公开另一实施例提供的三维半导体存储装置的立体图。如图4j所示，三维半导体存储装置包括：衬底401；位于衬底401上的存储结构；存储结构包括沿第一方向和第二方向阵列排布的多个电容结构431；电容结构431均沿第三方向延伸，包括依次包围半导体层403末端的第二电极4311、电容电介质层4312和第一电极4313；公共端引出结构441，公共端引出结构441的底面低于衬底401的顶面，公共端引出结构441与电容结构431的第一电极4313和衬底401电连接。
在本公开实施例中，第一方向为衬底401的厚度方向，即Z方向，第二方向为Y方向，第三方向为X方向，第二方向和第三方向均与第一方向垂直。
在一些实施例中，存储结构还包括：沿第三方向延伸的有源结构，有源结构包括沿第三方向排列的第一源漏区407、沟道区408和第二源漏区409。电容结构431的第二电极4311与第一源漏区407电连接。
在一些实施例中，三维半导体存储装置还包括：位线结构421，沿第一方向延伸，且与第二源漏区409电连接；浅沟槽隔离结构412，位于位线结构421的底部与衬底401之间，其在第一方向上的厚度T3大于初始氧化层402的厚度T4；沿第二方向延伸的字线结构413，字线结构413在第一方向上排布，并位于沟道区408沿第一方向相对的两侧。
在本公开实施例中，字线结构413作为晶体管结构的栅极，与有源结构共同构成晶体管结构，以同一个字线结构413作为栅极的晶体管结构沿第二方向排布。在第三方向上，一个晶体管结构的第一源漏区407与一个电容结构431的第二电极4311电连接，由此，构成一个存储单元。存储单元沿第一方向和第二方向阵列排布，共同构成三维半导体存储装置的存储结构。
在一具体示例中，浅沟槽隔离结构412在第一方向上的厚度T3是初始氧化层402厚度T4的3倍。在另一具体示例中，浅沟槽隔离结构412在第一方向上的厚度T3是初始氧化层402厚度T4的6倍。
在一些实施例中，浅沟槽隔离结构412在第一方向上的厚度T3大于最接近衬底401的有源结构的底部与衬底401之间的距离。
在一些实施例中，三维半导体存储装置还包括：栅极介质层414，位于字线结构413与沟道区408之间。
在一些实施例中，电容结构431沿第三方向对称分布于位线结构421的两侧。
在一些实施例中，三维半导体存储装置还包括：位于公共端引出结构441与衬底401之间的金属硅化物层442和粘合层443，其中粘合层443位于公共端引出结构441与金属硅化物层442之间。
在本公开实施例中，公共端引出结构441的材料包括掺杂半导体材料(例如，掺杂多晶硅、掺杂锗等)；金属硅化物层442的材料可以是硅化钨、硅化钴、硅化钛等；粘合层443的材料可以是导电金属氮化物(例如，氮化钛、氮化钽等)。金属硅化物层442和粘合层443可以有效降低公共端引出结构441与衬底401之间的接触电阻。
在本公开实施例中，三维半导体存储装置包括同时将多个沿第一方向和第二方向阵列排布的电容结构431的第一电极4313电连接至衬底401的公共端引出结构441，从而可以通过衬底401将电容结构431的公共电极连接至公共电压，在后端互连层的形成过程中，可以省略用于为电容结构431的公共电极提供公共电压的供电焊盘的设置，从而降低键合界面中焊盘的密度，减小焊盘之间的寄生电容。
在图4j所示的三维半导体存储装置中，位线结构421的底部与衬底401之间形成有浅沟槽隔离结构412，其在第一方向上的厚度T3大于初始氧化层402的厚度T4，由此，可以防止位线结构421与衬底401之间发生漏电，有效提高三维半导体存储装置的可靠性。
在一些实施例中，三维半导体存储装置为三维动态随机存取存储器(Dynamic Random Access Memory，DRAM)。
在一些实施例中，公共电压的大小可以为电源电压的一半，即VCC/2。
在本公开实施例中，由于三维半导体存储装置不需要使用衬底进行接地，因而可以通过形成公共端引出结构将阵列排布的电容结构的公共电极电连接至衬底，通过衬底为电容结构提供公共电压。由此，在后端互连层的形成过程中，可以省略用于为电容结构的公共电极提供公共电压的供电焊盘的设置，进而降低键合界面中焊盘的密度，减小焊盘之间的寄生电容。此外，在键合界面中焊盘密度保持不变的情况下，可以进一步增大存储阵列中电容结构的密度，提高三维半导体存储装置的集成度。
在本公开实施例中，三维半导体存储装置具有与衬底垂直的字线结构或位线结构，通过在隔离结构中形成字线开口或位线开口，以在字线结构与衬底之间或位线结构与衬底之间形成浅沟槽隔离结构，浅沟槽隔离结构的厚度大于位于衬底与堆叠结构之间的初始氧化层的厚度。因而，相较于在堆叠结构中形成字线开口或位线开口的方法，本公开实施例中的三维半导体存储装置的形成方法可以有效避免字线结构或位线结构与衬底之间产生漏电，显著提高三维半导体存储装置的可靠性。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个装置实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的装置实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供的三维半导体存储装置的形成方法，通过形成公共端引出结构将三维半导体存储装置中电容结构的公共电极电连接至衬底，从而可以通过衬底为电容结构提供公共电压，减少键合界面所需供电焊盘的数量，有效提高三维半导体存储装置的集成度。

Claims (15)

  1. 一种三维半导体存储装置的形成方法，包括：
    在衬底(201)上形成存储堆叠结构，并在所述存储堆叠结构中形成隔离结构(210)；所述隔离结构(210)将所述存储堆叠结构分隔成导电线区域和存储区域；
    蚀刻所述隔离结构(210)，以形成暴露所述存储区域中的电容区域和所述衬底(201)的多个第一开口(240)；所述第一开口(240)的底面低于所述衬底(201)的顶面；
    在所述电容区域形成沿第一方向和第二方向阵列排布的电容结构(231)；所述电容结构(231)的第一电极(2313)暴露于所述第一开口(240)中；所述电容结构(231)沿第三方向延伸；
    在所述第一开口(240)中形成将所述电容结构(231)的第一电极(2313)电连接至所述衬底(201)的公共端引出结构(241)。
  2. 根据权利要求1所述的三维半导体存储装置的形成方法，其中，所述在所述电容区域形成沿所述第一方向和第二方向阵列排布的电容结构(231)之前，还包括：
    在所述存储区域中的晶体管区域形成沿所述第一方向和所述第二方向阵列排布的有源结构；所述有源结构沿第三方向延伸，所述有源结构包括第一源漏区(207)、沟道区(208)和第二源漏区(209)；
    所述电容结构(231)的第二电极(2311)与所述有源结构中的所述第一源漏区(207)电连接。
  3. 根据权利要求2所述的三维半导体存储装置的形成方法，其中，还包括：
    蚀刻所述隔离结构(210)，以形成暴露所述沟道区(208)的第二开口(211)；所述第二开口(211)的底部与所述衬底(201)之间的隔离结构(210)构成浅沟槽隔离结构(212)；所述浅沟槽隔离结构(212)在所述第一方向上的厚度大于所述衬底(201)与所述存储堆叠结构之间的初始氧化层(202)的厚度；
    在所述第二开口(211)中形成沿所述第一方向延伸的字线结构(213)；
    在所述导电线区域形成沿所述第一方向排布，沿所述第二方向延伸，并与所述第二源漏区(209)电连接的位线结构(220)。
  4. 根据权利要求2所述的三维半导体存储装置的形成方法，其中，还包括：
    蚀刻所述隔离结构(210)，以形成暴露所述第二源漏区(209)的第三开口(420)；所述第三开口的底部与所述衬底(201)之间的隔离结构(210)构成浅沟槽隔离结构(212)；所述浅沟槽隔离结构(212)在所述第一方向上的厚度大于所述衬底(201)与所述存储堆叠结构之间的初始氧化层(202)的厚度；
    在所述第三开口中形成多个沿所述第一方向延伸的位线结构(220)，所述位线结构(220)与所述第二源漏区(209)电连接；
    在所述导电线区域中形成沿所述第一方向排布，沿所述第二方向延伸，并位于所述沟道区(208)两侧的字线结构(213)。
  5. 根据权利要求3或4所述的三维半导体存储装置的形成方法，其中，所述电容结构(231)沿所述第三方向对称分布于所述位线结构(220)两侧；或者，所述电容结构(231)分布于所述位线结构(220)一侧。
  6. 根据权利要求1至5任一项所述的三维半导体存储装置的形成方法，其中，所述在所述第一开口(240)中形成将所述电容结构(231)的第一电极(2313)电连接至所述衬底(201)的公共端引出结构(241)，包括：
    在所述第一开口(240)暴露的所述衬底(201)表面依次形成金属硅化物层(242)和粘合 层(243)；
    在所述粘合层(243)上沉积导电材料以填充所述第一开口(240)；所述导电材料包括多晶硅。
  7. 根据权利要求1至6任一项所述的三维半导体存储装置的形成方法，其中，所述在所述存储堆叠结构中形成隔离结构(210)，包括：
    在所述第一方向上蚀刻初始堆叠结构，以形成多个贯穿所述初始堆叠结构并暴露所述衬底(201)的隔离沟槽(205)；
    在所述隔离沟槽(205)中填充绝缘材料以形成所述隔离结构(210)。
  8. 根据权利要求2至5任一项所述的三维半导体存储装置的形成方法，其中，所述存储堆叠结构包括沿所述第一方向交替层叠的介质层(206)和半导体层(203)；所述在所述电容区域形成沿所述第一方向和第二方向阵列排布的电容结构(231)，包括：
    在所述第三方向上蚀刻所述介质层(206)，以形成暴露所述电容区域的所述半导体层(203)的第四开口(230)，所述第四开口(230)与所述第一开口(240)连通；
    在所述第一开口(240)和所述第四开口(230)暴露的所述半导体层(203)表面依次形成所述电容结构(231)的所述第二电极(2311)、电容电介质层(2312)和所述第一电极(2313)。
  9. 根据权利要求1至8任一项所述的三维半导体存储装置的形成方法，其中，所述在所述第一开口(240)中形成将所述电容结构(231)的第一电极(2313)电连接至所述衬底(201)的公共端引出结构(241)，包括：
    在所述第一开口(240)中及所述电容结构(231)之间填充导电材料，以形成所述公共端引出结构(241)。
  10. 一种三维半导体存储装置，包括：
    衬底(201)；
    位于所述衬底(201)上的存储结构；
    所述存储结构包括沿第一方向和第二方向阵列排布的电容结构(231)；所述电容结构(231)沿第三方向延伸；所述第一方向为所述衬底(201)的厚度方向，所述第二方向和所述第三方向均与所述第一方向垂直；
    公共端引出结构(241)，所述公共端引出结构(241)的底面低于所述衬底(201)的顶面；所述公共端引出结构(241)与所述电容结构(231)的第一电极(2313)和所述衬底(201)电连接。
  11. 根据权利要求10所述的三维半导体存储装置，其中，所述存储结构还包括：
    沿所述第三方向延伸的有源结构；所述有源结构包括沿所述第三方向依次排列的第一源漏区(207)、沟道区(208)和第二源漏区(209)；所述电容结构(231)的第二电极(2311)与所述第一源漏区(207)电连接。
  12. 根据权利要求11所述的三维半导体存储装置，其中，还包括：
    字线结构(213)，沿所述第一方向延伸；所述字线结构(213)位于所述沟道区(208)沿所述第二方向相对的两侧；
    浅沟槽隔离结构(212)，位于所述字线结构(213)与所述衬底(201)之间；所述浅沟槽隔离结构(212)在所述第一方向上的厚度大于初始氧化层(202)的厚度；所述初始氧化层(202)位于所述衬底(201)和所述存储结构之间；
    位线结构(220)，沿所述第一方向排布，沿所述第二方向延伸，并与所述第二源漏区(209)连接。
  13. 根据权利要求11所述的三维半导体存储装置，其中，还包括：
    位线结构(220)，沿所述第一方向延伸；所述位线结构(220)与所述第二源漏区(209) 电连接；
    浅沟槽隔离结构(212)，位于所述位线结构(220)的底部与所述衬底(201)之间；所述浅沟槽隔离结构(212)在所述第一方向上的厚度大于初始氧化层(202)的厚度；所述初始氧化层(202)位于所述衬底(201)和所述存储结构之间；
    字线结构(213)，沿所述第一方向排布，沿所述第二方向延伸，并位于所述沟道区(208)沿所述第一方向相对的两侧。
  14. 根据权利要求12或13所述的三维半导体存储装置，其中，所述电容结构(231)沿所述第三方向对称分布于所述位线结构(220)的两侧；或者，所述电容结构(231)位于所述位线结构(220)的一侧。
  15. 根据权利要求10至14任一项所述的三维半导体存储装置，其中，还包括：
    金属硅化物层(242)，位于所述公共端引出结构(241)与所述衬底(201)之间；
    粘合层(243)，位于所述公共端引出结构(241)与所述金属硅化物层(242)之间；所述公共端引出结构(241)的材料包括多晶硅。
PCT/CN2023/094451 2022-11-07 2023-05-16 三维半导体存储装置及其形成方法 WO2024098708A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180315769A1 (en) * 2015-10-28 2018-11-01 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method of manufacturing the same
CN112397509A (zh) * 2019-08-16 2021-02-23 长鑫存储技术有限公司 电容阵列结构及其形成方法、半导体存储器
CN114975286A (zh) * 2022-05-24 2022-08-30 长鑫存储技术有限公司 半导体结构及其形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180315769A1 (en) * 2015-10-28 2018-11-01 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method of manufacturing the same
CN112397509A (zh) * 2019-08-16 2021-02-23 长鑫存储技术有限公司 电容阵列结构及其形成方法、半导体存储器
CN114975286A (zh) * 2022-05-24 2022-08-30 长鑫存储技术有限公司 半导体结构及其形成方法

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