WO2023231092A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023231092A1
WO2023231092A1 PCT/CN2022/101005 CN2022101005W WO2023231092A1 WO 2023231092 A1 WO2023231092 A1 WO 2023231092A1 CN 2022101005 W CN2022101005 W CN 2022101005W WO 2023231092 A1 WO2023231092 A1 WO 2023231092A1
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Prior art keywords
layer
capacitor
memory chip
gate
array area
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PCT/CN2022/101005
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English (en)
French (fr)
Inventor
曹堪宇
李宗翰
刘志拯
杨怀伟
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长鑫存储技术有限公司
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Priority to US18/151,360 priority Critical patent/US20230389288A1/en
Publication of WO2023231092A1 publication Critical patent/WO2023231092A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the present disclosure relates to the field of semiconductor technology.
  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of forming the same.
  • Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
  • embodiments of the present disclosure provide a semiconductor structure, including: a memory chip, a control chip and a capacitor structure; wherein: the memory chip includes an array area, the control chip includes a peripheral area; the control chip and the The memory chip is bonded face to face; the capacitor structure is located on the surface of the memory chip away from the bonding surface, and the capacitor in the capacitor structure is electrically connected to the corresponding transistor in the array area.
  • the transistor includes: a channel pillar and a full gate-all-around structure surrounding the channel pillar; wherein the channel pillar extends along a first direction and is arranged along a second direction, and the capacitor and One end of the channel pillar is electrically connected.
  • the full-circle gate structure includes: a gate dielectric layer, a gate metal layer and an insulating layer; wherein: the gate dielectric layer is located on the outer wall of the channel pillar; the gate metal layer is connected to the gate The sidewalls of the dielectric layer are in contact; the insulating layer is located in the groove between the adjacent channel pillars and fills the groove.
  • the array area further includes: a bit line structure, the bit line structure is located on a surface of the memory chip close to the bonding surface, and the bit line structure is connected to the control The chip is electrically connected to the channel pillar.
  • the peripheral area includes a peripheral circuit and a contact pad electrically connected to the peripheral circuit; wherein the peripheral circuit is used to control the on and off of the transistor to provide the corresponding Data is stored in the capacitor and/or data is read from the corresponding capacitor; the contact pad is used to electrically connect the memory chip.
  • the memory chip further includes a non-array area; the structure further includes: an insulating structure located on the full-circle gate structure and the non-array area; a node located on the channel pillar. Contacts and/or landing pads; capacitors in the capacitive structure are electrically connected to transistors in the array area through the node contacts and/or landing pads.
  • the capacitor includes: a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer, wherein the first electrode The layer is electrically connected to the memory chip.
  • the capacitor includes: a first support layer and a second support layer arranged in parallel; wherein the first support layer is arranged on the middle periphery of the capacitor; and the second support layer is arranged on On the top periphery of the capacitor; the first support layer and the second support layer are jointly used to support the capacitor.
  • the structure further includes: a filling layer, a first metal layer and a first conductive pillar; wherein: the filling layer is located on a surface of the non-array area away from the bonding surface; Between the upper surface of the capacitor structure and the capacitor, the filling layer is electrically connected to the second electrode layer; the first metal layer is located on the filling layer; the first conductive pillar is located on the In the non-array area, two ends of the first conductive pillar are respectively connected to the first metal layer and the contact pad for electrically connecting the capacitor and the contact pad.
  • the structure further includes: an interlayer dielectric located on the first metal layer and the insulating structure; a second metal layer located on the interlayer dielectric; connecting the second metal layer layer and the second conductive pillar of the contact pad; wherein the second conductive pillar penetrates the interlayer dielectric, the insulating structure and the non-array area and is used to electrically connect the second metal layer and the contact pad.
  • embodiments of the present disclosure provide a method for forming a semiconductor structure, including: providing a control chip and a memory chip; wherein the control chip includes a peripheral area, and the memory chip includes an array area; and combining the control chip with The memory chip is bonded face to face; a capacitive structure is formed on the surface of the memory chip away from the bonding surface, wherein the capacitor in the capacitive structure is electrically connected to the corresponding transistor in the array area.
  • the transistor includes: a channel pillar and a full gate structure surrounding the channel pillar; the method of forming the memory chip includes: providing an initial substrate, the initial substrate includes a first substrate along a first The channel pillars and grooves extending in the second direction and arranged along the second direction form the full-surround gate structure surrounding the channel pillar.
  • the full-surround gate structure includes: a gate dielectric layer, a first sub-insulating layer, a gate metal layer and a second sub-insulating layer; forming the full-surround gate structure surrounding the channel pillar, including : forming the gate dielectric layer on the outer wall of the channel pillar; forming the first sub-insulating layer at the bottom of the groove forming the gate dielectric layer; forming the gate metal layer on the channel pillar , the gate metal layer surrounds the channel pillar; and the second sub-insulating layer flush with the surface of the initial substrate is formed in the groove.
  • the array area further includes: a bit line structure electrically connected to the channel pillar and the control chip; the method of forming the memory chip further includes: forming an initial liner of a full-all-around gate structure.
  • the bit line structure is formed on the bottom surface.
  • the method of forming a memory chip further includes: thinning the initial substrate until a surface of the bottom of the full-surround gate structure is exposed.
  • the method further includes: thinning the memory chip until the surface of the bottom of the full-surround gate structure is exposed.
  • the memory chip further includes a non-array area; after the control chip is bonded and connected to the memory chip, the method further includes: on the full-circle gate structure and on the non-array area. forming an insulating structure; forming a contact structure on the channel pillar, the contact structure including node contacts and/or landing pads, and the insulating structure on the full ring gate structure is used to isolate adjacent contact structures; wherein , the capacitor in the capacitor structure is electrically connected to the transistor in the array area through the contact structure.
  • forming a capacitive structure on a surface of the memory chip on a side away from the bonding surface includes: forming a stack on a surface on a side of the memory chip away from the bonding surface, the stack From bottom to top, it includes: an initial first sacrificial layer, an initial first support layer, an initial second sacrificial layer, and an initial second support layer; patterning the stack to form a layer away from the bonding surface of the memory chip.
  • Capacitor holes are formed on the surface of each side; a first electrode layer is formed on the inner wall of each capacitor hole; the remaining initial first support layer and the remaining initial second support layer are patterned to connect adjacent multiple An opening is formed between the capacitor holes; the remaining initial first sacrificial layer and the remaining initial second sacrificial layer are etched through the opening; a dielectric layer and a second sacrificial layer are sequentially formed on the surface of the first electrode layer. Two electrode layers to form the capacitor structure.
  • the method further includes: sequentially forming a filling layer and a third layer on a surface of the non-array area away from the bonding surface, an upper surface of the capacitor structure and the capacitor.
  • a metal layer wherein the filling layer is electrically connected to the second electrode layer; a first conductive pillar connecting the first metal layer and the contact pad is formed in the non-array area to connect the capacitor with The contact pads are electrically connected; wherein the contact pads are located in the peripheral area and are used to electrically connect the memory chip.
  • the method further includes: forming an interlayer dielectric on the first metal layer and the insulating structure; forming a second metal layer on the interlayer dielectric; forming an interlayer dielectric through the interlayer dielectric. , the insulating structure and the second conductive pillar in the non-array area, the second conductive pillar is used to connect the second metal layer and the contact pad.
  • the semiconductor structure includes a control chip and a memory chip that are face-to-face bonded and connected, and a capacitor structure located on a surface of the memory chip away from the bonding surface.
  • the memory chip and the control chip are face-to-face bonded and connected, that is, the front side of the memory chip and the front side of the control chip are relatively stacked together, compared with a planar semiconductor structure, the size of the semiconductor structure can be reduced, thereby achieving better shrinkage. ;
  • face-to-face bonding of control chips and memory chips can minimize the number and complexity of conductive routes, making the formation of control chips and memory chips more efficient while maintaining the expected yield. easy.
  • the memory chips and control chips constituting the semiconductor structure in the embodiments of the present disclosure can be produced at the same time and then bonded, which can save production time and thereby improve production efficiency.
  • Figure 1a is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 1b is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIGS. 2a to 2c are schematic structural diagrams of a semiconductor structure provided by embodiments of the present disclosure.
  • Figure 3a is a schematic structural diagram of a capacitor provided by an embodiment of the present disclosure.
  • 3b to 3d are schematic structural diagrams of a semiconductor structure provided by embodiments of the present disclosure.
  • Figure 4a is a schematic flow chart of another method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 4b to 4g are structural schematic diagrams of a formation process of a semiconductor structure provided by embodiments of the present disclosure.
  • Figure 5a is a schematic flow chart of another method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 5b is a schematic flow chart of the implementation of step S403 in a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 5c to 5f are structural schematic diagrams of a formation process of a semiconductor structure provided by embodiments of the present disclosure.
  • Figure 6a is a schematic flow chart of another method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 6b is a schematic structural diagram of a formation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 6c is a schematic flow chart of another method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • embodiments of the present disclosure provide a semiconductor structure, referring to FIGS. 1a and 1b , including: a memory chip 10 , a control chip 20 and a capacitor structure 30 .
  • the memory chip 10 includes an array area 11, and the control chip 20 includes a peripheral area 21;
  • control chip 20 and the memory chip 10 are face-to-face bonded and connected;
  • the capacitor structure 30 is located on the surface of the memory chip 10 away from the bonding surface AA.
  • the capacitor 31 in the capacitor structure 30 is electrically connected to the corresponding transistor 101 in the array area 11 .
  • face-to-face bonding refers to the bonding between the front side of the chip and the front side of another chip.
  • the front side of the chip usually includes functional areas such as device area (or active area) and interconnection lines, while the back side of the chip is connected to the front side.
  • the opposite side the face-to-face bonding connection method between the memory chip and the control chip may include direct bonding, thermal pressure bonding, plasma activation bonding or bonding agent bonding, etc.
  • the capacitor may be a cylindrical capacitor or a cylindrical capacitor, for example, it may be a cylindrical capacitor, a square capacitor or a cylindrical capacitor of other shapes.
  • the number of capacitors can be determined based on the number of transistors.
  • the semiconductor structure includes a control chip and a memory chip that are face-to-face bonded and connected, and a capacitor structure located on a surface of the memory chip away from the bonding surface.
  • the memory chip and the control chip are face-to-face bonded and connected, that is, the front side of the memory chip and the front side of the control chip are relatively stacked together, compared with a planar semiconductor structure, the size of the semiconductor structure can be reduced, thereby achieving better shrinkage. .
  • face-to-face bonding of control chips and memory chips can minimize the number and complexity of conductive routes, making it easier to form control chips and memory chips while maintaining the expected yield.
  • the memory chips and control chips constituting the semiconductor structure in the embodiments of the present disclosure can be produced at the same time and then bonded, which can save production time and thereby improve production efficiency.
  • the three directions may include the X-axis, Y-axis, and Z-axis directions.
  • the three directions may include the X-axis, Y-axis, and Z-axis directions.
  • the direction of the top surface and bottom surface of the memory chip that is, the plane where the memory chip is located
  • define two directions that intersect each other for example, are perpendicular to each other.
  • define the extension direction of the channel pillar as the first direction
  • the channel can be defined
  • the arrangement direction of the pillars is the second direction
  • the planar direction of the memory chip can be determined based on the second direction and the first direction.
  • the memory chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when flatness of the top surface and the bottom surface is ignored, a direction perpendicular to the top surface and the bottom surface of the memory chip is defined as a third direction. It can be seen from this that the first direction, the second direction and the third direction are perpendicular to each other.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • the transistor 101 in the memory chip 10 includes: a channel pillar 1011 and a full-circle gate structure 1012 surrounding the channel pillar 1011; wherein the channel pillar 1011 extends along the first direction (X-axis direction) and arranged along the second direction (Y-axis direction), the capacitor is electrically connected to one end of the channel pillar 1011, so that the capacitor is electrically connected to the transistor.
  • both ends of the channel pillar can serve as the source region and drain region of the transistor respectively.
  • the full-surround gate structure can surround the channel pillars, thereby further saving the area of the semiconductor structure in the plane space, and increasing the number of channel pillars per unit area, thereby increasing the number of capacitors. Increase the density of capacitors to improve the storage capacity of the semiconductor structure; secondly, the capacitor structure and bit line structure can be located at both ends of the channel pillar, which can reduce the difficulty of the manufacturing process in the array area; thirdly, the full surround gate structure It can have a wide channel area, which can reduce the short channel effect, thereby improving the performance of the memory chip.
  • the projected shape of the channel pillar on the backside of the memory chip may include a circle, an ellipse, a rectangle, a trapezoid, a rhombus, etc., which are not limited in the embodiments of the present disclosure.
  • the full-circle gate structure 1012 includes: a gate dielectric layer 1012a, a gate metal layer 1012b and an insulating layer 1012c.
  • the gate dielectric layer 1012a is located on the outer wall of the channel pillar 1011;
  • the gate metal layer 1012b is in contact with the sidewalls of the gate dielectric layer 1012a;
  • the insulating layer 1012c is located in the groove between adjacent channel pillars 1011 and fills the groove.
  • the full gate-all-around structure may include a gate electrode and a word line.
  • the material used for the gate dielectric layer may be a high-K dielectric material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or hafnium oxynitride (HfON). , one or any combination of hafnium silicate (HfSiO x ) or zirconium oxide (ZrO 2 ).
  • Using high-K dielectric materials as the gate dielectric layer can improve the gate leakage current problem.
  • the material used for the gate metal layer may include one or several combinations of polysilicon, metals (such as tungsten, copper, aluminum, titanium, tantalum, etc.), metal alloys, metal silicides, titanium nitride, and other conductive materials.
  • the material used for the insulating layer may be one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.
  • the array area 11 in the memory chip 10 also includes: a bit line structure 102, the bit line structure 102 is located on the surface of the side of the memory chip 10 close to the bonding surface (not labeled) , it can be known from FIG. 1 b and FIG. 2 a that the bit line structure 102 and the capacitor structure 30 are located on opposite sides of the memory chip 10 respectively.
  • the bit line structure 102 is electrically connected to the control chip 20 and the channel pillar 1011 .
  • the bit line structure can be electrically connected to the peripheral circuit through contact pads located on the control chip, so that some devices in the peripheral circuit can be electrically connected to the bit line structure accordingly, thereby enabling data reading or writing to the memory cell.
  • the materials used in the bit line structure can be conductive materials, such as polysilicon, metal silicide, conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.) and metals (such as One or more of tungsten, titanium, tantalum, etc.).
  • conductive materials such as polysilicon, metal silicide, conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.) and metals (such as One or more of tungsten, titanium, tantalum, etc.).
  • the transistors in the array region (which may include a full gate structure, a drain region, and a source region) and the capacitors in the capacitance structure may form a memory unit.
  • a capacitor may be coupled to the source/drain regions in the transistor to charge or discharge through the source/drain regions.
  • the word line in a gate-all-around structure can be coupled to the gate of a transistor to turn the transistor on or off.
  • the bit line structure may be coupled to the drain/source regions of the transistor and function as a path for charging or discharging the capacitor.
  • the peripheral area 21 in the control chip 20 includes peripheral circuits 211 and contact pads 212 .
  • the peripheral circuit 21 is used to control the on and off of the transistor to store data in the corresponding capacitor and/or read data from the corresponding capacitor.
  • the material used in the contact pad may be a metal material, such as tungsten, titanium, tantalum, etc.; the function of the contact pad is to electrically connect the control chip and the memory chip.
  • isolation material can be filled between adjacent contact pads.
  • peripheral transistors may be included in the peripheral area, and the peripheral transistors are used to form peripheral circuits.
  • peripheral circuits may also include row decoders, column decoders, input/output controllers, multiplexers, or sense amplifiers.
  • the row decoder is coupled to the word line of the memory cell and is used to turn on or off the gate of the transistor.
  • the column decoder is coupled to the bit line structure of the memory cell and is used to read or write the memory cell.
  • Input/output controllers are used to control input and output signals.
  • a multiplexer is a data selector that selects an input signal among several input signals and forwards the selected input signal to a single output line.
  • the sense amplifier is used to sense the voltage difference from the bit line structure and the complementary bit line structure, and increase the voltage difference to a recognizable logic level, so that the data can be correctly interpreted by the logic unit outside the memory device, and then
  • the storage unit is controlled to store data in the corresponding capacitor and/or read data from the corresponding capacitor.
  • the memory chip 10 further includes a non-array area 12 , and a plurality of conductive pillars electrically connecting the memory chip 10 and the control chip 20 may be provided in the non-array area 12 .
  • Semiconductor structures also include:
  • the insulation structure 40 located on the full-circle gate structure 1012 and the non-array area 12;
  • the node contact 50 and the landing pad 60 are located on the channel pillar 1011; the capacitor 31 in the capacitor structure 30 is electrically connected to the transistor 101 in the array area 11 through the node contact 50 and the landing pad 60.
  • the capacitors may be electrically connected to the transistors through the node contacts; in other embodiments, there may be landing pads on the channel pillars, and the capacitors may be electrically connected to the transistors through the landing pads.
  • the material used in the insulating structure may include at least one of the following: silicon oxide, silicon nitride, and silicon oxynitride.
  • the material used for the node contact may include doped polysilicon or undoped polysilicon.
  • the material used in the landing pad can be a conductive material, such as tungsten, tantalum, etc.; the capacitor can be formed on the surface of the landing pad. The function of the landing pad can be to electrically connect the node contact to the capacitor, or to connect the transistor and the capacitor. connect.
  • the occurrence of short circuits in the semiconductor structure can be reduced;
  • the contact resistance between the source/drain regions and the capacitor can be reduced.
  • the capacitor 31 includes: a first electrode layer 311 , a second electrode layer 312 , and a dielectric layer 313 located between the first electrode layer 311 and the second electrode layer 312 .
  • the first electrode layer 311 is electrically connected to the memory chip.
  • the material used for the first electrode layer may include metal nitride (such as titanium nitride) and/or metal silicide.
  • the material used for the second electrode layer may include metal nitride and/or metal silicide.
  • the material used for the dielectric layer may include at least one of the following: zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide, and aluminum oxide.
  • adjacent capacitors 31 include: a first support layer 314 and a second support layer 315 arranged in parallel. Among them: the first support layer 314 is disposed on the middle periphery of the capacitor 31 ; the second support layer 315 is disposed on the top periphery of the capacitor 31 ; the first support layer 314 and the second support layer 315 are jointly used to support the capacitor 31 .
  • the materials used in the first support layer and the second support layer may include at least one of the following: silicon oxide, silicon nitride, silicon nitride carbide, and silicon oxynitride.
  • the material used for the first support layer may be the same as the material used for the second support layer, or the material used for the first support layer may be different from the material used for the second support layer.
  • the first support layer is disposed on the middle periphery of the capacitor and the second support layer is disposed on the top periphery of the capacitor, it can be seen that the heights of the first support layer and the second support layer are different. That is to say, the capacitor structure is supported at two different heights, making the capacitor structure less likely to collapse and more stable.
  • the capacitor structure 30 further includes: a filling layer 32 located between adjacent capacitors 31.
  • the filling layer 32 may include but is not limited to a silicon layer or a silicon germanium (GeSi) layer for connecting the second electrode layer 312 .
  • the semiconductor structure further includes a filling layer 32 , a first metal layer 70 and a first conductive pillar 80 . in:
  • the filling layer 32 is located on the surface of the non-array region 12 away from the bonding surface, between the upper surface of the capacitor structure and the capacitor 31, and the filling layer 32 is electrically connected to the second electrode layer 312;
  • the first metal layer 70 is located on the filling layer 32;
  • the first conductive pillar 80 is located in the non-array area 12 . Two ends of the first conductive pillar 80 are respectively connected to the first metal layer 70 and the contact pad 22 for electrically connecting the capacitor 31 and the contact pad 22 .
  • the filling layer includes two parts: the first part is a filling layer located between adjacent capacitors, the second part is a filling layer located on the surface of the non-array area (or insulating structure) in the memory chip, and the filling layer of the first part
  • the height of the layers can be greater than the height of the capacitive structure. In this way, the height of the filling layer is greater than the height of the second electrode layer, which can better connect the second electrode layers in the capacitor structure together, and subsequently make it easier to electrically connect the capacitor structure to the contact pads in the control chip.
  • the first conductive pillar may be made of polysilicon, copper, aluminum, cobalt, tungsten, or metal alloys.
  • the extending direction of the first conductive pillar is the third direction (Z-axis direction), and the number of the first conductive pillar may be 1, 2 or more.
  • the first conductive pillar can be used as a wire. On the one hand, it can be used as a connection channel between the capacitor structure and the control chip, connecting the capacitor structure to the peripheral circuit, so that the capacitor in the capacitor structure can be controlled through the peripheral circuit (for example, applying a voltage to the capacitor) ); on the other hand, the first conductive pillar can also lead out the circuits in the control chip and rearrange the input/output interface.
  • the material used for the first metal layer may be metal (such as tungsten, cobalt, aluminum, etc.) or metal alloy.
  • the function of the first metal layer is to electrically connect the capacitor and the control chip, which can reduce the contact resistance between the capacitor and the control chip, thereby reducing the power consumption of the device.
  • the semiconductor structure further includes:
  • the second conductive pillar 110 connects the second metal layer 100 and the contact pad 22 .
  • the second conductive pillar 110 penetrates the interlayer dielectric 90 , the insulating structure 40 and the non-array area 12 , and is used to electrically connect the second metal layer 100 and the contact pad 22 .
  • the second conductive pillar is used to electrically connect the contact pad and the second metal layer. Since the contact pad is part of the control chip, the second conductive pillar realizes the electrical connection between the second metal layer and the control chip.
  • the second conductive pillar is also used to electrically connect the rewiring layer (that is, the second metal layer), lead out the circuits in the control chip, and rearrange the input/output interface.
  • the sizes of the filling layer 32 and the first metal layer 70 in the second direction are smaller than the size of the insulating structure 40 in the second direction. That is to say, the second conductive pillar 110 does not penetrate through the filling layer 32 and the first metal layer 70, in this way, the first conductive pillar 80 and the second conductive pillar 110 can be disconnected, so that the first conductive pillar 80 and the second conductive pillar 110 do not affect each other.
  • the extension direction of the second conductive pillar is the third direction (Z-axis direction).
  • any number of second conductive pillars can be provided as needed.
  • the role of the interlayer dielectric is not only to isolate adjacent second conductive pillars, but also to isolate the first metal layer and the second metal layer.
  • the second metal layer may be used as a bonding pad, in which case the entire layer where the second metal layer is located may include the bonding pad and an isolation material for isolating the bonding pad. Since isolation materials are provided between adjacent pads, leakage current between pads is reduced.
  • the material used for the interlayer dielectric may include at least one of the following: Boro-phospho-silicate Glass (BPSG), Un-doped Silicate Glass (Un-doped Silicate Glass, USG), Phospho Silicate Glass (PSG), Tetraethyl Orthosilicate (TEOS), SiH 4 oxide, silicon dioxide, Spin On Dielectric, SOD) or other appropriate dielectric.
  • BPSG Boro-phospho-silicate Glass
  • Un-doped Silicate Glass Un-doped Silicate Glass, USG
  • Phospho Silicate Glass Phospho Silicate Glass
  • TEOS Tetraethyl Orthosilicate
  • SiH 4 oxide silicon dioxide
  • Spin On Dielectric Spin On Dielectric
  • the material used in the second metal layer may be one of metal silicide, conductive metal nitride (such as titanium nitride, tantalum nitride, tungsten nitride, etc.) and metal (such as tungsten, copper, titanium, tantalum, etc.) or More variety.
  • the material used for the second metal layer may be the same as the material used for the first metal layer, or the material used for the second metal layer may be different from the material used for the first metal layer.
  • Embodiments of the present disclosure provide a method for forming a semiconductor structure. Refer to FIG. 4a, step S401 to step S403. in:
  • Step S401 provide a control chip and a memory chip; wherein, the control chip includes a peripheral area, and the memory chip includes an array area;
  • a memory chip 10 is provided, which includes an array area 11 .
  • a control chip 20 is provided, and the control chip 20 includes a peripheral area 21 .
  • Step S402 bond and connect the control chip and the memory chip face to face
  • the control chip 20 and the memory chip 10 are bonded and connected face to face, and the bonding surface is AA.
  • the control chip and the memory chip are bonded and connected in a face-to-face manner.
  • the subsequent bit line structure be placed above the transistor, which can reduce the process difficulty of forming the bit line structure, but also because the surface of the bit line structure can be used as a
  • the bonding surface can increase the conductive performance of the bit line structure and improve the transmission performance of the bit line structure.
  • the face-to-face bonding of the control chip and the memory chip can minimize the number and complexity of conductive routes, making it easier to form the control chip and the memory chip while maintaining the expected yield.
  • Step S403 Form a capacitive structure on the surface of the memory chip on the side away from the bonding surface, where the capacitors in the capacitive structure are electrically connected to corresponding transistors in the array area.
  • a capacitor structure 30 is formed on the surface of the memory chip 10 on the side away from the bonding surface AA, wherein the capacitor 31 in the capacitor structure 30 is electrically connected to the corresponding transistor 101 in the array area 11 .
  • the transistor 101 includes a channel pillar 1011 and a full gate-all-around structure 1012 surrounding the channel pillar 1011 .
  • the method of forming a memory chip includes the following steps:
  • Step S4011 provide an initial substrate, which includes channel pillars and grooves extending along the first direction and arranged along the second direction;
  • an initial substrate 10a which includes channel pillars 1011 and grooves 1012d extending along a first direction (X-axis direction) and arranged along a second direction (Y-axis direction).
  • the initial substrate may include a silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a germanium-silicon substrate, etc.; the initial substrate may also include other semiconductor elements, such as germanium; or Including semiconductor compounds, such as: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide; or including other semiconductor alloys, such as: silicon germanium, gallium arsenic phosphide, indium aluminum arsenide, Aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide, or
  • Step S4012 Form a full gate-all-around structure surrounding the channel pillar.
  • a full surround gate structure is formed in the groove.
  • the full-circuit gate structure includes: a gate dielectric layer, a first sub-insulating layer, a gate metal layer and a second sub-insulating layer.
  • forming a full gate structure surrounding the channel pillar includes steps S11 to S14:
  • Step S11 forming a gate dielectric layer on the outer wall of the channel pillar
  • a gate dielectric layer 1012a is formed on the outer wall of the channel pillar 1011, that is, the gate dielectric layer 1012a is formed in the groove.
  • the gate dielectric layer can be formed by any suitable deposition process, such as chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition) , ALD) process, spin coating process or coating process.
  • Step S12 forming a first sub-insulating layer at the bottom of the groove forming the gate dielectric layer
  • a first sub-insulating layer 112 is formed at the bottom of the groove (not labeled, please refer to FIG. 4b) forming the gate dielectric layer 1012a.
  • the material used for the first sub-insulating layer may be silicon nitride, which may be formed through suitable processes such as chemical vapor deposition and atomic layer deposition.
  • Step S13 forming a gate metal layer on the channel pillar, and the gate metal layer surrounds the channel pillar;
  • an initial gate metal layer 1012b' is formed on the channel pillar forming the gate dielectric layer.
  • the top surface of the initial gate metal layer 1012b' can be higher than the top surface of the initial substrate, and part of the initial gate metal layer 1012b is etched away.
  • the gate metal layer 1012b shown in Figure 4d is obtained.
  • the gate metal layer surrounds the channel pillar, that is to say, there are two parts of the gate metal layer in the groove, but the two parts of the gate metal layer are not in contact, leaving a gap in between.
  • Step S14 forming a second sub-insulating layer flush with the surface of the original substrate in the groove.
  • an initial second sub-insulating layer 113' is formed in the groove, and the top surface of the initial second sub-insulating layer 113' is higher than the top surface of the initial substrate 10a. Then chemical mechanical polishing, dry etching, wet etching or any combination thereof is used to remove the initial second sub-insulating layer 113' above the top surface of the initial substrate 10a (as well as remove the gate dielectric layer above the top surface of the initial substrate). 1012a), the second sub-insulating layer 113 flush with the surface of the initial substrate 10a is obtained as shown in Figure 4e.
  • the insulating layer 1012c includes a second sub-insulating layer 113 and a first sub-insulating layer 112.
  • the full-circle gate structure 1012 includes: a gate dielectric layer 1012a, a first sub-insulating layer 112, a gate metal layer 1012b and a second sub-insulating layer 113.
  • the material used for the initial second sub-insulating layer may be silicon nitride, and may be formed using the same process as the first sub-insulating layer.
  • the array area also includes: a bit line structure electrically connected to the channel pillar and the control chip; the method of forming the memory chip also includes:
  • Step S15 Form a bit line structure on the surface of the original substrate forming the full gate-all-around structure.
  • bit line structure 102 located above the transistor as shown in Figure 4f.
  • bit line structure can be formed directly above the transistor, the difficulty of forming the bit line structure can be reduced.
  • the forming method of forming the memory chip also includes:
  • step S16 the initial substrate is thinned until the surface of the bottom of the full surround gate structure is exposed.
  • the surface of the initial substrate on which the bit line structure is formed and the surface of the initial substrate on which the thinning process is performed are opposite surfaces and are not the same surface.
  • One surface of the memory chip is the bit line structure 102, and the other surface exposes the gate dielectric layer 1012a in the full gate-all-around structure.
  • the surface of the bottom of the full-surround gate structure is exposed, which is beneficial to electrically connecting the full-surround gate structure with the subsequently formed capacitor structure.
  • the memory chip can be thinned until the surface of the bottom of the full-surround gate structure is exposed.
  • the memory chip also includes a non-array area; after the control chip and the memory chip are bonded and connected, the method of forming a semiconductor structure further includes steps S404 and S405, wherein:
  • Step S404 forming an insulation structure on the full-circle gate structure and the non-array area
  • Step S405 form a contact structure on the channel pillar.
  • the contact structure includes node contacts and/or landing pads.
  • the insulation structure on the full ring gate structure is used to isolate adjacent contact structures.
  • the insulating material can be deposited on the full ring gate structure and the non-array area first; then the insulating material is etched to form a gap, which can expose the channel pillar; finally, a contact structure can be formed in the gap.
  • the contact structure may include node contacts, landing pads, or both node contacts and landing pads.
  • an insulation structure 40 is formed on the full-circle gate structure 1012 and the non-array area 12 .
  • a contact structure including node contacts 50 and landing pads 60 is formed on the channel pillar 1011 .
  • the capacitors in the capacitive structure are electrically connected to the transistors in the array area via node contacts and/or landing pads.
  • step S403 "forming a capacitive structure on the surface of the memory chip away from the bonding surface" may include steps S4031 to S4036, wherein:
  • Step S4031 Form a stack on the surface of the memory chip away from the bonding surface.
  • the stack includes from bottom to top: an initial first sacrificial layer, an initial first support layer, an initial second sacrificial layer, and an initial second sacrificial layer. support layer;
  • the materials used for both the initial first support layer and the initial second support layer may include at least one of the following: silicon oxide, silicon nitride, silicon nitride carbide, and silicon oxynitride.
  • the material used for the initial first sacrificial layer may be silicon oxide
  • the materials used for the initial first supporting layer and the initial second supporting layer may both be silicon nitride.
  • the initial first sacrificial layer, the initial first support layer, the initial second sacrificial layer and the initial second support layer can be formed by any suitable deposition process, for example, chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process or coating process.
  • a stack 33 is formed on the surface of the memory chip 10 on the side away from the bonding surface AA.
  • the stack 33 includes from bottom to top: an initial first sacrificial layer 316', an initial first support layer 314', An initial second sacrificial layer 317' and an initial second support layer 315'.
  • Step S4032 pattern the stack to form a capacitor hole on the surface of the memory chip away from the bonding surface
  • dry etching (such as plasma etching process, reactive ion etching process or ion milling process) can be used to etch the stack 33 to form the capacitor hole 318 as shown in FIG. 5d.
  • the gas used in dry etching can be trifluoromethane (CHF 3 ), carbon tetrafluoride (CF 4 ), difluoromethane (CH 2 F 2 ), hydrobromic acid (HBr), chlorine (Cl 2 ) or hexafluoromethane.
  • the stacked structure on the non-array area 12 will be etched away, exposing the surface of the insulating structure 40 .
  • Step S4033 forming a first electrode layer on the inner wall of each capacitor hole
  • a first electrode layer 311 is formed on the inner wall of each capacitor hole 318 .
  • Step S4034 pattern the remaining initial first support layer and the remaining initial second support layer to form openings between adjacent plurality of capacitor holes;
  • the function of forming the openings between the adjacent plurality of capacitor holes is to facilitate subsequent etching of the initial first sacrificial layer and the initial second sacrificial layer below the openings, thereby facilitating the formation of the dielectric layer and the second sacrificial layer on the surface of the first electrode layer.
  • the remaining initial first support layer and the remaining initial second support layer are patterned to form openings 319 between adjacent capacitor holes (or first electrode layers).
  • Step S4035 etching the remaining initial first sacrificial layer and the remaining initial second sacrificial layer through the opening;
  • the remaining initial first initial sacrificial layer 316' and the remaining initial second initial sacrificial layer 317' are etched through the opening 319, and the remaining initial first initial sacrificial layer 316' and the remaining initial second initial sacrificial layer 317' are removed. Layer 317'.
  • dry etching or wet etching may be used to remove the remaining initial first initial sacrificial layer and the remaining initial second initial sacrificial layer.
  • the wet etching solution may be a mixed solution including dilute hydrofluoric acid (DHF) and ammonia water (NH 4 OH), or a mixed solution including dilute hydrofluoric acid and tetramethylammonium hydroxide (TMAH).
  • Step S4036 Form a dielectric layer and a second electrode layer sequentially on the surface of the first electrode layer to form a capacitor structure.
  • the dielectric layer and the second electrode layer may be formed by any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process or coating process.
  • a dielectric layer 313 and a second electrode layer 312 are sequentially formed on the surface of the first electrode layer 311 to form the capacitor structure 30 .
  • the method of forming a semiconductor structure further includes steps S406 and S407, wherein:
  • Step S406 sequentially forming a filling layer and a first metal layer on the surface of the non-array area away from the bonding surface, the upper surface of the capacitor structure and between the capacitors; wherein the filling layer is electrically connected to the second electrode layer;
  • the filling layer and the first metal layer may be formed by any suitable deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process or a coating process.
  • a filling layer 32 and a first metal layer 70 are sequentially formed on the surface of the non-array area 12 away from the bonding surface, the upper surface of the capacitor structure 30 and the capacitor 31.
  • the filling layer 32 and the second electrode are Layer 312 is electrically connected.
  • Step S407 Form a first conductive pillar connecting the first metal layer and the contact pad in the non-array area to electrically connect the capacitor with the contact pad; wherein the contact pad is located in the peripheral area for electrically connecting the memory chip.
  • a first through hole 80 a is formed in the non-array area 12 , and a conductive material is filled in the first through hole 80 a to form a first conductive pillar 80 as shown in FIG. 3 c .
  • the method of forming a semiconductor structure further includes steps S408 to S410, wherein:
  • Step S408 forming an interlayer dielectric on the first metal layer and the insulating structure
  • an interlayer dielectric 90 is deposited on the first metal layer 70 and the insulating structure 40 .
  • Step S409 forming a second metal layer on the interlayer dielectric
  • the interlayer dielectric and the second metal layer can be formed through any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process or coating process.
  • a second metal layer 100 is deposited on the interlayer dielectric 90 .
  • Step S410 Form a second conductive pillar penetrating the interlayer dielectric, the insulating structure and the non-array area.
  • the second conductive pillar is used to connect the second metal layer and the contact pad.
  • a second conductive pillar 110 is formed penetrating the interlayer dielectric 90 , the insulating structure 40 and the non-array region 12 .
  • the steps of forming the second conductive pillar are similar to the steps of forming the first conductive pillar, and will not be described again here.
  • An embodiment of the present disclosure also provides a method for forming a semiconductor structure, including steps S501 to S503, wherein:
  • Step S501 provide a control chip and a memory chip; wherein, the control chip includes a peripheral area, and the memory chip includes an array area;
  • Step S502 forming a capacitor structure on the memory chip; wherein the capacitors in the capacitor structure are electrically connected to the corresponding memory cells in the array area;
  • Step S503 Bond and connect the memory chip and the control chip face to face; wherein, the capacitor structure is away from the bonding surface.
  • the difference between the formation method of the semiconductor structure provided by the embodiment of the present disclosure and the above-mentioned formation method is that the capacitor structure is first formed on the memory chip, and then the memory chip and the control chip are face-to-face bonded and connected. In this way, the impact of the high formation temperature of the capacitor structure on the peripheral circuits in the control chip can be reduced.
  • the units described above as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.
  • the semiconductor structure includes a control chip and a memory chip that are face-to-face bonded and connected, and a capacitor structure located on a surface of the memory chip away from the bonding surface.
  • the memory chip and the control chip are face-to-face bonded and connected, that is, the front side of the memory chip and the front side of the control chip are relatively stacked together, compared with a planar semiconductor structure, the size of the semiconductor structure can be reduced, thereby achieving better shrinkage. ;
  • face-to-face bonding of control chips and memory chips can minimize the number and complexity of conductive routes, making the formation of control chips and memory chips more efficient while maintaining the expected yield. easy.
  • the memory chips and control chips constituting the semiconductor structure in the embodiments of the present disclosure can be produced at the same time and then bonded, which can save production time and thereby improve production efficiency.

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Abstract

本公开实施例提供一种半导体结构及其形成方法。其中，所述半导体结构包括存储芯片、控制芯片和电容结构；其中：所述存储芯片包括阵列区域，所述控制芯片包括外围区域；所述控制芯片与所述存储芯片面对面键合连接；所述电容结构，位于所述存储芯片的远离键合面一侧的表面上，所述电容结构中的电容器与所述阵列区域中的对应晶体管电连接。

Description

半导体结构及其形成方法
相关的交叉引用
本公开基于申请号为202210610207.5、申请日为2022年05月31日、发明名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，本公开涉及但不限于一种半导体结构及其形成方法。
背景技术
随着电子设备朝着小型化和薄型化发展，对存储器芯片以及其它半导体结构的体积有了相应的要求，如何进一步缩小半导体结构的尺寸是目前需要解决的问题。
发明内容
本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构，包括：存储芯片、控制芯片和电容结构；其中：所述存储芯片包括阵列区域，所述控制芯片包括外围区域；所述控制芯片与所述存储芯片面对面键合连接；所述电容结构，位于所述存储芯片的远离键合面一侧的表面上，所述电容结构中的电容器与所述阵列区域中的对应晶体管电连接。
在一些实施例中，所述晶体管包括：沟道柱和环绕所述沟道柱的全环栅结构；其中，所述沟道柱沿第一方向延伸且沿第二方向排列，所述电容器与所述沟道柱的一端电连接。
在一些实施例中，所述全环栅结构包括：栅介质层、栅金属层和绝缘层；其中：所述栅介质层位于所述沟道柱的外壁；所述栅金属层与所述栅介质层的侧壁接触；所述绝缘层位于相邻的所述沟道柱之间的凹槽内，并填满所述凹槽。
在一些实施例中，所述阵列区域还包括：位线结构，所述位线结构位于所述存储芯片的靠近所述键合面的一侧的表面上，所述位线结构与所述控制芯片和所述沟道柱电连接。
在一些实施例中，所述外围区域包括外围电路和与所述外围电路电连接的接触垫；其中，所述外围电路，用于控制所述晶体管的导通与截止，以向对应的所述电容器中存储数据，和/或从对应的所述电容器中读取数据；所述接触垫，用于电连接所述存储芯片。
在一些实施例中，所述存储芯片还包括非阵列区域；所述结构还包括：位于所述全环栅结构上以及所述非阵列区域上的绝缘结构；位于所述沟道柱上的节点接触和/或着落垫；所述电容结构中的电容器通过所述节点接触和/或所述着落垫与所述阵列区域中的晶体管电连接。
在一些实施例中，所述电容器包括：第一电极层、第二电极层、和位于所述第一电极层与所述第二电极层之间的介电层，其中，所述第一电极层与所述存储芯片电连接。
在一些实施例中，所述电容器之间包括：平行设置的第一支撑层和第二支撑层；其中，所述第一支撑层设置于所述电容器的中部外周；所述第二支撑层设置于所述电容器的顶部外周；所述第一支撑层和所述第二支撑层共同用于支撑所述电容器。
在一些实施例中，所述结构还包括：填充层、第一金属层和第一导电柱；其中：所述填充层位于所述非阵列区域的远离所述键合面一侧的表面上、所述电容结构的上表面以及所述电容器之间，所述填充层与所述第二电极层电连接；所述第一金属层位于所述填充层上；所述第一导电柱位于所述非阵列区域内，所述第一导电柱的两端分别与所述第一金属层和所述接触垫连接，用于电连接所述电容器与所述接触垫。
在一些实施例中，所述结构还包括：位于所述第一金属层上和所述绝缘结构上的层间介质；位于所述层间介质上的第二金属层；连接所述第二金属层和所述接触垫的第二导电柱；其中，所述第二导电柱贯穿所述层间介质、绝缘结构以及所述非阵列区域，用于电连接所述第二金属层和所述接触垫。
第二方面，本公开实施例提供一种半导体结构的形成方法，包括：提供控制芯片和存储芯片；其中，所述控制芯片包括外围区域，所述存储芯片包括阵列区域；将所述控制芯片与所述存储芯片面对面键合连接；在所述存储芯片的远离键合面一侧的表面上形成电容结构，其中，所述电容结构中的电容器与所述阵列区域中的对应晶体管电连接。
在一些实施例中，所述晶体管包括：沟道柱和环绕所述沟道柱的全环栅结构；所述存储芯片的形成方法包括：提供初始衬底，所述初始衬底包括沿第一方向延伸、沿第二方向排列的所述沟道柱和凹槽；形成环绕所述沟道柱的所述全环栅结构。
在一些实施例中，所述全环栅结构包括：栅介质层、第一子绝缘层、栅金属层和第二子绝缘层；形成环绕所述沟道柱的所述全环栅结构，包括：在所述沟道柱的外壁形成所述栅介质层；在形成所述栅介质层的凹槽的底部形成所述第一子绝缘层；在所述沟道柱上形成所述栅金属层，所述栅金属层环绕所述沟道柱；在凹槽中形成与所述初始衬底的表面齐平的所述第二子绝缘层。
在一些实施例中，所述阵列区域还包括：与所述沟道柱和所述控制芯片电连接的位线结构；所述存储芯片的形成方法还包括：在形成全环栅结构的初始衬底的表面上形成所述位线结构。
在一些实施例中，所述存储芯片的形成方法还包括：对所述初始衬底进行减薄处理，直至暴露出所述全环栅结构的底部的表面。
在一些实施例中，在将所述控制芯片与所述存储芯片面对面键合连接之后，还包括：对所述存储芯片进行减薄处理，直至暴露出所述全环栅结构的底部的表面。
在一些实施例中，所述存储芯片还包括非阵列区域；在将所述控制芯片与所述存储芯片键合连接之后，还包括：在所述全环栅结构上以及所述非阵列区域上形成绝缘结构；在所述沟道柱上形成接触结构，所述接触结构包括节点接触和/或着落垫，所述全环栅结构上的绝缘结构用于隔离相邻的所述接触结构；其中，所述电容结构中的电容器通过所述接触结构与所述阵列区域中的晶体管电连接。
在一些实施例中，在所述存储芯片的远离键合面一侧的表面上形成电容结构，包括：在所述存储芯片的远离键合面一侧的表面上形成叠层，所述叠层自下而上依次包括：初始第一牺牲层、初始第一支撑层、初始第二牺牲层和初始第二支撑层；图案化所述叠层，以在所述存储芯片的远离键合面一侧的表面上形成电容孔；在每一所述电容孔的内壁形成第一电极层；图形化剩余的所述初始第一支撑层和剩余的所述初始第二支撑层，以在相邻多个电容孔之间形成开口；通过所述开口刻蚀剩余的所述初始第一牺牲层和剩余的所述初始第二牺牲层；在所述第一电极层的表面依次形成介电层和第二电极层，以形成所述电容结构。
在一些实施例中，所述方法还包括：在所述非阵列区域的远离所述键合面一侧的表面上、所述电容结构的上表面以及所述电容器之间依次形成填充层和第一金属层；其中，所述填充层与所述第二电极层电连接；在所述非阵列区域内形成连接所述第一金属层和 接触垫的第一导电柱，以将所述电容器与所述接触垫电连接；其中，所述接触垫位于所述外围区域，用于电连接所述存储芯片。
在一些实施例中，所述方法还包括：在所述第一金属层和所述绝缘结构上形成层间介质；在所述层间介质上形成第二金属层；形成贯穿所述层间介质、所述绝缘结构以及所述非阵列区域的第二导电柱，所述第二导电柱用于连接所述第二金属层和所述接触垫。
本公开实施例中，半导体结构包括面对面键合连接的控制芯片和存储芯片以及位于存储芯片的远离键合面一侧的表面的电容结构。一方面，由于存储芯片与控制芯片面对面键合连接，即存储芯片的正面和控制芯片的正面相对堆叠在一起，相较于平面半导体结构，可以减小半导体结构的尺寸，从而实现更好地微缩；相较于其他键合连接方式，控制芯片和存储芯片面对面键合连接可以使导电路由的数量和复杂性最小化，在保持预期的产率的同时使控制芯片和存储芯片的形成变得更加容易。另一方面，本公开实施例中的组成半导体结构的存储芯片和控制芯片可以同时生产，之后再进行键合，这样可以节省生产时间，进而提高生产效率。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1a为本公开实施例提供的一种半导体结构的组成结构示意图；
图1b为本公开实施例提供的一种半导体结构的组成结构示意图；
图2a至图2c为本公开实施例提供的一种半导体结构的组成结构示意图；
图3a为本公开实施例提供的一种电容器的组成结构示意图；
图3b至图3d为本公开实施例提供的一种半导体结构的组成结构示意图；
图4a为本公开实施例提供的另一种半导体结构的形成方法的实现流程示意图；
图4b至图4g为本公开实施例提供的一种半导体结构的形成过程的结构示意图；
图5a为本公开实施例提供的另一种半导体结构的形成方法的实现流程示意图；
图5b为本公开实施例提供的一种半导体结构的形成方法中的步骤S403的实现流程示意图；
图5c至图5f为本公开实施例提供的一种半导体结构的形成过程的结构示意图；
图6a为本公开实施例提供的另一种半导体结构的形成方法的实现流程示意图；
图6b为本公开实施例提供的一种半导体结构的形成过程的结构示意图；
图6c为本公开实施例提供的另一种半导体结构的形成方法的实现流程示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
有鉴于此，本公开实施例提供一种半导体结构，同时参考图1a和图1b，包括：存储芯片10、控制芯片20和电容结构30。
其中，存储芯片10包括阵列区域11，控制芯片20包括外围区域21；
控制芯片20与存储芯片10面对面键合连接；
电容结构30，位于存储芯片10的远离键合面AA一侧的表面上，电容结构30中的电容器31与阵列区域11中的对应晶体管101电连接。
这里，面对面键合是指芯片的正面与另一芯片的正面形成键合，其中，芯片的正面通常包括器件区(或有源区)、互连线路等功能区，而芯片的背面是与正面相对的另一面。实施时，存储芯片和控制芯片的面对面键合连接方式可以包括直接键合、热压键合、等离子活化键合或者键合剂键合等。
电容器可以为柱状电容器或筒状电容器，例如可以为圆柱状电容器、方形电容器或其他形状的柱状电容器。实施时，电容器的数量可以根据晶体管的数量来确定。
本公开实施例中，半导体结构包括面对面键合连接的控制芯片和存储芯片以及位于存储芯片的远离键合面一侧的表面的电容结构。一方面，由于存储芯片与控制芯片面对面键合连接，即存储芯片的正面和控制芯片的正面相对堆叠在一起，相较于平面半导体结构，可以减小半导体结构的尺寸，从而实现更好地微缩。相较于其他键合连接方式，控制芯片和存储芯片面对面键合连接可以使导电路由的数量和复杂性最小化，在保持预期的产率的同时使控制芯片和存储芯片的形成变得更加容易。另一方面，本公开实施例中的组成半导体结构的存储芯片和控制芯片可以同时生产，之后再进行键合，这样可以节省生产时间，进而提高生产效率。
在介绍本公开实施例之前，先定义一下以下实施例可能用到的描述立体结构的三个方向，以笛卡尔坐标系为例，三个方向可以包括X轴、Y轴和Z轴方向。在存储芯片的顶表面和底表面(即存储芯片所在的平面)方向上，定义两彼此相交(例如彼此垂直)的方向，例如，定义沟道柱的延伸方向为第一方向，可以定义沟道柱的排列方向为第二方向，基于第二方向和第一方向可以确定存储芯片的平面方向。存储芯片可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的 情况下，定义垂直存储芯片顶表面和底表面的方向为第三方向。由此可以看出，第一方向、第二方向和第三方向两两垂直。本公开实施例中，定义第一方向为X轴方向，定义第二方向为Y轴方向，定义第三方向为Z轴方向。
在一些实施例中，参考图2a，存储芯片10中的晶体管101包括：沟道柱1011和环绕沟道柱1011的全环栅结构1012；其中，沟道柱1011沿第一方向延伸(X轴方向)且沿第二方向(Y轴方向)排列，电容器与沟道柱1011的一端电连接，以使电容器与晶体管电连接。这里，沟道柱的两端可以分别作为晶体管的源极区和漏极区。本公开实施例中，第一方面，全环栅结构可以环绕沟道柱，从而可以进一步节省半导体结构平面空间上的面积，并且能够增加单位面积上的沟道柱数量，进而增加电容器的数量，提升电容器的密度，以提升半导体结构的存储能力；第二方面，电容结构和位线结构可以位于沟道柱的两端，从而可以降低阵列区域制造工艺的难度；第三方面，全环栅结构可以具有宽的沟道区，从而可以降低短沟道效应，进而可以提高存储芯片的性能。
实施时，沟道柱在存储芯片的背面(即远离键合面的表面)的投影形状可以包括圆形、椭圆形、矩形、梯形或菱形等，本公开实施例对此并不限定。
在一些实施例中，参考图2a，全环栅结构1012包括：栅介质层1012a、栅金属层1012b和绝缘层1012c。
其中：栅介质层1012a位于沟道柱1011的外壁；
栅金属层1012b与栅介质层1012a的侧壁接触；
绝缘层1012c位于相邻的沟道柱1011之间的凹槽内，并填满凹槽。
这里，全环栅结构可以包括栅极和字线。实施时，栅介质层采用的材料可以是高K介质材料，例如可以是氧化镧(La 2O 3)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、硅酸铪(HfSiO x)或氧化锆(ZrO 2)中的一种或任意组合。采用高K介质材料作为栅介质层可以改善栅极漏电流的问题。
栅金属层采用的材料可以包括多晶硅、金属(例如钨、铜、铝、钛、钽等)、金属合金、金属硅化物、氮化钛、其他导电材料中的一种或者几种组合。
绝缘层采用的材料可以是氮化硅、氮氧化硅、氧化硅中的一种或几种组合。
在一些实施例中，参考图2a，存储芯片10中的阵列区域11还包括：位线结构102，位线结构102位于存储芯片10的靠近键合面(未标出)的一侧的表面上，结合图1b和图2a可以知道，位线结构102和电容结构30分别位于存储芯片10的相对两面。位线结构102与控制芯片20和沟道柱1011均电连接。实施时，位线结构可以通过位于控制芯片上的接触垫电连接至外围电路，这样外围电路中的部分器件可以相应地电连接位线结构，从而实现对存储单元进行数据读取或写入。
位线结构采用的材料可以是导电材料，例如多晶硅、金属硅化物、导电金属氮化物(例如钛氮化物(TiN)、钽氮化物(TaN)、钨氮化物(WN)等)和金属(例如钨、钛、钽等)中的一种或更多种。
本公开实施例中，阵列区域中的晶体管(可以包括全环栅结构、漏极区和源极区)和电容结构中的电容器可以形成一个存储单元。电容器可以耦合至晶体管中的源极区/漏极区，以通过源极区/漏极区来充电或者放电。全环栅结构中的字线可以耦合至晶体管的栅极，以将晶体管导通或截止。位线结构可以耦合至晶体管的漏极区/源极区，并且起着用于对电容器充电或放电的路径的作用。
在一些实施例中，参考图2b，控制芯片20中的外围区域21包括外围电路211和接触垫212。外围电路21，用于控制晶体管的导通与截止，以向对应的电容器中存储数据，和/或从对应的电容器中读取数据。
实施时，接触垫采用的材料可以是金属材料，例如钨、钛、钽等；接触垫的作用是 电连接控制芯片和存储芯片。为了减小相邻接触垫之间短路的情况，可以在相邻接触垫之间填充隔离材料。
这里，外围区域中可以包括外围晶体管，外围晶体管用于形成外围电路。在一些实施例中，外围电路还可以包括行解码器、列解码器、输入/输出控制器、复用器或者感测放大器等。行解码器耦合至存储单元的字线，用于导通或者截止晶体管的栅极。列解码器耦合至存储单元的位线结构，用于对存储单元进行读或写。输入/输出控制器用于控制输入和输出信号。复用器是数据选择器，用于在几个输入信号当中选择输入信号并且将所选择的输入信号转发至单条输出线。感测放大器用于感测来自位线结构和互补位线结构之间的电压差，并且将该电压差大到可识别逻辑电平，从而能够由存储器件外的逻辑单元正确地解释数据，进而实现控制存储单元向对应的电容器中存储数据，和/或从对应的电容器中读取数据。
在一些实施例中，参考图2c，存储芯片10还包括非阵列区域12，非阵列区域12中可以设置多个电连接存储芯片10和控制芯片20的导电柱。半导体结构还包括：
位于全环栅结构1012上以及非阵列区域12上的绝缘结构40；
位于沟道柱1011上的节点接触50和着落垫60；电容结构30中的电容器31通过节点接触50和着落垫60与阵列区域11中的晶体管101电连接。
在一些实施例中，沟道柱上可以有节点接触，电容器可以通过节点接触与晶体管电连接；在另一些实施例中，沟道柱上可以有着落垫，电容器可以通过着落垫与晶体管电连接。
这里，绝缘结构采用的材料可以包括以下至少之一：氧化硅、氮化硅、氮氧化硅。节点接触采用的材料可以包括掺杂杂质的多晶硅或未掺杂杂质的多晶硅。着落垫采用的材料可以是导电材料，例如可以是钨、钽等；电容器可以形成于着落垫的表面上，着落垫的作用可以是将节点接触与电容器电连接，也可以是将晶体管与电容器电连接。
本公开实施例中，通过在沟道柱上方设置用于隔离相邻节点接触(和/或着落垫)的绝缘结构，以及非阵列区域上设置绝缘结构，可以减少半导体结构中短路情况的出现；通过设置节点接触和着落垫，可以减少源极区/漏极区与电容器之间的接触电阻。
在一些实施例中，参考图3a，电容器31包括：第一电极层311、第二电极层312、和位于第一电极层311与第二电极层312之间的介电层313。其中，第一电极层311与存储芯片电连接。
实施时，第一电极层采用的材料可以包括金属氮化物(例如氮化钛)和/或金属硅化物等。第二电极层采用的材料可以包括金属氮化物和/或金属硅化物等。介电层采用的材料可以包括以下至少之一：氧化锆、氧化铪、氧化钛锆、氧化钌、氧化锑、氧化铝。
在一些实施例中，参考图3b，相邻电容器31之间包括：平行设置的第一支撑层314和第二支撑层315。其中：第一支撑层314设置于电容器31的中部外周；第二支撑层315设置于电容器31的顶部外周；第一支撑层314和第二支撑层315共同用于支撑电容器31。
在一些实施例中，第一支撑层和第二支撑层采用的材料均可以包括以下至少之一：氧化硅、氮化硅、氮碳化硅、氮氧化硅。实施时，第一支撑层采用的材料可以与第二支撑层采用的材料可以相同，第一支撑层采用的材料也可以与第二支撑层采用的材料不相同。
本公开实施例中，由于第一支撑层设置于电容器的中部外周，第二支撑层设置于电容器的顶部外周，因此可知第一支撑层和第二支撑层的高度不同。也就是说电容结构在两个不同的高度处均有支撑，使得电容结构不易倒塌，更加稳定。
在一些实施例中，参考图3b，电容结构30还包括：位于相邻电容器31之间的填充 层32。实施时，填充层32可以包括但不限于硅层或者锗化硅(GeSi)层，用于连接第二电极层312。
在一些实施例中，参考图3c，半导体结构还包括填充层32、第一金属层70和第一导电柱80。其中：
填充层32位于非阵列区域12的远离键合面一侧的表面上、电容结构的上表面以及电容器31之间，填充层32与第二电极层312电连接；
第一金属层70位于填充层32上；
第一导电柱80位于非阵列区域12内，第一导电柱80的两端分别与第一金属层70和接触垫22连接，用于电连接电容器31与接触垫22。
这里，填充层包括两部分：第一部分为位于相邻电容器之间的填充层，第二部分为位于存储芯片中的非阵列区域(或者绝缘结构)的表面上的填充层，并且第一部分的填充层的高度可以大于电容结构的高度。这样，填充层的高度大于第二电极层的高度，可以更好地将电容结构中的第二电极层连接在一起，后续更容易将电容结构与控制芯片中的接触垫电连接。
在一些实施例中，第一导电柱采用的材料可以是多晶硅、铜、铝、钴、钨或金属合金等。第一导电柱的延伸方向为第三方向(Z轴方向)，第一导电柱的数量可以为1个、2个或者多个。其中，第一导电柱可以作为导线，一方面，可以作为电容结构和控制芯片的连接通道，将电容结构连接到外围电路，从而可以通过外围电路控制电容结构中的电容器(例如，向电容器施加电压)；另一方面，第一导电柱还可以将控制芯片中的线路引出，对输入/输出接口进行重新布局。
在一些实施例中，第一金属层采用的材料可以是金属(例如钨、钴、铝等)或者金属合金等。第一金属层的作用是电连接电容器和控制芯片，可以减少电容器和控制芯片之间的接触电阻，从而降低器件功耗。
在一些实施例中，参考图3d，半导体结构还包括：
位于第一金属层70上和绝缘结构40上的层间介质90；
位于层间介质90上的第二金属层100；
连接第二金属层100和接触垫22的第二导电柱110。
其中，第二导电柱110贯穿层间介质90、绝缘结构40以及非阵列区域12，第二导电柱110用于电连接第二金属层100和接触垫22。本公开实施例中，第二导电柱用于电连接接触垫和第二金属层，由于接触垫是控制芯片的一部分，所以第二导电柱实现电连接第二金属层和控制芯片。第二导电柱还用于电连接重布线层(即为第二金属层)，将控制芯片中的线路引出，对输入/输出接口进行重新布局。
从图3d可以看出填充层32和第一金属层70在第二方向上的尺寸均小于绝缘结构40在第二方向上的尺寸，也就是说第二导电柱110并未贯穿过填充层32和第一金属层70，如此，可以第一导电柱80和第二导电柱110之间不连通，从而使得第一导电柱80和第二导电柱110之间互不影响。
图3d中仅示出一个第二导电柱且第二导电柱的延伸方向为第三方向(Z轴方向)，但是在实施时，可以根据需要设置任意数量的第二导电柱，本公开实施例对此并不限定。层间介质的作用不仅是隔离相邻的第二导电柱，而且还可以隔离第一金属层和第二金属层。
实施时，第二金属层可以用作焊盘，这种情况下第二金属层所在的一整层可以包括焊盘和用于隔离焊盘的隔离材料。由于相邻焊盘之间设置有隔离材料，因此减少焊盘之间的漏电流。
在一些实施例中，层间介质采用的材料可以包括以下至少之一：硼磷硅酸盐玻璃 (Boro-phospho-silicate Glass，BPSG)、无掺杂硅酸盐玻璃(Un-doped Silicate Glass，USG)、磷硅酸盐玻璃(Phospho Silicate Glass，PSG)、正硅酸乙酯(Tetraethyl Orthosilicate，TEOS)、四氢化硅(SiH 4)氧化物、二氧化硅、旋涂电介质(Spin On Dielectric，SOD)或者其他适当电介质。
第二金属层采用的材料可以是金属硅化物、导电金属氮化物(例如钛氮化物、钽氮化物、钨氮化物等)和金属(例如钨、铜、钛、钽等)中的一种或更多种。实施时，第二金属层采用的材料可以与第一金属层采用的材料相同，第二金属层采用的材料也可以与第一金属层采用的材料不相同。
本公开实施例提供一种半导体结构的形成方法，参考图4a，步骤S401至步骤S403。其中：
步骤S401，提供控制芯片和存储芯片；其中，控制芯片包括外围区域，存储芯片包括阵列区域；
参考图2a，提供存储芯片10，存储芯片10包括阵列区域11。参考图2b，提供控制芯片20，控制芯片20包括外围区域21。
步骤S402，将控制芯片与存储芯片面对面键合连接；
参考图2c，将控制芯片20与存储芯片10面对面键合连接，键合面是AA。本公开实施例中，控制芯片与存储芯片按照面对面的方式键合连接不仅可以使后续位线结构设置在晶体管的上方，可以降低形成位线结构的工艺难度，而且由于位线结构的表面可以作为键合面，从而可以增加位线结构的导电性能，可以提高位线结构的传输性能。此外，控制芯片与存储芯片按照面对面的方式键合连接能够使导电路由的数量和复杂性最小化，在保持预期的产率的同时使控制芯片和存储芯片的形成变得更加容易。
步骤S403，在存储芯片的远离键合面一侧的表面上形成电容结构，其中，电容结构中的电容器与阵列区域中的对应晶体管电连接。
参考图2c，在存储芯片10的远离键合面AA一侧的表面上形成电容结构30，其中，电容结构30中的电容器31与阵列区域11中的对应晶体管101电连接。
在一些实施例中，参考图2a，晶体管101包括：沟道柱1011和环绕沟道柱1011的全环栅结构1012。对应地，存储芯片的形成方法包括以下步骤：
步骤S4011，提供初始衬底，初始衬底包括沿第一方向延伸、沿第二方向排列的沟道柱和凹槽；
参考图4b，提供初始衬底10a，初始衬底10a包括沿第一方向(X轴方向)延伸、沿第二方向(Y轴方向)排列的沟道柱1011和凹槽1012d。实施时，初始衬底可以包括硅衬底、绝缘体上硅衬底、锗衬底、绝缘体上锗衬底、锗硅衬底等等；初始衬底也可以包括其他半导体元素，例如：锗；或包括半导体化合物，例如：碳化硅、砷化镓、磷化镓、磷化铟、砷化铟或锑化铟；或包括其他半导体合金，例如：硅锗、磷化砷镓、砷化铟铝、砷化镓铝、砷化铟镓、磷化铟镓、和/或磷砷化铟镓或其组合。
步骤S4012，形成环绕沟道柱的全环栅结构。
这里，全环栅结构形成于凹槽中。在一些实施例中，全环栅结构包括：栅介质层、第一子绝缘层、栅金属层和第二子绝缘层。对应地，形成环绕沟道柱的全环栅结构，包括步骤S11至步骤S14：
步骤S11，在沟道柱的外壁形成栅介质层；
参考图4c，在沟道柱1011的外壁形成栅介质层1012a，也就是在凹槽中形成栅介质层1012a。实施时，可以通过任意一种合适的沉积工艺形成栅介质层，例如，化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工 艺或者涂敷工艺。
步骤S12，在形成栅介质层的凹槽的底部形成第一子绝缘层；
参考图4c，在形成栅介质层1012a的凹槽(未标出，可参考图4b)的底部形成第一子绝缘层112。这里，第一子绝缘层采用的材料可以是氮化硅，可以通过化学气相沉积、原子层沉积等合适工艺形成。
步骤S13，在沟道柱上形成栅金属层，栅金属层环绕沟道柱；
参考图4c，在形成栅介质层的沟道柱上形成初始栅金属层1012b＇，初始栅金属层1012b＇的顶表面可以高于初始衬底的顶表面，刻蚀掉部分初始栅金属层1012b＇，得到如图4d所示的栅金属层1012b。这里，栅金属层环绕沟道柱，也就是说，凹槽中有两部分栅金属层，但是这两部分栅金属层并不接触，中间留有空隙。
步骤S14，在凹槽中形成与初始衬底的表面齐平的第二子绝缘层。
参考图4d，在凹槽中形成初始第二子绝缘层113＇，初始第二子绝缘层113＇的顶表面高于初始衬底10a的顶表面。之后采用化学机械研磨、干法刻蚀、湿法刻蚀或其任意组合去除初始衬底10a的顶表面以上的初始第二子绝缘层113＇(以及去除初始衬底的顶表面以上栅介质层1012a)，得到如图4e所示的与初始衬底10a表面齐平的第二子绝缘层113。第二子绝缘层113和第一子绝缘层112是连通的，两者采用的材料可以相同，也可以不同。参考图4e，绝缘层1012c包括第二子绝缘层113和第一子绝缘层112。全环栅结构1012包括：栅介质层1012a、第一子绝缘层112、栅金属层1012b和第二子绝缘层113。
实施时，初始第二子绝缘层采用的材料可以是氮化硅，可以采用与第一子绝缘层相同的工艺形成。
在一些实施例中，阵列区域还包括：与沟道柱和控制芯片电连接的位线结构；存储芯片的形成方法还包括：
步骤S15，在形成全环栅结构的初始衬底的表面上形成位线结构。
参考图4e，在形成全环栅结构1012的初始衬底10a的表面沉积导电材料，形成如图4f所示的位于晶体管上方的位线结构102。这里，由于位线结构可以直接在晶体管上方形成，可以降低位线结构的形成难度。
在一些实施例中，若全环栅结构的底部的表面没有暴露出来，即全环栅结构在第三方向上的尺寸小于初始衬底在第三方向上的尺寸，可能会出现无法将全环栅结构与后续形成的电容结构电连接的情况。因此，形成存储芯片的形成方法还包括：
步骤S16，对初始衬底进行减薄处理，直至暴露出全环栅结构的底部的表面。
这里，形成位线结构的初始衬底的表面和进行减薄处理的初始衬底的表面是相对的两面，并不是同一个表面。参考图4f，采用化学机械研磨、干法刻蚀、湿法刻蚀或其任意组合对初始衬底进行减薄处理，直至暴露出如图4g所示的全环栅结构的底部的表面，这样就形成了存储芯片，存储芯片的一个表面是位线结构102，另一个表面暴露出全环栅结构中的栅介质层1012a。
本公开实施例中，通过对初始衬底进行减薄处理，暴露出全环栅结构的底部的表面，这样有利于将全环栅结构与后续形成电容结构进行电连接。
在一些实施例中，可以在将控制控制芯片与存储芯片面对面键合连接之后，再对存储芯片进行减薄处理，直至暴露出全环栅结构的底部的表面。
在一些实施例中，参见图5a，存储芯片还包括非阵列区域；在将控制芯片与存储芯片键合连接之后，形成半导体结构的方法还包括步骤S404和步骤S405，其中：
步骤S404，在全环栅结构上以及非阵列区域上形成绝缘结构；
步骤S405，在沟道柱上形成接触结构，接触结构包括节点接触和/或着落垫，全环 栅结构上的绝缘结构用于隔离相邻的接触结构。
实施时，可以先在全环栅结构上以及非阵列区域上沉积绝缘材料；之后通过刻蚀绝缘材料，形成空隙，空隙可以暴露出沟道柱；最后可以在空隙中形成接触结构。接触结构可以包括节点接触，也可以包括着落垫，也可以同时包括节点接触和着落垫。
同时参考图3b和图4g，在全环栅结构1012上以及非阵列区域12上形成绝缘结构40。在沟道柱1011上形成包括节点接触50和着落垫60的接触结构。
这里，电容结构中的电容器通过节点接触和/或着落垫与阵列区域中的晶体管电连接。
在一些实施例中，参考图5b，步骤S403“在存储芯片的远离键合面一侧的表面上形成电容结构”，可以包括步骤S4031至步骤S4036，其中：
步骤S4031，在存储芯片的远离键合面一侧的表面上形成叠层，叠层自下而上依次包括：初始第一牺牲层、初始第一支撑层、初始第二牺牲层和初始第二支撑层；
这里，初始第一支撑层和初始第二支撑层采用的材料均可以包括以下至少之一：氧化硅、氮化硅、氮碳化硅、氮氧化硅。本公开实施例中的初始第一牺牲层采用的材料可以为氧化硅，初始第一支撑层和初始第二支撑层采用的材料可以均为氮化硅。
初始第一牺牲层、初始第一支撑层、初始第二牺牲层和初始第二支撑层均可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺或者涂敷工艺。
参考图5c，在存储芯片10的远离键合面AA一侧的表面上形成叠层33，叠层33自下而上依次包括：初始第一牺牲层316＇、初始第一支撑层314＇、初始第二牺牲层317＇和初始第二支撑层315＇。
步骤S4032，图案化叠层，以在存储芯片的远离键合面一侧的表面上形成电容孔；
在图案化叠层时，需要沿Y轴方向刻蚀部分初始第一牺牲层、部分初始第一支撑层、部分初始第二牺牲层和部分第二支撑层。实施时，可以采用干法刻蚀(例如等离子刻蚀工艺、反应离子刻蚀工艺或者离子铣工艺)刻蚀叠层33，形成如图5d所示的电容孔318。干法刻蚀采用的气体可以为三氟甲烷(CHF 3)、四氟化碳(CF 4)、二氟甲烷(CH 2F 2)、氢溴酸(HBr)、氯气(Cl 2)或六氟化硫(SF 6)中的一种或它们的组合。
在一些实施例中，参考图5d，在形成电容孔的时候会刻蚀掉非阵列区域12上的叠层结构，暴露出绝缘结构40的表面。
步骤S4033，在每一电容孔的内壁形成第一电极层；
参考图5e，在每一电容孔318的内壁形成第一电极层311。
步骤S4034，图形化剩余的初始第一支撑层和剩余的初始第二支撑层，以在相邻多个电容孔之间形成开口；
这里，在相邻多个电容孔之间形成开口的作用是方便后续刻蚀开口下方的初始第一牺牲层和初始第二牺牲层，从而方便在第一电极层的表面形成介电层和第二电极层。
参考图5f，图形化剩余的初始第一支撑层和剩余的初始第二支撑层，以在相邻电容孔(或者第一电极层)之间形成开口319。
步骤S4035，通过开口刻蚀剩余的初始第一牺牲层和剩余的初始第二牺牲层；
参考图5f，通过开口319刻蚀剩余的初始第一初始牺牲层316＇和剩余的初始第二初始牺牲层317＇，去除剩余的初始第一初始牺牲层316＇和剩余的初始第二初始牺牲层317＇。其中，可以采用干法刻蚀或者湿法刻蚀去除剩余的初始第一初始牺牲层和剩余的初始第二初始牺牲层。湿法蚀刻溶液可以是包括稀释氢氟酸(DHF)与氨水(NH 4OH)的混合溶液，也可以是包括稀释氢氟酸与四甲基氢氧化铵(TMAH)的混合溶液。
步骤S4036，在第一电极层的表面依次形成介电层和第二电极层，以形成电容结构。
实施时，可以通过任意一种合适的沉积工艺形成介电层和第二电极层，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺或者涂敷工艺。参考图3b，在第一电极层311的表面依次形成介电层313和第二电极层312，以形成电容结构30。
在一些实施例中，参考图6a，形成半导体结构的方法还包括步骤S406和步骤S407，其中：
步骤S406，在非阵列区域的远离键合面一侧的表面上、电容结构的上表面以及电容器之间依次形成填充层和第一金属层；其中，填充层与第二电极层电连接；
实施时，可以通过任意一种合适的沉积工艺形成填充层和第一金属层，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺或者涂敷工艺。参考图3c，在非阵列区域12的远离键合面一侧的表面上、电容结构30的上表面以及电容器31之间依次形成填充层32和第一金属层70，填充层32与第二电极层312电连接。
步骤S407，在非阵列区域内形成连接第一金属层和接触垫的第一导电柱，以将电容器与接触垫电连接；其中，接触垫位于外围区域，用于电连接存储芯片。
参考图6b，在非阵列区域12内形成第一通孔80a，在第一通孔80a中填充导电材料，以形成如图3c所示的第一导电柱80。
在一些实施例中，参考图6c，形成半导体结构的方法还包括步骤S408至步骤S410，其中：
步骤S408，在第一金属层和绝缘结构上形成层间介质；
参考图3d，第一金属层70和绝缘结构40上沉积形成层间介质90。
步骤S409，在层间介质上形成第二金属层；
实施时，可以通过任意一种合适的沉积工艺形成层间介质和第二金属层，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺或者涂敷工艺。参考图3d，在层间介质90上沉积形成第二金属层100。
步骤S410，形成贯穿层间介质、绝缘结构以及非阵列区域的第二导电柱，第二导电柱用于连接第二金属层和接触垫。
参考图3d，形成贯穿层间介质90、绝缘结构40以及非阵列区域12的第二导电柱110。这里，第二导电柱的形成步骤与第一导电柱的形成步骤类似，此处不再赘述。
本公开实施例还提供一种半导体结构的形成方法，包括步骤S501至步骤S503，其中：
步骤S501，提供控制芯片和存储芯片；其中，控制芯片包括外围区域，存储芯片包括阵列区域；
步骤S502，在存储芯片上形成电容结构；其中，电容结构中的电容器与阵列区域中的对应存储单元电连接；
步骤S503，将存储芯片与控制芯片面对面键合连接；其中，电容结构远离键合面。
本公开实施例提供的半导体结构的形成方法与上述形成方法的区别在于：先在存储芯片上形成电容结构，之后再将存储芯片与控制芯片面对面键合连接。如此，可以减小由于电容结构形成温度较高对控制芯片中外围电路的影响。
在本公开所提供的几个实施例中，应该理解到，所揭露的结构和方法，可以通过非目标的方式实现。以上所描述的结构实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示 的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开实施例的一些实施方式，但本公开实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。因此，本公开实施例的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例中，半导体结构包括面对面键合连接的控制芯片和存储芯片以及位于存储芯片的远离键合面一侧的表面的电容结构。一方面，由于存储芯片与控制芯片面对面键合连接，即存储芯片的正面和控制芯片的正面相对堆叠在一起，相较于平面半导体结构，可以减小半导体结构的尺寸，从而实现更好地微缩；相较于其他键合连接方式，控制芯片和存储芯片面对面键合连接可以使导电路由的数量和复杂性最小化，在保持预期的产率的同时使控制芯片和存储芯片的形成变得更加容易。另一方面，本公开实施例中的组成半导体结构的存储芯片和控制芯片可以同时生产，之后再进行键合，这样可以节省生产时间，进而提高生产效率。

Claims (20)

  1. 一种半导体结构，包括：存储芯片、控制芯片和电容结构；其中：
    所述存储芯片包括阵列区域，所述控制芯片包括外围区域；
    所述控制芯片与所述存储芯片面对面键合连接；
    所述电容结构，位于所述存储芯片的远离键合面一侧的表面上，所述电容结构中的电容器与所述阵列区域中的对应晶体管电连接。
  2. 根据权利要求1所述的结构，其中，所述晶体管包括：沟道柱和环绕所述沟道柱的全环栅结构；其中，所述沟道柱沿第一方向延伸且沿第二方向排列，所述电容器与所述沟道柱的一端电连接。
  3. 根据权利要求2所述的结构，其中，所述全环栅结构包括：栅介质层、栅金属层和绝缘层；
    其中：所述栅介质层位于所述沟道柱的外壁；
    所述栅金属层与所述栅介质层的侧壁接触；
    所述绝缘层位于相邻的所述沟道柱之间的凹槽内，并填满所述凹槽。
  4. 根据权利要求3所述的结构，其中，所述阵列区域还包括：位线结构，所述位线结构位于所述存储芯片的靠近所述键合面的一侧的表面上，所述位线结构与所述控制芯片和所述沟道柱电连接。
  5. 根据权利要求2所述的结构，其中，所述外围区域包括外围电路和与所述外围电路电连接的接触垫；
    其中，所述外围电路，用于控制所述晶体管的导通与截止，以向对应的所述电容器中存储数据，和/或从对应的所述电容器中读取数据；
    所述接触垫，用于电连接所述存储芯片。
  6. 根据权利要求5所述的结构，其中，所述存储芯片还包括非阵列区域；所述结构还包括：
    位于所述全环栅结构上以及所述非阵列区域上的绝缘结构；
    位于所述沟道柱上的节点接触和/或着落垫；所述电容结构中的电容器通过所述节点接触和/或所述着落垫与所述阵列区域中的晶体管电连接。
  7. 根据权利要求6所述结构，其中，所述电容器包括：第一电极层、第二电极层、和位于所述第一电极层与所述第二电极层之间的介电层，其中，所述第一电极层与所述存储芯片电连接。
  8. 根据权利要求7所述的结构，其中，所述电容器之间包括：平行设置的第一支撑层和第二支撑层；
    其中，所述第一支撑层设置于所述电容器的中部外周；
    所述第二支撑层设置于所述电容器的顶部外周；
    所述第一支撑层和所述第二支撑层共同用于支撑所述电容器。
  9. 根据权利要求7或8所述的结构，其中，所述结构还包括：填充层、第一金属层和第一导电柱；其中：
    所述填充层位于所述非阵列区域的远离所述键合面一侧的表面上、所述电容结构的上表面以及所述电容器之间，所述填充层与所述第二电极层电连接；
    所述第一金属层位于所述填充层上；
    所述第一导电柱位于所述非阵列区域内，所述第一导电柱的两端分别与所述第一金属层和所述接触垫连接，用于电连接所述电容器与所述接触垫。
  10. 根据权利要求9所述的结构，其中，所述结构还包括：
    位于所述第一金属层上和所述绝缘结构上的层间介质；
    位于所述层间介质上的第二金属层；
    连接所述第二金属层和所述接触垫的第二导电柱；
    其中，所述第二导电柱贯穿所述层间介质、绝缘结构以及所述非阵列区域，用于电连接所述第二金属层和所述接触垫。
  11. 一种半导体结构的形成方法，包括：
    提供控制芯片和存储芯片；其中，所述控制芯片包括外围区域，所述存储芯片包括阵列区域；
    将所述控制芯片与所述存储芯片面对面键合连接；
    在所述存储芯片的远离键合面一侧的表面上形成电容结构，其中，所述电容结构中的电容器与所述阵列区域中的对应晶体管电连接。
  12. 根据权利要求11所述的方法，其中，所述晶体管包括：沟道柱和环绕所述沟道柱的全环栅结构；所述存储芯片的形成方法包括：
    提供初始衬底，所述初始衬底包括沿第一方向延伸、沿第二方向排列的所述沟道柱和凹槽；
    形成环绕所述沟道柱的所述全环栅结构。
  13. 根据权利要求12所述的方法，其中，所述全环栅结构包括：栅介质层、第一子绝缘层、栅金属层和第二子绝缘层；形成环绕所述沟道柱的所述全环栅结构，包括：
    在所述沟道柱的外壁形成所述栅介质层；
    在形成所述栅介质层的凹槽的底部形成所述第一子绝缘层；
    在所述沟道柱上形成所述栅金属层，所述栅金属层环绕所述沟道柱；
    在凹槽中形成与所述初始衬底的表面齐平的所述第二子绝缘层。
  14. 根据权利要求12或13所述的方法，其中，所述阵列区域还包括：与所述沟道柱和所述控制芯片电连接的位线结构；所述存储芯片的形成方法还包括：
    在形成全环栅结构的初始衬底的表面上形成所述位线结构。
  15. 根据权利要求14所述的方法，其中，所述存储芯片的形成方法还包括：
    对所述初始衬底进行减薄处理，直至暴露出所述全环栅结构的底部的表面。
  16. 根据权利要求14所述的方法，其中，在将所述控制芯片与所述存储芯片面对面键合连接之后，还包括：对所述存储芯片进行减薄处理，直至暴露出所述全环栅结构的底部的表面。
  17. 根据权利要求15所述的方法，其中，所述存储芯片还包括非阵列区域；在将所述控制芯片与所述存储芯片键合连接之后，还包括：
    在所述全环栅结构上以及所述非阵列区域上形成绝缘结构；
    在所述沟道柱上形成接触结构，所述接触结构包括节点接触和/或着落垫，所述全环栅结构上的绝缘结构用于隔离相邻的所述接触结构；
    其中，所述电容结构中的电容器通过所述接触结构与所述阵列区域中的晶体管电连接。
  18. 根据权利要求17所述的方法，其中，在所述存储芯片的远离键合面一侧的表面上形成电容结构，包括：
    在所述存储芯片的远离键合面一侧的表面上形成叠层，所述叠层自下而上依次包括：初始第一牺牲层、初始第一支撑层、初始第二牺牲层和初始第二支撑层；
    图案化所述叠层，以在所述存储芯片的远离键合面一侧的表面上形成电容孔；
    在每一所述电容孔的内壁形成第一电极层；
    图形化剩余的所述初始第一支撑层和剩余的所述初始第二支撑层，以在相邻多个电容孔之间形成开口；
    通过所述开口刻蚀剩余的所述初始第一牺牲层和剩余的所述初始第二牺牲层；
    在所述第一电极层的表面依次形成介电层和第二电极层，以形成所述电容结构。
  19. 根据权利要求18所述的方法，其中，所述方法还包括：
    在所述非阵列区域的远离所述键合面一侧的表面上、所述电容结构的上表面以及所述电容器之间依次形成填充层和第一金属层；其中，所述填充层与所述第二电极层电连接；
    在所述非阵列区域内形成连接所述第一金属层和接触垫的第一导电柱，以将所述电容器与所述接触垫电连接；其中，所述接触垫位于所述外围区域，用于电连接所述存储芯片。
  20. 根据权利要求19所述的方法，其中，所述方法还包括：
    在所述第一金属层和所述绝缘结构上形成层间介质；
    在所述层间介质上形成第二金属层；
    形成贯穿所述层间介质、所述绝缘结构以及所述非阵列区域的第二导电柱，所述第二导电柱用于连接所述第二金属层和所述接触垫。
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