WO2024098275A1 - 移相器、移相器阵列、天线阵列及电子设备 - Google Patents

移相器、移相器阵列、天线阵列及电子设备 Download PDF

Info

Publication number
WO2024098275A1
WO2024098275A1 PCT/CN2022/130817 CN2022130817W WO2024098275A1 WO 2024098275 A1 WO2024098275 A1 WO 2024098275A1 CN 2022130817 W CN2022130817 W CN 2022130817W WO 2024098275 A1 WO2024098275 A1 WO 2024098275A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
phase shifter
bias voltage
sub
dielectric substrate
Prior art date
Application number
PCT/CN2022/130817
Other languages
English (en)
French (fr)
Inventor
丁屹
崔钊
马勇
曲峰
姚琪
车春城
Original Assignee
京东方科技集团股份有限公司
北京京东方传感技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方传感技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/130817 priority Critical patent/WO2024098275A1/zh
Publication of WO2024098275A1 publication Critical patent/WO2024098275A1/zh

Links

Images

Definitions

  • the present disclosure belongs to the field of communication technology, and particularly relates to a phase shifter, a phase shifter array, an antenna array and an electronic device.
  • the liquid crystal phase shifter periodically introduces liquid crystal capacitors, and adjusts the dielectric constant of the liquid crystal layer by controlling the liquid crystal orientation, thereby adjusting the total capacitance per unit length branch, thereby achieving the effect of phase shifting.
  • the design parameters that can be adjusted are mainly concentrated on the area and capacitor spacing of the overlapping capacitors.
  • For the control of the liquid crystal material filled in the overlapping capacitors usually only a single drive signal is used to uniformly adjust the deflection of the liquid crystal molecules in all overlapping capacitors.
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provides a phase shifter, a phase shifter array, an antenna array and an electronic device.
  • an embodiment of the present disclosure provides a phase shifter, comprising: a first dielectric substrate and a second dielectric substrate arranged opposite to each other, a first transmission line and a second transmission line arranged on a side of the first dielectric substrate close to the second dielectric substrate, a plurality of patch electrodes arranged on a side of the second dielectric substrate close to the first dielectric substrate, and an adjustable dielectric layer located between a layer where the transmission line is located and a layer where the plurality of patch electrodes are located; two ends of each of the plurality of patch electrodes overlap with the orthographic projections of the first transmission line and the second transmission line on the first dielectric substrate, respectively; wherein at least two of the plurality of patch electrodes are connected to different first bias voltage lines.
  • each of the plurality of patch electrodes is connected to a different first bias voltage line.
  • At least two of the plurality of patch electrodes are connected to the same first bias signal line, and the patch electrodes connected to the same first bias voltage line are arranged adjacent to each other.
  • every two adjacent patch electrodes are connected to one first bias voltage line, and different first bias voltage lines are connected to different patch electrodes.
  • At least one patch electrode is spaced between the patch electrodes connected to the same first bias voltage line.
  • Part of the first bias voltage line includes a first sub-signal line and a second sub-signal line sequentially arranged in a direction away from the second dielectric substrate; a first interlayer insulating layer is arranged between the layer where the second sub-signal line is located and the layer where the first sub-signal line is located; the first sub-signal line and the second sub-signal line are electrically connected through a via penetrating the first interlayer insulating layer, and the first sub-signal line is electrically connected to the patch electrode.
  • Each of the plurality of patch electrodes is connected to the first bias voltage line via a switch unit, and different patch electrodes are connected to different switch units, and the switch units connected to the same first bias voltage line are connected to different scan lines.
  • the switch units connected to the patch electrodes located at odd numbers are connected to the same scan line, and the switch units connected to the patch electrodes located at even numbers are connected to the same scan line.
  • the switch unit comprises a thin film transistor; a first electrode of the thin film transistor is electrically connected to the first bias voltage line, a second electrode of the thin film transistor is electrically connected to the patch electrode, and a control electrode of the thin film transistor is electrically connected to the scan line.
  • the first bias voltage line includes a first sub-signal line and a second sub-signal line arranged in sequence along a direction away from the second dielectric substrate; and a first interlayer insulating layer is arranged between the layer where the second sub-signal line is located and the layer where the first sub-signal line is located; the first end of the first sub-signal line is connected to the patch electrode, the second end of the first sub-signal line is connected to the first connecting part, the first end of the second sub-signal line is connected to the second connecting part, and the first connecting part is connected to the second connecting part through a via hole penetrating the first interlayer insulating layer; and the line width of the first connecting part is greater than the line width of the first sub-signal line, and the line width of the second connecting part is greater than the line width of the second sub-signal line.
  • the materials of the first sub-signal line and the second sub-signal line are both metal.
  • the phase shifter further includes a signal electrode disposed on a side of the first dielectric substrate close to the second dielectric substrate, and the first transmission line and the second transmission line are respectively located on both sides of an extending direction of the signal electrode.
  • the phase shifter further includes a second bias voltage line electrically connected to the first transmission line and the second transmission line.
  • an embodiment of the present disclosure provides a phase shifter array, which includes a plurality of the phase shifters arranged in an array, and the phase shifters are any of the phase shifters described above.
  • the phase shifters located in the same row wherein the switching units connected to the odd-numbered patch electrodes in each phase shifter are connected to the same scan line, and the switching units connected to the even-numbered patch electrodes are connected to the same scan line; and/or, the phase shifters located in the same column, wherein the arrangement order in each phase shifter corresponds to that each patch electrode is connected to the same first bias voltage line.
  • an embodiment of the present disclosure provides an antenna array, which includes any of the phase shifter arrays described above.
  • the antenna array further comprises a radiation array, the radiation array comprises a plurality of radiation units, and the radiation units are arranged in a one-to-one correspondence with the phase shifters in the phase shifter array.
  • the antenna array further includes a feeding network, and the feeding network is configured to feed the phase shifter array.
  • the feeding network feeds the phase shifter array through any one of coupling slots, waveguides or conductive vias.
  • an embodiment of the present disclosure provides an electronic device, comprising any of the antenna arrays described above.
  • FIG. 1 is a top view of an exemplary phase shifter.
  • FIG2 is a cross-sectional view taken along line A-A' of FIG1.
  • FIG. 3 is a top view of a phase shifter according to an embodiment of the present disclosure.
  • FIG4 is a cross-sectional view taken along the line B-B' of FIG3.
  • FIG. 5 is a top view of a second exemplary phase shifter according to an embodiment of the present disclosure.
  • FIG. 6 is a top view of a third exemplary phase shifter according to an embodiment of the present disclosure.
  • FIG. 7 is a top view of a fourth exemplary phase shifter according to an embodiment of the present disclosure.
  • FIG. 8 is a top view of a fifth exemplary phase shifter according to an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view of a phase shifter according to a fifth example of an embodiment of the present disclosure.
  • FIG. 10 is a top view of a sixth exemplary phase shifter according to an embodiment of the present disclosure.
  • FIG. 11 is a top view of the phase shifter array according to an embodiment of the present disclosure.
  • FIG. 12 is a block diagram of an antenna array according to an embodiment of the present disclosure.
  • FIG1 is a top view of an exemplary phase shifter
  • FIG2 is a cross-sectional view taken along line A-A' of FIG1; as shown in FIGS. 1 and 2, the phase shifter comprises: a first dielectric substrate 10 and a second dielectric substrate 20 arranged opposite to each other, a first transmission line 11 and a second transmission line 12 arranged on the side of the first dielectric substrate 10 close to the second dielectric substrate 20, a plurality of patch electrodes 21 arranged on the side of the second dielectric substrate 20 close to the first dielectric substrate 10, and an adjustable dielectric layer arranged between the layer where the first transmission line 11 and the second transmission line 12 are located and the layer where the plurality of patch electrodes 21 are located.
  • the two ends of any patch electrode 21 overlap with the orthographic projections of the first transmission line 11 and the second transmission line 12 on the first dielectric substrate 10.
  • the adjustable dielectric layer includes but is not limited to the liquid crystal layer 30.
  • the adjustable dielectric layer uses the liquid crystal layer 30 as an example.
  • a plurality of patch electrodes 21 can be electrically connected through a first bias voltage line 22, and the first transmission line 11 and the second transmission line 12 can be electrically connected through a second bias voltage line 23.
  • the second bias voltage written into the second bias voltage line 23 is a ground voltage.
  • the two ends are at least partially overlapped with the orthographic projections of the first transmission line 11 and the second transmission line 12 on the first dielectric substrate 10, respectively, to define a capacitor region. At this time, the patch electrode 21 forms an overlapping capacitor with the first transmission line 11 and the second transmission line 12 in the capacitor region.
  • each patch electrode 21 is electrically connected through the same first bias voltage line 22, in order to meet the requirements of impedance matching, working bandwidth, phase shift efficiency, etc., the design parameters that can be adjusted are mainly concentrated on the area and capacitor spacing of the overlap capacitor, and for the control of the liquid crystal material filled in the overlap capacitor, usually only a single first bias voltage is used to uniformly adjust the deflection of the liquid crystal molecules in all overlap capacitors. As a result, the design freedom of the phase shifter is greatly limited.
  • FIG. 3 is a top view of a phase shifter of an embodiment of the present disclosure
  • FIG. 4 is a cross-sectional view of B-B' of FIG. 3; as shown in FIGS. 3 and 4, an embodiment of the present disclosure provides a phase shifter, which includes a first dielectric substrate 10 and a second dielectric substrate 20 arranged opposite to each other, a first transmission line 11 and a second transmission line 12 arranged on a side of the first dielectric substrate 10 close to the second dielectric substrate 20, a plurality of patch electrodes 21 arranged on a side of the second dielectric substrate 20 close to the first dielectric substrate 10, and an adjustable dielectric layer arranged between a layer where the first transmission line 11 and the second transmission line 12 are located and a layer where the plurality of patch electrodes 21 are located.
  • any patch electrode 21 overlap with the orthographic projections of the first transmission line 11 and the second transmission line 12 on the first dielectric substrate 10, respectively.
  • at least two of the plurality of patch electrodes 21 are connected to different first bias voltage lines 22.
  • the adjustable dielectric layer is the liquid crystal layer 30 and the first transmission line 11 and the second transmission line 12 are loaded with a ground voltage.
  • the multiple patch electrodes 21 in the disclosed embodiment are connected to different first bias voltage lines 22, different first bias voltages can be applied to the patch electrodes 21 connected to different first bias voltage lines 22, so that the liquid crystal molecules in the corresponding capacitor regions are deflected to different degrees and present different dielectric constants, thereby making the corresponding capacitor regions obtain different capacitance values.
  • a design variable can be added when designing the phase shifter to improve the design freedom.
  • the impedance matching of the phase shifter is optimized by sacrificing part of the adjustable performance of the liquid crystal layer 30, and the working bandwidth is expanded.
  • the design scheme based on the disclosed embodiment can adjust the dielectric constant of the liquid crystal molecules of the overlapping capacitor according to the actual size deviation of each overlapping capacitor to compensate for the capacitance value.
  • the plurality of patch electrodes 21 may be periodically arranged along the extension direction of the first transmission line 11, for example, the spacing between the patch electrodes 21 is equal.
  • the spacing between the patch electrodes 21 may also increase or decrease monotonically according to a certain rule.
  • the two ends of any patch electrode 21 are respectively referred to as the first end and the second end.
  • the capacitance region defined by the overlap of the first end of the patch electrode 21 and the orthographic projection of the first transmission line 11 on the first dielectric substrate 10 is the first capacitance region
  • the capacitance region defined by the overlap of the second end of the patch electrode 21 and the orthographic projection of the second transmission line 12 on the first dielectric substrate 10 is the second capacitance region.
  • the first capacitance region and the second capacitance region are set in one-to-one correspondence, and the areas of the correspondingly set first capacitance region and second capacitance region are equal.
  • the areas of the various first capacitor regions may be equal, or at least two of the multiple first capacitor regions may have unequal areas.
  • the areas of the various first capacitor regions may be equal, or at least two of the multiple first capacitor regions may have unequal areas.
  • the areas of the multiple first capacitor regions may have unequal areas, in the direction from the two ends of the first transmission line 11 to the midpoint, the area of the first capacitor region close to the midpoint is not less than the area of the first capacitor region far from the midpoint.
  • at least two of the multiple first capacitor regions having unequal areas include but are not limited to unequal widths of at least two first capacitor regions and unequal lengths of at least two first capacitor regions.
  • the method of achieving unequal widths of at least two first capacitor regions may be that at least two of the patch electrodes 21 have unequal widths; the method of achieving unequal lengths of at least two first capacitor regions includes at least two of the patch electrodes 21 having unequal lengths.
  • each second capacitor region can also be set in the same manner as the area of the first capacitor region, which will not be repeated here.
  • the phase shifter of the disclosed embodiment may further include a first protective layer 14 disposed on the side of the layer where the first transmission line 11 and the second transmission line 12 are located close to the liquid crystal layer 30, a second protective layer 23 disposed on the side of the layer where the signal electrode 17 is located close to the liquid crystal layer 30, and a support column 15 with both ends abutting against the first protective layer 14 and the second protective layer 23.
  • the first protective layer 14 is used to protect the first transmission line 11 and the second transmission line 12
  • the second protective layer 23 is used to protect the patch electrode 21
  • the materials of the first protective layer 14 and the second protective layer 23 can both be made of silicon nitride
  • the support column 15 is used to maintain the thickness of the liquid crystal box, and the material can be a resin material.
  • phase shifter in the embodiment of the present disclosure is described below with reference to specific examples.
  • each patch electrode 21 in the phase shifter is connected to the first bias voltage lines 22 in a one-to-one correspondence.
  • each patch electrode 21 can be loaded with the first bias voltage line 22 through an independent first bias voltage line 22.
  • the capacitance value of the overlapping capacitor formed by each patch electrode 21 and the first transmission line 11 and the second transmission line 12 can be controlled by controlling the magnitude of the voltage loaded on each first bias voltage line 22. In this way, a design variable can be added when designing the phase shifter, thereby improving the degree of design freedom.
  • the first transmission line 11, the second transmission line 12 and the patch electrode 21 can all be made of metal materials, such as copper, aluminum, molybdenum, or aluminum/molybdenum.
  • the first bias voltage line 22 and the second bias voltage line 23 can be made of transparent conductive materials, such as indium tin oxide. Further, the first bias voltage line 22 is arranged on the side of the layer where the patch electrode 21 is located close to the second dielectric substrate 20, and the second bias voltage line 23 is arranged on the side of the first transmission line 11 and the second transmission line 12 close to the first dielectric substrate 10.
  • the phase shifter not only includes the above structure, but also includes a first flexible circuit board, a plurality of first connection pads are arranged on the side of the second dielectric substrate 20 close to the liquid crystal layer 30, and the first bias voltage line 22 is connected to the first connection pads one by one, and the first flexible circuit board is bonded to the first connection pads, and the first flexible circuit board can load the first bias voltage to the first bias voltage line 22 through the first connection pads.
  • a second connection pad can be arranged on the side of the second dielectric substrate 20 close to the liquid crystal layer 30, and the second bias voltage line 23 can be electrically connected to the second connection pad through the ACF glue directly located between the first dielectric substrate 10 and the second dielectric substrate 20, and the second connection pad can also be electrically connected to the first flexible circuit board, and the first flexible circuit board can load the second bias voltage line 23 with the second bias voltage (ground voltage) through the second connection pad.
  • a second flexible circuit board can also be arranged in the phase shifter of the embodiment of the present disclosure, the second connection pad is arranged on the side of the first dielectric substrate 10 close to the liquid crystal layer 30, the second bias signal line is electrically connected to the second connection pad, and the second flexible circuit board is bonded to the second bias signal line.
  • FIG5 is a top view of the phase shifter of the second example of the embodiment of the present disclosure; as shown in FIG5, in this example, at least two of the multiple patch electrodes 21 are connected to the same first bias voltage line 22, and the patch electrodes 21 connected to the same first bias voltage line 22 are arranged adjacent to each other, for example: every two adjacently arranged patch electrodes 21 are connected to the same first bias voltage line 22, and different first bias voltage lines 22 are connected to different patch electrodes 21.
  • FIG5 only takes the example of each first bias voltage line 22 corresponding to two patch electrodes 21.
  • each first bias voltage line can also be connected to three or even more patch electrodes 21, which are not listed one by one here.
  • the setting of the first bias voltage line 22 can be appropriately reduced to facilitate wiring, and the number of ports required for the printed circuit can also be reduced, thereby reducing costs.
  • the remaining structures can adopt the same configuration as that of the first example, so they will not be repeated here.
  • FIG6 is a top view of a phase shifter of a third example of an embodiment of the present disclosure; as shown in FIG6 , in this example, at least two of the plurality of patch electrodes 21 are connected to the same first bias voltage line 22, and there is at least one patch electrode 21 between the patch electrodes 21 connected to the same first bias voltage line 22, and different first bias voltage lines 22 are connected to different patch electrodes 21.
  • the phase shifter includes 6 patch electrodes 21, which are arranged sequentially from the 1st to the 6th patch electrodes 21 from the left in the figure, wherein the 1st patch electrode 21 and the 3rd patch electrode 21 are connected to a first bias voltage line 22, the 2nd patch electrode 21 and the 5th patch electrode 21 are connected to a first bias voltage line 22, and the 4th patch electrode 21 and the 6th patch electrode 21 are connected to a first bias voltage line 22.
  • the adjacent patch electrodes 21 are connected to different first bias voltage lines 22, and at least one patch electrode 21 is also arranged between the patch electrodes 21 connected to the first bias voltage line 22, in order to avoid short circuit between the first bias voltage lines 22, part of the first bias voltage lines 22 adopts a structure in which the first sub-signal line 221 and the second sub-signal line 222 are arranged in layers and electrically connected.
  • part of the first bias voltage lines 22 include the first sub-signal line 221 and the second sub-signal line 222 arranged in sequence in a direction away from the second dielectric substrate 20; and a first interlayer insulating layer is arranged between the layer where the second sub-signal line 222 is located and the layer where the first sub-signal line 221 is located; the first sub-signal line 221 and the second sub-signal line 222 are electrically connected through a via penetrating the first interlayer insulating layer, and the first sub-signal line 221 is electrically connected to the patch electrode 21.
  • the second sub-signal line 222 is arranged in the same layer as another part of the first bias voltage lines 22.
  • the first bias voltage line 22 connecting the second patch electrode 21 and the fifth patch electrode 21 is formed by electrically connecting the first sub-signal line 221 and the second sub-signal line 222 , and the second sub-signal line 222 is arranged on the same layer as the remaining two first bias voltage lines 22 .
  • the remaining structures can adopt the same configuration as that of the first example, so they will not be described again.
  • FIG. 7 is a top view of the phase shifter in the fourth example of the embodiment of the present disclosure; as shown in FIG. 7 , the structure of the phase shifter in this example is substantially the same as that of the phase shifter in the second example, with the only difference being that the first bias voltage line 22 includes a first sub-signal line 221 and a second sub-signal line 222 sequentially arranged in a direction away from the second dielectric substrate 20; and a first interlayer insulating layer is arranged between the layer where the second sub-signal line 222 is located and the layer where the first sub-signal line 221 is located; the first end of the first sub-signal line 221 is connected to the patch electrode 21, the second end of the first sub-signal line 221 is connected to the first connecting portion 241, the first end of the second sub-signal line 222 is connected to the second connecting portion 242, and the first connecting portion 241 is connected to the second connecting portion 242 through a via penetrating the first interlayer insulating layer; and
  • first sub-signal line 221 and the second sub-signal line 222 may be made of the same material, both of which are made of metal material, such as copper.
  • first sub-signal line 221 and the second sub-signal line 222 may also be made of different materials.
  • the first bias voltage line 22 in the embodiment of the present disclosure may also be formed by connecting more sub-signal lines in series.
  • the multiple sub-signal lines may be the same, partially the same and partially different, or the materials of each sub-signal line may be different.
  • the remaining structures can adopt the same configuration as that of the first example, so they will not be described again.
  • FIG8 is a top view of the phase shifter of the fifth example of the embodiment of the present disclosure
  • FIG9 is a cross-sectional view of the phase shifter of the fifth example of the embodiment of the present disclosure
  • each patch electrode 21 is electrically connected to the corresponding first bias voltage line 22 through a switch unit 40
  • FIG8 takes the phase shifter in the second example as an example, in which each patch electrode 21 is electrically connected to the corresponding first bias voltage line 22 through a switch unit 40.
  • the switch units 40 connected to the same first bias voltage line 22 are connected to different scan lines 25.
  • the switch units 40 connected to the patch electrodes 21 located in an odd number are controlled by the same scan line 25, and the switch units 40 connected to the patch electrodes 21 located in an even number are controlled by the same scan line 25.
  • the switch unit 40 by setting the switch unit 40, and controlling the first bias voltage to be loaded on the patch electrode 21 through the combination of the scan line 25 and the first bias voltage, the number of the first bias voltage lines 22 can be reduced.
  • multiple scan lines 25 provide conduction levels in sequence, and the switch units 40 corresponding to the scan lines 25 with the conduction levels are turned on, so that the first bias voltage line 22 can transmit the first bias voltage to the corresponding patch electrode 21, that is, the first bias voltage line 22 can transmit the first bias voltage to the corresponding patch electrode 21 in a time-sharing manner, thereby saving the number of first bias voltage lines 22.
  • the switch unit 40 includes a thin film transistor 41 , a first electrode of the thin film transistor 41 is electrically connected to the first bias voltage line 22 , a second electrode of the thin film transistor 41 is electrically connected to the patch electrode 21 , and a control electrode of the thin film transistor 41 is electrically connected to the scan line 25 .
  • the thin film transistor 41 includes a control electrode disposed on the second dielectric substrate, a gate insulating layer disposed on the side of the control electrode away from the second dielectric substrate 20, an active layer, a first electrode, and a second electrode disposed on the side of the gate insulating layer away from the control electrode, and a passivation layer disposed on the side of the active layer, the first electrode, and the second electrode away from the gate insulating layer.
  • the patch electrode 21 is connected to the connecting line 16, and the connecting line 16 is connected to the second electrode of the thin film transistor 41 through a via hole penetrating the passivation layer, the first bias voltage line 22 is connected to the first electrode of the thin film transistor 41 through a via hole penetrating the passivation layer, and the scanning line 25 is connected to the control electrode of the thin film transistor 41.
  • FIG. 10 is a top view of the phase shifter of the sixth example of the embodiment of the present disclosure; as shown in FIG. 10 , the structure of the phase shifter of this example is substantially the same as that of the second example, except that the transmission line in this phase shifter is not the double-wire transmission line of the above examples, but a CPW (coplanar waveguide) transmission line, that is, the first dielectric substrate 10 includes not only the first transmission line 11 and the second transmission line 12, but also the signal electrode 17, and the first transmission line 11 and the second transmission line 12 are respectively arranged on both sides of the extension direction of the signal electrode 17.
  • the remaining structures can adopt the same structure as that of the second example, so they will not be repeated here.
  • phase shifter of the second example is modified.
  • the two-wire transmission line can be replaced with a CPW transmission line based on the phase shifters in the first, third, fourth and fifth examples, which is also within the protection scope of the embodiments of the present disclosure.
  • the embodiment of the present disclosure also provides a method for preparing a phase shifter.
  • the following takes the preparation of the first exemplary phase shifter as an example to illustrate the method for preparing the phase shifter of the embodiment of the present disclosure.
  • the preparation method specifically includes the following steps:
  • the first dielectric substrate 10 includes but is not limited to a glass substrate.
  • Step S11 includes a step of cleaning the first dielectric substrate 10 using a standard cleaning process.
  • step S12 may include forming a first metal film as a seed layer on the first dielectric substrate 10 using a technique including but not limited to physical vapor deposition (PVD), followed by electroplating the seed layer, and finally coating, exposing, developing, and etching (e.g., wet etching) to form a pattern including the first transmission line 11 and the second transmission line 12.
  • PVD physical vapor deposition
  • step S13 may include forming a first protective layer 14 by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the support column 15 is made of PS or OC material, and the orthographic projection of the support column 15 on the first dielectric substrate 10 does not overlap with the first transmission line 11 and the second transmission line 12, and also does not overlap with the orthographic projection of the patch electrode 21 formed on the second dielectric substrate 20 on the first dielectric substrate 10.
  • the first alignment layer may be a PI (polyimide) film layer.
  • Step S15 may include forming the PI film layer using an Inkjet process, and then completing a photo-alignment process of the PI film layer using an OA device.
  • the material of the second dielectric substrate 20 may be the same as that of the first dielectric substrate 10.
  • S16 may also include a step of cleaning the second dielectric substrate 20 using a standard cleaning process.
  • a first transparent conductive film layer can be formed by plasma enhanced chemical vapor deposition (PECVD) and then patterned by dry etching to form a first bias voltage line 22.
  • PECVD plasma enhanced chemical vapor deposition
  • step S18 may include forming a second conductive film by a method including but not limited to sputtering, and then coating, exposing, developing, and etching (eg, wet etching) to form a pattern including the patch electrode 21 .
  • a method including but not limited to sputtering, and then coating, exposing, developing, and etching (eg, wet etching) to form a pattern including the patch electrode 21 .
  • step S19 may include forming the first protection layer 14 by a CVD process.
  • the second alignment layer may be a PI (polyimide) film layer.
  • Step S110 may include forming the PI film layer by inkjet process, and then completing the photo-alignment process of the PI film layer by using OA equipment.
  • steps S16 to S110 can be performed before step S11.
  • the above-mentioned preparation method only provides an exemplary preparation method of the phase shifter, and the method may further include the step of forming the second bias voltage line 23.
  • the steps of forming the switch unit 40 and the scanning line 25 on the second dielectric substrate 20 may also be included, which are not listed one by one here.
  • FIG11 is a top view of the phase shifter array of an embodiment of the present disclosure; as shown in FIG11 , a phase shifter array is provided in an embodiment of the present disclosure, and the phase shifter array includes a plurality of phase shifters arranged in an array, and the phase shifter can adopt any of the above-mentioned phase shifters.
  • phase shifter adopts the phase shifter of the fifth example above, that is, the phase shifter adopts active drive
  • the phase shifters located in the same row wherein the switch units 40 connected to the patch electrodes 21 located in odd numbers in each phase shifter are connected to the same scan line 25, and the switch units 40 connected to the patch electrodes 21 located in even numbers are connected to the same scan line 25.
  • the control electrodes of the thin film transistors 41 located in the same row are connected to the same scan line 25
  • the first electrodes of the thin film transistors 41 located in the same column are connected to the same first bias voltage line 22, and the second electrode of each thin film transistor 41 is connected to the corresponding patch electrode 21.
  • first flexible circuit board 50 may be provided in the phase shifter array, and a plurality of first connection pads corresponding to the first bias voltage line 22 may be provided on the second dielectric substrate 20, and the first bias voltage line 22 is connected to the first connection pads in a one-to-one correspondence.
  • the first bias voltage is provided by the first flexible circuit board 50, and then when the thin film transistor 41 connected to each patch electrode 21 is selected, the first bias voltage is loaded to the corresponding patch electrode 21 through the first bias voltage line 22.
  • each patch electrode 21 does not need to be controlled by an independent first bias voltage line 22, so that the number of first bias voltage lines 22 can be reduced, and the wiring difficulty can be reduced.
  • FIG12 is a block diagram of an antenna array according to an embodiment of the present disclosure. As shown in FIG12 , an embodiment of the present disclosure provides an antenna array, which includes the above-mentioned phase shifter array.
  • the antenna array further includes a radiation array, which includes a plurality of radiation units, and the radiation units are arranged in a one-to-one correspondence with the phase shifters in the phase shifter array.
  • the radiation unit can be arranged on a side of the second dielectric substrate away from the patch electrode, and the radiation unit is used to receive or send a microwave signal. When the radiation unit receives the microwave signal, it will be transmitted to the phase shifter for phase shifting, and the microwave signal after phase shifting is sent through the radiation unit.
  • the antenna array includes a feeding network, and the feeding network is configured to feed the phase shifter.
  • the feeding network feeds the phase shifter array by any one of coupling slots, waveguides, or conductive vias.
  • a reference electrode layer such as a ground electrode layer, can also be provided on the side of the first dielectric substrate of the phase shifter facing away from the liquid crystal layer.
  • a slit opening is provided on the reference electrode.
  • a feeding port of the feeding network is coupled and connected with the phase shifter through the slit opening, thereby realizing feeding in a coupled slit manner.
  • a feeding port of the feeding network is electrically connected to the phase shifter through the first slit opening and the through hole that penetrates the first dielectric substrate, thereby realizing feeding in a conductive via manner.
  • a feeding port of the feeding network is coupled to the phase shifter through a waveguide and the first slit opening, thereby realizing feeding in a waveguide manner.
  • an electronic device in an embodiment of the present disclosure, which may include the above-mentioned antenna array.
  • the electronic device provided in the embodiment of the present disclosure also includes a transceiver unit, a radio frequency transceiver, a signal amplifier, a power amplifier, and a filtering unit.
  • the antenna in the antenna system can be used as a transmitting antenna or as a receiving antenna.
  • the transceiver unit may include a baseband and a receiving end, and the baseband provides a signal of at least one frequency band, for example, a 2G signal, a 3G signal, a 4G signal, a 5G signal, etc., and sends a signal of at least one frequency band to the radio frequency transceiver.
  • the antenna in the antenna system After the antenna in the antenna system receives the signal, it can be processed by the filtering unit, the power amplifier, the signal amplifier, and the radio frequency transceiver and then transmitted to the receiving end in the first launch unit.
  • the receiving end may be, for example, a smart gateway.
  • the RF transceiver is connected to the transceiver unit, and is used to modulate the signal sent by the transceiver unit, or to demodulate the signal received by the antenna and transmit it to the transceiver unit.
  • the RF transceiver may include a transmitting circuit, a receiving circuit, a modulating circuit, and a demodulating circuit. After the transmitting circuit receives various types of signals provided by the substrate, the modulating circuit can modulate various types of signals provided by the baseband and then send them to the antenna.
  • the antenna receives the signal and transmits it to the receiving circuit of the RF transceiver.
  • the receiving circuit transmits the signal to the demodulating circuit, and the demodulating circuit demodulates the signal and transmits it to the receiving end.
  • the RF transceiver is connected to a signal amplifier and a power amplifier, and the signal amplifier and the power amplifier are connected to a filter unit, and the filter unit is connected to at least one antenna.
  • the signal amplifier is used to improve the signal-to-noise ratio of the signal output by the RF transceiver and then transmit it to the filter unit;
  • the power amplifier is used to amplify the power of the signal output by the RF transceiver and then transmit it to the filter unit;
  • the filter unit may specifically include a duplexer and a filter circuit, and the filter unit combines the signals output by the signal amplifier and the power amplifier and transmits them to the antenna after filtering out clutter, and the antenna radiates the signal.
  • the antenna receives the signal and transmits it to the filter unit, and the filter unit filters out clutter from the signal received by the antenna and transmits it to the signal amplifier and the power amplifier, and the signal amplifier amplifies the signal received by the antenna to increase the signal-to-noise ratio; the power amplifier amplifies the power of the signal received by the antenna.
  • the signal received by the antenna is processed by the power amplifier and the signal amplifier and then transmitted to the RF transceiver, and the RF transceiver transmits it to the transceiver unit.
  • the signal amplifier may include multiple types of signal amplifiers, such as a low noise amplifier, which is not limited herein.
  • the electronic device provided by the embodiments of the present disclosure also includes a power management unit, which is connected to a power amplifier to provide the power amplifier with a voltage for amplifying a signal.

Landscapes

  • Waveguide Switches, Polarizers, And Phase Shifters (AREA)

Abstract

本公开提供一种移相器、移相器阵列、天线阵列及电子设备，属于通信技术领域。本公开的移相器，其包括：相对设置的第一介质基板和第二介质基板，设置在所述第一介质基板靠近所述第二介质基板一侧的第一传输线和第二传输线，设置在所述第二介质基板靠近所述第一介质基板一侧的多个贴片电极，以及位于所述传输线所在层和所述多个贴片电极所在层之间的可调电介质层；所述多个贴片电极中的每个的两端，分别与所述第一传输线和所述第二传输线在第一介质基板上的正投影存在交叠；其中，所述多个贴片电极中的至少两个连接不同的第一偏置电压线。

Description

移相器、移相器阵列、天线阵列及电子设备 技术领域
本公开属于通信技术领域，具体涉及一种移相器、移相器阵列、天线阵列及电子设备。
背景技术
液晶移相器周期性引入液晶电容，通过控制液晶取向调节液晶层介电常数，从而调节单位长度支路总电容，进而达到移相的作用。传统的液晶移相器设计中，为了满足阻抗匹配、工作带宽、移相效率等需求，可以进行调整的设计参数主要集中在交叠电容的面积和电容间距上，而对于交叠电容中所填充液晶材料的控制，通常只会采用单一驱动信号统一去调节所有交叠电容中液晶分子的偏转。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种移相器、移相器阵列、天线阵列及电子设备。
第一方面，本公开实施例提供一种移相器，其包括：相对设置的第一介质基板和第二介质基板，设置在所述第一介质基板靠近所述第二介质基板一侧的第一传输线和第二传输线，设置在所述第二介质基板靠近所述第一介质基板一侧的多个贴片电极，以及位于所述传输线所在层和所述多个贴片电极所在层之间的可调电介质层；所述多个贴片电极中的每个的两端，分别与所述第一传输线和所述第二传输线在第一介质基板上的正投影存在交叠；其中，所述多个贴片电极中的至少两个连接不同的第一偏置电压线。
其中，所述多个贴片电极中的每个连接的所述第一偏置电压线不同。
其中，所述多个贴片电极中的至少两个连接同一第一偏置信号线，且连接同一所述第一偏置电压线的所述贴片电极相邻设置。
其中，在所述多个贴片电极中，每两个相邻设置的贴片电极连接一条所述第一偏置电压线，且不同的所述第一偏置电压线所连接的所述贴片电极不同。
其中，在所述多个贴片电极中，连接同一所述第一偏置电压线的贴片电极之间间隔至少一个所述贴片电极。其中，部分所述第一偏置电压线包括包括沿背离所述第二介质基板方向依次设置的第一子信号线和第二子信号线；且在所述第二子信号线所在层和所述第一子信号线所在层之间设置有第一层间绝缘层；所述第一子信号线和所述第二子信号线通过贯穿所述第一层间绝缘层的过孔电连接，且所述第一子信号线与所述贴片电极电连接。
其中，所述多个贴片电极中的每个通过开关单元与所述第一偏置电压线连接，且不同的所述贴片电极所述连接的所述开关单元不同，连接同一所述第一偏置电压线的所述开关单元连接不同的扫描线。
其中，且位于奇数个的所述贴片电极所连接开关单元连接同一所述扫描线，位于偶数个的所述贴片电极所连接开关单元连接同一所述扫描线。
其中，所述开关单元包括薄膜晶体管；所述薄膜晶体管的第一极电连接所述第一偏置电压线，所述薄膜晶体管的第二极电连接所述贴片电极，所述薄膜晶体管的控制极电连接所述扫描线。
其中，所述第一偏置电压线包括沿背离所述第二介质基板方向依次设置的第一子信号线和第二子信号线；且在所述第二子信号线所在层和所述第一子信号线所在层之间设置有第一层间绝缘层；所述第一子信号线的第一端与所述贴片电极连接，所述第一子信号线的第二端连接第一连接部，所述第二子信号线的第一端连接第二连接部，且所述第一连接部通过贯穿所述第一层间绝缘层的过孔与所述第二连接部连接；且所述第一连接部线宽大于所述第一子信号线的线宽，所述第二连接部的线宽大于所述第二子信号线的线宽。
其中，所述第一子信号线和所述第二子信号线的材料均为金属。
其中，所述移相器还包括设置在所述第一介质基板靠近所述第二介质基板一侧的信号电极，所述第一传输线和所述第二传输线分别位于所述信号电极延伸方向的两侧。
其中，所述移相器还包括与所述第一传输线和第二传输线电连接的第二偏置电压线。
第二方面，本公开实施例提供一种移相器阵列，其包括呈阵列排布的多个所述移相器，所述移相器采用上述任一所述的移相器。
其中，当所述多个贴片电极中的每个均通过所述开关单元与所述第一偏置电压线连接时，位于同一行的所述移相器，其中各所述移相器中位于奇数个的所述贴片电极所连接的开关单元连接同一所述扫描线，位于偶数个的所述贴片电极所连接的开关单元连接同一所述扫描线；和/或，位于同一列的所述移相器，其中各所述移相器中排布次序对应各所述贴片电极连接同一所述第一偏置电压线。
第三方面，本公开实施例提供一种天线阵列，其包括上述任一所述的移相器阵列。
其中，所述天线阵列还包括辐射阵列，所述辐射阵列包括多个辐射单元，所述辐射单元与移相器阵列中的移相器一一对应设置。
其中，所述天线阵列还包括馈电网络，所述馈电网络被配置为所述移相器阵列馈电。
其中，所述馈电网络通过耦合狭缝、波导或者导电化过孔中的任意一种方式为所述移相器阵列馈电。
第四方面，本公开实施例提供一种电子设备，其包括上述任一所述的天线阵列。
附图说明
图1为一种示例性的移相器的俯视图。
图2为图1的A-A＇的剖面图。
图3为本公开实施例的移相器的俯视图。
图4为图3的B-B＇的剖面图。
图5为本公开实施例的第二种示例的移相器的俯视图。
图6为本公开实施例的第三种示例的移相器的俯视图。
图7为本公开实施例的第四种示例的移相器的俯视图。
图8为本公开实施例的第五种示例的移相器的俯视图。
图9为本公开实施例的第五种示例的移相器的截面图。
图10为本公开实施例的第六种示例的移相器的俯视图。
图11为本公开实施例的移相器阵列的俯视图。
图12为本公开实施例的天线阵列的框图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种示例性的移相器的俯视图；图2为图1的A-A＇的剖面图；如图1和2所示，该移相器包括：相对设置的第一介质基板10和第二介质基板20，设置在第一介质基板10靠近第二介质基板20一侧的第一传输线11和第二传输线12，设置在第二介质基板20靠近第一介质基板10一侧的多个贴片电极21，设置在第一传输线11和第二传输线12所在层和多个贴片电极21所在层之间的可调电介质层。其中，对于任一贴片电极21的两端分别与第一传输线11和第二传输线12在第一介质基板10上的正投影存在交叠。
在一些示例中，可调电介质层包括但不限于液晶层30，本公开实施例 中以可调电介质层采用液晶层30为例。多个贴片电极21可以通过第一偏置电压线22电连接，第一传输线11和第二传输线12可以通过第二偏置电压线23电连接，例如第二偏置电压线23被写入的第二偏置电压为接地电压。对于任一贴片电极21的两端分别与第一传输线11和第二传输线12在第一介质基板10上的正投影至少部分重叠，限定出电容区域，此时，贴片电极21分别与第一传输线11和第二传输线12在电容区域形成交叠电容。通过给贴片电极21加载第一偏置电压，给第一传输线11和第二传输线12加载第二偏置电压，使得电容区域形成电场，以使液晶层30的液晶分子偏转，从而改变液晶层30的介电常数，进而实现对微波信号的相位调整。
发明人发现，由于各个贴片电极21通过同一第一偏置电压线22电连接，因此为了满足阻抗匹配、工作带宽、移相效率等需求，可以进行调整的设计参数主要集中在交叠电容的面积和电容间距上，而对于交叠电容中所填充液晶材料的控制，通常只会采用单一的第一偏置电压统一去调节所有交叠电容中液晶分子的偏转。这样一来，移相器的设计自由度大大受限。
针对上述问题，在本公开实施例中提供如下技术方案。
第一方面，图3为本公开实施例的移相器的俯视图；图4为图3的B-B＇的剖面图；如图3和4所示，本公开实施例提供一种移相器，其包括相对设置的第一介质基板10和第二介质基板20，设置在第一介质基板10靠近第二介质基板20一侧的第一传输线11和第二传输线12，设置在第二介质基板20靠近第一介质基板10一侧的多个贴片电极21，设置在第一传输线11和第二传输线12所在层和多个贴片电极21所在层之间的可调电介质层。其中，对于任一贴片电极21的两端分别与第一传输线11和第二传输线12在第一介质基板10上的正投影存在交叠。特别的是，在公开实施例中多个贴片电极21中的至少两个连接不同的第一偏置电压线22。
需要说明的是，在本公开实施例中以可调电介质层为液晶层30，第一传输线11和第二传输线12被加载接地电压为例。
由于在本公开实施例中多个贴片电极21中的至少两个所连接的第一偏 置电压线22不同，故可以对连接不同的第一偏置电压线22的贴片电极21加载不同的第一偏置电压，从而使得对应的电容区域的液晶分子产生不同程度的偏转，呈现不同的介电常数，进而使得对应的电容区域获得不同的电容值。通过该种方式，可以在移相器设计时增加一个设计变量，提升设计自由度，一定程度上通过牺牲液晶层30的部分可调性能来优化移相器的阻抗匹配，拓展工作带宽。同时，移相器在制作过程中难免存在加工公差，使得交叠电容面积与设计值存在不同程度的偏差，基于本公开实施例的设计方案可以根据每个交叠电容的实际尺寸偏差相应调节交叠电容的液晶分子介电常数来进行电容值补偿。
在一些示例中，多个贴片电极21可以沿第一传输线11的延伸方向呈周期性排布，例如：各贴片电极21之间的间距均相等。当然，各贴片电极21之间的间距也可以按照一定规律单调增或者单调减。
在一些示例中，对于任一贴片电极21的两端分别称之为第一端和第二端。贴片电极21的第一端与第一传输线11在第一介质基板10上的正投影交叠所限定出的电容区域为第一电容区域，贴片电极21的第二端与第二传输线12在第一介质基板10上的正投影交叠所限定出的电容区域为第二电容区域。其中，第一电容区域和第二电容区域一一对应设置，且对应设置的第一电容区域和第二电容区域的面积相等。
进一步的，各个第一电容区域的面积可以相等，也可以是多个第一电容区域中至少两个面积不等。例如：当多个第一电容区域中至少两个面积不等时，由第一传输线11的两端指向中点的方向上，靠近中点第一电容区域的面积不小于远离中点的第一电容区域的面积。更进一步的，多个第一电容区域中至少两个面积不等包括但不限于至少两个第一电容区域的宽度不等、至少两个第一电容区域的长度不等。其中，实现至少两个第一电容区域的宽度不等的方式可以为各贴片电极21中的至少两个宽度不等；实现至少两个第一电容区域的长度不等方式包括至少各贴片电极21中的至少两个长度不等。
同理，各第二电容区域的面积也可以按照第一电容区域的面积相同的方 式设置，在此不再重复赘述。
在一些示例中，本公开实施例的移相器中还可以包括设置在第一传输线11和第二传输线12所在层靠近液晶层30一侧的第一保护层14，设置在信号电极17所在层靠近液晶层30一侧的第二保护层23，以及与两端与第一保护层14和第二保护层23相抵顶的支撑柱15。其中，第一保护层14用于保护第一传输线11和第二传输线12，第二保护层23用于保护贴片电极21，第一保护层14和第二保护层23的材料均可以采用氮化硅，支撑柱15用于维持液晶盒厚，材料可以采用树脂材料。
以下结合具体示例对本公开实施例中的移相器进行说明。
第一种示例：参照图3和4，移相器中的贴片电极21与第一偏置电压线22一一对应连接。在该种结构中每个贴片电极21可以通过独立第一偏置电压线22被加载第一偏置电线，此时可以通过控制各个第一偏置电压线22上被加载的电压的大小，每个贴片电极21与第一传输线11和第二传输线12所形成的交叠电容的电容值。通过该种方式，可以在移相器设计时增加一个设计变量，提升设计自由度。
在一些示例中，第一传输线11、第二传输线12和贴片电极21均可以采用金属材料，例如：铜、铝、钼，或者铝/钼等。第一偏置电压线22和第二偏置电压线23可以采用透明导电材料，例如：氧化铟锡等。进一步的，第一偏置电压线22设置在贴片电极21所在层靠近第二介质基板20的一侧，第二偏置电压线23设置在第一传输线11和第二传输线12靠近第一介质基板10的一侧。
在一些示例中，移相器不仅包括上述结构，而且还包括第一柔性电路板，在第二介质基板20靠近液晶层30的一侧设置有多个第一连接焊盘，且第一偏置电压线22与第一连接焊盘一一对应连接，第一柔性电路板与第一连接焊盘邦定连接，此时第一柔性电路板可以通过第一连接焊盘为第一偏置电压线22加载第一偏置电压。进一步的，在第二介质基板20靠近液晶层30的一侧还可以设置的第二连接焊盘，第二偏置电压线23可以通过位于第一介 质基板10和第二介质基板20直接的ACF胶与第二连接焊盘电连接，第二连接焊盘同样可以与第一柔性电路板电连接，第一柔性电路板可以通过第二连接焊盘为第二偏置电压线23加载第二偏置电压(接地电压)。当然，在本公开实施例的移相器中还可以设置的第二柔性电路板，第二连接焊盘设置在第一介质基板10靠近液晶层30的一侧，第二偏置信号线与第二连接焊盘电连接，第二柔性电路板与第二偏置信号线邦定连接。
第二种示例：图5为本公开实施例的第二种示例的移相器的俯视图；如图5所示，在该种示例中，多个贴片电极21中的至少两个连接同一第一偏置电压线22，且连接同一第一偏置电压线22的贴片电极21相邻设置，例如：每两个相邻设置的贴片电极21连接同一第一偏置电压线22，且不同的第一偏置电压线22连接的贴片电极21不同。图5中仅以每一条第一偏置电压线22对应连接两个贴片电极21为例。当然，每条第一偏偏置电压线也可以连接三个甚至更多个贴片电极21，在此不再一一列举。在该种情况下，可以适当的减少第一偏置电压线22的设置，便于布线，同时还可以减小对印刷电路的端口数量要求，从而降低成本。
对于第二种示例中的移相器，除上述的第一偏置电压线22的设置外，其余结构均可以采用第一种示例相同的设置方式，故在此不再重复赘述。
第三种示例：图6为本公开实施例的第三种示例的移相器的俯视图；如图6所示，在该种示例中，多个贴片电极21中的至少两个连接同一第一偏置电压线22，且连接同一第一偏置电压线22的贴片电极21之间间隔至少一个贴片电极21，不同的第一偏置电压线22所连接的贴片电极21不同。例如：参照图6，移相器中包括6个贴片电极21，由图中左指向由第1个至第6个贴片电极21顺次设置，其中，第1个贴片电极21和第3个贴片电极21连接一条第一偏置电压线22，第2个贴片电极21和第五个贴片电极21连接一条第一偏置电压线22，第4个贴片电极21和第6个贴片电极21连接一条第一偏置电压线22。
继续参照图6，由于相邻设置的贴片电极21连接不同的第一偏置电压线22，且第一偏置电压线22所连接贴片电极21之间还设置有至少一个贴 片电极21，因此为避免第一偏置电压线22之间短路，故部分第一偏置电压线22采用第一子信号线221和第二子信号线222分层设置且电连接的结构。具体的，部分第一偏置电压线22包括背离所述第二介质基板20方向依次设置的第一子信号线221和第二子信号线222；且在第二子信号线222所在层和第一子信号线221所在层之间设置有第一层间绝缘层；第一子信号线221和第二子信号线222通过贯穿第一层间绝缘层的过孔电连接，同时第一子信号线221与贴片电极21电连接。第二子信号线222与另一部分第一偏置电压线22同层设置。例如：连接第2个贴片电极21和第5个贴片电极21的第一偏置电压线22由第一子信号线221和第二子信号线222电连接形成，第二子信号线222与剩余的两个第一偏置电压线22同层设置。
对于第三种示例中的移相器，除上述的第一偏置电压线22的设置外，其余结构均可以采用第一种示例相同的设置方式，故在此不再重复赘述。
第四种示例：图7为本公开实施例的第四种示例中的移相器的俯视图；如图7所示，该种示例的移相器与第二种示例的移相器结构大致相同，区别仅在于，第一偏置电压线22包括沿背离所述第二介质基板20方向依次设置的第一子信号线221和第二子信号线222；且在第二子信号线222所在层和第一子信号线221所在层之间设置有第一层间绝缘层；第一子信号线221的第一端与贴片电极21连接，第一子信号线221的第二端连接第一连接部241，第二子信号线222的第一端连接第二连接部242，且第一连接部241通过贯穿第一层间绝缘层的过孔与第二连接部242连接；且第一连接部241线宽大于第一子信号线221的线宽，第二连接部242的线宽大于第二子信号线222的线宽。通过第一连接部241和第二连接部242实现第一子信号线221和第二子信号线222的连接，确保了连接的可靠性。
在一些示例中，第一子信号线221和第二子信号线222的材料可以相同，二者均采用金属材料，例如采用金属铜。当然，第一子信号线221和第二子信号线222的材料也可以不同。
在一些示例中，本公开实施例中的第一偏置电压线22也可采用更多条子信号线依次串接形成，多条子信号线可以采用相同，也可以部分相同部分 不同，还可以是各子信号线的材料均不同。
对于第四种示例中的移相器，除上述的第一偏置电压线22的设置外，其余结构均可以采用第一种示例相同的设置方式，故在此不再重复赘述。
第五种示例：图8为本公开实施例的第五种示例的移相器俯视图；图9为本公开实施例的第五种示例的移相器的截面图；如图8和9所示，在该种示例中，每个贴片电极21通过开关单元40和与之对应的第一偏置电压线22电连接，图8以在第二种示例中的移相器的基础，每个贴片电极21通过开关单元40和与之对应的第一偏置电压线22电连接为例。其中连接同一第一偏置电压线22的开关单元40连接不同的扫描线25。例如：位于奇数个的贴片电极21所连接的开关单元40采用同一扫描线25进行控制，位于偶数个的贴片电极21所连接的开关单元40采用同一扫描线25进行控制。在该种情况下，通过设置开关单元40，并且通过扫描线25和第一偏置电压组合控制在贴片电极21上加载第一偏置电压，可以减少第一偏置电压线22的设置数量。
具体的，在移相器工作时，多条扫描线25依次提供导通电平，具有导通电平的扫描线25所对应的开关单元40导通，使得第一偏置电压线22可以传输第一偏置电压至对应的贴片电极21，即第一偏置电压线22可以分时传输第一偏置电压至对应的贴片电极21，从而节省了第一偏置电压线22的数量。
在一些示例中，如图9所示，开关单元40包括薄膜晶体管41，薄膜晶体管41的第一极电连接第一偏置电压线22，薄膜晶体管41的第二极电连接贴片电极21，薄膜晶体管41的控制极电连接扫描线25。
具体的，薄膜晶体管41包括设置在第二介质基上的控制极，设置在控制极背离第二介质基板20一侧的栅极绝缘层，设置在栅极绝缘层背离控制极一侧的有源层、第一极和第二极，设置在有源层、第一极和第二极背离栅极绝缘层一侧的钝化层。贴片电极21与连接线16连接，连接线16通过贯穿钝化层的过孔与薄膜晶体管41的第二极连接，第一偏置电压线22通过贯 穿钝化层的过孔与薄膜晶体管41的第一极连接，扫描线25与薄膜晶体管41的控制极连接。
第六种示例：图10为本公开实施例的第六种示例的移相器的俯视图；如图10所示，该种示例与第二种示例的移相器结构大致相同，区别仅在于，该移相器中的传输线并不是采用上述几种示例的双线传输线，而是采用CPW(共面波导)传输线，也就是说，第一介质基板10上不仅包括第一传输线11和第二传输线12，而且还包括信号电极17，此时第一传输线11和第二传输线12分别设置在信号电极17延伸方向的两侧。其余结构均可以采用与第二种示例中相同的结构，故在此不再重复赘述。
另外，需要说明的是，在第六种示例中仅在第二种示例的移相器的基础上进行了变型，同样可以将第一种、第三种、第四种和第五种示例中的移相器基础上，将双线传输线换成CPW传输线，也在本公开实施例的保护范围内。
相应的，本公开实施例还提供一种移相器的制备方法，以下以制备第一种示例的移相器为例，对本公开实施例的移相器的制备方法进行说明。该制备方法具体包括如下步骤：
S11、提供第一介质基板10。
其中，第一介质基板10包括但不限于玻璃基。在步骤S11中包括对第一介质基板10采用标准清洗工艺进行清洗的步骤。
S12、在第一介质基板10上形成第一传输线11和第二传输线12。
在一些示例中，步骤S12可以包括在第一介质基板10上采用包括但不限于物理气相沉积技术PVD(Physical Vapor Deposition)形成第一金属薄膜，作为种子层，之后电镀种子层，最后涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括第一传输线11和第二传输线12的图形。
S13、在第一传输线11和第二传输线12背离第一介质基板10的一侧形成第一保护层14。
在一些示例中，步骤S13可以包括通过化学的气相沉积法的方式(CVD； Chemical Vapor Deposition)形成第一保护层14。
S14、在第一保护层14背离第一介质基板10的一侧形成支撑柱15。
在一些示例中，支撑柱15采用PS或者OC材料，支撑柱15在第一介质基板10上的正投影与第一传输线11和第二传输线12无重叠，同时也与形成在第二介质基板20上的贴片电极21在第一介质基板10上的正投影无重叠。
S15、在形成支撑柱15之后形成第一配向层。
在一些示例中，第一配向层可以采用PI(聚酰亚胺)膜层。步骤S15可以包括利用Inkjet工艺方式形成PI膜层，而后借助OA设备完成PI膜层的光配向工序。
S16、提供第二介质基板20。
在一些示例中，第二介质基板20的材料可以采用与第一介质基板10相同的材料。在S16中还可以包括对第二介质基板20采用标准清洗工艺进行清洗的步骤。
S17、在第二介质基板20上形成第一偏置电压线22。
在一些示例中，可以通过等离子体增强化学的气相沉积法的方式(PECVD；Plasma Enhanced Chemical Vapor Deposition)形成第一透明导电膜层，之后采用干法刻蚀进行图案化，第一偏置电压线22。
S18、在第一偏置电压线22背离第二介质基板20的一侧形成贴片电极21。
在一些示例中，步骤S18可以包括在采用包括但不限于溅射的方式形成第二导电薄膜，之后涂胶、曝光、显影、刻蚀(例如：湿法刻蚀)形成包括贴片电极21的图形。
S19、在贴片电极21背离第二介质基板20的一侧形成第二保护层23。
在一些示例中，步骤S19可以包括通过CVD工艺形成第一保护层14。
S110、在第二保护层23背离第二介质基板20的一侧形成第二配向层。
在一些示例中，第二配向层可以采用PI(聚酰亚胺)膜层。步骤S110可以包括利用Inkjet工艺方式形成PI膜层，而后借助OA设备完成PI膜层的光配向工序。
S111、将完成上述步骤的第一介质基板10和第二介质基板20对盒，并进行灌晶，完成移相器的制备。
需要说明的是，完成上述的第一介质基板10上的各膜层的制备和第二介质基板20上各膜层的制备的顺序可以互换，也即步骤S16-S110可以在步骤S11之前。
在上述制备方法中仅给出一种示例性的移相器的制备方法的，在该方法中还可以包括形成第二偏置电压线23的步骤。对于有开关单元40的移相器，还可以包括在第二介质基板20上形成开关单元40、扫描线25的步骤，在此不再一一列举。
第二方面，图11为本公开实施例的移相器阵列的俯视图；如图11所示，本公开实施例中提供移相器阵列，该移相器阵列包括多个呈阵列排布的移相器，且移相器可以采用上述任一移相器。
在一些示例中，当移相器采用上述第五种示例的移相器，也即移相器采用有源驱动时，位于同一行的移相器，其中各移相器中位于奇数个的贴片电极21所连接的开关单元40连接同一扫描线25，位于偶数个的贴片电极21所连接的开关单元40连接同一扫描线25。位于同一列的移相器，其中各移相器中排布次序对应各贴片电极21连接同一第一偏置电压线22。也就是说，位于同一行的开关单元40由同一扫描线25进行控制，位于同一列开关单元40由同一第一偏置电压线22提供第一偏置电压。
具体的，当开关单元40采用薄膜晶体管41时，位于同一行的薄膜晶体管41的控制极连接同一扫描线25，位于同一列的薄膜晶体管41的第一极连接同一第一偏置电压线22，每个薄膜晶体管41的第二极连接与之对应的贴片电极21。
进一步的，在移相器阵列中可以仅设置一第一柔性线路板50，在第二 介质基板20上设置与第一偏置电压线22对应的多个第一连接焊盘，第一偏置电压线22与第一连接焊盘一一对应连接。通过第一柔性线路板50提供第一偏置电压，之后通过在每个贴片电极21连接的薄膜晶体管41被选通是，通过第一偏置电压线22将第一偏置电压加载至相应的贴片电极21上。该种方式，无需每个贴片电极21通过独立第一偏置电压线22控制，从而可以减少第一偏置电压线22的数量，降低布线难度。
第三方面，图12为本公开实施例的天线阵列的框图；如图12所示，本公开实施例提供一种天线阵列，其包括上述的移相器阵列。
在一些示例中，天线阵列还包括辐射阵列，辐射阵列包括多个辐射单元，辐射单元与移相器阵列中的移相器一一对应设置。辐射单元可以设置在第二介质基板背离贴片电极的一侧，辐射单元用于接收或者发送微波信号，当辐射单元接收到微波信号后，将会传输至移相器进行移相，移相后的微波信号通过辐射单元将微波信号发送。
在一些示例中，天线阵列包括馈电网络，馈电网络被配置为移相器进行馈电。例如：馈电网络采用耦合狭缝、波导或者导电化过孔中的任意一种方式为所述移相器阵列馈电。
具体的，在移相器的第一介质基板背离液晶层的一侧还可以设置参考电极层，例如接地电极层。此时在参考电极上设置有狭缝开口。馈电网络的一个馈电端口与移相器通过贯穿狭缝开口耦合连接，从而实现耦合狭缝方式的馈电。馈电网络的一个馈电端口与移相器通过第一狭缝开口以及贯穿第一介质基板的通孔与移相器电连接，也即实现了导电化过孔的方式馈电。馈电网络的一个馈电端口通过波导和第一狭缝开口与移相器耦接，也即实现了波导的馈电方式。
第四方面，本公开实施例中提供一种电子设备，其可以包括上述的天线阵列。本公开实施例提供的电子设备还包括收发单元、射频收发机、信号放大器、功率放大器、滤波单元。天线系统中的天线可以作为发送天线，也可以作为接收天线。其中，收发单元可以包括基带和接收端，基带提供至少一 个频段的信号，例如提供2G信号、3G信号、4G信号、5G信号等，并将至少一个频段的信号发送给射频收发机。而天线系统中的天线接收到信号后，可以经过滤波单元、功率放大器、信号放大器、射频收发机的处理后传输给首发单元中的接收端，接收端例如可以为智慧网关等。
进一步地，射频收发机与收发单元相连，用于调制收发单元发送的信号，或用于解调天线接收的信号后传输给收发单元。具体地，射频收发机可以包括发射电路、接收电路、调制电路、解调电路，发射电路接收基底提供的多种类型的信号后，调制电路可以对基带提供的多种类型的信号进行调制，再发送给天线。而天线接收信号传输给射频收发机的接收电路，接收电路将信号传输给解调电路，解调电路对信号进行解调后传输给接收端。
进一步地，射频收发机连接信号放大器和功率放大器，信号放大器和功率放大器再连接滤波单元，滤波单元连接至少一个天线。在天线系统进行发送信号的过程中，信号放大器用于提高射频收发机输出的信号的信噪比后传输给滤波单元；功率放大器用于放大射频收发机输出的信号的功率后传输给滤波单元；滤波单元具体可以包括双工器和滤波电路，滤波单元将信号放大器和功率放大器输出的信号进行合路且滤除杂波后传输给天线，天线将信号辐射出去。在天线系统进行接收信号的过程中，天线接收到信号后传输给滤波单元，滤波单元将天线接收的信号滤除杂波后传输给信号放大器和功率放大器，信号放大器将天线接收的信号进行增益，增加信号的信噪比；功率放大器将天线接收的信号的功率放大。天线接收的信号经过功率放大器、信号放大器处理后传输给射频收发机，射频收发机再传输给收发单元。
在一些示例中，信号放大器可以包括多种类型的信号放大器，例如低噪声放大器，在此不做限制。
在一些示例中，本公开实施例提供的电子设备还包括电源管理单元，电源管理单元连接功率放大器，为功率放大器提供用于放大信号的电压。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而 言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种移相器，其包括：相对设置的第一介质基板和第二介质基板，设置在所述第一介质基板靠近所述第二介质基板一侧的第一传输线和第二传输线，设置在所述第二介质基板靠近所述第一介质基板一侧的多个贴片电极，以及位于所述传输线所在层和所述多个贴片电极所在层之间的可调电介质层；所述多个贴片电极中的每个的两端，分别与所述第一传输线和所述第二传输线在第一介质基板上的正投影存在交叠；其中，所述多个贴片电极中的至少两个连接不同的第一偏置电压线。
  2. 根据权利要求1所述的移相器，其中，所述多个贴片电极中的每个连接的所述第一偏置电压线不同。
  3. 根据权利要求1所述的移相器，其中，所述多个贴片电极中的至少两个连接同一第一偏置信号线，且连接同一所述第一偏置电压线的所述贴片电极相邻设置。
  4. 根据权利要求3所述的移相器，其中，在所述多个贴片电极中，每两个相邻设置的贴片电极连接一条所述第一偏置电压线，且不同的所述第一偏置电压线所连接的所述贴片电极不同。
  5. 根据权利要求1所述的移相器，其中，在所述多个贴片电极中，连接同一所述第一偏置电压线的贴片电极之间间隔至少一个所述贴片电极。
  6. 根据权利要求5所述的移相器，其中，部分所述第一偏置电压线包括包括沿背离所述第二介质基板方向依次设置的第一子信号线和第二子信号线；且在所述第二子信号线所在层和所述第一子信号线所在层之间设置有第一层间绝缘层；所述第一子信号线和所述第二子信号线通过贯穿所述第一层间绝缘层的过孔电连接，且所述第一子信号线与所述贴片电极电连接。
  7. 根据权利要求1所述的移相器，其中，所述多个贴片电极中的每个通过开关单元与所述第一偏置电压线连接，且不同的所述贴片电极所述连接的所述开关单元不同，连接同一所述第一偏置电压线的所述开关单元连接不同的扫描线。
  8. 根据权利要求7所述的移相器，其中，位于奇数个的所述贴片电极所连接开关单元连接同一所述扫描线，位于偶数个的所述贴片电极所连接开关单元连接同一所述扫描线。
  9. 根据权利要求7或8所述的移相器，其中，所述开关单元包括薄膜晶体管；所述薄膜晶体管的第一极电连接所述第一偏置电压线，所述薄膜晶体管的第二极电连接所述贴片电极，所述薄膜晶体管的控制极电连接所述扫描线。
  10. 根据权利要求1所述的移相器，其中，所述第一偏置电压线包括沿背离所述第二介质基板方向依次设置的第一子信号线和第二子信号线；且在所述第二子信号线所在层和所述第一子信号线所在层之间设置有第一层间绝缘层；所述第一子信号线的第一端与所述贴片电极连接，所述第一子信号线的第二端连接第一连接部，所述第二子信号线的第一端连接第二连接部，且所述第一连接部通过贯穿所述第一层间绝缘层的过孔与所述第二连接部连接；且所述第一连接部线宽大于所述第一子信号线的线宽，所述第二连接部的线宽大于所述第二子信号线的线宽。
  11. 根据权利要求7所述的移相器，其中，所述第一子信号线和所述第二子信号线的材料均为金属。
  12. 根据权利要求1所述的移相器，其中，还包括设置在所述第一介质基板靠近所述第二介质基板一侧的信号电极，所述第一传输线和所述第二传输线分别位于所述信号电极延伸方向的两侧。
  13. 根据权利要求1所述的移相器，其中，还包括与所述第一传输线和第二传输线电连接的第二偏置电压线。
  14. 一种移相器阵列，其包括呈阵列排布的多个所述移相器，所述移相器采用权利要求1-13中任一项所述的移相器。
  15. 根据权利要求14所述的移相器阵列，其中，当所述多个贴片电极中的每个均通过所述开关单元与所述第一偏置电压线连接时，位于同一行的所述移相器，其中各所述移相器中位于奇数个的所述贴片电极所连接的开关 单元连接同一所述扫描线，位于偶数个的所述贴片电极所连接的开关单元连接同一所述扫描线；和/或，位于同一列的所述移相器，其中各所述移相器中排布次序对应各所述贴片电极连接同一所述第一偏置电压线。
  16. 一种天线阵列，其包括权利要求14或15所述的移相器阵列。
  17. 根据权利要求16所述的天线阵列，其中，还包括辐射阵列，所述辐射阵列包括多个辐射单元，所述辐射单元与移相器阵列中的移相器一一对应设置。
  18. 根据权利要求16所述的天线阵列，其中，还包括馈电网络，所述馈电网络被配置为所述移相器阵列馈电。
  19. 根据权利要求18所述的天线阵列，其中，所述馈电网络通过耦合狭缝、波导或者导电化过孔中的任意一种方式为所述移相器阵列馈电。
  20. 一种电子设备，其包括权利要求16-19中任一项所述的天线阵列。
PCT/CN2022/130817 2022-11-09 2022-11-09 移相器、移相器阵列、天线阵列及电子设备 WO2024098275A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/130817 WO2024098275A1 (zh) 2022-11-09 2022-11-09 移相器、移相器阵列、天线阵列及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/130817 WO2024098275A1 (zh) 2022-11-09 2022-11-09 移相器、移相器阵列、天线阵列及电子设备

Publications (1)

Publication Number Publication Date
WO2024098275A1 true WO2024098275A1 (zh) 2024-05-16

Family

ID=91031605

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/130817 WO2024098275A1 (zh) 2022-11-09 2022-11-09 移相器、移相器阵列、天线阵列及电子设备

Country Status (1)

Country Link
WO (1) WO2024098275A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107528121A (zh) * 2017-08-29 2017-12-29 京东方科技集团股份有限公司 天线结构及其操作方法、天线设备
CN112448105A (zh) * 2019-08-29 2021-03-05 京东方科技集团股份有限公司 移相器及天线
WO2021104202A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 一种移相器和相控阵天线
CN113728512A (zh) * 2020-03-24 2021-11-30 京东方科技集团股份有限公司 移相器及天线
WO2022110013A1 (zh) * 2020-11-27 2022-06-02 京东方科技集团股份有限公司 移相器及天线
WO2022178805A1 (zh) * 2021-02-26 2022-09-01 京东方科技集团股份有限公司 移相器及天线

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107528121A (zh) * 2017-08-29 2017-12-29 京东方科技集团股份有限公司 天线结构及其操作方法、天线设备
CN112448105A (zh) * 2019-08-29 2021-03-05 京东方科技集团股份有限公司 移相器及天线
WO2021104202A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 一种移相器和相控阵天线
CN113728512A (zh) * 2020-03-24 2021-11-30 京东方科技集团股份有限公司 移相器及天线
WO2022110013A1 (zh) * 2020-11-27 2022-06-02 京东方科技集团股份有限公司 移相器及天线
WO2022178805A1 (zh) * 2021-02-26 2022-09-01 京东方科技集团股份有限公司 移相器及天线

Similar Documents

Publication Publication Date Title
CN110137636B (zh) 移相器和液晶天线
EP3695456B1 (en) Power couplers and related devices having antenna element power absorbers
US6611230B2 (en) Phased array antenna having phase shifters with laterally spaced phase shift bodies
CN111293425A (zh) 一种液晶有源相控阵天线
US20060077102A1 (en) Wafer scale beam forming antenna module with distributed amplification
KR20020024338A (ko) 위상 어레이 안테나
US6633260B2 (en) Electromechanical switching for circuits constructed with flexible materials
WO2019188413A1 (ja) アンテナモジュールおよびそれを搭載した通信装置
KR20190054066A (ko) 가변 유전상수 기반 장치
WO2009041895A1 (en) Antenna arrangement for a multi radiator base station antenna
EP1208615B1 (en) Four port hybrid
WO2019188471A1 (ja) アンテナモジュールおよびそれを搭載した通信装置
GB2159333A (en) Transceiver element
WO2024098275A1 (zh) 移相器、移相器阵列、天线阵列及电子设备
WO2022174481A1 (zh) 基于基片集成波导的可调控缝隙阵列天线
WO2023137690A1 (zh) 天线及天线系统
WO2022264737A1 (ja) アンテナモジュールおよびそれを搭載した通信装置
EP4123835A1 (en) Phased array antenna device
WO2024103200A1 (zh) 射频装置、天线及电子设备
CN211655054U (zh) 一种液晶有源相控阵天线
WO2023246542A1 (zh) 移相器及电子设备
US11316552B2 (en) High frequency switch and antenna device
WO2023141854A1 (zh) 移相器及天线
WO2024036550A1 (zh) 天线、天线阵列及电子设备
CN115693156B (zh) 天线、天线阵列及通信系统