WO2024092434A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024092434A1
WO2024092434A1 PCT/CN2022/128721 CN2022128721W WO2024092434A1 WO 2024092434 A1 WO2024092434 A1 WO 2024092434A1 CN 2022128721 W CN2022128721 W CN 2022128721W WO 2024092434 A1 WO2024092434 A1 WO 2024092434A1
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WIPO (PCT)
Prior art keywords
line
layer
transistor
electrode
exemplary embodiment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2022/128721
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English (en)
French (fr)
Chinese (zh)
Inventor
尚庭华
张毅
周洋
龙祎璇
张元其
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2022/128721 priority Critical patent/WO2024092434A1/zh
Priority to US18/279,384 priority patent/US20250089504A1/en
Priority to JP2024560561A priority patent/JP2025535215A/ja
Priority to CN202280003914.6A priority patent/CN118284969A/zh
Publication of WO2024092434A1 publication Critical patent/WO2024092434A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area, wherein the display area includes a driving structure layer arranged on a substrate, the driving structure layer at least includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along a second direction, wherein the first direction and the second direction intersect;
  • the circuit unit includes a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of a plurality of first connecting lines are correspondingly connected to the plurality of data signal lines, and the second ends of the plurality of first connecting lines are correspondingly connected to the plurality of second connecting lines;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are arranged at gaps between pixel driving circuits of adjacent unit columns.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, the first connecting line and the second connecting line are arranged in different conductive layers, and the data signal line and the second connecting line are arranged in the same conductive layer.
  • the multiple conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are arranged in sequence along a direction away from the substrate, the first connecting line is arranged in the second source-drain metal layer, the data signal line and the second connecting line are arranged in the third source-drain metal layer, the data signal line is connected to the first end of the first connecting line through a via, and the second connecting line is connected to the second end of the first connecting line through a via.
  • the pixel driving circuit includes at least a first transistor, a second transistor and a storage capacitor
  • the first transistor includes at least a first active layer
  • the second transistor includes at least a second active layer
  • the second region of the first active layer and the first region of the second active layer are an integrated structure connected to each other, and are connected to the first electrode plate of the storage capacitor through a first connecting electrode
  • the second source-drain metal layer also includes a shielding electrode, the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer and the first region of the second active layer on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode on the substrate.
  • the third source-drain metal layer further includes a first power line, and the first power line is connected to the shielding electrode through a via.
  • the display substrate further comprises a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the light-emitting structure layer comprising a plurality of light-emitting units, the light-emitting units comprising at least an anode; in at least one light-emitting unit, an orthographic projection of the anode on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate, and an orthographic projection of the anode on the substrate at least partially overlaps with an orthographic projection of the shielding electrode on the substrate.
  • the orthographic projection of the anode on the substrate and the orthographic projection of the first power line on the substrate have a first overlapping area
  • the orthographic projection of the anode on the substrate and the orthographic projection of the shielding electrode on the substrate have a second overlapping area, and the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the pixel driving circuit includes at least a fourth transistor, a first electrode of the fourth transistor is connected to the data signal line through a data connection electrode, and in at least one circuit unit, the first connection line is connected to the data connection electrode.
  • At least one circuit unit further includes a data connection block, a first end of the data connection block is connected to the first connection line, and a second end of the data connection block is connected to the data connection electrode.
  • the first connection line, the data connection electrode, and the data connection block are disposed in the same layer and are an integrated structure connected to each other.
  • At least one circuit unit further includes a second initial signal line extending along the first direction and a second initial connecting line extending along the second direction, the second initial connecting line being arranged between two adjacent second initial signal lines in the second direction and being respectively connected to the two second initial signal lines, forming a second initial signal line of a network connection structure in the display area.
  • the second initial connection line is disposed in an odd-numbered cell column, or the second initial connection line is disposed in an even-numbered cell column.
  • the cell column where the second initial connection line is located in one cell row is different from the cell column where the second initial connection line is located in the other cell row.
  • the second initial signal line and the second initial connection line are disposed in the same layer and are an integrated structure connected to each other.
  • the pixel driving circuit includes at least a storage capacitor and a plurality of transistors
  • the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer, which are sequentially arranged along a direction away from the substrate;
  • the shielding layer includes at least a shielding electrode
  • the first semiconductor layer includes at least an active layer of a plurality of low-temperature polysilicon transistors
  • the first gate metal layer includes at least a first scanning signal line, a light-emitting signal line and a first electrode plate of the storage capacitor
  • the second gate metal layer includes at least a second electrode plate of the storage capacitor
  • the second semiconductor layer includes at least an active layer of a plurality of oxide transistors
  • the third gate metal layer includes at least a second scanning signal line and a third scanning signal line
  • the plurality of transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon transistors.
  • the present disclosure further provides a display device, comprising the aforementioned display substrate.
  • the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a display area, and the preparation method includes:
  • a driving structure layer is formed on the substrate of the display area, the driving structure layer at least comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction and a plurality of second connecting lines extending along a second direction, wherein the first direction intersects with the second direction;
  • the circuit unit comprises a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, first ends of a plurality of first connecting lines are connected to a plurality of data signal lines correspondingly, and second ends of a plurality of first connecting lines are connected to a plurality of second connecting lines correspondingly;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and extending along the second direction, and the second connecting lines are arranged at gaps
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic structural diagram of a display substrate
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an arrangement of data connection lines according to an exemplary embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG9 is a schematic diagram of an embodiment of the present disclosure after forming a shielding layer pattern
  • FIGS. 10 and 11 are schematic diagrams of the embodiment of the present disclosure after forming a first semiconductor layer pattern
  • FIGS. 12 and 13 are schematic diagrams of the embodiment of the present disclosure after forming the first conductive layer pattern
  • 16 and 17 are schematic diagrams of the second semiconductor layer pattern formed in the embodiment of the present disclosure.
  • FIGS. 18 and 19 are schematic diagrams of the embodiment of the present disclosure after forming a third conductive layer pattern
  • FIG20 is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern
  • 21 and 22 are schematic diagrams of the fourth conductive layer pattern formed in the embodiment of the present disclosure.
  • FIG23 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern
  • 24 and 25 are schematic diagrams of the fifth conductive layer pattern formed in the embodiment of the present disclosure.
  • FIG26 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern
  • 27 to 28 are schematic diagrams of the sixth conductive layer pattern formed in the embodiment of the present disclosure.
  • FIG29 is a schematic diagram of an embodiment of the present disclosure after forming a third planar layer pattern
  • FIG30 is a schematic diagram of an embodiment of the present disclosure after forming an anode conductive layer pattern
  • FIG31 is a schematic diagram of an embodiment of the present disclosure after forming a pixel definition layer pattern
  • FIG. 32 is a schematic diagram of the planar structure of another display substrate according to an embodiment of the present disclosure.
  • 65 anode connection electrode
  • 70 first connection line
  • 71 first bonding block
  • 90 power supply wiring
  • 91 first shielding connection line
  • 92 second shielding connection line
  • 93 third shielding connection line
  • 94 shielding electrode
  • 100 display area
  • 101 substrate
  • 102 driving structure layer
  • 103 light-emitting structure layer
  • 104 Packaging structure layer; 200—Binding area; 300—Border area.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit connected to the circuit unit, the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • FIG2 is a schematic diagram of a structure of a display substrate.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, wherein the plurality of sub-pixels Pxij are configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.
  • the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area.
  • the fan-out area may be connected to the display area and include a plurality of data fan-out lines, and the data fan-out lines are configured to connect the data signal lines (Data Line) of the display area in a fan-out (Fanout) routing manner.
  • the bending area may be connected to the fan-out area and may include a composite insulating layer provided with a groove, and may be configured to bend the driver chip area and the binding pin area to the back of the display area.
  • the driver chip area may be connected to the bending area and may include an integrated circuit (IC), which is configured to be connected to the plurality of data fan-out lines.
  • the binding pin area may be connected to the driver chip area and may include a bonding pad, which is configured to be bonded and connected to an external flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the border area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence in a direction away from the display area.
  • the circuit area may be connected to the display area, and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area.
  • the power line area may be connected to the circuit area, and may include at least a power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area.
  • the crack dam area may be connected to the power line area, and may include at least a plurality of cracks set on the composite insulating layer.
  • the cutting area may be connected to the crack dam area, and may include at least a cutting groove set on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.
  • the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with at least one isolation dam, at least one of which may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area, and the edge of the display area is the edge of one side of the display area binding area or the border area.
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4.
  • Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit.
  • the light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal
  • the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement or a square arrangement, etc., which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangle arrangement, etc., which is not limited in the present disclosure.
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor.
  • the light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, forming an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a light emitting signal line E, a data signal line D, a first initial signal line INIT1, a second initial signal line INIT1 and a first power line VDD).
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively;
  • the second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively;
  • the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively;
  • the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fourth node N4 is also connected to the anode of the light emitting device EL.
  • a first end of the storage capacitor C is connected to the second node N2 , and a second end of the storage capacitor C is connected to the first power line VDD, that is, the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3 .
  • a gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits the first initialization voltage to the first end of the storage capacitor C, thereby initializing the storage capacitor C.
  • a gate electrode of the second transistor T2 is connected to the third scan signal line S3, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the gate electrode (second node N2) of the third transistor T3 to the second electrode (third node N3) of the third transistor T3.
  • the gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the light emitting device EL according to the potential difference between its gate electrode and the first electrode.
  • a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1
  • a first electrode of the fourth transistor T4 is connected to the data signal line D
  • a second electrode of the fourth transistor T4 is connected to the first node N1.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting signal line E
  • the first electrode of the fifth transistor T5 is connected to the first power line VDD
  • the second electrode of the fifth transistor T5 is connected to the first node N1
  • the signal of the first power line VDD is a high level signal that is continuously provided.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line E
  • the first electrode of the sixth transistor T6 is connected to the third node N3
  • the second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and a driving current path is formed between the first power line VDD and the light emitting device EL to make the light emitting device EL emit light.
  • a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1
  • a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2
  • a second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the seventh transistor T7 transmits the second initial voltage to the fourth node N4 to initialize or release the charge amount accumulated in the anode of the light emitting device EL.
  • the light emitting device EL may be an OLED including a stacked anode (first pole), an organic light emitting layer and a cathode (second pole), or may be a QLED including a stacked anode (first pole), a quantum dot light emitting layer and a cathode (second pole).
  • a first electrode of the light emitting device EL is connected to the fourth node N4, a second electrode of the light emitting device EL is connected to the second power line VSS, and a signal of the second power line VSS is a continuously provided low level signal.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor.
  • the active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the first transistor T1 and the second transistor T2 may be implemented as metal oxide transistors, and the third to seventh transistors T3 to T7 may be implemented as low temperature polysilicon transistors.
  • the operation process of the pixel driving circuit may include:
  • the signal of the second scan signal line S2 is a turn-on signal (high level), and the signals of the first scan signal line S1, the third scan signal line S3 and the light-emitting signal line E are turn-off signals.
  • the turn-on signal of the second scan signal line S2 turns on the first transistor T1
  • the signal of the first initial signal line INIT1 is provided to the second node N2 through the first transistor T1
  • the storage capacitor C is initialized (reset), and the original charge in the storage capacitor is cleared. Since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light.
  • the signals of the first scanning signal line S1 and the third scanning signal line S3 are on signals
  • the signals of the second scanning signal line S2 and the light emitting signal line E are off signals
  • the data signal line D outputs a data voltage.
  • the on signals of the first scanning signal line S1 and the third scanning signal line S3 turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage of the first end (the second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on to provide the signal of the second initial signal line INIT2 to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light.
  • the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the signal of the light-emitting signal line E is a conduction signal
  • the signals of the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 are disconnection signals.
  • the conduction signal of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the binding area usually includes a fan-out area, a bending area, a driver chip area and a binding pin area arranged in sequence along the direction away from the display area. Since the width of the binding area is smaller than the width of the display area, the signal lines of the driver chip and the binding pad in the binding area need to be introduced into the wider display area through the fan-out area in a fan-out routing manner.
  • a frame power lead is usually set in the frame area, and the frame power lead is configured to continuously provide a low-voltage power signal for transmission. In order to reduce the voltage drop of the low-voltage power signal, the width of the frame power lead is large, resulting in a large width of the left and right frames of the display device.
  • FIG6 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure.
  • the display substrate may include a driving structure layer disposed on a substrate, a light emitting structure layer disposed on a side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display substrate may include at least a display area 100, a binding area 200 located on one side of the second direction Y of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light emitting device.
  • the light emitting structure layer of the display area 100 may include a plurality of light emitting units, at least one light emitting unit may include a light emitting device, the light emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit
  • the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device.
  • the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.
  • a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row
  • a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column
  • a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array
  • the first direction X intersects the second direction Y.
  • the driving structure layer of the display area 100 may further include a plurality of data signal lines 60, a plurality of first connection lines 70, and a plurality of second connection lines 80.
  • the data signal lines 60 are respectively connected to a plurality of pixel driving circuits in a unit column, and the data signal lines 60 are configured to provide data signals to the connected pixel driving circuits.
  • the first ends of the plurality of first connection lines 70 are connected to the plurality of data signal lines 60, and the second ends of the plurality of first connection lines 70 are connected to the plurality of second connection lines 80.
  • the first connection lines 70 and the second connection lines 80 constitute data connection lines, forming a data connection line located in the display area (Fanout in AA, referred to as FIAA) structure.
  • a portion of the data signal lines 60 is connected to the lead-out lines 210 in the binding area 200 through the data connection lines, and another portion of the data signal lines 60 is directly connected to the lead-out lines 210 in the binding area 200.
  • the binding area 200 may include a lead area 201, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area, the lead area 201 is connected to the display area 100, and the bending area is connected to the lead area 201.
  • the lead area 201 may be provided with a plurality of lead lines 210, and the plurality of lead lines 210 may extend in a direction away from the display area, the first ends of a portion of the lead lines 210 are correspondingly connected to the data connection line 60 in the display area 100, and the first ends of another portion of the lead lines are correspondingly connected to the second connection line 80 in the display area 100, and the second ends of the plurality of lead lines 210 extend along the second direction Y and cross the bending area, and then are connected to the driver chip in the driver chip area, so that the driver chip applies the data signal provided by the driver chip to the data signal line 60 through the lead lines 210.
  • the length of the lead area in the second direction Y can be effectively reduced, the width of the lower frame can be greatly reduced, the screen ratio is improved, and it is conducive to achieving full-screen display.
  • the lead-out line 210 and the data signal line 60 and the second connection line 80 may be directly connected, or may be connected through a via hole, which is not limited in the present disclosure.
  • the first connection line 70 may be in a line shape extending along the first direction X
  • the second connection line 80 may be in a line shape extending along the second direction Y
  • the data signal line 60 may be in a line shape extending along the second direction Y.
  • the first connection line 70 may be disposed perpendicular to the data signal line 60
  • the second connection line 80 may be disposed parallel to the data signal line 60 .
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • “A extends along direction B” means "the main part of A extends along direction B".
  • the second direction Y may be a direction pointing from the display area to the binding area, and the opposite direction of the second direction Y may be a direction pointing from the binding area to the display area.
  • the driving structure layer of the display area 100 may further include a plurality of power lines 90.
  • the power lines 90 may be in the shape of a line extending along the second direction Y, and the plurality of power lines 90 may be sequentially arranged along the first direction X.
  • the power trace 90 may be disposed between two adjacent data signal lines 60 in the first direction X.
  • the power supply line 90 and the second connection line 80 may be arranged in the same layer and formed simultaneously by the same patterning process. At least one circuit column may be provided with only the power supply line 90, and the second connection line 80 is not provided in the circuit column. At least one circuit column may be provided with the power supply line 90 and the second connection line 80, and a break DF is provided between the power supply line 90 and the second connection line 80, and the break DF is configured to achieve insulation between the power supply line 90 and the second connection line 80.
  • the plurality of power lines 90 may be lines that continuously provide low voltage signals.
  • the power line may be a second power line VSS.
  • the plurality of power lines 90 may be connected to power leads provided in a binding area or a frame area.
  • the present disclosure realizes a structure in which a low voltage power line is provided in a sub-pixel (VSS in pixel) by providing a power line in the display area, which can not only effectively reduce the resistance of the power signal line, effectively reduce the voltage drop of the low voltage power signal, and achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the low voltage power line provided in the sub-pixel structure can greatly reduce the width of the power lead in the frame area and the binding area, which is conducive to achieving a narrow frame.
  • the display substrate may have a center line O, and multiple data signal lines 60, multiple first connection lines 70, multiple second connection lines 80, multiple power lines 90 and multiple lead lines 210 on the display substrate may be symmetrically arranged relative to the center line O.
  • the center line O may be a straight line that bisects the multiple unit columns of the display area 100 and extends along the second direction Y.
  • the driving structure layer may include multiple conductive layers, the first connecting line 70 and the second connecting line 80 may be set in different conductive layers, the data signal line 60 and the second connecting line 80 may be set in the same conductive layer, the first connecting line 70 may be connected to the data signal line 60 through a first connecting hole, and the second connecting line 80 may be connected to the first connecting line 70 through a second connecting hole.
  • FIG7 is a schematic diagram of the arrangement of a data connection line in an exemplary embodiment of the present disclosure, illustrating the structure of 6 data signal lines, 2 data connection lines and 6 lead lines in the left area of the display substrate.
  • the plurality of data signal lines in the left area may include data signal lines 60-1 to 60-6
  • the plurality of first connection lines may include first connection lines 70-1 and first connection lines 70-2
  • the plurality of second connection lines 80 may include second connection lines 80-1 and second connection lines 80-2
  • the plurality of lead lines may include lead lines 210-1 to 210-6.
  • the data signal lines 60-1 to 60-6 may be in the shape of lines extending along the second direction Y, and may be arranged in ascending order of numbers along the first direction X.
  • the first connection lines 70-1 and 70-2 may be in the shape of lines extending along the first direction X, and may be arranged in ascending order of numbers along the second direction Y.
  • the second connection lines 80-1 and 80-2 may be in the shape of lines extending along the second direction Y, and may be arranged in descending order of numbers along the first direction X.
  • the first end of the first connection line 70-1 is connected to the data signal line 60-1 through the first connection hole K1, and the second end of the first connection line 70-1 is extended along the first direction X, and is connected to the first end of the second connection line 80-1 through the second connection hole K2, and the second end of the second connection line 80-1 is extended along the second direction Y to the binding area, and is connected to the first end of the lead line 210-1, and the second end of the lead line 210-1 is extended along the second direction Y and crosses the bending area, and is connected to the driving chip in the driving chip area, thereby realizing the connection of the lead line 210-1 to the data signal line 60-1 through the second connection line 80-1 and the first connection line 70-1.
  • the first end of the first connection line 70-2 is connected to the data signal line 60-2 through the first connection hole K1, and the second end of the first connection line 70-2 is extended along the first direction X, and is connected to the first end of the second connection line 80-2 through the second connection hole K2, and the second end of the second connection line 80-2 is extended along the second direction Y to the binding area, and is connected to the first end of the lead line 210-2, and the second end of the lead line 210-2 is extended along the second direction Y and crosses the bending area, and is connected to the driving chip in the driving chip area, thereby realizing the connection of the lead line 210-2 to the data signal line 60-2 through the second connection line 80-2 and the first connection line 70-2.
  • the data signal lines 60-3 to 60-6 extend along the second direction Y to the binding area, they are correspondingly connected to the first ends of the lead lines 210-3 to 210-6, and after the second ends of the lead lines 210-3 to 210-6 extend along the second direction Y and cross the bending area, they are connected to the driving chip in the driving chip area.
  • the pins connected to the lead wires in the driver chip are arranged in an insertion sequence, and the second pin (the pin connected to the lead wire 210-2) is inserted between the third pin (the pin connected to the lead wire 210-3) and the fourth pin (the pin connected to the lead wire 210-4), and the first pin (the pin connected to the lead wire 210-1) is inserted between the fourth pin and the fifth pin (the pin connected to the lead wire 210-5).
  • the driver chip can use the insertion sequence design to achieve load-free data signal output without sudden changes, thereby improving display quality.
  • the insertion sequence design is only one implementation method, and the implementation method of the positive sequence design can be adopted in the actual design.
  • the order of the pin output signals of the driver chip can be consistent with the arrangement order of the data signal lines in the display area through the cross-line design.
  • the intervals between adjacent first connection lines 70 in the second direction Y may be the same or different, and the intervals between adjacent second connection lines 80 in the first direction X may be the same or different, which is not limited in the present disclosure.
  • At least one second connection line 80 may be disposed between two data signal lines 60 adjacent to each other in the first direction X.
  • the present invention provides a data connection line including a first connection line and a second connection line in the display area, so that the lead line of the binding area is connected to the data signal line through the data connection line, so that there is no need to provide a fan-shaped oblique line in the lead area, thereby effectively reducing the length of the lead area, greatly reducing the width of the lower frame, and improving the screen-to-body ratio, which is conducive to achieving full-screen display.
  • the display substrate includes a display area
  • the display area includes a driving structure layer arranged on a substrate
  • the driving structure layer includes at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connection lines extending along a first direction, and a plurality of second connection lines extending along a second direction, wherein the first direction and the second direction intersect
  • the circuit unit includes a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of the plurality of first connection lines are connected to the plurality of data signal lines correspondingly, and the second ends of the plurality of first connection lines are connected to the plurality of second connection lines correspondingly;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are arranged at gaps between pixel driving circuits of adjacent unit columns.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, the first connecting line and the second connecting line are arranged in different conductive layers, and the data signal line and the second connecting line are arranged in the same conductive layer.
  • the multiple conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are arranged in sequence along a direction away from the substrate, the first connecting line is arranged in the second source-drain metal layer, the data signal line and the second connecting line are arranged in the third source-drain metal layer, the data signal line is connected to the first end of the first connecting line through a via, and the second connecting line is connected to the second end of the first connecting line through a via.
  • the third source-drain metal layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are arranged at gaps between pixel driving circuits of adjacent unit columns.
  • the pixel driving circuit includes at least a storage capacitor and a plurality of transistors
  • the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer, which are sequentially arranged along a direction away from the substrate;
  • the shielding layer includes at least a shielding electrode
  • the first semiconductor layer includes at least an active layer of a plurality of low-temperature polysilicon transistors
  • the first gate metal layer includes at least a first scanning signal line, a light-emitting signal line and a first electrode plate of the storage capacitor
  • the second gate metal layer includes at least a second electrode plate of the storage capacitor
  • the second semiconductor layer includes at least an active layer of a plurality of oxide transistors
  • the third gate metal layer includes at least a second scanning signal line and a third scanning signal line
  • the plurality of transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon transistors.
  • FIG8 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating a pixel driving circuit structure of eight circuit units (2 unit rows and 4 unit columns) in a display area.
  • the display substrate may include a display area, and the display area may include at least a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate.
  • the driving structure layer may include at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of circuit units in each unit row are sequentially arranged along a first direction X, a plurality of unit rows are sequentially arranged along a second direction Y, a plurality of circuit units in each unit column are sequentially arranged along a second direction Y, a plurality of unit columns are sequentially arranged along a first direction X, and the first direction X and the second direction Y intersect.
  • the driving structure layer may also include a plurality of data signal lines 60 extending along the second direction Y, a plurality of first connecting lines 70 extending along the first direction X, and a plurality of second connecting lines 80 extending along the second direction Y
  • the circuit unit may include a pixel driving circuit
  • at least one data signal line 60 is electrically connected to a plurality of pixel driving circuits of a unit column
  • the data signal line 60 is configured to provide a data signal to the connected pixel driving circuit.
  • first ends of the plurality of first connection lines 70 are connected to the plurality of data signal lines 60
  • second ends of the plurality of first connection lines 70 are connected to the plurality of second connection lines 80
  • first connection lines 70 and the second connection lines 80 are configured to provide data signals to the connected data signal lines 60 .
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means “the main part of A extends along direction B".
  • the pixel driving circuits in adjacent unit columns may be mirror-symmetrical with respect to a center line, and the center line may be a straight line located between two adjacent unit columns and extending along the second direction Y.
  • the symmetrical structure forms gaps between the pixel driving circuits of adjacent unit columns, and a plurality of second connecting lines 80 may be respectively disposed in the gaps between the pixel driving circuits of adjacent unit columns.
  • At least one second connection line 80 may be disposed between two data signal lines 60 of adjacent cell columns, and the two data signal lines 60 may be mirror-symmetrical with respect to the second connection line 80 .
  • a minimum distance L1 between at least one second connection line 80 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the driving structure layer may include a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged on the substrate
  • the second source-drain metal layer may include at least a first connecting line 70
  • the third source-drain metal layer may include at least a data signal line 60 and a second connecting line 80, that is, the first connecting line 70 and the second connecting line 80 are arranged in different conductive layers, and the data signal line 60 and the second connecting line 80 are arranged in the same conductive layer.
  • the data signal line 60 can be connected to the first end of the first connection line 70 through the first overlapping via K1
  • the second connection line 80 can be connected to the second end of the first connection line 70 through the second overlapping via K2
  • the second connection line 80 extending along the second direction Y and located in the third source and drain metal layer is connected to the first connection line 70 extending along the first direction X and located in the second source and drain metal layer through the first overlapping via K1
  • the first connection line 70 extending along the first direction X and located in the second source and drain metal layer is connected to the data signal line 60 extending along the second direction Y and located in the third source and drain metal layer through the second overlapping via K2.
  • the driving structure layer may further include a plurality of power supply lines 90 extending along the second direction Y.
  • the plurality of power supply lines 90 may be respectively disposed at gaps between pixel driving circuits of adjacent unit columns.
  • At least one power trace 90 may be disposed between two data signal lines 60 of adjacent cell columns, and the two data signal lines 60 may be mirror-symmetrical with respect to the power trace 90 .
  • a minimum distance L2 between at least one power trace 90 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the power trace 90 may be disposed in the third source-drain metal layer.
  • the pixel driving circuit may include at least a first transistor, a second transistor and a storage capacitor, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, the second region of the first active layer and the first region of the second active layer are interconnected as an integral structure, and are connected to the first electrode plate of the storage capacitor through a first connecting electrode.
  • At least one circuit unit may also include a shielding electrode 63, the orthographic projection of the shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer and the first region of the second active layer on the substrate, and the orthographic projection of the shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode on the substrate.
  • At least one circuit unit may further include a first power line 64 , and the first power line 64 may be connected to the shielding electrode 63 .
  • the shielding electrode 63 may be disposed in the second source-drain metal layer, the first power line 64 may be disposed in the third source-drain metal layer, and the first power line 64 may be connected to the shielding electrode 63 through a via.
  • the pixel driving circuit may include at least a fourth transistor, and the data signal line 60 may be connected to a first electrode of the fourth transistor in the pixel driving circuit through a data connection electrode 61.
  • the first connection line 70 is connected to the data connection electrode 61.
  • At least one circuit unit may further include a data connection block 72 having a first end connected to the first connection line 70 and a second end connected to the data connection electrode 61 .
  • the first connection line 70 , the data connection block 72 and the data connection electrode 61 are disposed in the same layer and are an integrated structure connected to each other.
  • the plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the first transistor and the second transistor being oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor being low-temperature polysilicon transistors.
  • the pixel driving circuit includes at least a storage capacitor and a plurality of transistors
  • the plurality of conductive layers may include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged in a direction away from the substrate.
  • the shielding layer may include at least a shielding electrode
  • the first semiconductor layer may include at least an active layer of a plurality of low-temperature polysilicon transistors
  • the first gate metal layer may include at least a first scanning signal line, a light-emitting signal line, and a first electrode plate of the storage capacitor
  • the second gate metal layer may include at least a second electrode plate of the storage capacitor
  • the second semiconductor layer may include at least an active layer of a plurality of oxide transistors
  • the third gate metal layer may include at least a second scanning signal line and a third scanning signal line
  • the first source-drain metal layer may include at least a second initial signal line of a network connection structure
  • the second source-drain metal layer may include at least a shielding electrode and a first connection line
  • the third source-drain metal layer may include at least a first power supply line, a data signal line, and a second connection line.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the driving structure layer may include the following operations.
  • Forming a blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG. 9 .
  • the shielding layer pattern of each circuit unit may include at least a first shielding connection line 91 , a second shielding connection line 92 , a third shielding connection line 93 , and a shielding electrode 94 .
  • the shape of the shielding electrode 94 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the first shielding connection line 91 may be a straight line extending along the first direction X, and the first shielding connection line 91 may be arranged on one side of the shielding electrode 94 in the first direction X, and connected to the shielding electrode 94.
  • the shape of the second shielding connection line 92 may be a folded line extending along the second direction Y, and the second shielding connection line 92 may be arranged on one side of the shielding electrode 94 in the second direction Y, and connected to the shielding electrode 94.
  • the shape of the third shielding connection line 93 may be a folded line extending along the second direction Y, and the third shielding connection line 93 may be arranged on one side of the shielding electrode 94 in the opposite direction of the second direction Y, and connected to the shielding electrode 94.
  • the first shielding connection line 91 of each circuit unit is connected to the shielding electrode 94 of the circuit unit adjacent in the first direction X, so that the shielding layers in one unit row are connected as one, forming an interconnected integrated structure.
  • the second shielding connection line 92 of each circuit unit is connected to the third shielding connection line 93 of the adjacent circuit unit in the second direction Y, so that the shielding layers in one unit column are connected as a whole to form an interconnected integrated structure.
  • the shielding layers in the unit rows and unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the shielding layers of adjacent unit columns may be mirror-symmetrical with respect to a center line
  • the center line may be a straight line located between adjacent unit columns and extending along the second direction Y.
  • the shielding layer of the Nth column and the shielding layer of the N+1th column may be mirror-symmetrical with respect to the center line
  • the shielding layer of the N+1th column and the shielding layer of the N+2th column may be mirror-symmetrical with respect to the center line
  • the shielding layer of the N+2th column and the shielding layer of the N+3th column may be mirror-symmetrical with respect to the center line.
  • the shapes of the shielding layers in the plurality of cell rows may be substantially the same.
  • forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 10 and 11 , where FIG. 11 is a plan view schematic diagram of the first semiconductor layer in FIG. 10 .
  • the first semiconductor layer pattern of each circuit unit may include at least the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7 , and the third active layer 13 to the seventh active layer 17 are interconnected as an integral structure.
  • the orthographic projection of the third active layer 13 on the substrate at least partially overlaps the orthographic projection of the shielding electrode 94 on the substrate.
  • the sixth active layer 16 may be located on one side of the third active layer 13 in the present circuit unit in the first direction X, and the fourth active layer 14 and the fifth active layer 15 may be located on one side of the third active layer 13 in the present circuit unit in the opposite direction of the first direction X.
  • the fourth active layer 14 in the Mth row of circuit units may be located on the side of the third active layer 13 in the present circuit unit close to the M+1th row of circuit units, and the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 in the Mth row of circuit units may be located on the side of the third active layer 13 in the present circuit unit away from the M+1th row of circuit units, and M may be a positive integer greater than or equal to 1.
  • the third active layer 13 may have an inverted “ ⁇ ” shape
  • the fourth and fifth active layers 14 and 15 may have an “I” shape
  • the sixth and seventh active layers 16 and 17 may have an “L” shape.
  • the third to seventh active layers 13 to 17 may each include a first region, a second region, and a channel region between the first and second regions.
  • the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer
  • the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer
  • the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer
  • the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.
  • the first region 17 - 1 of the seventh active layer in the M+1th row circuit unit may be disposed in the Mth row circuit unit.
  • the first regions 15-1 of the fifth active layer in some adjacent two circuit units may be connected to each other.
  • the first region 15-1 of the fifth active layer in the N+1th column and the first region 15-1 of the fifth active layer in the N+2th column are connected to each other. Since the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the first regions of the fifth active layers of adjacent circuit units into an integrated structure connected to each other, it is possible to ensure that the first electrodes of the fifth transistors T5 of the adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the first semiconductor layer of the Nth column and the first semiconductor layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the first semiconductor layer of the N+1th column and the first semiconductor layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the first semiconductor layer of the N+2th column and the first semiconductor layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the first semiconductor layers in the plurality of cell rows may be substantially the same.
  • the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor to the seventh transistor are LTPS transistors.
  • patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, forming a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 12 and 13 , where FIG. 13 is a plan view schematically showing the first conductive layer in FIG. 12 .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit includes at least: a first scanning signal line 21 , a light emitting signal line 22 , and a first electrode plate 23 of a storage capacitor.
  • the shape of the first electrode plate 23 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 23 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode plate 23 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scan signal line 21 can be a line shape in which the main part extends along the first direction X, the first scan signal line 21 in the Mth row circuit unit can be located on the side of the first electrode 23 of the circuit unit close to the M+1th row circuit unit, the area where the first scan signal line 21 in the Mth row circuit unit overlaps with the fourth active layer of the circuit unit serves as the gate electrode of the fourth transistor T4, and the area where the first scan signal line 21 in the Mth row circuit unit overlaps with the seventh active layer in the M+1th row circuit unit serves as the gate electrode of the seventh transistor T7.
  • the shape of the light-emitting signal line 22 can be a line shape in which the main part extends along the first direction X.
  • the light-emitting signal line 22 in the Mth row circuit unit can be located on the side of the first electrode 23 of the circuit unit away from the M+1th row circuit unit.
  • the area where the light-emitting signal line 22 overlaps with the fifth active layer of the circuit unit serves as the gate electrode of the fifth transistor T5
  • the area where the light-emitting signal line 22 overlaps with the sixth active layer of the circuit unit serves as the gate electrode of the sixth transistor T6.
  • the first scanning signal line 21 and the light-emitting signal line 22 can be designed with unequal widths, and the widths of the first scanning signal line 21 and the light-emitting signal line 22 are the dimensions in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.
  • the present disclosure is not limited here.
  • the first scan signal line 21 may include an area overlapping with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the first scan signal line 21 in the area overlapping with the first semiconductor layer may be smaller than the width of the first scan signal line 21 in the area not overlapping with the first semiconductor layer.
  • the light emitting signal line 22 may include an overlapping area with the first semiconductor layer and an non-overlapping area with the first semiconductor layer, and the width of the first scanning signal line 21 in the overlapping area with the first semiconductor layer may be greater than the width of the first scanning signal line 21 in the non-overlapping area with the first semiconductor layer.
  • the first conductive layers of adjacent unit columns may be mirror-symmetric with respect to the center line.
  • the first conductive layer of the Nth column and the first conductive layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the first conductive layer of the N+1th column and the first conductive layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the first conductive layer of the N+2th column and the first conductive layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the first conductive layers in a plurality of unit rows may be substantially the same.
  • the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer.
  • the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the third transistor T3 to the seventh active layer are both conductorized.
  • forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 14 and 15 , where FIG. 15 is a plan view schematic diagram of the second conductive layer in FIG. 14 .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit includes at least a first initial signal line 31 , a second shielding line 32 , a third shielding line 33 , and a second electrode plate 34 of a storage capacitor.
  • the outline of the second electrode plate 34 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second electrode plate 34 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 23 on the substrate.
  • the second electrode plate 34 can serve as another electrode plate of the storage capacitor, and the first electrode plate 23 and the second electrode plate 34 constitute the storage capacitor of the pixel driving circuit.
  • an opening 35 is provided on the second electrode plate 34.
  • the opening 35 may be rectangular and may be located in the middle of the second electrode plate 34, so that the second electrode plate 34 forms a ring structure.
  • the opening 35 exposes the third insulating layer covering the first electrode plate 23, and the orthographic projection of the first electrode plate 23 on the substrate includes the orthographic projection of the opening 35 on the substrate.
  • the opening 35 is configured to accommodate a first via hole formed subsequently.
  • the first via hole is located in the opening 35 and exposes the first electrode plate 23, so that the second electrode of the first transistor T1 formed subsequently is connected to the first electrode plate 23.
  • part of the second plates 34 in two adjacent circuit units in a unit row can be connected to each other.
  • the second plates 34 in the N+1th column and the second plates 34 in the N+2th column are interconnected as an integrated structure.
  • the second plates 34 in each circuit unit are connected to the first power line formed subsequently, by forming the second plates 34 of adjacent circuit units into an integrated structure that is interconnected, the second plates of the integrated structure can be reused as power signal lines, which can ensure that multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the shape of the first initial signal line 31 can be a line shape with the main part extending along the first direction X, and the first initial signal line 31 in the Mth row circuit unit can be located on the side of the second electrode plate 34 of the circuit unit close to the M+1th row circuit unit.
  • the shape of the second shielding line 32 and the third shielding line 33 can be a line shape in which the main part extends along the first direction X, the second shielding line 32 and the third shielding line 33 in the Mth row circuit unit can be located between the first initial signal line 31 and the second electrode plate 34 of the circuit unit, and the second shielding line 32 can be located on the side of the third shielding line 33 away from the second electrode plate 34, that is, the third shielding line 33 can be located between the second shielding line 32 and the second electrode plate 34.
  • the second shielding line 32 is configured to shield the first active layer of the first transistor
  • the third shielding line 33 is configured to shield the second active layer of the second transistor.
  • the second shielding line 32 and the third shielding line 33 can be designed with unequal widths, and the widths of the second shielding line 32 and the third shielding line 33 are the dimensions in the second direction Y, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the second conductive layer of the Nth column and the second conductive layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the second conductive layer of the N+1th column and the second conductive layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the second conductive layer of the N+2th column and the second conductive layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the second conductive layers in a plurality of cell rows may be substantially the same.
  • Forming a second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIGS. 16 and 17 , where FIG. 17 is a plan view schematic diagram of the second semiconductor layer in FIG. 16 .
  • the second semiconductor layer pattern of each circuit unit includes at least a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2 .
  • the first active layer 11 and the second active layer 12 may be shaped like an "I", and the first active layer 11 in the Mth row of circuit units may be located on a side of the second active layer 12 of the circuit unit close to the M+1th row of circuit units.
  • the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 32 on the substrate, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the third shielding line 33 on the substrate.
  • the first active layer 11 and the second active layer 12 may each include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer may be located on a side of the second shielding line 32 away from the second active layer 12, and the second region 11-2 of the first active layer may be located on a side of the second shielding line 32 close to the second active layer 12.
  • the first region 12-1 of the second active layer may be located on a side of the third shielding line 33 away from the first active layer 11, and the second region 12-2 of the second active layer may be located on a side of the third shielding line 33 close to the first active layer 11.
  • the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer, that is, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer are an interconnected integral structure and can be located between the second shielding line 32 and the third shielding line 33.
  • the orthographic projections of the second region 11 - 2 of the first active layer and the first region 12 - 1 of the second active layer of the integrated structure on the substrate at least partially overlap with the orthographic projection of the first scan signal line 21 in the present circuit unit on the substrate.
  • the second semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the second semiconductor layer of the Nth column and the second semiconductor layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the second semiconductor layer of the N+1th column and the second semiconductor layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the second semiconductor layer of the N+2th column and the second semiconductor layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the second semiconductor layers in a plurality of cell rows may be substantially the same.
  • the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors.
  • the second semiconductor film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.
  • forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 18 and 19 , where FIG. 19 is a plan view schematically showing the third conductive layer in FIG. 18 .
  • the second conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer pattern of each circuit unit includes at least a second scan signal line 41 and a third scan signal line 42 .
  • the shape of the second scan signal line 41 and the third scan signal line 42 can be a line shape in which the main part extends along the first direction X, the second scan signal line 41 and the third scan signal line 42 in the Mth row circuit unit can be located between the first initial signal line 31 and the second electrode plate 34 of the circuit unit, and the second scan signal line 41 can be located on the side of the third scan signal line 42 away from the second electrode plate 34, that is, the third scan signal line 42 can be located between the second scan signal line 41 and the second electrode plate 34.
  • the region where the second scan signal line 41 overlaps the first active layer serves as the gate electrode of the first transistor T1
  • the region where the third scan signal line 42 overlaps the second active layer serves as the gate electrode of the second transistor T2 .
  • the orthographic projection of the second scanning signal line 41 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 32 on the substrate, and the second shielding line 32 and the second scanning signal line 41 can be connected to the same signal source, so that the second shielding line 32 can serve as the bottom gate electrode of the first transistor T1, and the second scanning signal line 41 can serve as the top gate electrode of the first transistor T1, forming a first transistor T1 with a dual-gate structure.
  • the orthographic projection of the third scanning signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third shielding line 33 on the substrate, and the third shielding line 33 and the third scanning signal line 42 can be connected to the same signal source, so that the third shielding line 33 can serve as the bottom gate electrode of the second transistor T2, and the third scanning signal line 42 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a dual-gate structure.
  • the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the third conductive layer of the Nth column and the third conductive layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the third conductive layer of the N+1th column and the third conductive layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the third conductive layer of the N+2th column and the third conductive layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the third conductive layers in a plurality of cell rows may be substantially the same.
  • Forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of vias are disposed on the sixth insulating layer, as shown in FIG. 20 .
  • the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10 and an eleventh via V11.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 35 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 23, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 23 through the via hole.
  • the second via hole V2 is located within the range of the positive projection of the second electrode plate 34 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second electrode plate 34, and the second via hole V2 is configured to connect the subsequently formed fourth connecting electrode to the second electrode plate 34 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the fifth active layer, and the third via hole V3 is configured to connect a subsequently formed fourth connecting electrode to the first area of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the fourth via hole V4 is configured to connect a subsequently formed sixth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of the third active layer (also the first area of the sixth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of the third active layer (also the first area of the sixth active layer), and the sixth via hole V6 is configured to connect a subsequently formed fifth connecting electrode to the second area of the third active layer (also the first area of the sixth active layer) through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of the seventh active layer, and the seventh via hole V7 is configured to connect a subsequently formed second initial signal line to the first area of the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the first active layer, and the eighth via hole V8 is configured to connect a subsequently formed second connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the ninth via hole V9 are etched away to expose the surface of the second region of the second active layer, and the ninth via hole V9 is configured to connect a subsequently formed fifth connecting electrode to the second region of the second active layer through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the tenth via hole V10 are etched away to expose the surface of the second area of the first active layer (also the first area of the second active layer), and the tenth via hole V10 is configured to connect a subsequently formed first connecting electrode to the second area of the first active layer (also the first area of the second active layer) through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first initial signal line 31, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the first initial signal line 31 through the via hole.
  • the plurality of vias in adjacent unit columns may be mirror-symmetric with respect to the center line.
  • the plurality of vias in the Nth column and the plurality of vias in the N+1th column may be mirror-symmetric with respect to the center line
  • the plurality of vias in the N+1th column and the plurality of vias in the N+2th column may be mirror-symmetric with respect to the center line
  • the plurality of vias in the N+2th column and the plurality of vias in the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the plurality of vias in the plurality of unit rows may be substantially the same.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 21 and 22 , where FIG. 22 is a plan view of the fourth conductive layer in FIG. 21 .
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a second initial signal line 57 and a second initial connection line 58.
  • the shape of the first connection electrode 51 may be a zigzag shape in which the main part extends along the second direction Y.
  • the first end of the first connection electrode 51 is connected to the first electrode plate 23 through the first via hole V1.
  • the second region of the first active layer also the first region of the second active layer
  • the first connection electrode 51 may simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2 (the second node N2 of the pixel driving circuit).
  • the second connection electrode 52 may be in the shape of a strip extending along the first direction X, a first end of the second connection electrode 52 is connected to the first region of the first active layer through an eighth via hole V8, and a second end of the second connection electrode 52 is connected to the first initial signal line 31 through an eleventh via hole V11, so that the first initial voltage transmitted by the first initial signal line 31 is written into the first electrode of the first transistor T1.
  • the second connection electrode 52 may serve as the first electrode of the first transistor T1.
  • the second connection electrode 52 of the Nth column and the second connection electrode 52 of the N+1th column may be an interconnected integral structure
  • the second connection electrode 52 of the N+2th column and the second connection electrode 52 of the N+3th column may be an interconnected integral structure
  • the shape of the third connection electrode 53 may be rectangular, and the third connection electrode 53 is connected to the first region of the fourth active layer through the fifth via hole V5.
  • the third connection electrode 53 may serve as a first electrode of the fourth transistor T4, and the third connection electrode 53 is configured to be connected to an eleventh connection electrode formed subsequently.
  • the fourth connection electrode 54 may be in a "Y" shape, the first end of the fourth connection electrode 54 is connected to the second electrode plate 34 through the second via hole V2, and the second end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the third via hole V3, thereby achieving the same potential for the first electrode of the fifth transistor T5 and the second electrode plate 34 of the storage capacitor in the circuit unit.
  • the fourth connection electrode 54 may serve as the first electrode of the fifth transistor T5, and the fourth connection electrode 54 is configured to be connected to a shielding electrode formed subsequently.
  • the fourth connection electrode 54 in the N+1th column and the fourth connection electrode 54 in the N+2th column may be an integrated structure connected to each other.
  • the fourth connection electrode 54 in each circuit unit is connected to the first power line formed subsequently, by forming the fourth connection electrodes 54 of adjacent circuit units into an integrated structure connected to each other, it is possible to ensure that the fourth connection electrodes 54 of adjacent circuit units have the same potential, thereby making the first electrodes of the fifth transistors T5 in the adjacent circuit units have the same potential, and the second electrodes 34 of the storage capacitors in the adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the orthographic projection of the fourth connection electrode 54 on the substrate at least partially overlaps with the orthographic projection of the second region of the seventh active layer on the substrate, and the fourth connection electrode 54 with a constant potential can play a shielding role to ensure the potential stability of key nodes in the pixel driving circuit.
  • the shape of the fifth connection electrode 55 may be rectangular, a first end of the fifth connection electrode 55 is connected to the second region of the third active layer (also the first region of the sixth active layer) through a sixth via hole V6, and a second end of the fifth connection electrode 55 is connected to the second region of the second active layer through a ninth via hole V9.
  • the fifth connection electrode 55 may simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 (the third node N3 of the pixel driving circuit).
  • the shape of the sixth connection electrode 56 may be polygonal, and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4.
  • the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to a twelfth connection electrode formed subsequently.
  • the second initial signal line 57 may be in the shape of a zigzag line with a main portion extending along the first direction X.
  • the second initial signal line 57 in the Mth row of circuit units may be disposed on a side of the storage capacitor close to the M+1th row of circuit units.
  • the second initial signal line 57 in the Mth row of circuit units is connected to the first region of the seventh active layer in the M+1th row of circuit units through the seventh via hole V7, so that the second initial voltage transmitted by the second initial signal line 57 is written into the first electrode of the seventh transistor T7.
  • the second initial signal line 57 is connected to the first region of all the seventh active layers in a unit row, it can be ensured that the first electrodes of all the seventh transistors T7 in a unit row have the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second initial connection line 58 may be in the shape of a zigzag line with the main part extending along the second direction Y.
  • the second initial connection line 58 may be disposed between two second initial signal lines 57 adjacent to each other in the second direction Y, and respectively connected to the two second initial signal lines 57.
  • the second initial signal lines 57 extending along the first direction X and the second initial connection lines 58 extending along the second direction Y form initial signal lines of a network connection structure in the display area, which not only can minimize the resistance of the initial signal lines, reduce the voltage drop of the initial voltage, effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the uniformity within the signal plane, and effectively improve the display uniformity, but also make the potential of the fourth node (anode) of the pixel driving circuit more uniform in the reset stage, and the light-emitting device lighting speed is easier to keep consistent, thereby improving the display quality and display quality.
  • the second initial connection line 58 may be disposed in odd-numbered cell columns, or may be disposed in even-numbered cell columns, that is, one second initial connection line 58 may be disposed in two cell columns.
  • the cell column where the second initial connection line 58 in one cell row is located is different from the cell column where the second initial connection line 58 in the other cell row is located.
  • the second initial connection line 58 respectively connecting the second initial signal line 57 in the M-1th row and the second initial signal line 57 in the Mth row may be located in the circuit unit of the Nth column
  • the second initial connection line 58 respectively connecting the second initial signal line 57 in the Mth row and the second initial signal line 57 in the M+1th row may be located in the circuit unit of the N+2th column.
  • the second preliminary signal line 57 and the second preliminary connection line 58 are simultaneously formed through the same patterning process and are an integral structure connected to each other.
  • first to sixth connection electrodes 51 to 56 and the second initial signal line 57 of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the shapes of the first to sixth connection electrodes 51 to 56 and the second initial signal line 57 in a plurality of cell rows may be substantially the same.
  • Forming a first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are disposed on the first planar layer, as shown in FIG. 23 .
  • the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connecting electrode 53, and the twenty-first via hole V21 is configured to connect the subsequently formed eleventh connecting electrode to the third connecting electrode 53 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-second via hole V22 is configured to connect the subsequently formed twelfth connecting electrode to the sixth connecting electrode 56 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the fourth connecting electrode 54, and the twenty-third via hole V232 is configured to connect a subsequently formed shielding electrode to the fourth connecting electrode 54 through the via hole.
  • the plurality of vias on the first planar layer of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the plurality of vias on the first planar layer in the plurality of cell rows may have substantially the same shape.
  • forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first flat layer, as shown in FIGS. 24 and 25 , where FIG. 25 is a plan view of the fifth conductive layer in FIG. 24 .
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the fifth conductive layer of each circuit unit includes at least an eleventh connecting electrode 61 , a twelfth connecting electrode 62 , and a shielding electrode 63 .
  • the shape of the eleventh connection electrode 61 can be a strip shape with the main part extending along the second direction Y.
  • the eleventh connection electrode 61 is connected to the third connection electrode 53 through the twenty-first via hole V21.
  • the eleventh connection electrode 61 is configured to be connected to a subsequently formed data signal line.
  • the eleventh connection electrode 61 can be called a data connection electrode.
  • the shape of the twelfth connection electrode 62 may be polygonal, the twelfth connection electrode 62 is connected to the sixth connection electrode 56 through the twelfth via hole V22, and the twelfth connection electrode 62 is configured to be connected to the subsequently formed anode connection electrode.
  • the shielding electrode 63 may be in a block shape with a main portion extending along the second direction Y.
  • the shielding electrode 63 is connected to the fourth connection electrode 54 through the twenty-third via hole V23 and is configured to be connected to a first power line formed subsequently.
  • the shielding electrode 63 may include a shielding main body portion 63-1 and a shielding connection portion 63-2.
  • the shielding main body portion 63-1 may be rectangular in shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the shielding main body portion 63-1 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate, and the orthographic projection of the shielding main body portion 63-1 on the substrate at least partially overlaps with the orthographic projection of the second area of the first active layer and the first area of the second active layer on the substrate.
  • the shielding connection portion 63-2 may be in the shape of a strip extending along the second direction Y, the first end of the shielding connection portion 63-2 is connected to the shielding main body portion 63-1, and the second end of the shielding connection portion 63-2 is extended in a direction away from the shielding main body portion 63-1, and is connected to the fourth connection electrode 54 through the twenty-third via hole V23, and the orthographic projection of the shielding connection portion 63-2 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate.
  • the shielding electrode 63 since the shielding electrode 63 completely blocks the second region of the first active layer and the first region of the second active layer, the shielding electrode 63 can block the light emission of the light emitting device and the reflected light of the film layer from irradiating the oxide transistor, and can prevent the characteristic drift of the oxide transistor due to light, thereby improving the electrical characteristics of the oxide transistor.
  • the shielding electrode 63 Since the shielding electrode 63 is connected to the first power line formed later, the shielding electrode 63 with a constant potential can not only effectively shield the influence of the data voltage jump and other signals on the second node N2 in the pixel driving circuit, avoid the influence of the data voltage jump and other signals on the potential of the second node N2, effectively avoid the deterioration of crosstalk, but also avoid the display difference caused by the fact that some circuit units are provided with the second connection line while some circuit units are not provided with the second connection line, thereby improving the display effect.
  • the fourth conductive layer may further include a first connection line 70 , a first bonding block 71 , and a data connection block 72 .
  • the shape of the first connection line 70 can be a zigzag line with the main part extending along the first direction X.
  • the first connection line 70 of the Mth row circuit unit can be arranged on the side of the shielding electrode 63 close to the M+1th row circuit unit, and the first connection line 70 is configured as a horizontal line in the data connection line.
  • a break may be provided on the first connection line 70, and the first connection line 70 on one side of the break serves as a lateral line in the data connection line, and the first connection line 70 on the other side of the break serves as a dummy line to ensure etching uniformity of the display substrate.
  • the first bridge block 71 may be in a polygonal shape, located between adjacent unit columns, and connected to the first connection line 70.
  • the first bridge block 71 may be disposed between the Nth column and the N+1th column, and the first bridge block 71 may be disposed between the N+2th column and the N+3th column.
  • a portion of the first bridge block 71 is configured to be connected to a second connection line formed subsequently, and another portion of the first bridge block 71 is used as a dummy bridge structure to ensure etching uniformity of the display substrate.
  • the data connection block 72 may be in a bar shape extending along the second direction Y, a first end of the data connection block 72 is connected to the first connection line 70 , and a second end of the data connection block 72 is connected to the third connection electrode 53 .
  • the first connection line 70 , the first bonding block 71 , and the data connection block 72 may be simultaneously formed by a same patterning process and are an integrated structure connected to each other.
  • the eleventh connection electrode 61, the twelfth connection electrode 62 and the shielding electrode 63 of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the shapes of the eleventh connection electrode 61, the twelfth connection electrode 62 and the shielding electrode 63 in a plurality of cell rows may be substantially the same.
  • Forming a second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are disposed on the second planar layer, as shown in FIG. 26 .
  • the plurality of vias in each circuit unit includes at least a thirty-first via V31 , a thirty-second via V32 , and a thirty-third via V33 .
  • the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the eleventh connection electrode 61 on the substrate, the second flat layer in the thirty-first via hole V31 is etched away, exposing the surface of the eleventh connection electrode 61, and the thirty-first via hole V31 is configured to allow a subsequently formed data signal line to be connected to the eleventh connection electrode 61 through the via hole.
  • the thirty-first via hole V31 on the eleventh connection electrode 61 (data connection electrode) connected to the first connection line 70 can be referred to as a first lap via hole.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 62 on the substrate, the second flat layer in the thirty-second via hole V32 is etched away to expose the surface of the twelfth connecting electrode 62, and the thirty-second via hole V32 is configured to connect a subsequently formed anode connecting electrode to the twelfth connecting electrode 62 through the via hole.
  • the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the shielding connection portion 63-2 in the shielding electrode 63 on the substrate, the second flat layer in the thirty-third via V33 is etched away to expose the surface of the shielding connection portion 63-2, and the thirty-third via V33 is configured to connect a subsequently formed first power line to the shielding electrode 63 through the via.
  • the plurality of vias on the second flat layer may further include a thirty-fourth via V34.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first lap block 71 on the substrate, the second flat layer in the thirty-fourth via V34 is etched away, exposing the surface of the first lap block 71, and the thirty-fourth via V34 is configured to allow a second connecting line formed subsequently to be connected to the first connecting line 70 through the via.
  • the thirty-fourth via V34 is provided on part of the first lap block 71, and the thirty-fourth via V34 may be referred to as a second lap via.
  • the thirty-first via V31, the thirty-second via V32, and the thirty-third via V33 of adjacent unit columns may be mirror-symmetric with respect to the center line.
  • the shapes of the thirty-first via V31, the thirty-second via V32, and the thirty-third via V33 in multiple unit rows may be substantially the same.
  • forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the second flat layer, as shown in FIGS. 27 and 28 , where FIG. 28 is a plan view of the sixth conductive layer in FIG. 27 .
  • the sixth conductive layer may be referred to as a third source-drain metal (SD3) layer.
  • the sixth conductive layer of each circuit unit includes at least a data signal line 60 , a first power line 64 , and an anode connection electrode 65 .
  • the data signal line 60 may be in the shape of a line whose main body portion extends along the second direction Y, and the data signal line 60 is connected to the eleventh connection electrode 61 through the thirty-first via hole V31. Since the eleventh connection electrode 61 is connected to the third connection electrode 53 through the via hole, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 60 is connected to the first electrode of the fourth transistor T4, and the data signal line 60 can write the data signal to the first electrode of the fourth transistor T4.
  • the data signal line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first and second planar layers, the distance between the data signal line and the corresponding signal line is increased, and the parasitic capacitance between the data signal line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the data signal line.
  • SD3 source-drain metal
  • the first power line 64 may be in the shape of a zigzag line with a main body extending along the second direction Y, and the first power line 64 is connected to the shielding connection portion 63-2 of the shielding electrode 63 through the thirty-third via hole V33.
  • the shielding electrode 63 is connected to the fourth connection electrode 54 through the via hole, and the fourth connection electrode 54 is connected to the first region and the second electrode plate 34 of the fifth active layer through the via hole, the connection between the first power line 64 and the first electrode and the second electrode plate 34 of the fifth transistor T5 is realized, and the first power line 64 can write a power signal to the first electrode of the fifth transistor T5, and the first electrode of the fifth transistor T5 and the second electrode plate 34 of the storage capacitor have the same potential.
  • the first power line 64 may be a zigzag line of unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.
  • the shape of the anode connection electrode 65 may be polygonal, and the anode connection electrode 65 is connected to the twelfth connection electrode 62 through the thirty-second via hole V32, and the anode connection electrode 65 is configured to be connected to the subsequently formed anode. Since the twelfth connection electrode 62 is connected to the sixth connection electrode 56 through the via hole, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.
  • the sixth conductive layer may further include a second connection line 80 , a second strapping block 81 , and a power trace 90 .
  • the second connection line 80 may be in the shape of a line whose main part extends along the second direction Y, and may be located at the gap between the pixel driving circuits of adjacent unit columns, and the second connection line 80 is connected to the first bridge block 71 through the thirty-fourth via hole V34. Since the first bridge block 71 is connected to the first connection line 70, the connection between the second connection line 80 and the first connection line 70 is achieved. Since the first connection line 70 is connected to the eleventh connection electrode 61 through the data connection block 72, and the eleventh connection electrode 61 is connected to the data signal line 60 through the via hole, the data signal line 60, the first connection line 70, and the second connection line 80 are sequentially connected.
  • the second overlap block 81 may be in a polygonal shape, located between adjacent unit columns, and aligned with the second connection line 80.
  • the second overlap block 81 may be disposed between the Nth column and the N+1th column, and the second overlap block 81 may be disposed between the N+2th column and the N+3th column.
  • the orthographic projection of the second overlap block 81 on the substrate at least partially overlaps the orthographic projection of the first overlap block 71 on the substrate, a portion of the second overlap block 81 is connected to the first overlap block 71 through the thirty-fourth via hole V34, and another portion of the second overlap block 81 serves as a dummy overlap structure to ensure etching uniformity of the display substrate.
  • the pixel driving circuit of the display area adopts a mirror-symmetrical structure
  • the pixel driving circuits of adjacent unit columns are mirror-symmetrical. Therefore, when the size of the circuit unit remains unchanged, a gap can be formed between the pixel driving circuits of adjacent unit columns through central compression, so that the second connecting line extending longitudinally in the display area can be set at the gap between the adjacent pixel driving circuits, thereby maximizing the distance between the second connecting line and the data signal line and minimizing the interference caused by capacitive coupling between the second connecting line and the data signal line.
  • At least one second connection line 80 may be disposed between two data signal lines 60 of adjacent cell columns, the two data signal lines 60 may be mirror-symmetrical with respect to the center line, and the two data signal lines 60 may be mirror-symmetrical with respect to the second connection line 80 .
  • a minimum distance L1 between at least one second connection line 80 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the second connecting line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first flat layer and the second flat layer, the distance between the second connecting line and the corresponding signal line is increased, and the parasitic capacitance between the second connecting line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the second connecting line.
  • SD3 third source-drain metal
  • the first connecting line is arranged in the second source-drain metal (SD2) layer and the second connecting line is arranged in the third source-drain metal (SD3) layer, the first connecting line and the second connecting line only need one flat layer via to be connected, thereby minimizing the occupied space and facilitating the realization of high-resolution display.
  • SD2 second source-drain metal
  • SD3 third source-drain metal
  • the power supply line 90 may be in the shape of a line whose main part extends along the second direction Y, and is located between some adjacent unit columns. Between at least one unit column, only the power supply line 90 may be provided, and no second connection line 80 may be provided. Between at least one unit column, the second connection line 80 and the power supply line 90 may be provided, respectively, and the power supply line 90 and the second connection line 80 may be located on the same straight line extending along the second direction Y, and a break is provided between the power supply line 90 and the second connection line 80, and the break is configured to achieve insulation between the power supply line 90 and the second connection line 80.
  • At least one power trace 90 may be disposed between two data signal lines 60 of adjacent cell columns, and the two data signal lines 60 may be mirror-symmetrical with respect to the power trace 90 .
  • a minimum distance L2 between at least one power trace 90 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the plurality of power lines 90 may be lines that continuously provide low voltage signals.
  • the power line may be a second power line VSS.
  • the plurality of power lines 90 may be connected to power leads provided in a binding area or a frame area.
  • the present disclosure realizes a structure in which a low voltage power line is provided in a sub-pixel (VSS in pixel) by providing a power line in the display area, which can not only effectively reduce the resistance of the power signal line, effectively reduce the voltage drop of the low voltage power signal, and achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the low voltage power line provided in the sub-pixel structure can greatly reduce the width of the power lead in the frame area and the binding area, which is conducive to achieving a narrow frame.
  • the data signal lines 60, first power lines 64 and anode connection electrodes 65 of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the shapes of the data signal lines 60, first power lines 64 and anode connection electrodes 65 in a plurality of cell rows may be substantially the same.
  • forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of vias are disposed on the third planar layer, as shown in FIG. 29 .
  • the vias of each circuit unit include at least an anode via V40.
  • the orthographic projection of the anode via V40 on the substrate is within the range of the orthographic projection of the anode connection electrode 65 on the substrate, the third flat layer in the anode via V40 is removed, exposing the surface of the anode connection electrode 65, and the anode via V40 is configured to connect a subsequently formed anode to the anode connection electrode 65 through the via.
  • the drive structure layer is prepared on the substrate.
  • the drive structure layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel drive circuit.
  • the drive structure layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer sequentially arranged on the substrate.
  • the blocking layer may include at least a blocking electrode
  • the first semiconductor layer may include at least an active layer of a third transistor to a seventh transistor
  • the first conductive layer may include at least a first scanning signal line, a light-emitting signal line and a first electrode plate of a storage capacitor
  • the second conductive layer may include at least a first initial signal line and a second electrode plate of a storage capacitor
  • the second semiconductor layer may include at least an active layer of a first transistor to a second transistor
  • the third conductive layer may include at least a second scanning signal line and a third scanning signal line
  • the fourth conductive layer may include at least a second initial signal line, a second initial connecting line and a plurality of connecting electrodes
  • the fifth conductive layer may include at least a shielding electrode and a first connecting line
  • the sixth conductive layer may include at least a data signal line, a first power line, a second power line and a second connecting line.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called a gate insulating (GI) layer
  • the sixth insulating layer may be called an interlayer insulating (ILD) layer.
  • the first planar layer, the second planar layer and the third planar layer may be made of organic materials, such as resin, etc.
  • the pixel driving circuits in two adjacent circuit units in one unit row may be substantially mirror-symmetrical with respect to a center line, where the center line is a straight line located between the two adjacent circuit units and extending along the second direction Y.
  • the pixel driving circuits in the Nth column and the pixel driving circuits in the N+1th column may be mirror-symmetrical with respect to the center line.
  • the pixel driving circuits in the N+1th column and the pixel driving circuits in the N+2th column may be mirror-symmetrical with respect to the center line.
  • the pixel driving circuits in two adjacent circuit units may be substantially mirror-symmetrical with respect to a center line and may include any one or more of the following: the first semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, the first conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, the second conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, the second semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, and the third conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line.
  • a light-emitting structure layer is prepared on the driving structure layer, and the preparation process of the light-emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the third flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, as shown in FIG. 30 .
  • the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the plurality of anode patterns may include a first anode 90A located at a red light emitting unit emitting red light, a second anode 90B located at a blue light emitting unit emitting blue light, a third anode 90C located at a first green light emitting unit emitting green light, and a fourth anode 90D located at a second green light emitting unit emitting green light.
  • the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be connected to the anode connection electrode 65 of the circuit unit through the anode via hole V40 , respectively.
  • At least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting part that are connected to each other.
  • the shape of the anode main body may be rectangular, and the corners of the rectangle may be provided with arc-shaped chamfers.
  • the shape of the anode connecting part may be strip-shaped, and the first end of the anode connecting part is connected to the anode main body, and the second end of the anode connecting part extends in a direction away from the anode main body and is connected to the anode connecting electrode 65 through the anode via V40.
  • the orthographic projections of the first anode, the second anode, the third anode and the fourth anode on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projection of the shielding electrode on the substrate.
  • the orthographic projection of the first anode on the substrate and the orthographic projection of the first power line on the substrate have a first overlapping area
  • the orthographic projection of the first anode on the substrate and the orthographic projection of the shielding electrode on the substrate have a second overlapping area
  • the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the orthographic projection of the second anode on the substrate and the orthographic projection of the first power line on the substrate have a first overlapping area
  • the orthographic projection of the second anode on the substrate and the orthographic projection of the shielding electrode on the substrate have a second overlapping area
  • the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the present disclosure effectively reduces the overlapping area of the first anode and the second anode with the first power line by setting the shielding electrode on the second source-drain metal layer SD2 and the first power line on the third source-drain metal layer SD3, effectively reduces the parasitic capacitance of the fourth node N4 of the pixel driving circuit, and improves the lighting speed of the light-emitting device.
  • forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer covering the anode conductive layer pattern, wherein a plurality of pixel openings 90E are provided on the pixel definition layer, and the pixel definition film in the pixel openings 90E is removed to expose the surfaces of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D, respectively, as shown in FIG. 31 .
  • the subsequent preparation process may include: first forming an organic light-emitting layer by evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a packaging structure layer
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of organic materials
  • the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the display substrate provided by the exemplary embodiment of the present disclosure, by setting the data connection line in the display area, the lead line of the binding area is connected to the data signal line through the data connection line, so that the fan-shaped oblique line does not need to be set in the lead area, effectively reducing the length of the lead area, greatly reducing the width of the lower frame, and improving the screen ratio, which is conducive to the realization of full-screen display.
  • the present disclosure sets the first connection line in the second source and drain metal layer, and the second connection line is set in the third source and drain metal layer, so that the first connection line and the second connection line only need a flat layer via to achieve connection, which minimizes the occupied space, is conducive to the realization of high-resolution display, and can increase the resolution (PPI) of the LTPO display substrate to 480 while realizing a narrow frame.
  • the present disclosure sets the data signal line and the second connection line in the third source and drain metal layer, increases the distance between the data signal line and the second connection line and the corresponding signal line, reduces the parasitic capacitance between the data signal line and the second connection line and the corresponding signal line, and thus effectively reduces the capacitive load of the data signal line and the second connection line.
  • the present disclosure adopts the mirror symmetry and center compression of the pixel driving circuit, sets the second connection line at the gap between the adjacent unit columns, maximizes the distance between the second connection line and the data signal line, and minimizes the interference caused by capacitive coupling between the second connection line and the data signal line.
  • the present disclosure sets a shielding electrode in the second source-drain metal layer.
  • the shielding electrode can block the light emission of the light-emitting device and the reflected light of the film layer from irradiating the oxide transistor, which can prevent the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.
  • the shielding electrode can effectively shield the influence of data voltage jump and other signals on the second node N2 in the pixel driving circuit, thereby avoiding the influence of data voltage jump and other signals on the potential of the second node N2, effectively avoiding the deterioration of crosstalk, and avoiding the display difference caused by the fact that some circuit units are set with the second connection line while some circuit units are not set with the second connection line, thereby improving the display effect.
  • the present disclosure forms a second initial signal line with a network connection structure in the display area, which can not only minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the uniformity in the signal surface, and effectively improve the display uniformity, but also make the potential of the fourth node (anode) of the pixel driving circuit in the reset stage more uniform, and the light-emitting device lighting speed is easier to keep consistent, thereby improving the display quality and display quality.
  • the present disclosure effectively reduces the overlapping area of the anode and the first power line by setting the shielding electrode in the second source and drain metal layer and the first power line in the third source and drain metal layer, effectively reduces the parasitic capacitance of the fourth node N4 of the pixel driving circuit, and improves the lighting speed of the light-emitting device.
  • the present disclosure realizes the structure of VSS in pixel by setting the power line in the display area, which can greatly reduce the width of the frame power lead, greatly reduce the width of the left and right frame, improve the screen ratio, and facilitate the realization of full-screen display.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.
  • FIG32 is a schematic diagram of a planar structure of another display substrate of the embodiment of the present disclosure.
  • the main structure of the display substrate of the present exemplary embodiment is substantially similar to the main structure of the display substrate of the aforementioned embodiment, except that the minimum distance L1 between at least one second connection line 80 and an adjacent data signal line 60 in the first direction X can be approximately 1/2 of the minimum distance L3 between two data signal lines 60 in adjacent unit columns in the first direction X, and the minimum distance L2 between at least one power supply line 90 and an adjacent data signal line 60 in the first direction X can be approximately 1/2 of the minimum distance L3 between two data signal lines 60 in adjacent unit columns in the first direction X.
  • the second connection line 80 in the display substrate shown in FIG8 is arranged between two data signal lines 60 with a larger spacing in adjacent unit columns
  • the second connection line 80 in the display substrate shown in FIG32 is arranged between two data signal lines 60 with a smaller spacing in adjacent unit columns.
  • the structure and preparation process shown above in the present disclosure are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.
  • the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.
  • the present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment.
  • the display substrate includes a display area
  • the preparation method includes:
  • a driving structure layer is formed on the substrate of the display area, the driving structure layer at least comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction and a plurality of second connecting lines extending along a second direction, wherein the first direction intersects with the second direction;
  • the circuit unit comprises a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, first ends of a plurality of first connecting lines are connected to a plurality of data signal lines correspondingly, and second ends of a plurality of first connecting lines are connected to a plurality of second connecting lines correspondingly;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and extending along the second direction, and the second connecting lines are arranged at gaps

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PCT/CN2022/128721 2022-10-31 2022-10-31 显示基板及其制备方法、显示装置 Ceased WO2024092434A1 (zh)

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US18/279,384 US20250089504A1 (en) 2022-10-31 2022-10-31 Display Substrate and Preparation Method therefor, and Display Apparatus
JP2024560561A JP2025535215A (ja) 2022-10-31 2022-10-31 表示基板及びその製造方法、表示装置
CN202280003914.6A CN118284969A (zh) 2022-10-31 2022-10-31 显示基板及其制备方法、显示装置

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