WO2024088332A1 - 芯片组件、电子设备以及芯片组件的制备方法 - Google Patents

芯片组件、电子设备以及芯片组件的制备方法 Download PDF

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Publication number
WO2024088332A1
WO2024088332A1 PCT/CN2023/126689 CN2023126689W WO2024088332A1 WO 2024088332 A1 WO2024088332 A1 WO 2024088332A1 CN 2023126689 W CN2023126689 W CN 2023126689W WO 2024088332 A1 WO2024088332 A1 WO 2024088332A1
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WIPO (PCT)
Prior art keywords
chip
thermoelectric module
conductive
electrically connected
wiring layer
Prior art date
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Ceased
Application number
PCT/CN2023/126689
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English (en)
French (fr)
Inventor
金豆
黎志冬
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Publication date
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Publication of WO2024088332A1 publication Critical patent/WO2024088332A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/28—Arrangements for cooling comprising Peltier coolers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass

Definitions

  • the present application belongs to the technical field of communication equipment, and specifically relates to a chip component and an electronic device.
  • the purpose of the embodiments of the present application is to provide a chip assembly, an electronic device and a method for preparing a chip assembly, which can solve the problem of poor heat dissipation effect of the current chip assembly.
  • an embodiment of the present application provides a chip assembly, comprising a wiring layer, a chip, at least two conductive pillars and a thermoelectric module, wherein the chip is stacked on the wiring layer, the thermoelectric module has a cold end and a hot end that are opposite to each other, the cold end of the thermoelectric module is arranged on a side of the chip that is away from the wiring layer, the at least two conductive pillars are arranged in the wiring layer, and the at least two conductive pillars are electrically connected to the thermoelectric module.
  • an embodiment of the present application further provides an electronic device comprising the above-mentioned chip assembly.
  • the present application also provides a method for preparing a chip assembly, which is applied to the above-mentioned chip assembly, including: bonding the wiring layer to a glass carrier, and setting the at least two conductive pillars on the wiring layer; setting the chip on the wiring layer, and the chip is located in the accommodation space formed by the at least two conductive pillars; setting the thermoelectric module on the side of the chip away from the wiring layer, and the cold end of the thermoelectric module is set on the side of the chip away from the wiring layer, and the at least two conductive pillars are electrically connected to the thermoelectric module; and releasing the bonding of the glass carrier.
  • thermoelectric module is arranged on the side of the chip away from the wiring layer in a stacking manner, and the wiring layer is electrically connected to the thermoelectric module through at least two conductive columns, so as to transmit current to the thermoelectric module.
  • a temperature gradient appears at both ends of the thermoelectric module, thereby forming a cold end and a hot end, wherein the cold end of the thermoelectric module is arranged relative to the chip, and the heat generated when the chip is working will be absorbed by the cold end of the thermoelectric module to achieve the purpose of cooling the chip.
  • thermoelectric module in the embodiment of the present application is part of the chip assembly, which is arranged inside the chip assembly, so the thermoelectric module is closer to the chip, and its heat dissipation effect will be greatly improved. Therefore, the embodiment of the present application can solve the problem of poor heat dissipation effect of the current chip assembly.
  • FIG1 is a cross-sectional view of the structure of a chip assembly disclosed in an embodiment of the present application.
  • FIG2 is a schematic diagram of a partial structure of a chip assembly disclosed in an embodiment of the present application.
  • 3 to 4 are schematic diagrams of the structure of the chip assembly disclosed in the embodiment of the present application at different viewing angles;
  • 5 and 6 are schematic structural diagrams of a chip assembly disclosed in another embodiment of the present application at different viewing angles;
  • FIG7 is a schematic diagram of the structure of the thermoelectric module disclosed in the embodiment of the present application.
  • FIG8 is a schematic diagram of a packaging structure of a chip assembly disclosed in an embodiment of the present application.
  • FIG9 is a partial enlarged view of the structure shown in FIG8 at A;
  • 10 to 17 are schematic diagrams of the structure of the chip assembly disclosed in the embodiments of the present application in different packaging states.
  • the present application discloses a chip assembly.
  • the chip assembly may be an integrated circuit, or other chip assembly, which is not specifically limited here.
  • the chip assembly includes a wiring layer 110, a chip 120, at least two conductive pillars 130, and a thermoelectric module 140.
  • the chip 120 is stacked with the wiring layer 110, and the chip 120 is electrically connected to the wires in the wiring layer 110.
  • the wiring layer 110 is used to supply power to the chip 120, the thermoelectric module 140 and other structures.
  • the thermoelectric module 140 has a cold end 148 and a hot end 149 that are separated from each other.
  • the cold end 148 of the thermoelectric module 140 is arranged on the side of the chip 120 that is away from the wiring layer 110, that is, the cold end 148 of the thermoelectric module 140 is arranged opposite to the chip 120, and the hot end 149 of the thermoelectric module 140 is far away from the chip 120.
  • the thermoelectric module 140 cools down the chip 120.
  • the thermoelectric module 140 has the characteristics of small size, light weight, no active firmware and no pollution.
  • the chip 120 has a first pad 220 on one side facing the wiring layer 110, and the wiring layer 110 has a second pad on one side facing the chip 120, and the first pad 220 and the second pad are connected by a micro bump 230.
  • At least two conductive pillars 130 are disposed on the wiring layer 110, and at least two conductive pillars 130 are electrically connected to the thermoelectric module 140.
  • the conductive pillars 130 are used to deliver current to the thermoelectric module 140 so that the thermoelectric module 140 generates a thermoelectric effect, thereby cooling the chip 120.
  • the conductive pillars 130 may be copper pillars, or other conductive structures, which are not specifically limited here.
  • thermoelectric module 140 is arranged on the side of the chip 120 away from the wiring layer 110 in a stacking manner.
  • the wiring layer 110 is electrically connected to the thermoelectric module 140 through at least two conductive pillars 130, so as to transmit current to the thermoelectric module 140.
  • a temperature gradient appears at both ends of the thermoelectric module 140, thereby forming a cold end 148 and a hot end 149, wherein the cold end 148 of the thermoelectric module 140 is arranged opposite to the chip 120, and the heat generated by the chip 120 when working will be absorbed by the cold end 148 of the thermoelectric module 140, so as to achieve the purpose of cooling the chip 120.
  • thermoelectric module 140 in the embodiment of the present application is a part of the chip component, which is arranged inside the chip component, so the thermoelectric module 140 is closer to the chip 120, and its heat dissipation effect will be greatly improved; and, compared with structures such as fans, the thermoelectric module 140 occupies a smaller space, which is conducive to reducing the volume of the chip component. Therefore, the embodiment of the present application can solve the problem of poor heat dissipation effect of the current chip assembly. In addition, the embodiment of the present application uses the thermoelectric module 140 to cool the chip 120, which has the characteristics of long service life and easy control.
  • the thermoelectric module 140 has an input terminal 141 and an output terminal 142 on a side facing away from the chip 120, and at least two conductive pillars 130 are arranged at intervals along the circumference of the chip 120.
  • the electric posts are arranged irregularly, and this arrangement is more conducive to the structural design of the thermoelectric module.
  • At least two conductive posts 130 include a positive conductive post 131 and a negative conductive post 132.
  • each positive conductive post 131 and each negative conductive post 132 can be arranged in parallel, so as to reduce resistance, increase the current flow of the thermoelectric module 140, and improve the thermoelectric efficiency of the electric heating module 140.
  • thermoelectric module 140 includes at least two heat-conducting units, the at least two heat-conducting units include a first heat-conducting unit and a second heat-conducting unit, the first heat-conducting unit and the second heat-conducting unit each include a P-type semiconductor 143, an N-type semiconductor 144 and a connector 145, the P-type semiconductor 143 and the N-type semiconductor 144 are arranged at intervals on the wiring layer 110, the connector 145 is connected between the P-type semiconductor 143 and the N-type semiconductor 144, and the connector 145 is located on a side of the P-type semiconductor and the N-type semiconductor close to the chip 120, that is, the connector 145 is connected to one end of the P-type semiconductor close to the chip 120 and one end of the N-type semiconductor close to the chip 120.
  • the connector 145 and the chip 120 can be arranged in a close relationship, thereby improving the cooling efficiency of the thermoelectric module 140.
  • One end of the P-type semiconductor facing away from the chip 120 of the first heat-conducting unit is connected to one end of the N-type semiconductor facing away from the chip 120 of the second heat-conducting unit.
  • one end of the P-type semiconductor facing away from the chip 120 of the first heat-conducting unit and one end of the N-type semiconductor facing away from the chip 120 of the second heat-conducting unit can be connected by a connector 145.
  • other structures with conductive functions can also be used for connection, which is not specifically limited here.
  • thermoelectric module 140 One end of the N-type semiconductor facing away from the chip 120 of the first heat-conducting unit is the input end 141 of the thermoelectric module 140, and one end of the P-type semiconductor 143 of the second heat-conducting unit facing away from the chip 120 is the output end 142 of the thermoelectric module 140.
  • thermoelectric module 140 when there are multiple heat-conducting units, the heat-conducting units are connected in series, and only the end of the N-type semiconductor of the head heat-conducting unit facing away from the chip 120 is the input end 141 of the thermoelectric module 140, and the end of the P-type semiconductor 143 of the tail heat-conducting unit facing away from the chip 120 is the output end 142 of the thermoelectric module 140, thereby simplifying the structure of the thermoelectric module 140.
  • thermoelectric module 140 may include only one heat-conducting unit. Relatively speaking, the thermoelectric module 140 including multiple heat-conducting units has a larger area, and thus can bring about a better heat dissipation effect.
  • the P-type semiconductor 143 and the N-type semiconductor 144 can be made by hot pressing and sintering, and then connected in series to form a heat conduction unit through the connector 145.
  • the P-type semiconductor 143 and the N-type semiconductor 144 can also be made of thermoelectric thin films to make the thermoelectric module 140 thinner and lighter.
  • the volume of the thermoelectric module 140 can be controlled by increasing or decreasing the number of heat conducting units, ie, P-type semiconductors and N-type semiconductors, that is, the volume of the thermoelectric module 140 can be flexibly customized according to the size of the chip 120 .
  • the thermoelectric module 140 also includes a first metal conductor 146 and a second metal conductor 147, which are arranged at intervals along the circumference of the thermoelectric module 140, the first metal conductor 146 is electrically connected to the input end 141 of the thermoelectric module 140, and the second metal conductor 147 is electrically connected to the output end 142 of the thermoelectric module 140, the first metal conductor 146 has a plurality of first protrusions 146a, and each first protrusion 146a is electrically connected to each positive conductive column 131 in a one-to-one correspondence.
  • each positive conductive column 131 is provided with a welding pad on a side facing each first protrusion 146a, and the first protrusion 146a is connected to the welding pad to improve the connection stability.
  • the second metal conductor 147 has a plurality of second protrusions 147a, and the second protrusions 147a are electrically connected to the negative electrode conductive column 132.
  • each negative electrode conductive column 132 is provided with a pad on one side facing each second protrusion 147a, and the second protrusion 147a is connected to the pad to improve the connection stability.
  • the first metal conductor 146 and the second metal conductor 147 with a continuous structure are provided to facilitate the electrical connection of the thermoelectric module 140 with each positive electrode conductive column 131 and each negative electrode conductive column 132, so as to realize the parallel connection of each positive electrode conductive column 131 and each negative electrode conductive column 132, so as to reduce the resistance, increase the current flow of the thermoelectric module 140, and improve the thermoelectric effect of the thermoelectric module 140.
  • the first metal guide 146 includes a first conductive segment 146b and a second conductive segment 146c connected vertically, that is, the first metal guide 146 is in an L-shaped structure, and the first conductive segment 146b and the second conductive segment 146c are both provided with a plurality of first protrusions 146a, and the second metal guide 147 includes a vertical conductive segment 146b and a second conductive segment 146c.
  • the third conductive segment 147b and the fourth conductive segment 147c that is, the second metal conductive sheet 147, which are directly connected, are in an L-shaped structure.
  • the third conductive segment 147b and the fourth conductive segment 147c are both provided with a plurality of second protrusions 147a.
  • the first conductive segment 146b, the second conductive segment 146c, the third conductive segment 147b and the fourth conductive segment 147c are arranged along the circumference of the chip 120, that is, the first metal conductive sheet 146 and the second metal conductive sheet 147 are surrounded by a rectangle to match the shape of the chip 120, thereby making the structure of the chip assembly more compact.
  • the first metal conductive sheet 146 and the second metal conductive sheet 147 can also be flexibly designed according to the shape of the chip 120, for example, both are set to an arc structure.
  • thermoelectric module 140 There is a first gap between the second conductive segment 146 c and the third conductive segment 147 b , and there is a second gap between the fourth conductive segment 147 c and the first conductive segment 146 b , so as to prevent the output terminal 142 of the thermoelectric module 140 and the input terminal 141 of the thermoelectric module 140 from being short-circuited.
  • the chip assembly 120 further includes a first binding wire 150 and a second binding wire 160, one end of the first binding wire 150 is electrically connected to the positive electrode conductive column 131, the other end of the first binding wire 150 is electrically connected to the input end 141 of the thermoelectric module 140, one end of the second binding wire 160 is electrically connected to the negative electrode conductive column 132, and the other end of the second binding wire 160 is electrically connected to the output end 142 of the thermoelectric module 140. Since both the first binding wire 150 and the second binding wire 160 are bendable, connecting the thermoelectric module 140 and the conductive column 130 through the first binding wire 150 and the second binding wire 160 will be more flexible, which is convenient for the manufacture of the chip assembly.
  • the first binding wire 150 and the second binding wire 160 can be flexible connecting wires, which have good bendability and are easy to set up.
  • a third solder pad and a fourth solder pad are provided on a side of the thermoelectric module 140 facing away from the chip 120, the other end of the first binder 150 is electrically connected to the input end 141 of the thermoelectric module 140 through the third solder pad, and the other end of the second binder 160 is electrically connected to the output end 142 of the thermoelectric module 140 through the fourth solder pad. Since the solder pad area is large, the setting of the first binder 150 and the second binder 160 is convenient.
  • thermoelectric module 140 may be filled between the thermoelectric module 140 and the chip 120 for connection.
  • bonding structures may also be used for connection, which is not specifically limited here.
  • the chip assembly further includes an input pin 170 and an output pin 180, and the input end 141 of the thermoelectric module 140 is electrically connected to the positive electrode conductive column 131 through the input pin 170, and the input pin 170 is arranged in close contact with the positive electrode conductive column 131.
  • the cross-sectional area of 170 is relatively large, and the input pin 170 is arranged in close contact with the positive conductive column 131, which is conducive to improving the connection stability between the input end 141 of the thermoelectric module 140 and the positive conductive column 131.
  • the output end 142 of the thermoelectric module 140 is electrically connected to the negative conductive column 132 through the output pin 180, and the output pin 180 is arranged in close contact with the negative conductive column 132. Since the cross-sectional area of the output pin 180 is relatively large, and the output pin 180 is arranged in close contact with the negative conductive column 132, it is conducive to improving the connection stability between the output end 142 of the thermoelectric module 140 and the negative conductive column 132.
  • an adhesive 280 may be provided between the thermoelectric module 140 and the chip 120 for bonding.
  • the adhesive 280 has a filling function so as to fill the gap between the thermoelectric module 140 and the chip 120 to ensure the stability of the thermoelectric module 140 .
  • thermoelectric module 140 further includes a first metal conductor 146 and a second metal conductor 147
  • the chip assembly further includes an input pin 170 and an output pin 180, and the input end 141 of the thermoelectric module 140 is electrically connected to the first metal conductor 146 via the input pin 170, and the output end 142 of the thermoelectric module 140 is electrically connected to the second metal conductor 147 via the output pin 180, so as to facilitate the arrangement of the first metal conductor 146 and the second metal conductor 147
  • the chip assembly further includes a first binding wire 150 and a second binding wire 160, and the input end 141 of the thermoelectric module 140 is electrically connected to the first metal conductor 146 via the first binding wire 150, and the output end 142 of the thermoelectric module 140 is electrically connected to the second metal conductor 147 via the second binding wire 160, so as to facilitate the arrangement of the first metal conductor 146 and the second metal conductor 147.
  • the chip assembly further includes a first packaging layer 190 and a second packaging layer 210, the wiring layer 110, the first packaging layer 190 and the second packaging layer 210 are stacked in sequence, the first packaging layer 190 is provided with a chip 120 and at least two conductive pillars 130, the first packaging layer 190 can not only play a role in protecting the chip 120 and the conductive pillars 130, but also can fix the chip 120 and the conductive pillars 130.
  • the second packaging layer 210 is provided with a thermoelectric module 140, the second packaging layer 210 can not only play a role in protecting the thermoelectric module 140, but also can fix the thermoelectric module 140.
  • first packaging layer 190 and the second packaging layer 210 can both be made of polyimide material, and of course can also be made of other materials, which is not specifically limited here.
  • first packaging layer 190 and the second packaging layer 210 can also be made of different materials.
  • the chip assembly further includes a metal bump 240 and a solder ball 250.
  • the metal bump 240 is disposed on a side of the wiring layer 110 facing away from the chip 120.
  • the metal bump 240 is connected between the wiring layer 110 and the solder ball 250.
  • the solder ball 250 is used to directly connect to a circuit board of an electronic device, thereby avoiding the need for an additional substrate for the chip assembly to connect to the circuit board of the electronic device.
  • the embodiments of the present application also disclose an electronic device, which includes the chip assembly of any of the above embodiments.
  • the embodiment of the present application further discloses a method for preparing a chip assembly, which is applied to the chip assembly described in any of the above embodiments.
  • the method for preparing the chip assembly includes:
  • the at least two conductive pillars 130 in this step include a positive conductive pillar 131 and a negative conductive pillar 132.
  • the chip 120 has a first pad 220 on one side facing the wiring layer 110, and the wiring layer 110 has a second pad on one side facing the chip 120, and the first pad 220 and the second pad are connected via a micro bump 230, so that the wiring layer 110 is connected to the chip 120.
  • the chip 120 in this step is a single chip after cutting.
  • the chip 120 is arranged on the wiring layer 110 by bonding.
  • the number of chips 120 can be multiple, but only one chip 120 is arranged in the accommodating space formed by at least two conductive pillars 130 to form a chip component, and the number of chip components can be multiple.
  • a first packaging layer 190 is arranged on the wiring layer 110, and the chip 120 and at least two conductive pillars 130 are located in the first packaging layer 190 to protect the chip 120 and at least two conductive pillars 130, and at the same time fix the chip 120 and each conductive pillar 130; then a thinning process is performed to expose the conductive pillars 130, and at this time, the silicon is exposed at one end of the chip 120 away from the wiring layer 110, and when the chip 120 is working, the end exposed to the silicon is the heat dissipation end of the chip 120.
  • thermoelectric module 140 disposing the thermoelectric module 140 on the side of the chip 120 away from the wiring layer 110, and The cold end 148 of the module 140 is disposed on a side of the chip 120 away from the wiring layer 110 , and at least two conductive pillars 130 are electrically connected to the thermoelectric module 140 .
  • the input end 141 of the thermoelectric module 140 may be electrically connected to the positive conductive column 131 through a first binding wire 150, and the output end 142 of the thermoelectric module 140 may be electrically connected to the negative conductive column 132 through a second binding wire 160.
  • the input end 141 of the thermoelectric module 140 may be electrically connected to the positive conductive column 131 through an input pin 170, and the output end 142 of the thermoelectric module 140 may be electrically connected to the negative conductive column 132 through an output pin 180.
  • thermoelectric module 140 when the thermoelectric module 140 is disposed on the side of the chip 120 away from the wiring layer 110 , a second packaging layer 210 is disposed on the first packaging layer 190 , and the thermoelectric module 140 is disposed in the second packaging layer 210 to protect the thermoelectric module 140 and fix the thermoelectric module 140 at the same time.
  • laser may be used to remove the glass carrier 101, thereby obtaining a reconstructed wafer, also called an artificial wafer.
  • step S400 the following steps are further included:
  • solder balls 250 formed in this step are used to directly connect to the circuit board of the electronic device, so that the chip assembly does not need to be provided with an additional substrate.
  • thermoelectric module 140 is disposed on the side of the chip 120 away from the wiring layer 110 in a stacking manner.
  • the wiring layer 110 is electrically connected to the thermoelectric module 140 through at least two conductive pillars 130, thereby transmitting current to the thermoelectric module 140.
  • a temperature gradient appears at both ends of the thermoelectric module 140, thereby forming a cold end 148 and a hot end 149, wherein the cold end 148 of the thermoelectric module 140 is disposed opposite to the chip 120, and the heat generated by the chip 120 when working will be absorbed by the cold end 148 of the thermoelectric module 140, so as to achieve the purpose of cooling the chip 120.
  • the embodiment of the present application uses a bonding process to dissipate the thermoelectric module 140 inside the chip assembly.
  • the thermoelectric module 140 is closer to the chip 120. 120 is closer, and its heat dissipation effect will be greatly improved; and, compared with structures such as fans, the space occupied by the thermoelectric module 140 is smaller, which is conducive to reducing the volume of the chip assembly. Therefore, the embodiment of the present application can solve the problem of poor heat dissipation effect of the current chip assembly.
  • the embodiment of the present application adopts a wafer-level packaging method to package the thermoelectric module 140 in the package body, so that the final chip assembly has the characteristics of being light, thin, short and small.
  • the electronic device disclosed in the embodiments of the present application may be a smart phone, a tablet computer, an e-book reader, a wearable device (such as a smart watch), an electronic game console, or other electronic device.
  • the embodiments of the present application do not impose any specific restrictions on the type of electronic device.

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Abstract

本申请公开了一种芯片组件、电子设备以及芯片组件的制备方法，涉及通信设备技术领域。该芯片组件包括布线层、芯片、至少两个导电柱和热电模块，所述芯片与所述布线层叠置，所述热电模块具有相背离的冷端和热端，所述热电模块的冷端设置于所述芯片背离所述布线层的一侧，所述至少两个导电柱设置于所述布线层，所述至少两个导电柱与所述热电模块电连接。

Description

芯片组件、电子设备以及芯片组件的制备方法
交叉引用
本发明要求在2022年10月28日提交中国专利局、申请号为202211336686.2、发明名称为“芯片组件、电子设备以及芯片组件的制备方法”的中国专利申请的优先权，该申请的全部内容通过引用结合在本发明中。
技术领域
本申请属于通信设备技术领域，具体涉及一种芯片组件和电子设备。
背景技术
随着电子设备的不断小型化，以及集成电路的快速发展，目前芯片处理能力得到了很大的提升，然而如何在有限的空间内，改善芯片的散热效果成为亟待解决的一个问题。
目前大多采用外部涂抹散热材料、加装散热片或额外增加散热风扇来解决芯片发热的问题，但上述几种解决方式均设置于芯片组件的外部，其散热效果较差。
发明内容
本申请实施例的目的是提供一种芯片组件、电子设备和芯片组件的制备方法，能够解决目前芯片组件的散热效果较差的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种芯片组件，包括布线层、芯片、至少两个导电柱和热电模块，所述芯片与所述布线层叠置，所述热电模块具有相背离的冷端和热端，所述热电模块的冷端设置于所述芯片背离所述布线层的一侧，所述至少两个导电柱设置于所述布线层，所述至少两个导电柱与所述热电模块电连接。
第二方面，本申请实施例还提供了一种电子设备，包括上述的芯片组件。
第三方面，本申请还提供了一种芯片组件的制备方法，应用于上述的芯片组件，包括：将所述布线层键合于玻璃载体，并将所述至少两个导电柱设置于所述布线层；将所述芯片设置于所述布线层，所述芯片位于所述至少两个导电柱形成的容纳空间内；将所述热电模块设置于所述芯片背离所述布线层的一侧，且所述热电模块的冷端设置于所述芯片背离所述布线层的一侧，所述至少两个导电柱与所述热电模块电连接；将所述玻璃载体解除键合。
在本申请实施例中，采用堆叠方式将热电模块设置于芯片背离布线层的一侧，布线层通过至少两个导电柱与热电模块电连接，从而对热电模块输送电流，此时热电模块的两端出现温度梯度，从而形成冷端和热端，其中热电模块的冷端与芯片相对设置，芯片工作时产生的热量将被热电模块的冷端吸收，以实现芯片降温的目的。由此可知，相对于在芯片组件的封装体之外涂抹散热材料、加装散热片或额外增加散热风扇等措施，本申请实施例中的热电模块属于芯片组件的一部分，其设置于芯片组件的内部，因此热电模块距离芯片较近，其散热效果将大大提高。因此，本申请实施例能够解决目前芯片组件的散热效果较差的问题。
附图说明
图1为本申请实施例公开的芯片组件的结构剖视图；
图2为本申请实施例公开的芯片组件的部分结构示意图；
图3至图4为本申请实施例公开的芯片组件处于不同视角下的结构示意图；
图5至图6为本申请另一实施例公开的芯片组件处于不同视角下的结构示意图；
图7为本申请实施例公开的热电模组的结构示意图；
图8为本申请实施例公开的芯片组件的封装结构示意图；
图9为图8所示结构的A处的局部放大图；
图10至图17为本申请实施例公开的芯片组件处于不同封装状态下的结构示意图。
附图标记说明：
101-玻璃载体、110-布线层、120-芯片、130-导电柱、131-正极导线柱、
132-负极导线柱、140-热电模块、141-输入端、142-输出端、143-P型半导体、144-N型半导体、145-连接件、146-第一金属导片、146a-第一凸起部、146b-第一导电段、146c-第二导电段、147-第二金属导片、147a-第二凸起部、147b-第三导电段、147c-第四导电段、148-冷端、149-热端、150-第一绑线、160-第二绑线、170-输入管脚、180-输出管脚、190-第一封装层、210-第二封装层、220-第一焊盘、230微凸块、240-金属凸块、250-焊球、260-银胶、270-粘接件。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的芯片组件、电子设备以及芯片组件的制备方法进行详细地说明。
参考图1至图9，本申请实施例公开一种芯片组件，可选地，该芯片组件可以为集成电路，当然也可以为其它芯片组件，这里不作具体限制。该芯片组件包括布线层110、芯片120、至少两个导电柱130和热电模块140，芯 片120与布线层110叠置，芯片120与布线层110中的导线电导通，布线层110用于为芯片120、热电模块140等结构供电。热电模块140具有相背离的冷端148和热端149，热电模块140的冷端148设置于芯片120背离布线层110的一侧，即热电模块140的冷端148与芯片120相对设置，热电模块140的热端149则远离芯片120，当芯片120工作产生热量时，热电模块140对芯片120进行降温。热电模块140具有体积小、重量轻、无活动固件以及无污染等特点。可选地，芯片120朝向布线层110的一面具有第一焊盘220，布线层110朝向芯片120的一面具有第二焊盘，第一焊盘220和第二焊盘之间通过微凸块230连接。至少两个导电柱130设置于布线层110，至少两个导电柱130与热电模块140电连接，导电柱130用于为热电模块140输送电流，以使热电模块140产生热电效应，从而为芯片120降温。可选地，导电柱130可以为铜柱，当然也可以为其它导电结构，这里不作具体限制。
在本申请实施例中，采用堆叠方式将热电模块140设置于芯片120背离布线层110的一侧，布线层110通过至少两个导电柱130与热电模块140电连接，从而对热电模块140输送电流，此时热电模块140的两端出现温度梯度，从而形成冷端148和热端149，其中热电模块140的冷端148与芯片120相对设置，芯片120工作时产生的热量将被热电模块140的冷端148吸收，以实现芯片120降温的目的。由此可知，相对于在芯片组件的封装体之外涂抹散热材料、加装散热片或额外增加散热风扇等措施，本申请实施例中的热电模块140属于芯片组件的一部分，其设置于芯片组件的内部，因此热电模块140距离芯片120较近，其散热效果将大大提高；并且，热电模块140相对于风扇等结构，其占据的空间较小，有利于减小芯片组件的体积。因此，本申请实施例能够解决目前芯片组件的散热效果较差的问题。另外，本申请实施例采用热电模块140对芯片120进行降温，其具有使用寿命较长，且易于控制的特点。
一种可选的实施例中，热电模块140背离芯片120的一侧具有输入端141和输出端142，至少两个导电柱130沿芯片120的周向间隔布置，相比于导 电柱无规则排布的方式，此种设置方式更有利于热电模块的结构设计。至少两个导电柱130包括正极导电柱131和负极导电柱132，正极导电柱131的一端和负极导电柱132的一端均与布线层110电连接，正极导电柱131的另一端与热电模块140的输入端141电连接，负极导电柱132的另一端与热电模块140的输出端142电连接，以使布线层110中的电流通过正极导电柱131自热电模块140的输入端141流入，然后自热电模块140的输出端流出并经过负极导电柱132流入布线层110。可选地，各正极导电柱131和各负极导电柱132可以分别采用并联的设置方式，从而减小电阻，增大热电模块140的电流流通量，以提高电热模块140的热电效率。
进一步可选的实施例中，热电模块140包括至少两个导热单元，至少两个导热单元包括第一导热单元和第二导热单元，第一导热单元和第二导热单元均包括P型半导体143、N型半导体144和连接件145，P型半导体143和N型半导体144间隔地设置于布线层110，连接件145连接于P型半导体143与N型半导体144之间，连接件145位于P型半导体和N型半导体靠近芯片120的一侧，也就是说，连接件145连接于P型半导体靠近芯片120的一端和N型半导体靠近芯片120的一端。可选地，连接件145与芯片120可以贴合设置，从而提高热电模块140的降温效率。第一导热单元的P型半导体背离芯片120的一端与第二导热单元的N型半导体背离芯片120的一端相连，可选地，第一导热单元的P型半导体背离芯片120的一端与第二导热单元的N型半导体背离芯片120的一端可以采用连接件145连接，当然也可以采用其它具有导电功能的结构进行连接，这里不作具体限制。第一导热单元的N型半导体背离芯片120的一端为热电模块140的输入端141，第二导热单元的P型半导体143背离芯片120的一端为热电模块140的输出端142。需要说明的是，当导热单元的数量为多个时，各导热单元之间串联，仅首部的导热单元的N型半导体背离芯片120的一端为热电模块140的输入端141，尾部的导热单元的P型半导体143背离芯片120的一端为热电模块140的输出端142，从而简化热电模块140的结构。
当然，在其他实施例中，热电模块140可以仅包括一个导热单元，相对而言，包括多个导热单元的热电模块具140有更大的面积，因此可以带来更好的散热效果。
可选地，P型半导体143和N型半导体144可以通过热压烧结制成，然后通过连接件145串联以形成导热单元。另一实施例中，P型半导体143和N型半导体144也可以通过热电薄膜制成，以使热电模块140的体积更加轻薄。
另外，需要说明的是，热电模块140的体积可以通过增加或减少导热单元即P型半导体和N型半导体的数量进行控制，即根据芯片120的尺寸灵活定制热电模块140的体积。
参考图7，另一可选的实施例中，热电模块140还包括第一金属导片146和第二金属导片147，第一金属导片146和第二金属导片147沿热电模块140的周向间隔设置，第一金属导片146与热电模块140的输入端141电连接，第二金属导片147与热电模块140的输出端142电连接，第一金属导片146具有多个第一凸起部146a，各第一凸起部146a与各正极导电柱131一一对应电连接，可选地，各正极导电柱131朝向各第一凸起部146a的一面设有焊盘，第一凸起部146a与焊盘连接，以提高连接稳定性。第二金属导片147具有多个第二凸起部147a，第二凸起部147a与负极导电柱132电连接，可选地，各负极导电柱132朝向各第二凸起部147a的一面设有焊盘，第二凸起部147a与焊盘连接，以提高连接稳定性。本实施例中通过设置结构连续的第一金属导片146和第二金属导片147，以便于热电模块140与各正极导电柱131和各负极导电柱132电连接，从而实现各正极导电柱131并联以及各负极导电柱132并联，以减小电阻，增大热电模块140的电流流通量，提高热电模块140的热电效应。
进一步可选的实施例中，第一金属导片146包括垂直相连的第一导电段146b和第二导电段146c，即第一金属导片146呈L形结构，第一导电段146b和第二导电段146c均设有多个第一凸起部146a，第二金属导片147包括垂 直相连的第三导电段147b和第四导电段147c，即第二金属导片147呈L形结构，第三导电段147b和第四导电段147c均设有多个第二凸起部147a，第一导电段146b、第二导电段146c、第三导电段147b和第四导电段147c沿芯片120的周向排布，即第一金属导片146和第二金属导片147围成矩形，以便于与芯片120的形状相适配，从而使得芯片组件的结构更加紧凑。当然实际制作过程中，也可以根据芯片120的形状对第一金属导片146和第二金属导片147进行灵活设计，例如将两者设置成弧形结构。第二导电段146c和第三导电段147b之间具有第一间隙，第四导电段147c和第一导电段146b之间具有第二间隙，以避免热电模块140的输出端142与热电模块140的输入端141之间被短路。
参考图3至图4，一种可选的实施例中，芯片组件120还包括第一绑线150和第二绑线160，第一绑线150的一端与正极导电柱131电连接，第一绑线150的另一端与热电模块140的输入端141电连接，第二绑线160的一端与负极导电柱132电连接，第二绑线160的另一端与热电模块140的输出端142电连接。由于第一绑线150和第二绑线160均可弯曲，故通过第一绑线150和第二绑线160连接热电模块140与导电柱130将更加灵活，便于芯片组件的制作。可选地，第一绑线150和第二绑线160可以为柔性连接线，其弯折性较好，便于设置。
可选地，热电模块140背离芯片120的一面设有第三焊盘和第四焊盘，第一绑线150的另一端通过第三焊盘与热电模块140的输入端141电连接，第二绑线160的另一端通过第四焊盘与热电模块140的输出端142电连接，由于焊盘面积较大，便于第一绑线150和第二绑线160的设置。
可选地，热电模块140与芯片120之间可以填充银胶270进行连接，当然也可以采用其它粘接结构进行连接，这里不作具体限制。
参考图5至图6，另一可选的实施例中，芯片组件还包括输入管脚170和输出管脚180，热电模块140的输入端141通过输入管脚170与正极导电柱131电连接，且输入管脚170与正极导电柱131贴合设置，由于输入管脚 170的横截面积较大，且输入管脚170与正极导电柱131之间贴合设置，有利于提升热电模块140的输入端141与正极导电柱131之间的连接稳定性。热电模块140的输出端142通过输出管脚180与负极导电柱132电连接，且输出管脚180与负极导电柱132贴合设置，由于输出管脚180的横截面积较大，且输出管脚180与负极导电柱132之间贴合设置，有利于提升热电模块140的输出端142与负极导电柱132之间的连接稳定性。
可选地，热电模块140与芯片120之间可以设置粘接件280进行粘接，与此同时该粘接件280具有填充的作用，以便于填充热电模块140与芯片120的之间间隙，确保热电模块140的稳定性。
在热电模块140还包括第一金属导片146和第二金属导片147的实施例中，可选地，芯片组件还包括输入管脚170和输出管脚180，热电模块140的输入端141通过输入管脚170与第一金属导片146电连接，热电模块140的输出端142通过输出管脚180与第二金属导片147电连接，以便于第一金属导片146和第二金属导片147的设置；另一实施例中，芯片组件还包括第一绑线150和第二绑线160，热电模块140的输入端141通过第一绑线150与第一金属导片146电连接，热电模块140的输出端142通过第二绑线160与第二金属导片147电连接，以便于第一金属导片146和第二金属导片147的设置。
再一可选的实施例中，芯片组件还包括第一封装层190和第二封装层210，布线层110、第一封装层190和第二封装层210依次层叠设置，第一封装层190中设置有芯片120和至少两个导电柱130，第一封装层190不仅可以起到保护芯片120和导电柱130的作用，而且可以对芯片120和导电柱130进行固定。第二封装层210中设置有热电模块140，第二封装层210不仅可以起到保护热电模块140的作用，而且可以对热电模块140进行固定。可选地，第一封装层190和第二封装层210可以均由聚酰亚胺材料制成，当然也可以由其他材料制成，这里不作具体限制。当然，第一封装层190和第二封装层210也可以由不同的材料制成。
可选地，芯片组件还包括金属凸块240和焊球250，金属凸块240设置于布线层110背离芯片120的一面，金属凸块240连接于布线层110与焊球250之间，焊球250用于与电子设备的电路板直接连接，从而避免芯片组件额外设置基板与电子设备的电路板连接。
基于本申请实施例公开的芯片组件，本申请实施例还公开了一种电子设备，其包括上述任意实施例的芯片组件。
参考图10至图17，基于本申请实施例公开的芯片组件，本申请实施例还公开了一种芯片组件的制备方法，其应用于上述任一实施例所述的芯片组件，该芯片组件的制备方法包括：
S100、将布线层110键合于玻璃载体101，并将至少两个导电柱130设置于布线层110。
该步骤中的至少两个导电柱130包括正极导电柱131和负极导电柱132。可选地，芯片120朝向布线层110的一面具有第一焊盘220，布线层110朝向芯片120的一面具有第二焊盘，第一焊盘220和第二焊盘之间通过微凸块230连接，以使布线层110与芯片120连接。
S200、将芯片120设置于布线层110，芯片120位于至少两个导电柱130形成的容纳空间内。
本步骤中的芯片120为切割后的单个芯片，芯片120通过键合的方式设置于布线层110，芯片120的数量可以为多个，但至少两个导电柱130形成的容纳空间内仅设置一个芯片120，以形成一个芯片组件，而芯片组件的数量可以为多个。
可选地，当芯片120设置于布线层110后，在布线层110设置第一封装层190，芯片120和至少两个导电柱130位于第一封装层190中，以保护芯片120和至少两个导电柱130，同时对芯片120和各导电柱130进行固定；然后进行减薄处理，以使导电柱130外露，并且此时芯片120背离布线层110的一端露硅，当芯片120工作时，该露硅的一端为芯片120的散热端。
S300、将热电模块140设置于芯片120背离布线层110的一侧，且热电 模块140的冷端148设置于芯片120背离布线层110的一侧，至少两个导电柱130与热电模块140电连接。
可选地，热电模块140的输入端141可以通过第一绑线150与正极导电柱131电连接，热电模块140的输出端142可以通过第二绑线160与负极导电柱132电连接。其它实施例中，热电模块140的输入端141可以通过输入管脚170与正极导电柱131电连接，热电模块140的输出端142可以通过输出管脚180与负极导电柱132电连接。
可选地，当热电模块140设置于芯片120背离布线层110的一侧时，在第一封装层190上设置第二封装层210，热电模块140设置于第二封装层210中，以保护热电模块140，同时对热电模块140进行固定。
S400、将玻璃载体101解除键合。
该步骤中可以采用激光解除玻璃载体101，从而得到重构晶圆，也称为人造晶圆。
可选地，步骤S400之后还包括：
S500、在重构晶圆的布线层110的底部制作金属凸块240，并在金属凸块240的底部植球，以形成焊球250，最后进行切割工艺，以得到封装单体，即上述任一实施例中的芯片组件。
该步骤中形成的焊球250用于与电子设备的电路板直接连接，从而使芯片组件无需额外设置基板。
在本申请实施例中，采用堆叠方式将热电模块140设置于芯片120背离布线层110的一侧，布线层110通过至少两个导电柱130与热电模块140电连接，从而对热电模块140输送电流，此时热电模块140的两端出现温度梯度，从而形成冷端148和热端149，其中热电模块140的冷端148与芯片120相对设置，芯片120工作时产生的热量将被热电模块140的冷端148吸收，以实现芯片120降温的目的。由此可知，相对于在芯片组件的封装体之外涂抹散热材料、加装散热片或额外增加散热风扇等措施，本申请实施例采用键合工艺将热电模块140设置于芯片组件的内部，此时热电模块140距离芯片 120较近，其散热效果将大大提高；并且，热电模块140相对于风扇等结构，其占据的空间较小，有利于减小芯片组件的体积。因此，本申请实施例能够解决目前芯片组件的散热效果较差的问题。另外，本申请实施例采用晶圆级封装方式，将热电模块140封装在封装体内，以使最终形成的芯片组件具有轻、薄、短、小的特点。
本申请实施例公开的电子设备可以是智能手机、平板电脑、电子书阅读器、可穿戴设备(例如智能手表)、电子游戏机等电子设备，本申请实施例对电子设备的种类不作具体限制。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (10)

  1. 一种芯片组件，包括布线层、芯片、至少两个导电柱和热电模块，所述芯片与所述布线层叠置，所述热电模块具有相背离的冷端和热端，所述热电模块的冷端设置于所述芯片背离所述布线层的一侧，所述至少两个导电柱设置于所述布线层，所述至少两个导电柱与所述热电模块电连接。
  2. 根据权利要求1所述的芯片组件，其中，所述热电模块背离所述芯片的一侧具有输入端和输出端，所述至少两个导电柱沿所述芯片的周向间隔布置，所述至少两个导电柱包括正极导电柱和负极导电柱，所述正极导电柱的一端和所述负极导电柱的一端均与所述布线层电连接，所述正极导电柱的另一端与所述热电模块的输入端电连接，所述负极导电柱的另一端与所述热电模块的输出端电连接。
  3. 根据权利要求2所述的芯片组件，其中，所述热电模块包括至少两个导热单元，所述至少两个导热单元包括第一导热单元和第二导热单元，所述第一导热单元和所述第二导热单元均包括P型半导体、N型半导体和连接件，所述P型半导体和所述N型半导体间隔地设置于所述布线层，所述连接件连接于所述P型半导体与所述N型半导体之间，所述第一导热单元的所述P型半导体背离所述芯片的一端与所述第二导热单元的所述N型半导体背离所述芯片的一端相连，所述第一导热单元的所述N型半导体背离所述芯片的一端为所述热电模块的输入端，所述第二导热单元的所述P型半导体背离所述芯片的一端为所述热电模块的输出端。
  4. 根据权利要求2所述的芯片组件，其中，所述热电模块还包括第一金属导片和第二金属导片，所述第一金属导片和所述第二金属导片沿所述热电模块的周向间隔设置，所述第一金属导片与所述热电模块的输入端电连接，所述第二金属导片与所述热电模块的输出端电连接，所述第一金属导片具有多个第一凸起部，各所述第一凸起部与各所述正极导电柱一一对应电连接，所述第二金属导片具有多个第二凸起部，所述第二凸起部与所述负极导电柱 电连接。
  5. 根据权利要求4所述的芯片组件，其中，所述第一金属导片包括垂直相连的第一导电段和第二导电段，所述第一导电段和所述第二导电段均设有多个所述第一凸起部，所述第二金属导片包括垂直相连的第三导电段和第四导电段，所述第三导电段和所述第四导电段均设有多个所述第二凸起部，所述第一导电段、所述第二导电段、所述第三导电段和所述第四导电段沿所述芯片的周向排布，所述第二导电段和所述第三导电段之间具有第一间隙，所述第四导电段和所述第一导电段之间具有第二间隙。
  6. 根据权利要求2所述的芯片组件，其中，所述芯片组件还包括第一绑线和第二绑线，所述第一绑线的一端与所述正极导电柱电连接，所述第一绑线的另一端与所述热电模块的输入端电连接，所述第二绑线的一端与所述负极导电柱电连接，所述第二绑线的另一端与所述热电模块的输出端电连接。
  7. 根据权利要求2所述的芯片组件，其中，所述芯片组件还包括输入管脚和输出管脚，所述热电模块的输入端通过所述输入管脚与所述正极导电柱电连接，且所述输入管脚与所述正极导电柱贴合设置，所述热电模块的输出端通过所述输出管脚与所述负极导电柱电连接，且所述输出管脚与所述负极导电柱贴合设置。
  8. 根据权利要求1所述的芯片组件，其中，所述芯片组件还包括第一封装层和第二封装层，所述布线层、所述第一封装层和所述第二封装层依次层叠设置，所述第一封装层中设置有所述芯片和所述至少两个导电柱，所述第二封装层中设置有所述热电模块。
  9. 一种电子设备，包括权利要求1至8中任一项所述的芯片组件。
  10. 一种芯片组件的制备方法，应用于权利要求1至8任一项所述的芯片组件，包括：
    将所述布线层键合于玻璃载体，并将所述至少两个导电柱设置于所述布线层；
    将所述芯片设置于所述布线层，所述芯片位于所述至少两个导电柱形成 的容纳空间内；
    将所述热电模块设置于所述芯片背离所述布线层的一侧，且所述热电模块的冷端设置于所述芯片背离所述布线层的一侧，所述至少两个导电柱与所述热电模块电连接；
    将所述玻璃载体解除键合。
PCT/CN2023/126689 2022-10-28 2023-10-26 芯片组件、电子设备以及芯片组件的制备方法 Ceased WO2024088332A1 (zh)

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