WO2024087192A1 - 显示模组及其制备方法、显示装置 - Google Patents

显示模组及其制备方法、显示装置 Download PDF

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Publication number
WO2024087192A1
WO2024087192A1 PCT/CN2022/128348 CN2022128348W WO2024087192A1 WO 2024087192 A1 WO2024087192 A1 WO 2024087192A1 CN 2022128348 W CN2022128348 W CN 2022128348W WO 2024087192 A1 WO2024087192 A1 WO 2024087192A1
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WIPO (PCT)
Prior art keywords
routing
target portion
orthographic projection
substrate
base substrate
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PCT/CN2022/128348
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English (en)
French (fr)
Inventor
伏宝泽
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京东方科技集团股份有限公司
南京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 南京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/128348 priority Critical patent/WO2024087192A1/zh
Publication of WO2024087192A1 publication Critical patent/WO2024087192A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present application relates to the field of display technology, and in particular to a display module and a preparation method thereof, and a display device.
  • the present application provides a display module and a manufacturing method thereof, and a display device, and the technical solution is as follows:
  • a display module comprising:
  • a base substrate having a display area and a fan-out area located at one side of the display area;
  • a first routing layer located at one side of the substrate and in the fan-out area, the first routing layer comprising a first routing line, a first target portion of the first routing line extending along a first direction;
  • a first insulating layer located on a side of the first wiring layer away from the substrate;
  • a second routing layer is located on a side of the first insulating layer away from the substrate and located in the fan-out area, the second routing layer includes a second routing corresponding to the first routing, and a second target portion of the second routing extends along the first direction;
  • a second insulating layer located on a side of the second wiring layer away from the substrate;
  • the third routing layer located on a side of the second insulating layer away from the substrate and located in the fan-out region, the third routing layer comprising a third routing corresponding to the second routing, and a third target portion of the third routing extending along the first direction;
  • the orthographic projection of the first target portion on the substrate and the orthographic projection of the second target portion on the substrate have a first overlapping region formed by partial overlap, and the first overlapping region extends along the first direction;
  • One of the first routing and the second routing is a first target routing, and the other routing is a second target routing; an orthographic projection of a target portion of the first target routing on the substrate and an orthographic projection of the third target portion on the substrate have a second overlapping area formed by partial overlap, and the second overlapping area extends along the first direction; the target portion of one of the second target routing and the third routing is located within the orthographic projection of the target portion of the other routing on the substrate.
  • the first target routing is the first routing
  • the second target routing is the second routing
  • the first routing line includes a first boundary slope and a second boundary slope extending along the first direction
  • the second routing line includes a third boundary slope and a fourth boundary slope extending along the first direction
  • the orthographic projection of the third boundary slope surface on the substrate, the orthographic projection of the first boundary slope surface on the substrate, the orthographic projection of the fourth boundary slope surface on the substrate, and the orthographic projection of the second boundary slope surface on the substrate are arranged in sequence along a second direction, and the second direction intersects with the first direction;
  • the first boundary slope surface and the second boundary slope surface both intersect with the bearing surface of the substrate, and the extended surfaces of the third boundary slope surface and the fourth boundary slope surface intersect with the bearing surface of the substrate.
  • an angle between an extension surface of the third boundary slope surface and a support surface of the substrate, and an angle between an extension surface of the fourth boundary slope surface and a support surface of the substrate are both in a range of 40 degrees to 50 degrees.
  • the second target portion includes a first climbing portion located between the third boundary slope surface and the fourth boundary slope surface, and an orthographic projection of the first climbing portion on the substrate at least partially overlaps with an orthographic projection of the first boundary slope surface on the substrate.
  • the third target portion includes: a second climbing portion, a third climbing portion and a fourth climbing portion;
  • the orthographic projection of the second climbing portion on the substrate at least partially overlaps with the orthographic projection of the third boundary slope surface on the substrate
  • the orthographic projection of the third climbing portion on the substrate at least partially overlaps with the orthographic projection of the first boundary slope surface on the substrate
  • the orthographic projection of the fourth climbing portion on the substrate at least partially overlaps with the orthographic projection of the fourth boundary slope surface on the substrate.
  • the orthographic projection of the first target portion on the substrate has a first central axis extending along the first direction
  • the orthographic projection of the second target portion on the substrate has a second central axis extending along the first direction
  • the orthographic projection of the third target portion on the substrate has a third central axis extending along the first direction
  • the first central axis and the second central axis are parallel and spaced apart, and the second central axis and the third central axis overlap.
  • a ratio of a minimum distance between the first central axis and the second central axis to a length of an orthographic projection of the first target portion on the substrate along the second direction ranges from 1/8 to 3/4.
  • a minimum distance between the first central axis and the second central axis ranges from 0.5 microns to 1.5 microns.
  • the minimum distance between the first central axis and the second central axis is 1 micron.
  • the length of the orthographic projection of the first target portion on the substrate along the second direction, the length of the orthographic projection of the second target portion on the substrate along the second direction, and the length of the orthographic projection of the third target portion on the substrate along the second direction are all in the range of 2 microns to 4 microns.
  • the first routing layer includes multiple first routing lines
  • the second routing layer includes multiple second routing lines corresponding one-to-one to the multiple first routing lines
  • the third routing layer includes multiple third routing lines corresponding one-to-one to the multiple second routing lines.
  • the first target portions of the plurality of first routing lines are arranged at equal intervals along the second direction
  • the second target portions of the plurality of second routing lines are arranged at equal intervals along the second direction
  • the third target portions of the plurality of third routing lines are arranged at equal intervals along the second direction.
  • the plurality of first routing lines include at least a first first routing line and a second first routing line
  • the plurality of second routing lines include at least a first second routing line and a second second routing line
  • the first second routing line corresponds to the first first routing line
  • the second second routing line corresponds to the second first routing line
  • the distance between the first central axis of the first first line and the second central axis of the first second line is equal to the distance between the first central axis of the second first line and the second central axis of the second second line.
  • the display module includes a touch panel and a display panel;
  • the touch panel includes at least a plurality of emitting electrode wirings, and the display panel includes at least a plurality of gate lines and a plurality of data lines;
  • the first wiring is the emitter electrode wiring
  • the second wiring is the gate line
  • the third wiring is the data line.
  • a method for preparing a display module comprising:
  • the substrate substrate having a display area and a fan-out area located at one side of the display area;
  • the second wiring layer is located in the fan-out area, the second wiring layer includes a second wiring corresponding to the first wiring, and a second target portion of the second wiring extends along the first direction;
  • the third wiring layer includes a third wiring corresponding to the second wiring, and a third target portion of the third wiring extends along the first direction;
  • the orthographic projection of the first target portion on the substrate and the orthographic projection of the second target portion on the substrate have a first overlapping region formed by partial overlap, and the first overlapping region extends along the first direction;
  • One of the first and second routings is a first target routing, and the other routing is a second target routing; an orthographic projection of a target portion of the first target routing on the substrate and an orthographic projection of the third target portion on the substrate have a second overlapping area formed by partial overlap, and the second overlapping area extends along the first direction; the target portion of one of the second and third routings is located within the orthographic projection of the target portion of the other routing on the substrate.
  • the first mask has a first opening, and the first opening is used to form the first routing line;
  • the second mask has a second opening, and the second opening is used to form the second routing line;
  • the third mask has a third opening, and the third opening is used for a third routing line;
  • the orthographic projection of the first opening on the base substrate partially overlaps with the orthographic projection of the second opening on the base substrate; the orthographic projection of the first opening on the base substrate partially overlaps with the orthographic projection of the third opening on the base substrate;
  • the orthographic projection of one of the second opening and the third opening on the base substrate is located within the orthographic projection of the other opening on the base substrate.
  • the display module includes a touch panel and a display panel;
  • the touch panel includes at least a plurality of emitting electrode wirings, and the display panel includes at least a plurality of gate lines and a plurality of data lines;
  • the first wiring is the emitter electrode wiring
  • the second wiring is the gate line
  • the third wiring is the data line.
  • a display device comprising: a power supply component and the display module as described in the above aspect;
  • the power supply component is used to supply power to the display module.
  • FIG1 is a partial top view of a display module in the related art
  • FIG2 is a cross-sectional SEM image of the display module shown in FIG1 along the AA direction;
  • FIG3 is a cross-sectional SEM image of the display module shown in FIG1 along the BB direction;
  • FIG. 4 is a schematic diagram of photoresist exposure and development when forming a second wiring layer in the related art
  • FIG5 is a schematic diagram of etching when forming a second wiring layer in the related art
  • FIG. 6 is a schematic diagram of photoresist exposure and development when forming a third wiring layer in the related art
  • FIG7 is a schematic diagram of etching when forming a third wiring layer in the related art.
  • FIG8 is a schematic diagram of the structure of a display module provided in an embodiment of the present application.
  • FIG9 is a top view of a substrate provided in an embodiment of the present application.
  • FIG10 is a partial top view of a display module provided in an embodiment of the present application.
  • FIG11 is a cross-sectional view of the display module shown in FIG10 along the CC direction;
  • FIG12 is another cross-sectional view of the display module shown in FIG10 along the CC direction;
  • FIG13 is another cross-sectional view of the display module shown in FIG10 along the CC direction;
  • FIG14 is a partial top view of another display module provided in an embodiment of the present application.
  • FIG15 is a cross-sectional SEM image of the display module shown in FIG14 along the DD direction;
  • FIG16 is a cross-sectional view of the display module shown in FIG14 along the DD direction;
  • FIG. 17 is a flow chart of a method for preparing a display module provided in an embodiment of the present application.
  • FIG. 18 is a schematic diagram of a photoresist exposure and development process when forming a third wiring layer according to an embodiment of the present application.
  • FIG19 is a schematic diagram of etching when forming a third wiring layer provided in an embodiment of the present application.
  • FIG. 20 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the display module includes a base substrate, and a first wiring layer, a first insulating layer, a second wiring layer, a second insulating layer, and a third wiring layer stacked in sequence on the base substrate.
  • a design scheme in which three layers of wiring are completely overlapped is adopted, and the edges of the three layers of wiring are completely flush. That is, the first wiring of the first wiring layer, the second wiring of the second wiring layer, and the third wiring of the third wiring layer are completely overlapped, and the edges are completely flush.
  • the preparation methods of the first routing, the second routing and the third routing are all: first forming a routing film, and then patterning the routing film to obtain the routing.
  • Patterning the metal film may include: coating a photoresist on the side of the routing film away from the substrate, exposing the photoresist using a mask, developing the exposed photoresist, etching the portion of the routing film that is not protected by the photoresist after development, and removing the remaining photoresist.
  • the etching solution can etch the second routing film along the side of the photoresist, and the lateral etching rate can increase, thereby causing the angle (taper angle) between the boundary slope of the second routing finally formed and the bearing surface of the substrate substrate to be too large, and even deteriorate to 80 ° (degree) to 90 °.
  • the edge of the third routing is completely flush with the edges of the second routing and the first routing, the step difference of the third routing climbing is relatively large (the step difference is the total thickness of the first routing and the second routing).
  • the taper angle of the second routing is relatively large, in the subsequent preparation process of the third routing, referring to FIG6, the slope of the photoresist after exposure and development is relatively large, so the coverage of the photoresist is relatively poor.
  • the etching rate of the etching solution increases significantly, resulting in excessive lateral etching of the third routing, resulting in a high incidence of broken wire defects or large-area small gap defects, which directly affects the product shipment yield and product stability.
  • the taper angle of the second routing is very large (close to 90°), resulting in excessive lateral etching of the third routing.
  • the third routing is thinned by the lateral etching and is directly etched and disconnected at severe locations.
  • FIG8 is a schematic diagram of the structure of a display module provided by an embodiment of the present application.
  • the display module 10 may include a base substrate 101, a first wiring layer 102, a first insulating layer 103, a second wiring layer 104, a second insulating layer 105, and a third wiring layer 106.
  • the first wiring layer 102, the first insulating layer 103, the second wiring layer 104, the second insulating layer 105, and the third wiring layer 106 are stacked in sequence in a direction away from the base substrate 101.
  • the base substrate 101 may have a display area 101a and a fan-out area 101b located on one side of the display area 101a.
  • the first routing layer 102, the second routing layer 104 and the third routing layer 106 may be located in the fan-out area 101b.
  • the first routing layer 102 may include a first routing line 1021, and a first target portion a1 of the first routing line 1021 extends along a first direction X.
  • the second routing layer 104 includes a second routing line 1041 corresponding to the first routing line 1021, and a second target portion a2 of the second routing line 1041 extends along the first direction X.
  • the third routing layer 106 includes a third routing line 1061 corresponding to the second routing line 1041, and a third target portion a3 of the third routing line 1061 extends along the first direction X.
  • Two routing lines corresponding may refer to that the orthographic projections of the target portions of the two routing lines on the base substrate 101 at least partially overlap.
  • the first direction X intersects both the pixel row direction and the pixel column direction.
  • the region where the first target portion a1, the second target portion a2 and the third target portion a3 are located may be an oblique wiring region in the fan-out region.
  • the orthographic projection of the first target portion a1 on the substrate 101 and the orthographic projection of the second target portion a2 on the substrate 101 have a first overlapping region b1 formed by partial overlap in the second direction Y, and the first overlapping region b1 extends along the first direction X. That is, the orthographic projection of the first target portion a1 on the substrate 101 includes, in addition to the first overlapping region b1 formed by overlapping with the orthographic projection of the second target portion a2 on the substrate 101, a first non-overlapping region c1 that does not overlap with the orthographic projection of the second target portion a2 on the substrate 101.
  • the orthographic projection of the second target portion a2 on the substrate 101 includes, in addition to the first overlapping region b1 formed by overlapping with the orthographic projection of the first target portion a1 on the substrate 101, a second non-overlapping region c2 that does not overlap with the orthographic projection of the first target portion a1 on the substrate 101.
  • the first non-overlapping region c1, the first overlapping region b1, and the second non-overlapping region c2 are arranged along the second direction Y, and all extend along the first direction X.
  • the second direction Y intersects the first direction X.
  • the second direction Y is perpendicular to the first direction X. That is, the first wiring 1021 and the second wiring 1041 are shifted in the second direction Y.
  • One of the first routing line 1021 and the second routing line 1041 is a first target routing line, and the other routing line is a second target routing line.
  • the orthographic projection of the target portion of the first target routing line on the substrate 101 and the orthographic projection of the third target portion a3 on the substrate 101 have a second overlapping area b2 formed by partial overlap, and the second overlapping area b2 extends along the first direction X.
  • the orthographic projection of the target portion of the first target routing line on the substrate 101 includes not only the second overlapping area b2 formed by overlapping with the orthographic projection of the third target portion a3 on the substrate 101, but also includes a third non-overlapping area c3 that does not overlap with the orthographic projection of the third target portion a3 on the substrate 101.
  • the orthographic projection of the third target portion a3 on the substrate 101 includes not only the second overlapping area b2 formed by overlapping with the orthographic projection of the target portion of the first target routing line on the substrate 101, but also includes a fourth non-overlapping area c4 that does not overlap with the orthographic projection of the target portion of the first target routing line on the substrate 101.
  • the third non-overlapping region c3 , the second overlapping region b2 , and the fourth non-overlapping region c4 are arranged along the second direction Y, and all extend along the first direction X.
  • the first target routing line can be offset from the third routing line 1061 in the second direction Y.
  • the first routing line 1021 can be offset from the third routing line 1061 in the second direction Y.
  • the second overlapping area b2, the third non-overlapping area c3 and the fourth non-overlapping area c4 are shown in FIG. 12.
  • the first target routing line is the second routing line 1041
  • the second routing line 1041 can be offset from the third routing line 1061 in the second direction Y.
  • the orthographic projection of the target portion of one of the second target routing and the third routing 1061 on the base substrate 101 is located within the orthographic projection of the target portion of the other routing on the base substrate 101.
  • the orthographic projection of the target portion of the second target routing on the base substrate 101 is located within the orthographic projection of the third target portion a3 on the base substrate 101.
  • the orthographic projection of the third target portion a3 of the third routing 1061 on the base substrate 101 is located within the orthographic projection of the target portion of the second target routing on the base substrate 101.
  • the orthographic projection of the target portion of one of the routing lines on the substrate 101 is within the orthographic projection of the target portion of the other routing line on the substrate 101, which can also be used to indicate that the area of the orthographic projection of the target portion of one of the routing lines on the substrate 101 is less than or equal to the area of the orthographic projection of the target portion of the other routing line on the substrate 101.
  • the area of the orthographic projection of the target portion of the second target routing line on the substrate 101 is less than or equal to the area of the orthographic projection of the third target portion a3 of the third routing line 1061 on the substrate 101.
  • the area of the orthographic projection of the third target portion a3 of the third routing line 1061 on the substrate 101 is less than or equal to the area of the orthographic projection of the target portion of the second target routing line on the substrate 101.
  • the first target portion a1 of the first routing line 1021 may include a first boundary slope d1 and a second boundary slope d2 extending along the first direction X. Since the second routing line 1041 is located on the side of the first routing line 1021 away from the substrate 101, the second target portion a2 may cover one of the boundary slopes of the first target portion a1 and not overlap with the other boundary slope. For example, in FIG. 13 , the second target portion a2 may cover the first boundary slope d1 of the first target portion a1, and the second target portion a2 does not overlap with the second boundary slope d2 of the first target portion a1.
  • the second target portion a2 may be arranged to climb the first boundary slope d1 extending along the first direction X of the first target portion a1, and not climb the second boundary slope d2 of the first target portion a1.
  • This design can avoid the two boundary slopes of the second target part a2 (the third boundary slope d3 and the fourth boundary slope d4) from overlapping with the two boundary slopes of the first target part a1 (the first boundary slope d1 and the second boundary slope d2), thereby avoiding too large an angle between the two boundary slopes of the second routing 1041 and the bearing surface of the base substrate 101.
  • the third line 1061 is located on the side of the second line 1041 away from the base substrate 101, so the third target part a3 will not only climb the boundary slope extending along the first direction X of the first target part a1, but also climb the boundary slope extending along the first direction X of the second target part a2. That is, the third target part a3 can be changed from climbing the boundary slope extending along the first direction X of only the first target part a1 to climbing the boundary slope extending along the first direction X of the first target part a1 and the second target part a2.
  • the climbing positions of the third target part a3 are increased, so that the step difference of the third target part a3 at each climbing position is small.
  • the third line 1061 can be avoided from being virtual connection or broken, the stability and reliability of the third line 1061 can be ensured, and the yield of the display module 10 can be improved. For example, it is found through testing that the defective occurrence rate is reduced to 0.5%.
  • the embodiment of the present application provides a display module, which includes a first routing layer, a second routing layer, a third routing layer, a first insulating layer between the first routing layer and the second routing layer, and a second insulating layer between the second routing layer and the third routing layer.
  • the third target portion of the third routing can climb the boundary slope extending along the first direction between the first target portion and the second target portion, increasing the climbing position of the third target portion, so that the step difference of the third target portion at each climbing position is smaller. In this way, it is possible to avoid the third routing being virtually connected or broken, ensure the stability and reliability of the third routing, and improve the yield and display effect of the display module.
  • the materials of the first routing line 1021, the second routing line 1041 and the third routing line 1061 can all be metal materials. Therefore, the first routing line 1021 can also be called Metal_1 routing line, the second routing line 1041 can also be called Metal_2 routing line, and the third routing line 1061 can also be called Metal_3 routing line.
  • the first routing 1021, the second routing 1041 and the third routing 1061 may be two-layer stacks or three-layer stacks.
  • the first routing 1021, the second routing 1041 and the third routing 1061 may be two-layer stacks of Ti (titanium) / Cu (copper), two-layer stacks of MoNb (molybdenum-niobium alloy) / Cu, two-layer stacks of MTD (molybdenum-nickel-titanium alloy) / Cu, and three-layer stacks of Mo (molybdenum) / Al (aluminum) / Mo.
  • the first target routing is the first routing 1021
  • the second target routing is the second routing 1041. That is, referring to FIG12, the orthographic projection of the first target portion a1 of the first routing 1021 on the substrate 101 and the orthographic projection of the third target portion a3 on the substrate 101 have a second overlapping area b2 formed by partial overlap.
  • the orthographic projection of the target portion of one of the second routing 1041 and the third routing 1061 on the substrate 101 is located within the orthographic projection of the target portion of the other routing on the substrate 101.
  • the orthographic projection of the second target portion a2 of the second routing 1041 on the substrate 101 is located within the orthographic projection of the third target portion a3 of the third routing 1061 on the substrate 101.
  • the first target portion a1 of the first line 1021 is offset relative to the second target portion a2 of the second line 1041 and is offset relative to the third target portion a3 of the third line 1061.
  • the second target portion a2 of the second line 1041 and the third target portion a3 of the third line 1061 may not be offset.
  • the orthographic projection of the third boundary slope d3 on the base substrate 101 , the orthographic projection of the first boundary slope d1 on the base substrate 101 , the orthographic projection of the fourth boundary slope d4 on the base substrate 101 , and the orthographic projection of the second boundary slope d2 on the base substrate 101 are arranged in sequence along the second direction Y.
  • the first boundary slope d1 and the second boundary slope d2 both intersect with the bearing surface of the base substrate 101.
  • the extended surfaces of the third boundary slope d3 and the fourth boundary slope d4 intersect with the bearing surface of the base substrate 101. It should be noted that the reason why the boundary slope or the extended surface of the boundary slope intersects with the bearing surface of the base substrate 101 is that the etching liquid etches along the side wall of the photoresist when etching the wiring film.
  • the angle between the boundary slope or the extended surface of the boundary slope and the bearing surface of the substrate 101 is an acute angle.
  • the area of the orthographic projection of the surface of the first target portion a1 away from the substrate 101 on the substrate 101 is smaller than the area of the orthographic projection of the surface of the first target portion a1 close to the substrate 101 on the substrate 101, and the orthographic projection of the surface of the first target portion a1 away from the substrate 101 on the substrate 101 is located within the orthographic projection of the surface of the first target portion a1 close to the substrate 101 on the substrate 101.
  • the area of the orthographic projection of the surface of the second target portion a2 away from the substrate 101 on the substrate 101 is smaller than the area of the orthographic projection of the surface of the second target portion a2 close to the substrate 101 on the substrate 101, and the orthographic projection of the surface of the second target portion a2 away from the substrate 101 on the substrate 101 is located within the orthographic projection of the surface of the second target portion a2 close to the substrate 101 on the substrate 101.
  • an angle ⁇ 1 between an extension surface of the third boundary slope surface d3 and a bearing surface of the base substrate 101 , and an angle ⁇ 2 between an extension surface of the fourth boundary slope surface d4 and a bearing surface of the base substrate 101 are both in a range of 40° to 50°.
  • the second target portion a2 of the second trace 1041 includes a first climbing portion e1 located between the third boundary slope d3 and the fourth boundary slope d4.
  • the orthographic projection of the first climbing portion e1 on the base substrate 101 at least partially overlaps with the orthographic projection of the first boundary slope d1 on the base substrate 101.
  • the orthographic projection of the first climbing portion e1 on the base substrate 101 covers the orthographic projection of the first boundary slope d1 on the base substrate 101.
  • the first climbing portion e1 is arranged to climb at the first boundary slope d1.
  • the third target portion a3 includes a second climbing portion e2, a third climbing portion e3 and a fourth climbing portion e4.
  • the orthographic projection of the second climbing portion e2 on the substrate 101 overlaps at least partially with the orthographic projection of the third boundary slope d3 on the substrate 101
  • the orthographic projection of the third climbing portion e3 on the substrate 101 overlaps at least partially with the orthographic projection of the first boundary slope d1 on the substrate 101
  • the orthographic projection of the fourth climbing portion e4 on the substrate 101 overlaps at least partially with the orthographic projection of the fourth boundary slope d4 on the substrate 101. That is, the third target portion a3 may include three climbing positions.
  • the solution of the embodiment of the present application increases the number of climbing positions of the third target portion a3. Moreover, due to the increase in the number of climbing positions, the angle between the extension surface of the boundary slope at each climbing position and the bearing surface of the substrate 101 can be reduced.
  • the orthographic projection of the first target portion a1 of the first trace 1021 on the base substrate 101 has a first central axis extending along the first direction X
  • the orthographic projection of the second target portion a2 on the base substrate 101 has a second central axis extending along the first direction X
  • the orthographic projection of the third target portion a3 on the base substrate 101 has a third central axis extending along the first direction X.
  • the first central axis and the second central axis are parallel and spaced apart, and the second central axis and the third central axis overlap.
  • the offset setting of the first target portion a1 of the first routing 1021 and the second target portion a2 of the second routing 1041 may refer to: the first central axis of the first target portion a1 and the second central axis of the second target portion a2 are offset, that is, the first central axis and the second central axis do not overlap.
  • the non-offset setting of the second target portion a2 of the second routing 1041 and the third target portion a3 of the third routing 1061 may refer to: the second central axis of the second target portion a2 and the third central axis of the third target portion a3 are not offset, that is, the second central axis and the third central axis overlap.
  • the offset size of the first central axis and the second central axis may affect the narrow frame of the display module 10. If the offset size of the first central axis and the second central axis is too small, the first climbing portion e1 of the second target portion a2 may be too close to one of the boundary slopes of the second target portion a2, which may cause the angle between the boundary slope of the second target portion a2 and the bearing surface of the base substrate 101 to be too large. As a result, the third target portion a3 on the upper side of the second target portion a2 may be virtual connected or broken.
  • the ratio of the minimum spacing between the first central axis and the second central axis to the length of the orthographic projection of the first target portion a1 on the base substrate 101 along the second direction Y is in the range of 1/8 to 3/4. This allows the offset size of the first central axis of the first target portion a1 and the second central axis of the second target portion a2 to be neither too small nor too large. On the one hand, it is convenient to realize the narrow frame of the display module, and on the other hand, it can avoid the third target portion a3 from being virtually connected or broken.
  • the minimum spacing h1 between the first central axis and the second central axis may range from 0.5 ⁇ m (micrometer) to 1.5 ⁇ m.
  • the first target portion a1 is offset from the second target portion a2 by 0.5 ⁇ m to 1.5 ⁇ m.
  • the minimum spacing between the first central axis and the second central axis may be 1 ⁇ m.
  • the length of the orthographic projection of the first target portion a1 on the substrate 101 along the second direction Y i.e., the projection width of the first target portion a1
  • the length of the orthographic projection of the second target portion a2 on the substrate 101 along the second direction Y i.e., the projection width of the second target portion a2
  • the length of the orthographic projection of the third target portion a3 on the substrate 101 along the second direction Y i.e., the projection width of the third target portion a3 are all in the range of 2 ⁇ m to 4 ⁇ m.
  • the actual width of the first target portion a1 can be equal to the projected width of the first target portion a1. Since the second target portion a2 and the third target portion a3 are both arranged to climb, the actual width of the second target portion a2 is greater than the projected width of the second target portion a2, and the actual width of the third target portion a3 is greater than the projected width of the third target portion a3.
  • the actual width of the second target portion a2 can range from 2.2 ⁇ m to 4.2 ⁇ m, and the ratio of the actual width of the second target portion a2 to the projected width can range from 1.05 to 1.1.
  • the actual width of the third target portion a3 can range from 2.4 ⁇ m to 4.4 ⁇ m, and the ratio of the actual width of the third target portion a3 to the projected width can range from 1.10 to 1.15.
  • the first target routing is the second routing 1041
  • the second target routing is the first routing 1021. That is, the orthographic projection of the second target portion a2 of the second routing 1041 on the base substrate 101 and the orthographic projection of the third target portion a3 on the base substrate 101 have a second overlapping region b2 formed by partial overlap.
  • the orthographic projection of the target portion of one of the first routing 1021 and the third routing 1061 on the base substrate 101 is located within the orthographic projection of the target portion of the other routing on the base substrate 101.
  • the second target portion a2 of the second routing line 1041 is offset relative to the first target portion a1 of the first routing line 1021, and is offset relative to the third target portion a3 of the third routing line 1061.
  • the first target portion a1 of the first routing line 1021 and the third target portion a3 of the third routing line 1061 may not be offset.
  • the first target portion a1 of the first routing line 1021 is offset relative to the second target portion a2 of the second routing line 1041 and the third target portion a3 of the third routing line 1061.
  • the second target portion a2 of the second routing line 1041 is offset relative to the first target portion a1 of the first routing line 1021 and the third target portion a3 of the third routing line 1061.
  • the first target portion a1 of the first wiring 1021 is closer to the base substrate 101 than the second target portion a2 of the second wiring 1041, when preparing the display module, the first target portion a1 needs to be formed before the second target portion a2. Therefore, the solution of offsetting the first target portion a1 (the first implementation method) is easier to align and determine the offset size of the first central axis and the second central axis than the solution of offsetting the second target portion a2 (the second implementation method), and the preparation accuracy can be higher.
  • the first routing layer 102 may include multiple first routing lines 1021
  • the second routing layer 104 includes multiple second routing lines 1041 corresponding one-to-one to the multiple first routing lines 1021
  • the third routing layer 106 includes multiple third routing lines 1061 corresponding one-to-one to the multiple second routing lines 1041.
  • the second routing line 1041 corresponding to the first routing line 1021, and the third routing line 1061 corresponding to the second routing line 1041 can be offset in the manner provided in the embodiment of the present application.
  • the first target portions a1 of the multiple first lines 1021 can be arranged at equal intervals along the second direction Y
  • the second target portions a2 of the multiple second lines 1041 can also be arranged at equal intervals along the second direction Y
  • the third target portions a3 of the multiple third lines 1061 can also be arranged at equal intervals along the second direction Y.
  • the first target parts a1 of the plurality of first lines 1021 are arranged at equal intervals along the second direction Y, which may mean that the first central axes of the first target parts a1 of the plurality of first lines 1021 are arranged at equal intervals along the second direction Y.
  • the second target parts a2 of the plurality of second lines 1041 are arranged at equal intervals along the second direction Y, which may mean that the second central axes of the second target parts a2 of the plurality of second lines 1041 are arranged at equal intervals along the second direction Y.
  • the third target parts a3 of the plurality of third lines 1061 are arranged at equal intervals along the second direction Y, which may mean that the third axes of the third target parts a3 of the plurality of third lines 1061 are arranged at equal intervals along the second direction Y.
  • the distance between the first central axes of two adjacent first target portions a1 along the second direction Y may range from 2 ⁇ m to 4 ⁇ m.
  • the distance between the second central axes of two adjacent second target portions a2 along the second direction Y may range from 2 ⁇ m to 4 ⁇ m.
  • the distance between the third central axes of two adjacent third target portions a3 along the second direction Y may range from 2 ⁇ m to 4 ⁇ m.
  • the first line 1021 except the first target portion a1, the second line 1041 except the second target portion a2, and the third line 1061 except the third target portion a3 may not overlap each other and have a spacing.
  • the distance g1 between the orthographic projections of any two adjacent lines on the substrate 101 may range from 4 ⁇ m to 6 ⁇ m.
  • the offset size of the first central axis of the first target portion a1 of the first line 1021 and the second central axis of the second target portion a2 of the second line 1041 can be a fixed size. That is, the distance between the first central axis of the first target portion a1 of each first line 1021 and the second central axis of the second target portion a2 of the corresponding second line 1041 can be equal.
  • the plurality of first routing lines 1021 at least include a first first routing line 1021 and a second first routing line 1021.
  • the plurality of second routing lines 1041 at least include a first second routing line 1041 and a second second routing line 1041.
  • the first second routing line 1041 corresponds to the first first routing line 1021
  • the second second routing line 1041 corresponds to the second first routing line 1021.
  • the distance between the first central axis of the first routing line 1021 and the second central axis of the first second routing line 1041 is equal to the distance between the first central axis of the second first routing line 1021 and the second central axis of the second second routing line 1041.
  • the length of the orthographic projection of the first target portion a1 of the first routing line 1021 on the substrate 101 along the second direction Y is about 2.58 ⁇ m.
  • the length of the orthographic projection of the second target portion a2 of the second routing line 1041 on the substrate 101 along the second direction Y is about 2.09 ⁇ m.
  • the length of the orthographic projection of the third target portion a3 of the third routing line 1061 on the substrate 101 along the second direction Y is about 2.61 ⁇ m.
  • the lengths of the orthographic projections of the target portions of the respective routing lines on the substrate 101 along the second direction Y may be different.
  • the display module 10 may include a touch panel and a display panel.
  • the touch panel may include at least a plurality of transmitting electrode wires
  • the display panel may include at least a plurality of gate lines and a plurality of data lines.
  • the first wire 1021 may be a transmitting electrode wire (Tx wire)
  • the second wire 1041 may be a gate line (gate line)
  • the third wire 1061 may be a data line (source line).
  • the boundary between the second wiring 1041 and the third wiring 1061 may not be completely flush due to the influence of the manufacturing process and other reasons.
  • the uneven situation will not affect other related effects of the embodiment of the present application.
  • the display module shown in FIG. 15 or FIG. 16 can also avoid the third wiring 1061 from being virtually connected or broken.
  • the two boundary slopes of the first routing line 1021 may not be strictly planes, but may be arc surfaces that are concave toward the direction close to the base substrate 101.
  • the surfaces of the second routing line 1041 and the third routing line 1061 away from the base substrate 101 may also be uneven surfaces.
  • the surface morphology of each routing line is related to the preparation process, for example, it may be affected by the material, etching process, thickness of the film layer, and thickness of the insulating layer between adjacent routing lines.
  • the embodiment of the present application provides a display module, which includes a first routing layer, a second routing layer, a third routing layer, a first insulating layer between the first routing layer and the second routing layer, and a second insulating layer between the second routing layer and the third routing layer.
  • the third target portion of the third routing can climb the boundary slope extending along the first direction between the first target portion and the second target portion, increasing the climbing position of the third target portion, so that the step difference of the third target portion at each climbing position is small. In this way, it is possible to avoid the third routing from being virtually connected or broken, ensure the stability and reliability of the third routing, improve the yield of the display module, and achieve a better display effect of the display module.
  • FIG17 is a flow chart of a method for preparing a display module provided in an embodiment of the present application.
  • the method can be used to prepare the display module 10 provided in the above embodiment.
  • the method may include:
  • Step S101 provide a substrate.
  • a base substrate 101 when preparing the display module 10, a base substrate 101 may be first obtained.
  • the base substrate 101 may be a glass substrate or a flexible substrate.
  • the base substrate 101 may have a display area 101a and a fan-out area 101b located on one side of the display area 101a.
  • Step S102 forming a first wiring thin film on one side of the base substrate, and patterning the first wiring thin film using a first mask to form a first wiring layer.
  • the first mask may have a first opening, and the first opening may be used to form the first wiring 1021 of the first wiring layer 102.
  • the process of patterning the first wiring thin film using the first mask includes: coating a layer of photoresist on the side of the first wiring thin film away from the substrate 101; exposing the photoresist using the first mask; developing the exposed photoresist; etching the first wiring thin film that is not protected by the photoresist after development using an etching solution; and removing the remaining photoresist.
  • the first routing layer 102 may be located in the fan-out area 101 b , and the first routing layer 102 includes a first routing line 1021 , and a first target portion a1 of the first routing line 1021 extends along the first direction X.
  • the display module may include a touch panel, and the touch panel may include an emitting electrode wiring.
  • the first wiring 1021 in the first wiring layer 102 may be an emitting electrode wiring in the touch panel.
  • Step S103 forming a first insulating layer on a side of the first wiring layer away from the substrate.
  • a first insulating layer 103 may be formed on a side of the first wiring layer 102 away from the substrate 101.
  • the first insulating layer 103 may be used to insulate the first wiring layer 102 and the subsequently formed second wiring layer 104.
  • Step S104 forming a second wiring film on a side of the first insulating layer away from the base substrate, and patterning the second wiring film using a second mask to form a second wiring layer.
  • the process of patterning the second routing film using a second mask includes: coating a layer of photoresist on the side of the second routing film away from the substrate 101; exposing the photoresist using a second mask; developing the exposed photoresist; etching the second routing film that is not protected by the photoresist after development using an etching solution; and removing the remaining photoresist.
  • the second routing layer 104 may be located in the fan-out area 101b, and the second routing layer 104 includes a second routing 1041, and the second target portion a2 of the second routing 1041 extends along the first direction X.
  • the second mask may have a second opening, and the second opening may be used to form the second routing 1041 of the second routing layer 104.
  • the orthographic projection of the second opening on the base substrate 101 partially overlaps with the orthographic projection of the first opening on the base substrate 101.
  • the orthographic projection of the first target portion a1 of the first routing 1021 on the base substrate 101 and the orthographic projection of the second target portion a2 of the second routing 1041 on the base substrate 101 may partially overlap to form a first overlapping region b1.
  • the display module 10 may include a display panel, the display control panel may include gate lines, and the second wiring 1041 in the second wiring layer 104 may be the gate lines in the display panel.
  • Step S105 forming a second insulating layer on a side of the second wiring layer away from the substrate.
  • a second insulating layer 105 may be formed on a side of the second wiring layer 104 away from the substrate 101.
  • the second insulating layer 105 may be used to insulate the second wiring layer 104 and the subsequently formed third wiring layer 106.
  • Step S106 forming a third wiring thin film on a side of the second insulating layer away from the base substrate, and patterning the third wiring thin film using a third mask to form a third wiring layer.
  • the process of patterning the third routing 1061 film using a third mask includes: coating a layer of photoresist on the side of the third routing 1061 film away from the substrate 101; exposing the photoresist using a third mask; developing the exposed photoresist; etching the third routing 1061 film that is not protected by the photoresist after development using an etching solution; and removing the remaining photoresist.
  • the third routing layer 106 may be located in the fan-out region 101 b , and the third routing layer 106 includes a third routing line 1061 , and a third target portion a3 of the third routing line 1061 extends along the first direction X.
  • the third mask may have a third opening, and the third opening may be used to form the third routing line 1061 of the third routing layer 106 .
  • the orthographic projection of the third opening in the third mask on the base substrate 101 may partially overlap with the orthographic projection of the first opening of the first mask on the base substrate 101, and the orthographic projection of one of the second opening and the third opening on the base substrate 101 is located within the orthographic projection of the other opening on the base substrate 101.
  • the orthographic projection of the first target portion a1 of the first wiring 1021 on the base substrate 101 may partially overlap with the orthographic projection of the third target portion a3 of the third wiring 1061 on the base substrate 101 to form a second overlapping region b2.
  • the second overlapping region b2 extends along the first direction X.
  • the orthographic projection of the target portion of one of the second wiring 1041 and the third wiring 1061 on the base substrate 101 is located within the orthographic projection of the target portion of the other wiring on the base substrate 101.
  • the orthographic projection of the third opening in the third mask on the base substrate 101 may partially overlap with the orthographic projection of the second opening of the second mask on the base substrate 101, and the orthographic projection of one of the first opening and the third opening on the base substrate 101 is located within the orthographic projection of the other opening on the base substrate 101.
  • the orthographic projection of the second target portion a2 of the second wiring 1041 on the base substrate 101 may partially overlap with the orthographic projection of the third target portion a3 of the third wiring 1061 on the base substrate 101 to form a second overlapping region b2.
  • the second overlapping region b2 extends along the first direction X.
  • the orthographic projection of the target portion of one of the first wiring 1021 and the third wiring 1061 on the base substrate 101 is located within the orthographic projection of the target portion of the other wiring on the base substrate 101.
  • the slope angle of the photoresist formed on the third wiring film is small, so the coverage performance of the photoresist is good. Therefore, as shown in FIG19 , during the etching process of the third wiring film, the problem of excessive lateral etching causing a high incidence of broken wires or small gaps will not occur, and the broken wires or virtual connections can be effectively improved.
  • the display module may include a display panel, and the display control panel may include a data line.
  • the third wiring 1061 in the third wiring layer 106 may be a data line in the display panel.
  • one of the first mask used to form the first wiring 1021 and the second mask used to form the second wiring 1041 can be offset by a certain distance relative to the other mask when preparing the first wiring 1021 or the second wiring 1041. In this way, there is no need to design a new mask.
  • the design position of the first opening of the first mask can be directly changed or the design position of the second opening of the second mask can be changed. In this method, the mask needs to be redesigned.
  • the embodiment of the present application provides a method for preparing a display module, and the display module prepared by the method includes a first routing layer, a second routing layer, a third routing layer, a first insulating layer located between the first routing layer and the second routing layer, and a second insulating layer located between the second routing layer and the third routing layer.
  • the third target portion of the third routing can climb the boundary slope extending along the first direction between the first target portion and the second target portion, increasing the climbing position of the third target portion, so that the step difference of the third target portion at each climbing position is small. In this way, it is possible to avoid the third routing from being virtually connected or broken, ensure the stability and reliability of the third routing, improve the yield of the display module, and achieve a better display effect of the display module.
  • Fig. 20 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the display device may include a power supply component 20 and a display panel 10 provided in the above embodiment.
  • the power supply component 20 may be used to supply power to the display panel 10.
  • the display device can be: a liquid crystal display device (LCD), an organic light-emitting diode (OLED) display device, electronic paper, a low-temperature polysilicon (LTPS) display device, a low-temperature polycrystalline oxide (LTPO) display device, an oxide display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • LCD liquid crystal display device
  • OLED organic light-emitting diode
  • LTPS low-temperature polysilicon
  • LTPO low-temperature polycrystalline oxide
  • oxide display device a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the display device can have substantially the same technical effects as the display module described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.
  • Words such as “include” or “include” mean that the elements or objects appearing in front of “include” or “include” include the elements or objects listed after “include” or “include” and their equivalents, and do not exclude other elements or objects.
  • Words such as “connect” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up”, “down”, “left”, “right” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

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Abstract

本申请公开了一种显示模组及其制备方法、显示装置，涉及显示技术领域。显示模组包括第一走线，第二走线以及第三走线。通过使得第一走线的第一目标部分和第二走线的第二目标部分偏移设置，可以避免第二目标部分的两个边界坡面与第一目标部分的两个边界坡面重叠，进而避免第二目标部分的边界坡面与衬底基板的承载面的夹角过大。进一步的，第三走线的第三目标部分能够在第一目标部分和第二目标部分沿第一方向延伸的边界坡面爬坡，增多了第三目标部分的爬坡位置，从而使得第三目标部分在每个爬坡位置的段差较小。由此，可以避免第三走线虚接或断裂，保证第三走线的稳定性和可靠性，提高显示模组的良率，显示模组的显示效果较好。

Description

显示模组及其制备方法、显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示模组及其制备方法、显示装置。
背景技术
随着显示行业的发展，人们对于显示产品的技术和品质要求也逐步提高，显示模组的极致窄边框已经愈发成为发展趋势。显示模组的边框尺寸的不断压缩对扇出区的布线提出了更高的要求。
发明内容
本申请提供了一种显示模组及其制备方法、显示装置，所述技术方案如下：
一方面，提供了一种显示模组，所述显示模组包括：
衬底基板，所述衬底基板具有显示区以及位于所述显示区的一侧的扇出区；
第一走线层，位于所述衬底基板的一侧且位于所述扇出区，所述第一走线层包括第一走线，所述第一走线的第一目标部分沿第一方向延伸；
第一绝缘层，位于所述第一走线层远离所述衬底基板的一侧；
第二走线层，位于所述第一绝缘层远离所述衬底基板的一侧且位于所述扇出区，所述第二走线层包括与所述第一走线对应的第二走线，所述第二走线的第二目标部分沿所述第一方向延伸；
第二绝缘层，位于所述第二走线层远离所述衬底基板的一侧；
以及第三走线层，位于所述第二绝缘层远离所述衬底基板的一侧且位于所述扇出区，所述第三走线层包括与所述第二走线对应的第三走线，所述第三走线的第三目标部分沿所述第一方向延伸；
其中，所述第一目标部分在所述衬底基板上的正投影与所述第二目标部分在所述衬底基板上的正投影具有部分交叠而成的第一交叠区域，所述第一交叠区域沿所述第一方向延伸；
所述第一走线和所述第二走线中其中一条走线为第一目标走线，另一条走线为第二目标走线；所述第一目标走线的目标部分在所述衬底基板上的正投影与所述第三目标部分在所述衬底基板上的正投影具有部分交叠而成的第二交叠区域，所述第二交叠区域沿所述第一方向延伸；所述第二目标走线和所述第三走线中其中一条走线的目标部分在所述衬底基板上的正投影内位于另一条走线的目标部分在所述衬底基板上的正投影内。
可选的，所述第一目标走线为所述第一走线，所述第二目标走线为所述第二走线。
可选的，所述第一走线包括沿所述第一方向延伸的第一边界坡面和第二边界坡面，所述第二走线包括沿所述第一方向延伸的第三边界坡面和第四边界坡面；
所述第三边界坡面在所述衬底基板上的正投影，所述第一边界坡面在所述衬底基板上的正投影，所述第四边界坡面在所述衬底基板上的正投影以及所述第二边界坡面在所述衬底基板上的正投影沿第二方向依次排布，所述第二方向与所述第一方向相交；
其中，对于所述第一边界坡面和所述第二边界坡面均与所述衬底基板的承载面相交，所述第三边界坡面和所述第四边界坡面的延伸面与所述衬底基板的承载面相交。
可选的，所述第三边界坡面的延伸面和所述衬底基板的承载面之间的夹角，以及所述第四边界坡面的延伸面和所述衬底基板的承载面之间的夹角的范围均为40度至50度。
可选的，所述第二目标部分包括位于所述第三边界坡面和所述第四边界坡面之间的第一爬坡部，所述第一爬坡部在所述衬底基板上的正投影，与所述第一边界坡面在所述衬底基板上的正投影至少部分重叠。
可选的，所述第三目标部分包括：第二爬坡部，第三爬坡部和第四爬坡部；
其中所述第二爬坡部在所述衬底基板上的正投影与所述第三边界坡面在所述衬底基板上的正投影至少部分重叠，所述第三爬坡部在所述衬底基板上的正投影与所述第一边界坡面在所述衬底基板上的正投影至少部分重叠，所述第四爬坡部在所述衬底基板上的正投影与所述第四边界坡面在所述衬底基板上的正投影至少部分重叠。
可选的，所述第一目标部分在所述衬底基板上的正投影具有沿所述第一方向延伸的第一中轴线，所述第二目标部分在所述衬底基板上的正投影具有沿所述第一方向延伸的第二中轴线，所述第三目标部分在所述衬底基板上的正投影具有沿所述第一方向延伸的第三中轴线；
其中，所述第一中轴线和所述第二中轴线平行且间隔设置，所述第二中轴线和所述第三中轴线重叠。
可选的，所述第一中轴线和所述第二中轴线的最小间距，与所述第一目标部分在所述衬底基板上的正投影沿第二方向的长度的比值范围为1/8至3/4。
可选的，所述第一中轴线和所述第二中轴线的最小间距的范围为0.5微米至1.5微米。
可选的，所述第一中轴线和所述第二中轴线的最小间距为1微米。
可选的，所述第一目标部分在所述衬底基板上的正投影沿第二方向的长度，所述第二目标部分在所述衬底基板上的正投影沿所述第二方向的长度，以及所述第三目标部分在所述衬底基板上的正投影沿所述第二方向的长度的范围均为2微米至4微米。
可选的，所述第一走线层包括多条所述第一走线，所述第二走线层包括与多条所述第一走线一一对应的多条所述第二走线，所述第三走线层包括与多条所述第二走线一一对应的多条所述第三走线。
可选的，多条所述第一走线的第一目标部分沿第二方向等间距排布，多条所述第二走线的第二目标部分沿所述第二方向等间距排布，多条所述第三走线的第三目标部分沿所述第二方向等间距排布。
可选的，多条所述第一走线至少包括第一条第一走线和第二条第一走线，多条所述第二走线至少包括第一条第二走线和第二条第二走线，所述第一条第二走线和所述第一条第一走线对应，所述第二条第二走线和所述第二条第一走线对应；
其中，所述第一条第一走线的第一中轴线和所述第一条第二走线的第二中轴线之间的距离，与所述第二条第一走线的第一中轴线和所述第二条第二走线的第二中轴线之间的距离相等。
可选的，所述显示模组包括触控面板和显示面板；所述触控面板至少包括多条发射电极走线，所述显示面板至少包括多条栅线和多条数据线；
其中，所述第一走线为所述发射电极走线，所述第二走线为所述栅线，所述第三走线为所述数据线。
另一方面，提供了一种显示模组的制备方法，所述方法包括：
提供一衬底基板，所述衬底基板具有显示区以及位于所述显示区的一侧的扇出区；
在所述衬底基板的一侧形成第一走线薄膜，采用第一掩膜对所述第一走线薄膜进行图案化处理形成第一走线层，所述第一走线层位于所述扇出区，所述第一走线层包括第一走线，所述第一走线的第一目标部分沿第一方向延伸；
在所述第一走线层远离所述衬底基板的一侧形成第一绝缘层；
在所述第一绝缘层远离衬底基板的一侧形成第二走线薄膜，采用第二掩膜对所述第二走线薄膜进行图案化处理以形成第二走线层，所述第二走线层位于所述扇出区，所述第二走线层包括与所述第一走线对应的第二走线，所述第二走线的第二目标部分沿所述第一方向延伸；
在所述第二走线层远离所述衬底基板的一侧形成第二绝缘层；
在所述第二绝缘层远离所述衬底基板的一侧形成第三走线薄膜，采用第三掩膜对所述第三走线薄膜进行图案化处理以形成第三走线层，所述第三走线层包括与所述第二走线对应的第三走线，所述第三走线的第三目标部分沿所述第一方向延伸；
其中，所述第一目标部分在所述衬底基板上的正投影与所述第二目标部分在所述衬底基板上的正投影具有部分交叠而成的第一交叠区域，所述第一交叠区域沿所述第一方向延伸；
所述第一走线和所述第二走线中其中一条走线为第一目标走线，另一条走线为第二目标走线，所述第一目标走线的目标部分在所述衬底基板上的正投影与所述第三目标部分在所述衬底基板上的正投影具有部分交叠而成的第二交叠区域，所述第二交叠区域沿所述第一方向延伸；所述第二目标走线和所述第三走线中其中一条走线的目标部分在所述衬底基板上的正投影内位于另一条走线的目标部分在所述衬底基板上的正投影内。
可选的，所述第一掩膜具有第一开口，所述第一开口用于形成所述第一走线；所述第二掩膜具有第二开口，所述第二开口用于形成所述第二走线；所述第三掩膜具有第三开口，所述第三开口用于一条第三走线；
所述第一开口在所述衬底基板上的正投影与所述第二开口在所述衬底基板上的正投影部分交叠；所述第一开口在所述衬底基板上的正投影与所述第三开口在所述衬底基板上的正投影部分交叠；
所述第二开口和所述第三开口中的一个开口在所述衬底基板上的正投影位于另一个开口在所述衬底基板上的正投影内。
可选的，所述显示模组包括触控面板和显示面板；所述触控面板至少包括多条发射电极走线，所述显示面板至少包括多条栅线和多条数据线；
其中，所述第一走线为所述发射电极走线，所述第二走线为所述栅线，所述第三走线为所述数据线。
又一方面，提供了一种显示装置，所述显示装置包括：供电组件以及如上述方面所述的显示模组；
所述供电组件用于为所述显示模组供电。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中显示模组的局部俯视图；
图2是图1所示的显示模组沿AA方向的截面扫描电镜图；
图3是图1所示的显示模组沿BB方向的截面扫描电镜图；
图4是相关技术中形成第二走线层时的光刻胶曝光和显影后的示意图；
图5是相关技术中形成第二走线层时的刻蚀的示意图；
图6是相关技术中形成第三走线层时的光刻胶曝光和显影后的示意图；
图7是相关技术中形成第三走线层时的刻蚀的示意图；
图8是本申请实施例提供的一种显示模组的结构示意图；
图9是本申请实施例提供的一种衬底基板的俯视图；
图10是本申请实施例提供的一种显示模组的局部俯视图；
图11是图10所示的显示模组沿CC方向的一种截面图；
图12是图10所示的显示模组沿CC方向的另一种截面图；
图13是图10所示的显示模组沿CC方向的又一种截面图；
图14是本申请实施例提供的另一种显示模组的局部俯视图；
图15是图14所示的显示模组沿DD方向的截面扫描电镜图；
图16是图14所示的显示模组沿DD方向的一种截面图；
图17是本申请实施例提供的一种显示模组的制备方法的流程图；
图18是本申请实施例提供的一种形成第三走线层时的光刻胶曝光和显影后的示意图；
图19是本申请实施例提供的一种形成第三走线层时的刻蚀的示意图；
图20是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
显示模组包括衬底基板，以及位于衬底基板上依次层叠的第一走线层，第一绝缘层，第二走线层，第二绝缘层以及第三走线层。相关技术中，为了节省显示模组的扇出区的版图空间，采用三层走线完全交叠的设计方案，且三层走线的边缘完全平齐。即第一走线层的第一走线，第二走线层的第二走线以及第三走线层的第三走线完全交叠，且边缘完全平齐。
其中，第一走线，第二走线以及第三走线的制备方法均为：先形成一层走线薄膜，之后再对走线薄膜进行图案化处理得到走线。对金属薄膜进行图案化处理可以包括：在走线薄膜远离衬底基板的一侧涂覆光刻胶，采用掩膜版对光刻胶进行曝光，对曝光后的光刻胶进行显影，对显影后未被光刻胶保护的走线薄膜的部分进行刻蚀，去除剩余的光刻胶。
但是上述方案通过验证发现第三走线层中的第三走线容易虚接或断裂(如图1至图3)，且不良发生率高达38.12％。通过分析发现此种方案不良高发的主要原因在于：由于第二走线层中第二走线的边缘设计的和第一走线层中第一走线的边缘平齐，因此参考图4，在形成第二走线的过程中，曝光并显影后的光刻胶在第一走线的边界坡面处会进行爬坡(图4中两个虚线框所在区)。由此，参考图5，后续刻蚀第二走线薄膜的过程中，刻蚀液会顺着光刻胶的侧面刻蚀第二走线薄膜，侧向刻蚀率会增大，从而导致最终形成的第二走线的边界坡面与 衬底基板的承载面之间的夹角(taper角)过大，甚至恶化至80°(度)至90°。
进一步的，由于第三走线的边缘与第二走线和第一走线的边缘完全平齐，因此第三走线爬坡的段差较大(段差为第一走线和第二走线的总厚度)。另外由于第二走线的taper角偏大，因此后续在第三走线的制备过程中，参考图6，曝光并显影后的光刻胶爬坡的坡度较大，因此光刻胶的覆盖性较差。之后，参考图7，在刻蚀第三层金属薄膜以形成第三走线的过程中，刻蚀液的刻蚀率大幅增加，从而导致第三走线侧向刻蚀过多引起断线不良高发或者大面积小缺口不良高发，直接影响产品出货良率以及产品的稳定性。
如图2和图3，第二走线的taper角很大(接近90°)，导致第三走线的侧向刻蚀过大，第三走线被侧刻线宽变细，严重位置直接刻蚀断开。
图8是本申请实施例提供的一种显示模组的结构示意图。参考图8，该显示模组10可以包括衬底基板101，第一走线层102，第一绝缘层103，第二走线层104，第二绝缘层105以及第三走线层106。其中，第一走线层102，第一绝缘层103，第二走线层104，第二绝缘层105以及第三走线层106沿远离衬底基板101的方向依次层叠。
参考图9，该衬底基板101可以具有显示区101a以及位于显示区101a的一侧的扇出(fanout)区101b。结合图8至图10，第一走线层102，第二走线层104以及第三走线层106可以位于扇出区101b。该第一走线层102可以包括第一走线1021，该第一走线1021的第一目标部分a1沿第一方向X延伸。第二走线层104包括与第一走线1021对应的第二走线1041，该第二走线1041的第二目标部分a2沿第一方向X延伸。第三走线层106包括与第二走线1041对应的第三走线1061，该第三走线1061的第三目标部分a3沿第一方向X延伸。两条走线对应可以是指两条走线的目标部分在衬底基板101上的正投影至少部分重叠。
第一方向X与像素行方向以及像素列方向均相交。第一目标部分a1，第二目标部分a2以及第三目标部分a3所在区域可以为扇出区中的斜配线区。
参考图11，第一目标部分a1在衬底基板101上的正投影与第二目标部分a2在衬底基板101上的正投影在第二方向Y上具有部分交叠而成的第一交叠区域b1，该第一交叠区域b1沿第一方向X延伸。也即是，第一目标部分a1在衬底 基板101上的正投影除了包括与第二目标部分a2在衬底基板101上的正投影交叠而成的第一交叠区域b1之外，还包括与第二目标部分a2在衬底基板101上的正投影未交叠的第一非交叠区域c1。相应的，第二目标部分a2在衬底基板101上的正投影除了包括与第一目标部分a1在衬底基板101上的正投影交叠而成的第一交叠区域b1之外，还包括与第一目标部分a1在衬底基板101上的正投影未交叠的第二非交叠区域c2。并且，第一非交叠区域c1，第一交叠区域b1以及第二非交叠区域c2沿第二方向Y排布，且均沿第一方向X延伸。其中，第二方向Y与第一方向X相交。例如，第二方向Y与第一方向X垂直。也即是，第一走线1021和第二走线1041在第二方向Y上偏移(shift)设置。
该第一走线1021和第二走线1041中的一条走线为第一目标走线，另一条走线为第二目标走线。其中，第一目标走线的目标部分在衬底基板101上的正投影与第三目标部分a3在衬底基板101上的正投影具有部分交叠而成的第二交叠区域b2，该第二交叠区域b2沿第一方向X延伸。也即是，其中第一目标走线的目标部分在衬底基板101上的正投影除了包括与第三目标部分a3在衬底基板101上的正投影交叠而成的第二交叠区域b2之外，还包括与第三目标部分a3在衬底基板101上的正投影未交叠的第三非交叠区域c3。相应的，第三目标部分a3在衬底基板101上的正投影除了包括与第一目标走线的目标部分在衬底基板101上的正投影交叠而成的第二交叠区域b2之外，还包括与第一目标走线的目标部分在衬底基板101上的正投影未交叠的第四非交叠区域c4。并且，第三非交叠区域c3，第二交叠区域b2以及第四非交叠区域c4沿第二方向Y排布，且均沿第一方向X延伸。
也即是，该第一目标走线可以与第三走线1061在第二方向Y上偏移设置。例如，若第一目标走线为第一走线1021，则第一走线1021可以与第三走线1061在第二方向Y上偏移设置。第二交叠区域b2，第三非交叠区域c3和第四非交叠区域c4如图12所示。若第一目标走线为第二走线1041，则第二走线1041可以与第三走线1061在第二方向Y上偏移设置。
另外，第二目标走线以及第三走线1061中的其中一条走线的目标部分在衬底基板101上的正投影位于另一条走线的目标部分在衬底基板101上的正投影内。例如，第二目标走线的目标部分在衬底基板101上的正投影位于第三目标部分a3在衬底基板101上的正投影内。或者，第三走线1061的第三目标部分 a3在衬底基板101上的正投影位于第二目标走线的目标部分在衬底基板101上的正投影内。
由此，其中一条走线的目标部分在衬底基板101上的正投影位于另一条走线的目标部分在衬底基板101上的正投影内还可以用于表示：其中一条走线的目标部分在衬底基板101上的正投影的面积，小于或等于另一条走线的目标部分在衬底基板101上的正投影的面积。例如，第二目标走线的目标部分在衬底基板101上的正投影的面积，小于或等于第三走线1061的第三目标部分a3在衬底基板101上的正投影的面积。或者，第三走线1061的第三目标部分a3在衬底基板101上的正投影的面积，小于或等于第二目标走线的目标部分在衬底基板101上的正投影的面积。
在本申请实施例中，参考图13，第一走线1021的第一目标部分a1可以包括沿第一方向X延伸的第一边界坡面d1和第二边界坡面d2。由于第二走线1041位于第一走线1021远离衬底基板101的一侧，因此第二目标部分a2可以覆盖第一目标部分a1其中一个边界坡面，且与另一个边界坡面不重叠。例如，图13中，第二目标部分a2可以覆盖第一目标部分a1的第一边界坡面d1，且第二目标部分a2与第一目标部分a1的第二边界坡面d2不重叠。由此可以使得第二目标部分a2在第一目标部分a1沿第一方向X延伸的第一边界坡面d1爬坡设置，而在第一目标部分a1的第二边界坡面d2处不爬坡设置。通过该设计可以避免第二目标部分a2的两个边界坡面(第三边界坡面d3和第四边界坡面d4)与第一目标部分a1的两个边界坡面(第一边界坡面d1和第二边界坡面d2)重叠，进而避免第二走线1041的两个边界坡面与衬底基板101的承载面之间的夹角过大。
并且，第三走线1061位于第二走线1041远离衬底基板101的一侧，因此第三目标部分a3不仅会在第一目标部分a1沿第一方向X延伸的边界坡面爬坡，还会在第二目标部分a2沿第一方向X延伸的边界坡面爬坡。也即是，可以将第三目标部分a3由原先仅在第一目标部分a1沿第一方向X延伸的边界坡面爬坡，变更为在第一目标部分a1和第二目标部分a2沿第一方向X延伸的边界坡面爬坡。由此，在减小了第二走线1041的两个边界坡面与衬底基板101的承载面之间的夹角的基础上，增多了第三目标部分a3的爬坡位置，从而使得第三目标部分a3在每个爬坡位置的段差较小。进一步的，可以避免第三走线1061虚接或 断裂，保证第三走线1061的稳定性和可靠性，提高显示模组10的良率，例如通过测试发现不良发生率降低至0.5％。
综上所述，本申请实施例提供了一种显示模组，该显示模组包括第一走线层，第二走线层，第三走线层，位于第一走线层和第二走线层之间的第一绝缘层，以及位于第二走线层和第三走线层之间的第二绝缘层。通过使得第一走线的第一目标部分和第二走线的第二目标部分偏移设置，可以避免第二目标部分的两个边界坡面与第一目标部分的两个边界坡面重叠，进而避免第二目标部分的边界坡面与衬底基板的承载面的夹角过大。进一步的，第三走线的第三目标部分能够在第一目标部分和第二目标部分沿第一方向延伸的边界坡面爬坡，增多了第三目标部分的爬坡位置，从而使得第三目标部分在每个爬坡位置的段差较小。由此，可以避免第三走线虚接或断裂，保证第三走线的稳定性和可靠性，提高显示模组的良率和显示效果。
在本申请实施例中，第一走线1021，第二走线1041以及第三走线1061的材料可以均为金属(Metal)材料。故而第一走线1021还可以称为Metal_1走线，第二走线1041还可以称为Metal_2走线，第三走线1061还可以称为Metal_3走线。
可选的，第一走线1021，第二走线1041以及第三走线1061可以为两层叠层或三层叠层。例如，第一走线1021，第二走线1041以及第三走线1061可以为Ti(钛)/Cu(铜)的两层叠层，MoNb(钼铌合金)/Cu的两层叠层，MTD(钼镍钛合金)/Cu的两层叠层，Mo(钼)/Al(铝)/Mo的三层叠层中的一种或多种。
作为第一种可选的实现方式，第一目标走线为第一走线1021，第二目标走线为第二走线1041。也即是，参考图12，第一走线1021的第一目标部分a1在衬底基板101上的正投影与第三目标部分a3在衬底基板101上的正投影具有部分交叠而成的第二交叠区域b2。第二走线1041和第三走线1061中的其中一条走线的目标部分在衬底基板101上的正投影位于另一条走线的目标部分在衬底基板101上的正投影内。例如图12中，第二走线1041的第二目标部分a2在衬底基板101上的正投影位于第三走线1061的第三目标部分a3在衬底基板101上的正投影内。
在该实现方式中，第一走线1021的第一目标部分a1相对于第二走线1041 的第二目标部分a2偏移设置，且相对于第三走线1061的第三目标部分a3偏移设置。而第二走线1041的第二目标部分a2和第三走线1061的第三目标部分a3可以不偏移设置。
参考图12，第三边界坡面d3在衬底基板101上的正投影，第一边界坡面d1在衬底基板101上的正投影，第四边界坡面d4在衬底基板101上的正投影以及第二边界坡面d2在衬底基板101上的正投影沿第二方向Y依次排布。
其中，第一边界坡面d1和第二边界坡面d2均与衬底基板101的承载面相交。第三边界坡面d3和第四边界坡面d4的延伸面与衬底基板101的承载面相交。需要说明的是，边界坡面或边界坡面的延伸面与衬底基板101的承载面相交的原因在于刻蚀走线薄膜时刻蚀液顺着光刻胶的侧壁刻蚀形成。
可选的，边界坡面或边界坡面的延伸面与衬底基板101的承载面之间的夹角为锐角。例如，第一目标部分a1远离衬底基板101的表面在衬底基板101上的正投影的面积，小于第一目标部分a1靠近衬底基板101的表面在衬底基板101上的正投影的面积，且第一目标部分a1远离衬底基板101的表面在衬底基板101上的正投影位于第一目标部分a1靠近衬底基板101的表面在衬底基板101上的正投影内。第二目标部分a2远离衬底基板101的表面在衬底基板101上的正投影的面积，小于第二目标部分a2靠近衬底基板101的表面在衬底基板101上的正投影的面积，且第二目标部分a2远离衬底基板101的表面在衬底基板101上的正投影位于第二目标部分a2靠近衬底基板101的表面在衬底基板101上的正投影内。
可选的，第三边界坡面d3的延伸面和衬底基板101的承载面之间的夹角α1，以及第四边界坡面d4的延伸面和衬底基板101的承载面之间的夹角α2的范围均为40°至50°。
在本申请实施例中，第二走线1041的第二目标部分a2包括位于第三边界坡面d3和第四边界坡面d4之间的第一爬坡部e1。该第一爬坡部e1在衬底基板101上的正投影，与第一边界坡面d1在衬底基板101上的正投影至少部分重叠。例如，该第一爬坡部e1在衬底基板101上的正投影覆盖第一边界坡面d1在衬底基板101上的正投影。该第一爬坡部e1在第一边界坡面d1处爬坡设置。
参考图13，该第三目标部分a3包括第二爬坡部e2，第三爬坡部e3和第四爬坡部e4。第二爬坡部e2在衬底基板101上的正投影与第三边界坡面d3在衬 底基板101上的正投影至少部分重叠，第三爬坡部e3在衬底基板101上的正投影与第一边界坡面d1在衬底基板101上的正投影至少部分重叠，第四爬坡部e4在衬底基板101上的正投影与第四边界坡面d4在衬底基板101上的正投影至少部分重叠。也即是，第三目标部分a3可以包括三个爬坡位置，相对于现有技术中的两个爬坡位置，本申请实施例的方案增多了第三目标部分a3的爬坡位置的数量。并且，由于爬坡位置数量的增多，因此可以减小各爬坡位置处的边界坡面的延伸面与衬底基板101的承载面之间的夹角角度。
在本申请实施例中，参考图10，第一走线1021的第一目标部分a1在衬底基板101上的正投影具有沿第一方向X延伸的第一中轴线，第二目标部分a2在衬底基板101上的正投影具有沿第一方向X延伸的第二中轴线，第三目标部分a3在衬底基板101上的正投影具有沿第一方向X延伸的第三中轴线。其中，第一中轴线和第二中轴线平行且间隔设置，第二中轴线和第三中轴线重叠。
需要说明的是，第一走线1021的第一目标部分a1和第二走线1041的第二目标部分a2偏移设置可以是指：第一目标部分a1的第一中轴线和第二目标部分a2的第二中轴线偏移设置，即第一中轴线和第二中轴线不重叠。第二走线1041的第二目标部分a2和第三走线1061的第三目标部分a3不偏移设置可以是指：第二目标部分a2的第二中轴线和第三目标部分a3的第三中轴线不偏移设置，即第二中轴线和第三中轴线重叠。
在本申请实施例中，如果第一中轴线和第二中轴线的偏移尺寸太大，可能会影响显示模组10的窄边框化。如果第一中轴线和第二中轴线的偏移尺寸太小，可能会导致第二目标部分a2的第一爬坡部e1太靠近第二目标部分a2的其中一个边界坡面，进而可能导致第二目标部分a2的边界坡面与衬底基板101的承载面之间的夹角太大。由此可能会导致第二目标部分a2上侧的第三目标部分a3虚接或断裂。
可选的，第一中轴线和第二中轴线的最小间距，与第一目标部分a1在衬底基板101上的正投影沿第二方向Y的长度的比值范围为1/8至3/4。由此可以使得第一目标部分a1的第一中轴线和第二目标部分a2的第二中轴线的偏移尺寸不会太小，也不会太大。一方面能够便于实现显示模组的窄边框化，另一方面可以避免第三目标部分a3虚接或断裂。
可选的，参考图8，第一中轴线和第二中轴线的最小间距h1的范围可以为 0.5μm(微米)至1.5μm。也是，第一目标部分a1相对于第二目标部分a2偏移0.5μm至1.5μm设置。例如，第一中轴线和第二中轴线的最小间距可以为1μm。
可选的，第一目标部分a1在衬底基板101上的正投影沿第二方向Y的长度(即第一目标部分a1的投影宽度)，第二目标部分a2在衬底基板101上的正投影沿第二方向Y的长度(即第二目标部分a2的投影宽度)，以及第三目标部分a3在衬底基板101上的正投影沿第二方向Y的长度(即第三目标部分a3的投影宽度)的范围均为2μm至4μm。
另外，由于第一目标部分a1未爬坡设置，因此第一目标部分a1的实际宽度可以与第一目标部分a1的投影宽度相等。而由于第二目标部分a2以及第三目标部分a3均爬坡设置，因此第二目标部分a2的实际宽度大于第二目标部分a2的投影宽度，且第三目标部分a3的实际宽度大于第三目标部分a3的投影宽度。可选的，第二目标部分a2的实际宽度范围可以为2.2μm至4.2μm，第二目标部分a2的实际宽度与投影宽度的比值范围可以为1.05至1.1。第三目标部分a3的实际宽度范围可以为2.4μm至4.4μm，第三目标部分a3的实际宽度与投影宽度的比值范围可以为1.10至1.15。
作为第二种可选的实现方式，第一目标走线为第二走线1041，第二目标走线为第一走线1021。也即是，第二走线1041的第二目标部分a2在衬底基板101上的正投影与第三目标部分a3在衬底基板101上的正投影具有部分交叠而成的第二交叠区域b2。第一走线1021和第三走线1061中的其中一条走线的目标部分在衬底基板101上的正投影位于另一条走线的目标部分在衬底基板101上的正投影内。
在该实现方式中，第二走线1041的第二目标部分a2相对于第一走线1021的第一目标部分a1偏移设置，且相对于第三走线1061的第三目标部分a3偏移设置。而第一走线1021的第一目标部分a1和第三走线1061的第三目标部分a3可以不偏移设置。
需要说明的是，该实现方式中的其他相关内容，可以参见上述第一种实现方式的描述，本申请实施例在此不再赘述。
对比第一种可选的实现方式和第二种可选的实现方式，第一种实现方式中将第一走线1021的第一目标部分a1相对于第二走线1041的第二目标部分a2以及第三走线1061的第三目标部分a3偏移设置。第二种实现方式中将第二走 线1041的第二目标部分a2相对于第一走线1021的第一目标部分a1以及第三走线1061的第三目标部分a3偏移设置。
由于第一走线1021的第一目标部分a1相对于第二走线1041的第二目标部分a2靠近衬底基板101，因此制备显示模组时，需要先形成第一目标部分a1之后才形成第二目标部分a2。由此，将第一目标部分a1偏移的方案(第一种实现方式)相对于将第二目标部分a2偏移的方案(第二种实现方式)更容易对位确定第一中轴线和第二中轴线的偏移尺寸，制备精度可以较高。
在本申请实施例中，参考图10，第一走线层102可以包括多条第一走线1021，第二走线层104包括与多条第一走线1021一一对应的多条第二走线1041，第三走线层106包括与多条第二走线1041一一对应的多条第三走线1061。
其中，对于每条第一走线1021，与该第一走线1021对应的第二走线1041，以及与第二走线1041对应的第三走线1061均可以采用本申请实施例提供的方式进行偏移设置。
可选的，多条第一走线1021的第一目标部分a1可以沿第二方向Y等间距排布，多条第二走线1041的第二目标部分a2也可以沿第二方向Y等间距排布，多条第三走线1061的第三目标部分a3也可以沿第二方向Y等间距排布。
其中，多条第一走线1021的第一目标部分a1沿第二方向Y等间距排布可以是指：多条第一走线1021的第一目标部分a1的第一中轴线沿第二方向Y等间距排布。多条第二走线1041的第二目标部分a2沿第二方向Y等间距排布可以是指：多条第二走线1041的第二目标部分a2的第二中轴线沿第二方向Y等间距排布。多条第三走线1061的第三目标部分a3沿第二方向Y等间距排布可以是指：多条第三走线1061的第三目标部分a3的第三种轴线沿第二方向Y等间距排布。
可选的，相邻的两个第一目标部分a1的第一中轴线沿第二方向Y的距离范围可以为2μm至4μm。相邻的两个第二目标部分a2的第二中轴线沿第二方向Y的距离范围可以为2μm至4μm。相邻的两个第三目标部分a3的第三中轴线沿第二方向Y的距离范围可以为2μm至4μm。
另外，参考图10，第一走线1021除第一目标部分a1之外的部分，第二走线1041除第二目标部分a2之外的部分，以及第三走线1061除第三目标部分a3之外的部分可以互不重叠，且具有间距。并且任意相邻的两条走线在衬底基板 101上的正投影之间的距离g1的范围可以为4μm至6μm。
由此第一走线1021的第一目标部分a1的第一中轴线和第二走线1041的第二目标部分a2的第二中轴线的偏移尺寸可以为固定尺寸。也即是，各条第一走线1021的第一目标部分a1的第一中轴线以及对应的第二走线1041的第二目标部分a2的第二中轴线之间的距离可以相等。
例如，多条第一走线1021至少包括第一条第一走线1021和第二条第一走线1021。多条第二走线1041至少包括第一条第二走线1041和第二条第二走线1041。第一条第二走线1041和第一条第一走线1021对应，第二条第二走线1041和第二条第一走线1021对应。第一条第一走线1021的第一中轴线和第一条第二走线1041的第二中轴线之间的距离，与第二条第一走线1021的第一中轴线和第二条第二走线1041的第二中轴线之间的距离相等。
如图14，通过使得各个走线层中的走线按照本申请实施例提供的方式进行设置，可以避免走线虚接或断裂。并且如图15所示，通过使得各个走线层中的走线按照本申请实施例提供的方式进行设置，可以避免第二走线的taper角过大，降低第三走线的爬坡段差。
另外，参考图15，第一走线1021的第一目标部分a1在衬底基板101上的正投影沿第二方向Y的长度约为2.58μm。第二走线1041的第二目标部分a2在衬底基板101上的正投影沿第二方向Y的长度约为2.09μm。第三走线1061的第三目标部分a3在衬底基板101上的正投影沿第二方向Y的长度约为2.61μm。各个走线的目标部分在衬底基板101上的正投影沿第二方向Y的长度可以不同。
在本申请实施例中，显示模组10可以包括触控面板和显示面板。触控面板可以至少包括多条发射电极走线，显示面板至少包括多条栅线和多条数据线。其中，第一走线1021可以为发射电极走线(Tx走线)，第二走线1041可以为栅线(gate线)，第三走线1061可以为数据线(source线)。
需要说明的是，参考图15，可能会由于制备工艺等原因的影响，导致第二走线1041和第三走线1061的边界并不完全平齐。但是不平齐的情况也不会影响本申请实施例的其他相关效果。例如，图15或图16所示的显示模组同样可以避免第三走线1061虚接或断裂。
另外，参考图15，实际产品中，第一走线1021的两个边界坡面可以不是严格的平面，而可以是向靠近衬底基板101的方向凹陷的弧面。第二走线1041以 及第三走线1061远离衬底基板101的表面也可以是凹凸不平的表面。其中，各个走线的表面形貌与制备过程相关，例如可能受到材料，刻蚀工艺，膜层的厚度以及相邻走线之间的绝缘层的厚度的影响。
综上所述，本申请实施例提供了一种显示模组，该显示模组包括第一走线层，第二走线层，第三走线层，位于第一走线层和第二走线层之间的第一绝缘层，以及位于第二走线层和第三走线层之间的第二绝缘层。通过使得第一走线的第一目标部分和第二走线的第二目标部分偏移设置，可以避免第二目标部分的两个边界坡面与第一目标部分的两个边界坡面重叠，进而避免第二目标部分的边界坡面与衬底基板的承载面的夹角过大。进一步的，第三走线的第三目标部分能够在第一目标部分和第二目标部分沿第一方向延伸的边界坡面爬坡，增多了第三目标部分的爬坡位置，从而使得第三目标部分在每个爬坡位置的段差较小。由此，可以避免第三走线虚接或断裂，保证第三走线的稳定性和可靠性，提高显示模组的良率，显示模组的显示效果较好。
图17是本申请实施例提供的一种显示模组的制备方法的流程图。该方法可以用于制备上述实施例所提供的显示模组10。参考图17，该方法可以包括：
步骤S101、提供一衬底基板。
在本申请实施例中，制备显示模组10时，可以先获取一衬底基板101。该衬底基板101可以为玻璃基板，也可以为柔性基板。该衬底基板101可以具有显示区101a以及位于显示区101a的一侧的扇出区101b。
步骤S102、在衬底基板的一侧形成第一走线薄膜，采用第一掩膜对第一走线薄膜进行图案化处理形成第一走线层。
在本申请实施例中，第一掩膜可以具有第一开口，该第一开口可以用于形成第一走线层102的第一走线1021。采用第一掩膜对第一走线薄膜进行图案化处理的过程包括：在第一走线薄膜远离衬底基板101的一侧涂覆一层光刻胶；采用第一掩膜对光刻胶进行曝光；对曝光后的光刻胶进行显影；采用刻蚀液对显影后未被光刻胶保护的第一走线薄膜进行刻蚀；去除剩余光刻胶。
其中，第一走线层102可以位于扇出区101b，第一走线层102包括第一走线1021，且该第一走线1021的第一目标部分a1沿第一方向X延伸。
可选的，显示模组可以包括触控面板，触控面板可以包括发射电极走线， 该第一走线层102中的第一走线1021即可以为触控面板中的发射电极走线。
步骤S103、在第一走线层远离衬底基板的一侧形成第一绝缘层。
在本申请实施例中，形成第一走线层102之后，可以在该第一走线层102远离衬底基板101的一侧形成第一绝缘层103。该第一绝缘层103可以用于将第一走线层102以及后续形成的第二走线层104绝缘。
步骤S104、在第一绝缘层远离衬底基板的一侧形成第二走线薄膜，采用第二掩膜对第二走线薄膜进行图案化处理以形成第二走线层。
在本申请实施例中，采用第二掩膜对第二走线薄膜进行图案化处理的过程包括：在第二走线薄膜远离衬底基板101的一侧涂覆一层光刻胶；采用第二掩膜对光刻胶进行曝光；对曝光后的光刻胶进行显影；采用刻蚀液对显影后未被光刻胶保护的第二走线薄膜进行刻蚀；去除剩余光刻胶。
可选的，第二走线层104可以位于扇出区101b，第二走线层104包括第二走线1041，该第二走线1041的第二目标部分a2沿第一方向X延伸。第二掩膜可以具有第二开口，该第二开口可以用于形成第二走线层104的第二走线1041。第二开口在衬底基板101上的正投影与第一开口在衬底基板101上的正投影部分交叠。由此可以使得第一走线1021的第一目标部分a1在衬底基板101上的正投影与第二走线1041的第二目标部分a2在衬底基板101上的正投影具有部分交叠而成的第一交叠区域b1。
可选的，显示模组10可以包括显示面板，显示控面板可以包括栅线，该第二走线层104中的第二走线1041即可以为显示面板中的栅线。
步骤S105、在第二走线层远离衬底基板的一侧形成第二绝缘层。
在本申请实施例中，形成第二走线层104之后，可以在该第二走线层104远离衬底基板101的一侧形成第二绝缘层105。该第二绝缘层105可以用于将第二走线层104以及后续形成的第三走线层106绝缘。
步骤S106、在第二绝缘层远离衬底基板的一侧形成第三走线薄膜，采用第三掩膜对第三走线薄膜进行图案化处理以形成第三走线层。
在本申请实施例中，采用第三掩膜对第三走线1061薄膜进行图案化处理的过程包括：在第三走线1061薄膜远离衬底基板101的一侧涂覆一层光刻胶；采用第三掩膜对光刻胶进行曝光；对曝光后的光刻胶进行显影；采用刻蚀液对显影后未被光刻胶保护的第三走线1061薄膜进行刻蚀；去除剩余光刻胶。
可选的，第三走线层106可以位于扇出区101b，第三走线层106包括第三走线1061，该第三走线1061的第三目标部分a3沿第一方向X延伸。第三掩膜可以具有第三开口，该第三开口可以用于形成第三走线层106的第三走线1061。
作为第一种可选的实现方式，若上述制备第一走线层102和第二走线层104的过程中，将第一掩膜偏移设置，而未将第二掩膜偏移设置。那么第三掩膜中的第三开口在衬底基板101上的正投影可以与第一掩膜的第一开口在衬底基板101上的正投影部分交叠，且第二开口和第三开口中的一个开口在衬底基板101上的正投影位于另一个开口在衬底基板101上的正投影内。
由此，制备得到的显示模组中，第一走线1021的第一目标部分a1在衬底基板101上的正投影可以与第三走线1061的第三目标部分a3在衬底基板101上的正投影具有部分交叠而成的第二交叠区域b2。该第二交叠区域b2沿第一方向X延伸。并且，第二走线1041和第三走线1061中的一条走线的目标部分在衬底基板101上的正投影位于另一条走线的目标部分在衬底基板101上的正投影内。
作为第二种可选的实现方式，若上述制备第一走线层102和第二走线层104的过程中，将第二掩膜偏移设置，而未将第一掩膜偏移设置。那么第三掩膜中的第三开口在衬底基板101上的正投影可以与第二掩膜的第二开口在衬底基板101上的正投影部分交叠，且第一开口和第三开口中的一个开口在衬底基板101上的正投影位于另一个开口在衬底基板101上的正投影内。
由此，制备得到的显示模组中，第二走线1041的第二目标部分a2在衬底基板101上的正投影可以与第三走线1061的第三目标部分a3在衬底基板101上的正投影具有部分交叠而成的第二交叠区域b2。该第二交叠区域b2沿第一方向X延伸。并且，第一走线1021和第三走线1061中的一条走线的目标部分在衬底基板101上的正投影位于另一条走线的目标部分在衬底基板101上的正投影内。
参考图18，形成在第三走线薄膜上的光刻胶的爬坡角度较小，因此光刻胶的覆盖性能较好。故而在如图19中，在第三走线薄膜的刻蚀过程中，不会发生侧向刻蚀过大引起断线不良或小缺口不良高发的问题，断线或虚接不良得以有效改善。
可选的，显示模组可以包括显示面板，显示控面板可以包括数据线，该第 三走线层106中的第三走线1061即可以为显示面板中的数据线。
在本申请实施例中，从工艺角度来讲，为了使得制备得到的第一走线1021和第二走线1041偏移设置，可以在制备第一走线1021或第二走线1041时，将用于形成第一走线1021的第一掩膜和用于形成第二走线1041的第二掩膜中的一个掩膜相对于另一个掩膜偏移一定距离。此种方式中，无需新设计掩膜版。
从设计角度来讲，可以直接更改第一掩膜的第一开口的设计位置或更改第二掩膜的第二开口的设计位置。此种方式中，需要重新设计掩膜版。
综上所述，本申请实施例提供了一种显示模组的制备方法，该方法制备得到的显示模组包括第一走线层，第二走线层，第三走线层，位于第一走线层和第二走线层之间的第一绝缘层，以及位于第二走线层和第三走线层之间的第二绝缘层。通过使得第一走线的第一目标部分和第二走线的第二目标部分偏移设置，可以避免第二目标部分的两个边界坡面与第一目标部分的两个边界坡面重叠，进而避免第二目标部分的边界坡面与衬底基板的承载面的夹角过大。进一步的，第三走线的第三目标部分能够在第一目标部分和第二目标部分沿第一方向延伸的边界坡面爬坡，增多了第三目标部分的爬坡位置，从而使得第三目标部分在每个爬坡位置的段差较小。由此，可以避免第三走线虚接或断裂，保证第三走线的稳定性和可靠性，提高显示模组的良率，显示模组的显示效果较好。
图20是本申请实施例提供的一种显示装置的结构示意图。参考图20，该显示装置可以包括供电组件20以及如上述实施例所提供的显示面板10。该供电组件20可以用于为显示面板10供电。
可选的，该显示装置可以为：液晶显示装置(liquid crystal display，LCD)、有机发光二极管(organic light-emitting diode，OLED)显示装置、电子纸、低温多晶硅(low temperature poly-silicon，LTPS)显示装置、低温多晶氧化物(low temperature poly-silicon oxide，LTPO)显示装置、氧化物(oxide)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于显示装置可以与前面实施例描述的显示模组具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置的技术效果。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。如本文中使用的“约”或“大约”或“大致相同”包括所陈述的值且意味着在如由本领域普通技术人员考虑到所讨论的测量和与具体量的测量有关的误差(即，测量系统的限制)而确定的对于具体值的可接受的偏差范围内。例如，“约”可意味着相对于所陈述的值的差异在一种或多种标准偏差范围内，或者在±30％、20％、10％、5％范围内。
在附图中，为了清楚，放大了层、膜、面板、区域等的厚度。在本文中参照作为理想化实施方式的示意图的横截面图描述示例性实施方式。这样，将预计到作为例如制造技术和/或公差的结果的与图的形状的偏差。因而，本文中描述的实施方式不应解释为限于如本文中所示的区域的具体形状，而是包括由例如制造所导致的形状方面的偏差。例如，图示或描述为平坦的区域可典型地具有粗糙的和/或非线性的特征。此外，所图示的尖锐的角可为圆形的。因而，图中所示的区域在本质上是示意性的，并且它们的形状不意图图示区域的精确形状，且不意图限制本权利要求的范围。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种显示模组，其特征在于，所述显示模组包括：
    衬底基板(101)，所述衬底基板(101)具有显示区(101a)以及位于所述显示区(101a)的一侧的扇出区(101b)；
    第一走线层(102)，位于所述衬底基板(101)的一侧且位于所述扇出区(101b)，所述第一走线层(102)包括第一走线(1021)，所述第一走线(1021)的第一目标部分(a1)沿第一方向(X)延伸；
    第一绝缘层(103)，位于所述第一走线层(102)远离所述衬底基板(101)的一侧；
    第二走线层(104)，位于所述第一绝缘层(103)远离所述衬底基板(101)的一侧且位于所述扇出区(101b)，所述第二走线层(104)包括与所述第一走线(1021)对应的第二走线(1041)，所述第二走线(1041)的第二目标部分(a2)沿所述第一方向(X)延伸；
    第二绝缘层(105)，位于所述第二走线层(104)远离所述衬底基板(101)的一侧；
    以及第三走线层(106)，位于所述第二绝缘层(105)远离所述衬底基板(101)的一侧且位于所述扇出区(101b)，所述第三走线层(106)包括与所述第二走线(1041)对应的第三走线(1061)，所述第三走线(1061)的第三目标部分(a3)沿所述第一方向(X)延伸；
    其中，所述第一目标部分(a1)在所述衬底基板(101)上的正投影与所述第二目标部分(a2)在所述衬底基板(101)上的正投影具有部分交叠而成的第一交叠区域(b1)，所述第一交叠区域(b1)沿所述第一方向(X)延伸；
    所述第一走线(1021)和所述第二走线(1041)中其中一条走线为第一目标走线，另一条走线为第二目标走线；所述第一目标走线的目标部分在所述衬底基板(101)上的正投影与所述第三目标部分(a3)在所述衬底基板(101)上的正投影具有部分交叠而成的第二交叠区域(b2)，所述第二交叠区域(b2)沿所述第一方向(X)延伸；所述第二目标走线和所述第三走线(1061)中其中一条走线的目标部分在所述衬底基板(101)上的正投影内位于另一条走线的目标部分在所述衬底基板(101)上的正投影内。
  2. 根据权利要求1所述的显示模组，其特征在于，所述第一目标走线为所述第一走线(1021)，所述第二目标走线为所述第二走线(1041)。
  3. 根据权利要求2所述的显示模组，其特征在于，所述第一走线(1021)包括沿所述第一方向(X)延伸的第一边界坡面(d1)和第二边界坡面(d2)，所述第二走线(1041)包括沿所述第一方向(X)延伸的第三边界坡面(d3)和第四边界坡面(d4)；
    所述第三边界坡面(d3)在所述衬底基板(101)上的正投影，所述第一边界坡面(d1)在所述衬底基板(101)上的正投影，所述第四边界坡面(d4)在所述衬底基板(101)上的正投影以及所述第二边界坡面(d2)在所述衬底基板(101)上的正投影沿第二方向(Y)依次排布，所述第二方向(Y)与所述第一方向(X)相交；
    其中，所述第一边界坡面(d1)和所述第二边界坡面(d2)均与所述衬底基板(101)的承载面相交，所述第三边界坡面(d3)和所述第四边界坡面(d4)的延伸面与所述衬底基板(101)的承载面相交。
  4. 根据权利要求3所述的显示模组，其特征在于，所述第三边界坡面(d3)的延伸面和所述衬底基板(101)的承载面之间的夹角，以及所述第四边界坡面(d4)的延伸面和所述衬底基板(101)的承载面之间的夹角的范围均为40度至50度。
  5. 根据权利要求3所述的显示模组，其特征在于，所述第二目标部分(a2)包括位于所述第三边界坡面(d3)和所述第四边界坡面(d4)之间的第一爬坡部(e1)，所述第一爬坡部(e1)在所述衬底基板(101)上的正投影，与所述第一边界坡面(d1)在所述衬底基板(101)上的正投影至少部分重叠。
  6. 根据权利要求5所述的显示模组，其特征在于，所述第三目标部分(a3)包括：第二爬坡部(e2)，第三爬坡部(e3)和第四爬坡部(e4)；
    其中所述第二爬坡部(e2)在所述衬底基板(101)上的正投影与所述第三 边界坡面(d3)在所述衬底基板(101)上的正投影至少部分重叠，所述第三爬坡部(e3)在所述衬底基板(101)上的正投影与所述第一边界坡面(d1)在所述衬底基板(101)上的正投影至少部分重叠，所述第四爬坡部(e4)在所述衬底基板(101)上的正投影与所述第四边界坡面(d4)在所述衬底基板(101)上的正投影至少部分重叠。
  7. 根据权利要求2至6任一所述的显示模组，其特征在于，所述第一目标部分(a1)在所述衬底基板(101)上的正投影具有沿所述第一方向(X)延伸的第一中轴线，所述第二目标部分(a2)在所述衬底基板(101)上的正投影具有沿所述第一方向(X)延伸的第二中轴线，所述第三目标部分(a3)在所述衬底基板(101)上的正投影具有沿所述第一方向(X)延伸的第三中轴线；
    其中，所述第一中轴线和所述第二中轴线平行且间隔设置，所述第二中轴线和所述第三中轴线重叠。
  8. 根据权利要求7所述的显示模组，其特征在于，所述第一中轴线和所述第二中轴线的最小间距，与所述第一目标部分(a1)在所述衬底基板(101)上的正投影沿第二方向(Y)的长度的比值范围为1/8至3/4。
  9. 根据权利要求7或8所述的显示模组，其特征在于，所述第一中轴线和所述第二中轴线的最小间距的范围为0.5微米至1.5微米。
  10. 根据权利要求9所述的显示模组，其特征在于，所述第一中轴线和所述第二中轴线的最小间距为1微米。
  11. 根据权利要求9或10所述的显示模组，其特征在于，所述第一目标部分(a1)在所述衬底基板(101)上的正投影沿第二方向(Y)的长度，所述第二目标部分(a2)在所述衬底基板(101)上的正投影沿所述第二方向(Y)的长度，以及所述第三目标部分(a3)在所述衬底基板(101)上的正投影沿所述第二方向(Y)的长度的范围均为2微米至4微米。
  12. 根据权利要求1至11任一所述的显示模组，其特征在于，所述第一走线层(102)包括多条所述第一走线(1021)，所述第二走线层(104)包括与多条所述第一走线(1021)一一对应的多条所述第二走线(1041)，所述第三走线层(106)包括与多条所述第二走线(1041)一一对应的多条所述第三走线(1061)。
  13. 根据权利要求12所述的显示模组，其特征在于，多条所述第一走线(1021)的第一目标部分(a1)沿第二方向(Y)等间距排布，多条所述第二走线(1041)的第二目标部分(a2)沿所述第二方向(Y)等间距排布，多条所述第三走线(1061)的第三目标部分(a3)沿所述第二方向(Y)等间距排布。
  14. 根据权利要12或13所述的显示模组，其特征在于，多条所述第一走线(1021)至少包括第一条第一走线(1021)和第二条第一走线(1021)，多条所述第二走线(1041)至少包括第一条第二走线(1041)和第二条第二走线(1041)，所述第一条第二走线(1041)和所述第一条第一走线(1021)对应，所述第二条第二走线(1041)和所述第二条第一走线(1021)对应；
    其中，所述第一条第一走线(1021)的第一中轴线和所述第一条第二走线(1041)的第二中轴线之间的距离，与所述第二条第一走线(1021)的第一中轴线和所述第二条第二走线(1041)的第二中轴线之间的距离相等。
  15. 根据权利要求1至14任一所述的显示模组，其特征在于，所述显示模组包括触控面板和显示面板；所述触控面板至少包括多条发射电极走线，所述显示面板至少包括多条栅线和多条数据线；
    其中，所述第一走线(1021)为所述发射电极走线，所述第二走线(1041)为所述栅线，所述第三走线(1061)为所述数据线。
  16. 一种显示模组的制备方法，其特征在于，所述方法包括：
    提供一衬底基板(101)，所述衬底基板(101)具有显示区(101a)以及位于所述显示区(101a)的一侧的扇出区(101b)；
    在所述衬底基板(101)的一侧形成第一走线薄膜，采用第一掩膜对所述第 一走线薄膜进行图案化处理形成第一走线层(102)，所述第一走线层(102)位于所述扇出区(101b)，所述第一走线层(102)包括第一走线(1021)，所述第一走线(1021)的第一目标部分(a1)沿第一方向(X)延伸；
    在所述第一走线层(102)远离所述衬底基板(101)的一侧形成第一绝缘层(103)；
    在所述第一绝缘层(103)远离衬底基板(101)的一侧形成第二走线薄膜，采用第二掩膜对所述第二走线薄膜进行图案化处理以形成第二走线层(104)，所述第二走线层(104)位于所述扇出区(101b)，所述第二走线层(104)包括与所述第一走线(1021)对应的第二走线(1041)，所述第二走线(1041)的第二目标部分(a2)沿所述第一方向(X)延伸；
    在所述第二走线层(104)远离所述衬底基板(101)的一侧形成第二绝缘层(105)；
    在所述第二绝缘层(105)远离所述衬底基板(101)的一侧形成第三走线(1061)薄膜，采用第三掩膜对所述第三走线(1061)薄膜进行图案化处理以形成第三走线层(106)，所述第三走线层(106)包括与所述第二走线(1041)对应的第三走线(1061)，所述第三走线(1061)的第三目标部分(a3)沿所述第一方向(X)延伸；
    其中，所述第一目标部分(a1)在所述衬底基板(101)上的正投影与所述第二目标部分(a2)在所述衬底基板(101)上的正投影具有部分交叠而成的第一交叠区域(b1)，所述第一交叠区域(b1)沿所述第一方向(X)延伸；
    所述第一走线(1021)和所述第二走线(1041)中其中一条走线为第一目标走线，另一条走线为第二目标走线，所述第一目标走线的目标部分在所述衬底基板(101)上的正投影与所述第三目标部分(a3)在所述衬底基板(101)上的正投影具有部分交叠而成的第二交叠区域(b2)，所述第二交叠区域(b2)沿所述第一方向(X)延伸；所述第二目标走线和所述第三走线(1061)中其中一条走线的目标部分在所述衬底基板(101)上的正投影内位于另一条走线的目标部分在所述衬底基板(101)上的正投影内。
  17. 根据权利要求16所述的方法，其特征在于，所述第一掩膜具有第一开口，所述第一开口用于形成所述第一走线(1021)；所述第二掩膜具有第二开口， 所述第二开口用于形成所述第二走线(1041)；所述第三掩膜具有第三开口，所述第三开口用于一条第三走线(1061)；
    所述第一开口在所述衬底基板(101)上的正投影与所述第二开口在所述衬底基板(101)上的正投影部分交叠；所述第一开口在所述衬底基板(101)上的正投影与所述第三开口在所述衬底基板(101)上的正投影部分交叠；
    所述第二开口和所述第三开口中的一个开口在所述衬底基板(101)上的正投影位于另一个开口在所述衬底基板(101)上的正投影内。
  18. 根据权利要求16或17所述的方法，其特征在于，所述显示模组包括触控面板和显示面板；所述触控面板至少包括多条发射电极走线，所述显示面板至少包括多条栅线和多条数据线；
    其中，所述第一走线(1021)为所述发射电极走线，所述第二走线(1041)为所述栅线，所述第三走线(1061)为所述数据线。
  19. 一种显示装置，其特征在于，所述显示装置包括：供电组件(20)以及如权利要求1至15任一所述的显示模组(10)；
    所述供电组件(20)用于为所述显示模组(10)供电。
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