WO2024083240A1 - 信号传输电路、电路板和电子设备 - Google Patents

信号传输电路、电路板和电子设备 Download PDF

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Publication number
WO2024083240A1
WO2024083240A1 PCT/CN2023/125740 CN2023125740W WO2024083240A1 WO 2024083240 A1 WO2024083240 A1 WO 2024083240A1 CN 2023125740 W CN2023125740 W CN 2023125740W WO 2024083240 A1 WO2024083240 A1 WO 2024083240A1
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WIPO (PCT)
Prior art keywords
working
circuit
voltage
level
signal
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PCT/CN2023/125740
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English (en)
French (fr)
Inventor
刘福兴
马甲坤
毛红斌
张楠赓
Original Assignee
上海嘉楠捷思信息技术有限公司
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Priority claimed from CN202211469240.7A external-priority patent/CN117955332A/zh
Application filed by 上海嘉楠捷思信息技术有限公司 filed Critical 上海嘉楠捷思信息技术有限公司
Publication of WO2024083240A1 publication Critical patent/WO2024083240A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output

Definitions

  • the present application relates to the field of signal transmission technology, and in particular to a signal transmission circuit, a circuit board and an electronic device.
  • a computing board in order to improve computing power, a computing board usually places multiple chips on the same circuit board.
  • a computing unit In order to be efficient and energy-saving, a computing unit is usually composed of multiple computing chips.
  • the core voltage power supply of the computing chip is mostly in series power supply mode.
  • Embodiments of the present application provide a signal transmission circuit, a circuit board, and an electronic device to solve or alleviate one or more technical problems in the prior art.
  • the embodiment of the present application provides a signal transmission circuit, including: N-level working circuits connected in series, each working circuit includes at least one working chip, the first-level working circuit is connected to the first system voltage, the N-level working circuit is connected to the second system voltage, the second system voltage is higher than the first system voltage, and the voltage difference between the second system voltage and the first system voltage provides the core working voltage for each level of the working circuit; N-level signal transmission power supply circuits, corresponding to the N-level working circuits one by one, each signal transmission power supply circuit includes at least one power chip, which is used to provide a transmission signal voltage for the working chip in at least one working circuit, wherein N is an integer greater than 1.
  • the core working voltage is the main voltage of the chip, such as the voltage used to provide the chip with operation.
  • the high voltage of the transmission signal input to the working chip is greater than the threshold high voltage
  • the low voltage of the transmission signal input to the working chip is less than the threshold low voltage
  • the core working voltage of the working chip is less than the difference between the transmission signal voltage and the threshold high voltage
  • the working chip includes at least one power supply domain for supplying power to the working chip.
  • the chip provides power for signal transmission.
  • the N-level working circuit includes at least one first working chip, the first working chip includes a first power supply domain and a second power supply domain, and the transmission signal voltage input to the first power supply domain of the first working chip and the transmission signal voltage input to the second power supply domain are both provided by the same signal transmission power supply circuit.
  • the first power supply domain and the second power supply domain of the first working chip are connected inside or outside the first working chip through a transmission line.
  • all working chips in the N-stage working circuit are configured as first working chips.
  • the N-level working circuit also includes at least one second working chip, the second working chip includes a third power supply domain and a fourth power supply domain, and the transmission signal voltage input to the third power supply domain of the second working chip and the transmission signal voltage input to the fourth power supply domain are provided by different signal transmission power supply circuits.
  • the signal transmission voltage input to the third power supply domain of the second working chip is provided by the previous level signal transmission power supply circuit, and the signal transmission voltage input to the fourth power supply domain of the second working chip is provided by the corresponding level signal transmission power supply circuit.
  • the working chips in the first-level working circuit are all configured as first working chips, and the second-level to N-th-level working circuits respectively include at least one first working chip and at least one second working chip.
  • the reference voltages of the working chips in the same level of working circuits are the same, and the reference voltages of the working chips in two adjacent levels of working circuits are different.
  • the reference voltage of each working chip in the (i+1)th level working circuit all comes from the (i)th level working circuit, where i is an integer greater than or equal to 1.
  • the low-level voltage output by the i-th level working circuit is equal to the low-level voltage input by the i+1-th level working circuit, and the low-level voltage output by the i+1-th level working circuit is greater than the low-level voltage input by the i+1-th level working circuit;
  • the high-level voltage output by the i-th level working circuit is equal to the high-level voltage input by the i+1-th level working circuit, and the high-level voltage output by the i+1-th level working circuit is greater than the high-level voltage input by the i+1-th level working circuit.
  • the signal transmission circuit further includes: a signal voltage conversion circuit, which is used to send a control board signal sent by the control board to the N-level working circuit or send a working circuit signal sent by the N-level working circuit to the control board.
  • the first-stage working circuit is used to receive a control board signal
  • the signal voltage conversion circuit is used to send a working circuit signal of the Nth-stage working circuit to the control board.
  • the signal transmission circuit further includes: a pull-up resistor connected in series between two adjacent working circuits, for converting the first high level voltage output by the i-th working circuit into the input voltage of the i+1-th working circuit.
  • a second high level voltage is defined as follows: wherein the second high level voltage is higher than the first high level voltage, and i is a positive integer greater than or equal to 1 and less than or equal to N-1.
  • the third high level voltage output by the (i+1)th stage working circuit is equal to the second high level voltage input by the (i+1)th stage working circuit.
  • the first low level voltage output by the i-th level working circuit is equal to the second low level voltage input by the i+1-th level working circuit, and the second low level voltage output by the i+1-th level working circuit is greater than the second low level voltage input by the i+1-th level working circuit.
  • the reference voltages of the working chips in the same level of working circuits are the same, and the reference voltages of the working chips in two adjacent levels of working circuits are different.
  • the first reference voltage output by the i-th stage working circuit is less than the second reference voltage input by the (i+1)-th stage working circuit.
  • a difference between the first high level voltage and the corresponding first reference voltage is equal to a difference between the second high level voltage and the corresponding second reference voltage.
  • the reference voltage of each working chip in the (i+1)th level working circuit comes from the (i)th level working circuit
  • the reference voltage of each working chip in the first level working circuit comes from the first system voltage
  • the signal transmission circuit also includes: a signal voltage conversion circuit, a first input and output end of the signal voltage conversion circuit is connected to the Nth level working circuit, a second input and output end of the signal voltage conversion circuit is connected to the control board, and the signal voltage conversion circuit is used to convert the control board signal sent by the control board into a voltage and send it to the N-level working circuit; or, the signal voltage conversion circuit is used to convert the working circuit signal sent by the N-level working circuit into a voltage and send it to the control board.
  • the first-stage working circuit is used to receive a control board signal
  • the signal voltage conversion circuit is used to send a working circuit signal of the Nth-stage working circuit to the control board.
  • an embodiment of the present application provides a circuit board, comprising a signal transmission circuit according to any one of the above embodiments of the present application.
  • an embodiment of the present application provides an electronic device, including a circuit board according to the above-mentioned second aspect of the present application.
  • the embodiment of the present application adopts the above-mentioned technical solution to meet the normal transmission of signals of the working chips of the second to Nth level working circuits, thereby realizing the normal transmission of chip signals of multiple working circuits.
  • FIG1 shows a circuit diagram of a signal transmission circuit according to an embodiment of the present application
  • FIG2A shows another circuit diagram of a signal transmission circuit according to an embodiment of the present application
  • FIG2B shows another circuit diagram of a signal transmission circuit according to an embodiment of the present application.
  • FIG3 shows a timing diagram of input signals and output signals of a signal transmission circuit according to an embodiment of the present application
  • FIG4 shows a circuit diagram of a signal transmission circuit according to another embodiment of the present application.
  • FIG5 shows a timing diagram of input signals and output signals of a signal transmission circuit according to another embodiment of the present application.
  • FIG6 shows a circuit diagram of a signal transmission circuit according to yet another embodiment of the present application.
  • FIG. 7 shows a timing diagram of input signals and output signals of a signal transmission circuit according to yet another embodiment of the present application.
  • 10 Signal transmission circuit
  • 100 working circuit
  • 110 working chip
  • 111 first power supply domain
  • 112 second power supply domain
  • 113 third power supply domain
  • 114 fourth power supply domain
  • 200 first system voltage
  • 300 second system voltage
  • 400 signal transmission power supply circuit
  • 410 power chip
  • 500 pull-up resistor
  • 20 Control panel.
  • the signal transmission circuit 10 according to the first embodiment of the present application is described below in conjunction with Figures 1 to 7.
  • FIG1 shows a circuit diagram of a signal transmission circuit 10 according to an embodiment of the present application.
  • the signal transmission circuit 10 includes N-stage working circuits 100 and N-stage signal transmission power supply circuits 400 connected in series.
  • the N-stage working circuits 100 are numbered A 1 , A 2 , A 3 . . . AN-1 , AN respectively.
  • N is an integer greater than 1.
  • Each working circuit 100 includes at least one working chip 110.
  • the working chip 110 can be any of various A computing chip or a control chip, etc., is used to realize the corresponding core functions such as computing functions or control functions.
  • the plurality of working chips 110 can be connected in parallel.
  • three working chips 110 can be included in each level of working circuit 100, and the three working chips 110 in the same level of working circuit 100 are connected in parallel.
  • N levels of working circuits 100 are connected in series.
  • the number of working chips 110 in each level of working circuit 100 may be equal or unequal. It is understandable that the number of working chips 110 in each level of working circuit 100 may be specifically configured according to actual needs to better meet actual applications.
  • each working chip 110 in the current working circuit 100 performs calculations according to the input signal of the current working circuit 100, and generates the output signal of the current working circuit 100 according to the calculation result.
  • the input signal of the current working circuit 100 comes from the output signal of the previous working circuit 100, and the output signal of the current working circuit 100 is output to the next working circuit 100.
  • the first-level working circuit 100A 1 is connected to the first system voltage 200
  • the N-th level working circuit 100A N is connected to the second system voltage 300
  • the second system voltage 300 is higher than the first system voltage 200
  • the voltage difference between the second system voltage 300 and the first system voltage 200 provides the core working voltage for each level of the working circuit 100.
  • the N-stage working circuit 100 is connected in series between the first system voltage 200 and the second system voltage 300.
  • the first system voltage 200 may be a system ground voltage
  • the second system voltage 300 may be a system power supply voltage.
  • the first system voltage 200 may be provided by the ground terminal of the electronic device
  • the second system voltage 300 may be provided by connecting the electronic device to a power supply.
  • the signal transmission direction of the N-stage working circuit 100 is not limited in this embodiment.
  • the signal can be transmitted from A1 to AN , or from AN to A1 .
  • the N-level signal transmission power supply circuits 400 correspond one-to-one to the N-level working circuits 100 .
  • Each signal transmission power supply circuit 400 includes at least one power chip 410 for providing a transmission signal voltage for the working chip 110 in at least one working circuit 100 .
  • the transmission signal voltage can provide auxiliary function voltage for special functions other than the core function of the working circuit 100, for example, as the input/output voltage or clock signal voltage of the working circuit 100.
  • the N-level signal transmission power supply circuits 400 are B1 , B2 , B3 ... BN-1 , BN .
  • B1 is at least connected to A1 to provide at least one transmission signal voltage for A1 ;
  • B2 is at least connected to A2 to provide at least one transmission signal voltage for A2 ...
  • BN is at least connected to AN to provide at least one transmission signal voltage for AN .
  • its power supply end may include a series circuit power supply end, and may also include a signal transmission voltage power supply end, and the number of the signal transmission voltage power supply end may be multiple;
  • the ground terminal thereof is the series port thereof close to the first system voltage 200 connection terminal.
  • the transmission signal high voltage input to the working chip 110 is greater than the threshold high voltage
  • the transmission signal low voltage input to the working chip 110 is less than the threshold low voltage
  • the core working voltage of the working chip 110 is less than the difference between the transmission signal voltage and the threshold high voltage.
  • each level of the working circuit 100 may include a plurality of working chips 110.
  • the plurality of working chips 110 in the first level of the working circuit 100 are C1 to CX
  • the plurality of working chips 110 in the second level of the working circuit 100 are D1 to DY
  • the plurality of working chips 110 in the third level of the working circuit 100 are E1 to EZ , where X, Y and Z are all integers greater than 1.
  • the ground reference point of the signal level of C 1 to C X is the same. If the same power chip 410 is used for power supply, the transmission signal high voltage (IO power supply 1) of C 1 to C X is the same, the transmission signal low voltage (GND) of C 1 to C X is the same, the high level VIOH1 is the same, and the low level VIOL1 is the same.
  • the ground reference point of the signal level of D 1 to D Y is the same. If the same power chip 410 is used for power supply, the transmission signal high voltage (IO power supply 2) of D 1 to D Y is the same, the transmission signal low voltage (GND1) of D 1 to D Y is the same, the high level VIOH2 is the same, and the low level VIOL2 is the same.
  • the ground reference point of the signal level of E 1 to E Z is the same. If the same power chip 410 is used for power supply, the transmission signal high voltage (IO power supply 3) of E 1 to E Z is the same, the transmission signal low voltage (GND2) of E 1 to E Z is the same, the high level VIOH3 is the same, and the low level VIOL3 is the same.
  • the transmission signal high voltage (IO power supply 3) of E 1 to E Z is the same
  • the transmission signal low voltage (GND2) of E 1 to E Z is the same
  • the high level VIOH3 is the same
  • the low level VIOL3 is the same.
  • the signals of C1 ⁇ CX are transmitted normally, and the amplitudes of the input signal and the output signal are equal or similar.
  • the input signals of D1 ⁇ DY are shown in FIG3.
  • the high voltage of the transmission signal input by D1 ⁇ DY is IO power supply 2
  • the high threshold voltage of D1 ⁇ DY is VIOH2
  • the low threshold voltage of D1 ⁇ DY is VIOL2
  • the core working voltage of D1 ⁇ DY is chip power supply 2
  • the reference voltage of D1 ⁇ DY is GND1.
  • the voltage of IO power supply 2 is higher than the high threshold voltage VIOH2, and the voltage of GND is lower than the low threshold voltage VIOL2.
  • the input signal of D1 ⁇ DY is a normal signal 1
  • the signal low level is less than the threshold high voltage VIOL2
  • the input signal of D1 ⁇ DY is a normal signal 0. Since the power supply and signal level ground reference points of D1 ⁇ DY are different from those of C1 ⁇ CX , when D1 ⁇ DY outputs, the power supply level of D1 ⁇ DY is fully output, and the same is true for E1 ⁇ EZ .
  • the technical solution of the embodiment of the present application can meet the normal transmission of signals of the working chips 110 of the second to N-th level working circuits, thereby realizing the normal transmission of chip signals of multiple working circuits 100.
  • the working chip 110 includes at least one power supply domain, and the power supply domain is used to provide signal transmission power to the working chip 110. That is, the working chip 110 may include a power supply domain for providing signal transmission power; or the working chip 110 may also include multiple A power supply domain used to provide power for signal transmission.
  • each power supply domain can be switched on and off independently. For example, when a power supply domain does not need to work, the power supply domain can be turned off to reduce power consumption.
  • different power supply domains in the same working chip 110 can use the same power supply voltage; or, different power supply domains in the same working chip 110 can use different power supply voltages, so that lower voltage can bring lower power consumption.
  • the N-level working circuit 100 includes at least one first working chip, the first working chip includes a first power supply domain 111 and a second power supply domain 112, and the transmission signal voltage input to the first power supply domain 111 of the first working chip and the transmission signal voltage input to the second power supply domain 112 are both provided by the same signal transmission power supply circuit 400, that is, the first power supply domain 111 and the second power supply domain 112 are powered by the same IO.
  • the first power supply domain 111 and the second power supply domain 112 can be used for signal transmission.
  • the transmission signal voltage input to the first power supply domain 111 and the transmission signal voltage input to the second power supply domain 112 can both be provided by the signal transmission power supply circuit 400 corresponding to the working circuit 100 at this level, and the signal transmission power supply circuit 400 at the same level as the first working chip is connected to the first working chip, thereby providing the first power supply domain 111 and the second power supply domain 112 with a transmission signal voltage.
  • the first power supply domain 111 and the second power supply domain 112 use the same power chip 410 to output power.
  • the first power supply domain 111 and the second power supply domain 112 of the first working chip are connected inside or outside the first working chip through a transmission line. That is, the first power supply domain 111 and the second power supply domain 112 can be connected inside the first working chip through a transmission line, and the transmission line can be located inside the first working chip (as shown in FIG. 2A ); or, the first power supply domain 111 and the second power supply domain 112 can be connected outside the first working chip through a transmission line, and the transmission line can be located outside the first working chip (as shown in FIG. 2B ).
  • the transmission line can be a voltage transmission line.
  • the signal transmission power supply circuit 400 may include a first transmission line and a second transmission line.
  • the first transmission line may be connected between the power chip 410 and the working chip 110
  • the second transmission line may be connected between the first power supply domain 111 and the second power supply domain 112 of the first working chip.
  • the second transmission line may be located inside the first working chip or outside the first working chip.
  • the first power supply domain 111 and the second power supply domain 112 can realize signal transmission through the transmission line; on the other hand, the setting position of the transmission line can be flexibly selected according to actual needs, that is, the connection method of the first power supply domain 111 and the second power supply domain 112 can be selected according to actual needs, so as to better meet actual needs.
  • the transmission line may be a voltage transmission line or a signal transmission line.
  • the type of transmission line is selected according to the actual use in the circuit. It should be noted that the number of each transmission line in the drawings of the present specification is only for schematic illustration, and the number of each voltage transmission line and signal transmission line is not limited to 1.
  • all working chips 110 in the N-level working circuit 100 are configured as first working chips.
  • B1 is connected to A1 to provide a transmission signal voltage for the first power supply domain 111 and the second power supply domain 112 of the first working chip in the first-level working circuit 100;
  • B2 is connected to A2 to provide a transmission signal voltage for the first power supply domain 111 and the second power supply domain 112 of the first working chip in the second-level working circuit 100...
  • BN is connected to AN to provide a transmission signal voltage for the first power supply domain 111 and the second power supply domain 112 of the first working chip in the N-level working circuit 100.
  • the N-level working circuit 100 further includes at least one second working chip, the second working chip includes a third power supply domain 113 and a fourth power supply domain 114, and the transmission signal voltage input to the third power supply domain 113 of the second working chip and the transmission signal voltage input to the fourth power supply domain 114 are provided by different signal transmission power supply circuits 400, that is, the third power supply domain 113 and the fourth power supply domain 114 are powered by different IOs.
  • one of the third power supply domain 113 and the fourth power supply domain 114 may be provided by the signal transmission power supply circuit 400 corresponding to the working circuit 100 of this level, and the other of the third power supply domain 113 and the fourth power supply domain 114 may be provided by the signal transmission power supply circuit 400 corresponding to the working circuit 100 of other levels; or, both the third power supply domain 113 and the fourth power supply domain 114 are provided by the signal transmission power supply circuit 400 corresponding to the working circuit 100 of other levels, and the third power supply domain 113 and the fourth power supply domain 114 use different power chips 410 to output power.
  • the signal transmission voltage input to the third power supply domain 113 of the second working chip is provided by the previous level signal transmission power supply circuit 400
  • the signal transmission voltage input to the fourth power supply domain 114 of the second working chip is provided by the corresponding level signal transmission power supply circuit 400.
  • the signal transmission voltage input to the third power supply domain 113 of the second working chip is provided by the first level signal transmission power supply circuit 400
  • the signal transmission voltage input to the fourth power supply domain 114 of the second working chip is provided by the second level signal transmission power supply circuit 400.
  • the signal transmission circuit 10 may further include an isolation circuit/isolation chip.
  • the signal may or may not pass through the isolation circuit/isolation chip.
  • the signal may be transmitted to A1 through the outside or inside of AN , and then transmitted from A1 to the control board.
  • the signal transmission path from A N to A 1 and to the control board refers to the signal dotted line.
  • the signal transmission between adjacent working chips can be transmitted by signal lines or other suitable methods, which are not limited here.
  • the working chips 110 in the first-stage working circuit 100 are all configured as first working chips, and the second-stage to N-stage working circuits 100 respectively include at least one first working chip and at least one second working chip.
  • each stage of the working circuit 100 includes two working chips 110.
  • the two working chips 110 in the first-stage working circuit 100 are both first working chips, and the two working chips 110 in the second-stage to N-stage are respectively the first working chip and the second working chip.
  • the output of the first-stage working circuit 100 is one voltage and one power supply with the input high level of the second-stage working circuit 100
  • the output of the second-stage working circuit 100 is one voltage and one power supply with the input high level of the third-stage working circuit 100
  • the output of the N-1-stage working circuit 100 is one voltage and one power supply with the input high level of the N-stage working circuit 100, so that the full-scale output of the power supply level of the chips of the second-stage to N-stage working circuits 100 can also be satisfied.
  • FIG4 shows that each level of the working circuit 100 includes two working chips 110 for illustrative purposes.
  • an ordinary technician can obviously understand that the solution can be applied to the technical solution of other numbers of working chips 110, which also falls within the scope of protection of the present application.
  • the reference voltages of the working chips 110 in the same level of working circuits 100 are the same, and the reference voltages of the working chips 110 in two adjacent levels of working circuits 100 are different.
  • the reference voltages of C1 - CX are the same, the reference voltages of D1 - DY are the same, the reference voltages of E1 - EZ are the same, and the reference voltages of C1 - CX , D1 - DY , and E1 - EZ are different.
  • the reference voltages of each working chip 110 in the i+1-th level working circuit 100 are all from the i-th level working circuit 100, i is an integer greater than or equal to 1, for example, the reference voltages of each working chip 110 in the second-level working circuit 100 are all from the first-level working circuit 100, the reference voltages of each working chip 110 in the third-level working circuit 100 are all from the second-level working circuit 100, ...
  • the reference voltages of each working chip 110 in the N-th level working circuit 100 are all from the N-1-th level working circuit 100.
  • the reference voltages of each working chip 110 in the first-level working circuit 100 may be from the first system voltage 200.
  • the low level voltage output by the i-th stage working circuit 100 is equal to the low level voltage input by the i+1-th stage working circuit 100, and the low level voltage output by the i+1-th stage working circuit 100 is greater than the low level voltage input by the i+1-th stage working circuit 100.
  • the high level voltage output by the i-th stage working circuit 100 is equal to the high level voltage input by the i+1-th stage working circuit 100, and the high level voltage output by the i+1-th stage working circuit 100 is greater than the high level voltage input by the i+1-th stage working circuit 100.
  • the signal waveform output by the i-th level working circuit 100 may be the same as the signal waveform input by the i+1-th level working circuit 100.
  • the signal waveform output by the first level working circuit 100 is the same as the signal waveform input by the second level working circuit 100.
  • the low level voltage output by the first level working circuit 100 is equal to the low level voltage input by the second level working circuit 100
  • the high level voltage output by the first level working circuit 100 is equal to the high level voltage input by the second level working circuit 100.
  • the signal waveform output by the second-stage working circuit 100 is the same as the signal waveform input by the third-stage working circuit 100.
  • the low-level voltage output by the second-stage working circuit 100 is equal to the low-level voltage input by the third-stage working circuit 100
  • the high-level voltage output by the second-stage working circuit 100 is equal to the high-level voltage input by the third-stage working circuit 100.
  • the signal transmission circuit 10 further includes a signal voltage conversion circuit, which is used to send the control board signal sent by the control board 20 to the N-level working circuit 100.
  • the control board 20 sends its own control board signal to the signal voltage conversion circuit, and the signal voltage conversion circuit can perform voltage conversion on the control board signal and then send it to the N-level working circuit 100; the N-level working circuit 100 works according to the control board signal after voltage conversion, and generates a working circuit signal according to the final working result (such as a calculation result), and sends the working circuit signal to the control board 20.
  • control board 20 sends a control board signal to the signal voltage conversion circuit
  • the signal voltage conversion circuit is used to send the voltage-converted control board signal to the N-th level working circuit 100A N
  • the first level working circuit 100A 1 is used to send the working circuit signal to the control board 20. That is, the signal transmission direction of the N-level working circuit 100 is: transmission from A N to A 1 .
  • the signal voltage conversion circuit can realize parallel transmission of control board signals and working circuit signals between the N-level working circuit 100 and the control board 20, thereby improving working efficiency.
  • the signal voltage conversion circuit may transmit one or more signals, that is, the signal voltage conversion circuit may realize the parallel transmission of multiple control board signals and working circuit signals with different waveforms.
  • the signal voltage conversion circuit is used to send the working circuit signal sent by the N-level working circuit 100 to the control board 20.
  • the control board 20 sends its own control board signal to the N-level working circuit 100; the N-level working circuit 100 works according to the control board signal, and generates a working circuit signal according to the final working result, and then sends the working circuit signal to the signal voltage conversion circuit; the signal voltage conversion circuit converts the working circuit signal into a voltage and sends it to the control board 20.
  • the working circuit signal may be a data signal such as a calculation result
  • the control board signal may be a data signal such as a data source.
  • the N-level working circuit 100 calculates or operates the data source in the control board signal to obtain a calculation result.
  • the first-stage working circuit 100A1 is used to receive the control board signal of the control board 20, and the signal voltage conversion circuit is used to send the working circuit signal of the N-stage working circuit 100AN to the control board 20. That is, the signal transmission direction of the N-stage working circuit 100 is: transmission from A1 to AN .
  • each working chip 110 includes a plurality of power supply domains
  • the signal transmission power supply circuit 400 includes a plurality of sub-power supply transmission circuits, which are respectively connected to the power supply chip 410 and the working chip 110.
  • the sub-power transmission circuits connected between the multiple power supply domains of the same working chip 110 are located inside or outside the corresponding working chip 110.
  • the multiple power supply domains can be connected inside the working chip 110 or outside the working chip 110, so that the connection mode of the power supply domains can be selected according to actual needs while realizing signal transmission.
  • FIG6 shows a circuit diagram of a signal transmission circuit 10 according to an embodiment of the second aspect of the present application.
  • the signal transmission circuit 10 includes N-level working circuits 100, N-level signal transmission power supply circuits 400, and pull-up resistors 500 connected in series.
  • the N-level working circuits 100 are numbered A 1 , A 2 , A 3 . . . AN-1 , AN respectively.
  • N is an integer greater than 1.
  • Each working circuit 100 includes at least one working chip 110, and the working chip 110 can be various computing chips or control chips, etc., to realize corresponding core functions such as computing functions or control functions.
  • the plurality of working chips 110 can be connected in parallel.
  • the number of working chips 110 in each level of working circuit 100 may be equal or unequal. It is understandable that the number of working chips 110 in each level of working circuit 100 may be specifically configured according to actual needs to better meet actual applications.
  • the pull-up resistor 500 is connected in series between two adjacent working circuits 100, and is used to convert the first high-level voltage output by the i-th working circuit 100 into the second high-level voltage input by the i+1-th working circuit 100, wherein the second high-level voltage is higher than the first high-level voltage, and i is a positive integer greater than or equal to 1 and less than or equal to N-1.
  • the level voltage output by the first-stage working circuit 100 when the level voltage output by the first-stage working circuit 100 is 0, the level voltage input to the corresponding second-stage working circuit 100 is 0; when the first high-level voltage output by the first-stage working circuit 100 is z, the second high-level voltage is converted into the second high-level voltage by the pull-up resistor 500 located between the first-stage working circuit 100 and the second-stage working circuit 100, so that the IO power supply 2 is high level.
  • z corresponds to the high-level output.
  • the pull-up resistor 500 can select different values according to the driving current.
  • the third high level voltage output by the i-th stage working circuit 100 is equal to the second high level voltage input by the i-th stage working circuit 100.
  • the high level of the signal input by the same stage working circuit 100 is consistent with the high level of the signal output.
  • the high level voltage output by the first stage working circuit 100 is equal to the high level voltage input by the first stage working circuit 100.
  • the high level voltage output by the second stage working circuit 100 is equal to the high level voltage input by the second stage working circuit 100.
  • the voltage is equal to the high level voltage input to the second stage working circuit 100, and the high level voltage input to the second stage working circuit 100 can be greater than the high level voltage output by the first stage working circuit 100.
  • the high level voltage output by the third stage working circuit 100 is equal to the high level voltage input to the third stage working circuit 100, and the high level voltage output by the third stage working circuit 100 can be greater than the high level voltage output by the second stage working circuit 100.
  • the first low level voltage output by the i-th level working circuit 100 is equal to the second low level voltage input by the i+1-th level working circuit 100, and the second low level voltage output by the i+1-th level working circuit is greater than the second low level voltage input by the i+1-th level working circuit 100.
  • the low level of the signal output by the previous level working circuit 100 is consistent with the low level of the signal input by the next level working circuit 100.
  • the high level of the signal input by the same level working circuit is consistent with the high level of the signal output.
  • the low level voltage output by the first level working circuit 100 is equal to the low level voltage input by the second level working circuit 100.
  • the low level voltage output by the second level working circuit 100 is equal to the low level voltage input by the third level working circuit 100.
  • the low level voltage output by the second level working circuit 100 may be greater than the low level voltage input by the second level working circuit 100.
  • the minimum difference between the second high level voltage and the corresponding threshold voltage is greater than 0V.
  • the threshold high voltage corresponding to the second stage working circuit 100 is VIOH2
  • the threshold low voltage is VIOL2
  • the core working voltage is chip power supply 2
  • the reference voltage is GND2.
  • the second high level voltage is IO power supply 2
  • the minimum difference between IO power supply 2 and the corresponding threshold voltage is the difference between IO power supply 2 and the threshold high voltage VIOH2.
  • the difference between IO power supply 2 and the threshold high voltage VIOH2 is greater than 0V.
  • the reference voltages of the working chips 110 in the same level of working circuits 100 are the same, and the reference voltages of the working chips 110 in two adjacent levels of working circuits 100 are different.
  • the reference voltages of the working chips 110 in the i+1th working circuit 100 are all from the i-th working circuit 100, i is an integer greater than or equal to 1, for example, the reference voltages of the working chips 110 in the second-level working circuit 100 are all from the first-level working circuit 100, the reference voltages of the working chips 110 in the third-level working circuit 100 are all from the second-level working circuit 100...
  • the reference voltages of the working chips 110 in the N-1th working circuit 100 are all from the first system voltage 200.
  • the first reference voltage output by the i-th working circuit may be less than the second reference voltage input by the i+1th working circuit.
  • the difference between the first high-level voltage and the corresponding first reference voltage may be equal to the difference between the second high-level voltage and the corresponding second reference voltage.
  • the signal transmission circuit 10 further includes a signal voltage conversion circuit, wherein the first input and output terminals of the signal voltage conversion circuit are connected to the Nth stage working circuit, and the second input and output terminals of the signal voltage conversion circuit are connected to the Nth stage working circuit.
  • the signal voltage conversion circuit is used to convert the control board signal sent by the control board and send it to the N-level working circuit 100; or, the signal voltage conversion circuit is used to convert the working circuit signal sent by the N-level working circuit and send it to the control board. Therefore, in this embodiment, the signal voltage conversion circuit can realize parallel transmission of the control board signal and the working circuit signal between the N-level working circuit 100 and the control board 20, thereby improving work efficiency.
  • the first-stage working circuit 100 is used to receive a control board signal, and the signal voltage conversion circuit is used to send a working circuit signal of the Nth-stage working circuit 100 to the control board.
  • the circuit board according to the embodiment of the third aspect of the present application includes the signal transmission circuit 10 according to any implementation of the first aspect or the second aspect of the present application.
  • the circuit board may include a substrate, a first system voltage 200 interface and a second system voltage 300 interface, wherein the first system voltage 200 interface and the second system voltage 300 interface are respectively used to connect to the system power supply and the system ground terminal to respectively provide the first system voltage 200 and the second system voltage 300.
  • the substrate is provided with the above-mentioned signal transmission circuit 10.
  • the circuit board may be a computing circuit board, which may also be called a computing power board, to meet the computing power requirements in the fields of artificial intelligence and big data.
  • the electronic device includes the circuit board according to the third aspect of the present application.
  • the electronic device can be a computing device used in high-computation scenarios in the fields of artificial intelligence and big data.
  • circuit board or the electronic device in the above-mentioned embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of “plurality” is two or more, unless otherwise clearly and specifically defined.
  • the terms “installed”, “connected”, “connected”, “fixed” and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; It can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements.
  • installed can be a fixed connection, a detachable connection, or an integral one
  • It can be a mechanical connection, an electrical connection, or a communication
  • it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements.
  • a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them.
  • a first feature being “above”, “above” and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature.
  • a first feature being “below”, “below” and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

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Abstract

本申请实施例提供一种信号传输电路、电路板和电子设备，其中，信号传输电路包括：串联的N级工作电路，各工作电路中包括至少一个工作芯片，第一级工作电路连接于第一系统电压，第N级工作电路连接于第二系统电压；N级信号传输供电电路，与N级工作电路一一对应，各信号传输供电电路中分别包括至少一个电源芯片，用于为至少一个工作电路中的工作芯片提供传输信号电压，其中，N为大于1的整数。本申请实施例的技术方案可以满足第二级至第N级工作电路的工作芯片的信号的正常传输。

Description

信号传输电路、电路板和电子设备
本申请要求于2022年10月20日提交中国专利局、申请号为202211284348.9、名称为“信号传输电路、电路板和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请要求于2022年11月22日提交中国专利局、申请号为202211469240.7、名称为“信号传输电路、电路板和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信号传输技术领域，尤其涉及一种信号传输电路、电路板和电子设备。
背景技术
相关技术中，算力板为了提高算力，通常将多个芯片布局在同一电路板上。为了高效节能，通常由多个运算芯片组成运算单元。运算芯片的核心电压供电多采用串联供电模式。
发明内容
本申请实施例提供一种信号传输电路、电路板和电子设备，以解决或缓解现有技术中的一项或更多项技术问题。
作为本申请实施例的第一方面，本申请实施例提供一种信号传输电路，包括：串联的N级工作电路，各工作电路中包括至少一个工作芯片，第一级工作电路连接于第一系统电压，第N级工作电路连接于第二系统电压，第二系统电压高于第一系统电压，第二系统电压与第一系统电压之间的压差为各级工作电路提供核心工作电压；N级信号传输供电电路，与N级工作电路一一对应，各信号传输供电电路中分别包括至少一个电源芯片，用于为至少一个工作电路中的工作芯片提供传输信号电压，其中，N为大于1的整数。其中，其中，核心工作电压是芯片的主要电压，如用于给芯片提供运算的电压。
在一种实施方式中，所述工作芯片输入的传输信号高电压大于阈值高电压，所述工作芯片输入的传输信号低电压小于阈值低电压，所述工作芯片的核心工作电压小于所述传输信号电压与所述阈值高电压之差。
在一种实施方式中，所述工作芯片包括至少一个供电电源域，用于给所述工作芯 片提供信号传输供电。
在一种实施方式中，N级工作电路中包括至少一个第一工作芯片，第一工作芯片包括第一供电电源域和第二供电电源域，第一工作芯片的第一供电电源域输入的传输信号电压和第二供电电源域输入的传输信号电压均由相同的信号传输供电电路提供。
在一种实施方式中，所述第一工作芯片的第一供电电源域和第二供电电源域通过传输线在所述第一工作芯片内部或外部连接。
在一种实施方式中，N级工作电路中的所有工作芯片均配置为第一工作芯片。
在一种实施方式中，N级工作电路还包括至少一个第二工作芯片，第二工作芯片包括第三供电电源域和第四供电电源域，第二工作芯片的第三供电电源域输入的传输信号电压和第四供电电源域输入的传输信号电压由不同的信号传输供电电路提供。
在一种实施方式中，第二工作芯片的第三供电电源域输入的信号传输电压由前一级信号传输供电电路提供，第二工作芯片的第四供电电源域输入的信号传输电压由对应级的信号传输供电电路提供。
在一种实施方式中，第一级工作电路中的工作芯片均配置为第一工作芯片，第二级至第N级工作电路分别包括至少一个第一工作芯片和至少一个第二工作芯片。
在一种实施方式中，同一级工作电路中的工作芯片的参考电压相同，相邻两级工作电路中的工作芯片的参考电压不同。
在一种实施方式中，第i+1级工作电路中的各工作芯片的参考电压均来自于第i级工作电路，其中，i为大于等于1的整数。
在一种实施方式中，第i级工作电路输出的低电平电压等于第i+1级工作电路输入的低电平电压，所述第i+1级工作电路输出的低电平电压大于所述第i+1级工作电路输入的低电平电压；第i级工作电路输出的高电平电压等于第i+1级工作电路输入的高电平电压，所述第i+1级工作电路输出的高电平电压大于所述第i+1级工作电路输入的高电平电压。
在一种实施方式中，信号传输电路还包括：信号电压转换电路，用于将控制板发送的控制板信号发送给N级工作电路或将N级工作电路发送的工作电路信号发送给控制板。
在一种实施方式中，第一级工作电路用于接收控制板信号，信号电压转换电路用于向控制板发送第N级工作电路的工作电路信号。
在一种实施方式中，信号传输电路还包括：上拉电阻，串联连接于相邻两级工作电路之间，用于将第i级工作电路输出的第一高电平电压转换为第i+1级工作电路输入 的第二高电平电压，其中，所述第二高电平电压高于所述第一高电平电压，i为大于等于1且小于等于N-1的正整数。
在一种实施方式中，所述第i+1级工作电路输出的第三高电平电压等于所述第i+1级工作电路输入的第二高电平电压。
在一种实施方式中，第i级工作电路输出的第一低电平电压等于第i+1级工作电路输入的第二低电平电压，所述第i+1级工作电路输出的第二低电平电压大于所述第i+1级工作电路输入的第二低电平电压。
在一种实施方式中，同一级工作电路中的工作芯片的参考电压相同，相邻两级工作电路中的工作芯片的参考电压不同。
在一种实施方式中，第i级工作电路输出的第一参考电压小于第i+1级工作电路输入的第二参考电压。
在一种实施方式中，第一高电平电压与对应的第一参考电压的差值等于第二高电平电压与对应的第二参考电压的差值。
在一种实施方式中，第i+1级工作电路中的各工作芯片的参考电压均来自于第i级工作电路，第一级工作电路中的各工作芯片的参考电压来自于第一系统电压。
在一种实施方式中，信号传输电路还包括：信号电压转换电路，信号电压转换电路的第一输入输出端连接于第N级工作电路，信号电压转换电路的第二输入输出端连接于控制板，信号电压转换电路用于将控制板发送的控制板信号进行电压转换后发送给N级工作电路；或者，信号电压转换电路用于将N级工作电路发送的工作电路信号进行电压转换后发送给控制板。
在一种实施方式中，第一级工作电路用于接收控制板信号，信号电压转换电路用于向控制板发送第N级工作电路的工作电路信号。
作为本申请实施例的第二方面，本申请实施例提供一种电路板，包括根据本申请上述任一实施方式的信号传输电路。
作为本申请实施例的第三方面，本申请实施例提供一种电子设备，包括根据本申请上述第二方面的电路板。
本申请实施例采用上述技术方案可以满足第二级至第N级工作电路的工作芯片的信号的正常传输，从而实现多个工作电路的芯片信号的正常传输。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本申请进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本申请公开的一些实施方式，而不应将其视为是对本申请范围的限制。
图1示出根据本申请一实施例的信号传输电路的电路图；
图2A示出根据本申请一实施例的信号传输电路的另一个电路图；
图2B示出根据本申请一实施例的信号传输电路的又一个电路图；
图3示出根据本申请一实施例的信号传输电路的输入信号和输出信号的时序图；
图4示出根据本申请另一实施例的信号传输电路的电路图；
图5示出根据本申请另一实施例的信号传输电路的输入信号和输出信号的时序图；
图6示出根据本申请又一实施例的信号传输电路的电路图；
图7示出根据本申请又一实施例的信号传输电路的输入信号和输出信号的时序图。
附图标记说明：
10：信号传输电路；
100：工作电路；110：工作芯片；111：第一供电电源域；112：第二供电电源域；
113：第三供电电源域；114：第四供电电源域；200：第一系统电压；300：第二系统电压；400：信号传输供电电路；410：电源芯片；500：上拉电阻；
20：控制板。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可认识到的那样，在不脱离本申请的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
下面结合图1-图7描述根据本申请第一方面实施例的信号传输电路10。
图1示出根据本申请一实施例的信号传输电路10的电路图。如图1所示，该信号传输电路10包括串联的N级工作电路100以及N级信号传输供电电路400。为了便于说明，如图1所示，N级工作电路100分别编号为A1、A2、A3……AN-1、AN。其中，N为大于1的整数。
其中，各工作电路100中包括至少一个工作芯片110，工作芯片110可以是各种计 算芯片或控制芯片等，以实现相应的计算功能或控制功能等核心功能。在同一级工作电路100中包括多个工作芯片110的情况下，多个工作芯片110可以并联连接。例如，各级工作电路100中可以包括三个工作芯片110，且同一级工作电路100中的三个工作芯片110并联连接。N级工作电路100串联连接。
可选地，各级工作电路100中的工作芯片110的数量可以相等，也可以不相等。可以理解的是，各级工作电路100中的工作芯片110的数量可以根据实际需求具体配置，以更好地满足实际应用。
示例性地，当前级工作电路100中的各工作芯片110，根据当前级工作电路100的输入信号进行计算，并根据计算结果生成当前级工作电路100的输出信号。其中，当前级工作电路100的输入信号来自于前一级工作电路100的输出信号，当前级工作电路100的输出信号输出至下一级工作电路100。
进一步地，结合图1和图2A，第一级工作电路100A1连接于第一系统电压200，第N级工作电路100AN连接于第二系统电压300，第二系统电压300高于第一系统电压200，第二系统电压300与第一系统电压200之间的压差为各级工作电路100提供核心工作电压。
示例性地，N级工作电路100串联于第一系统电压200与第二系统电压300之间。第一系统电压200可以为系统接地电压，第二系统电压300可以为系统电源电压。例如，当N级工作电路100应用于电子设备中时，第一系统电压200可以由电子设备的接地端提供，第二系统电压300可以由电子设备连接电源而提供。
这里，需要说明的是，N级工作电路100的信号传输方向，本实施例并不作限定，例如：可以从A1到AN的方向传输，也可以从AN向A1的方向传输。
N级信号传输供电电路400与N级工作电路100一一对应，各信号传输供电电路400中分别包括至少一个电源芯片410，用于为至少一个工作电路100中的工作芯片110提供传输信号电压。
示例性地，传输信号电压可以为工作电路100的核心功能以外的特殊功能提供辅助功能电压，例如作为工作电路100的输入/输出电压或时钟信号电压等。为了便于说明，N级信号传输供电电路400分别为B1、B2、B3……BN-1、BN。其中，B1至少与A1连接，以为A1提供至少一个传输信号电压；B2至少与A2连接，以为A2提供至少一个传输信号电压……BN至少与AN连接，以为AN提供至少一个传输信号电压。
基于以上说明可知，对于每级工作电路100来说，其供电端可以包括串联电路供电端，也可以包括信号传输电压供电端，且信号传输电压供电端的数量可以是多个； 其接地端即为其靠近第一系统电压200连接端的串联端口。
其中，工作芯片110输入的传输信号高电压大于阈值高电压，工作芯片110输入的传输信号低电压小于阈值低电压，工作芯片110的核心工作电压小于传输信号电压与阈值高电压之差。
例如，在图2A-图3的示例中，各级工作电路100可以包括多个工作芯片110。以前三级工作电路100为例进行说明，第一级工作电路100中的多个工作芯片110分别为C1～CX，第二级工作电路100中的多个工作芯片110分别为D1～DY，第三级工作电路100中的多个工作芯片110分别为E1～EZ，X、Y和Z均为大于1的整数。
C1～CX信号电平的接地参考点相同，如果采用相同的电源芯片410供电，则C1～CX的传输信号高电压(IO供电1)相同，C1～CX的传输信号低电压(GND)相同，高电平VIOH1相同，低电平VIOL1相同。D1～DY信号电平的接地参考点相同，如果采用相同的电源芯片410供电，则D1～DY的传输信号高电压(IO供电2)相同，D1～DY的传输信号低电压(GND1)相同，高电平VIOH2相同，低电平VIOL2相同。同理，E1～EZ信号电平的接地参考点相同，如果采用相同的电源芯片410供电，则E1～EZ的传输信号高电压(IO供电3)相同，E1～EZ的传输信号低电压(GND2)相同，高电平VIOH3相同，低电平VIOL3相同。
结合图3，C1～CX的信号正常传输，输入信号和输出信号的幅度相等或相近。在信号跨级传输时，由于第一级工作电路100和第二级工作电路100中的工作芯片110信号电平的接地参考点不同，D1～DY的输入信号如图3所示。D1～DY输入的传输信号高电压为IO供电2，D1～DY阈值高电压为VIOH2，D1～DY阈值低电压为VIOL2，D1～DY的核心工作电压为芯片供电2，D1～DY的参考电压为GND1。其中，IO供电2的电压高于阈值高电压VIOH2，GND的电压小于阈值低电压VIOL2。
由于信号高电平幅度大于阈值高电压VIOH2，D1～DY的输入信号为正常信号1，信号低电平小于阈值高电压VIOL2，D1～DY的输入信号为正常信号0。由于D1～DY的供电电源和信号电平的接地参考点与C1～CX不同，D1～DY输出时，满足D1～DY的供电电平满量程输出，E1～EZ同理。
根据本申请实施例的信号传输电路10，本申请实施例的技术方案可以满足第二级至第N级工作电路的工作芯片110的信号的正常传输，从而实现多个工作电路100的芯片信号的正常传输。
在一种实施方式中，如图2A和图2B所示，工作芯片110包括至少一个供电电源域，供电电源域用于给工作芯片110提供信号传输供电。也就是说，工作芯片110可以包括一个用于提供信号传输供电的供电电源域；或者，工作芯片110也可以包括多 个用于提供信号传输供电的供电电源域。
示例性地，在工作芯片110的供电电源域为多个的情况下，各供电电源域可以独立开关。例如，在某个供电电源域不需要工作的情况下，可以将该供电电源域关闭，从而降低功耗。另外，同一工作芯片110中不同的供电电源域可以采用相同的供电电压；或者，同一工作芯片110中不同的供电电源域可以采用不同的供电电压，从而更低的电压可以带来更低的功耗。
在一种实施方式中，参照图1-图3，N级工作电路100中包括至少一个第一工作芯片，第一工作芯片包括第一供电电源域111和第二供电电源域112，第一工作芯片的第一供电电源域111输入的传输信号电压和第二供电电源域112输入的传输信号电压均由相同的信号传输供电电路400提供，即第一供电电源域111和第二供电电源域112采用相同的IO供电。
示例性地，第一供电电源域111和第二供电电源域112可以用于信号传输。第一供电电源域111输入的传输信号电压和第二供电电源域112输入的传输信号电压可以均由本级工作电路100对应的信号传输供电电路400提供，与第一工作芯片同级的信号传输供电电路400与第一工作芯片连接，从而为第一供电电源域111和第二供电电源域112提供传输信号电压，此时第一供电电源域111和第二供电电源域112采用相同的电源芯片410输出电源。
在一种实施方式中，如图2A-图4所示，第一工作芯片的第一供电电源域111和第二供电电源域112通过传输线在第一工作芯片内部或外部连接。也就是说，第一供电电源域111和第二供电电源域112可以通过传输线在第一工作芯片内部连接，此时传输线可以位于第一工作芯片内部(如图2A所示)；或者，第一供电电源域111和第二供电电源域112可以通过传输线在第一工作芯片外部连接，此时传输线可以位于第一工作芯片外部(如图2B所示)。其中，传输线可以为电压传输线。
示例性地，信号传输供电电路400可以包括第一传输线和第二传输线。第一传输线可以连接于电源芯片410与工作芯片110之间，第二传输线可以连接于第一工作芯片的第一供电电源域111和第二供电电源域112之间。其中，第二传输线可以位于第一工作芯片的内部，也可以位于第一工作芯片的外部。由此，一方面，第一供电电源域111和第二供电电源域112可以通过传输线实现信号传输；另一方面，可以根据实际需求灵活选择传输线的设置位置，即可以根据实际需求选择第一供电电源域111和第二供电电源域112的连接方式，从而能够更好地满足实际需要。
本领域技术人员可以理解的是，传输线可以为电压传输线，也可以为信号传输线， 根据实际电路中的使用情况对传输线的类型进行选择。需要说明的是，本发明说明书附图中的各传输线数量仅为示意性说明，各电压传输线与信号传输线的数量不限为1。
在一种实施方式中，N级工作电路100中的所有工作芯片110均配置为第一工作芯片。此时B1与A1连接，为第一级工作电路100中的第一工作芯片的第一供电电源域111和第二供电电源域112提供传输信号电压；B2与A2连接，为第二级工作电路100中的第一工作芯片的第一供电电源域111和第二供电电源域112提供传输信号电压……BN与AN连接，为第N级工作电路100中的第一工作芯片的第一供电电源域111和第二供电电源域112提供传输信号电压。如此设置，在实现多个工作电路100的芯片信号的正常传输的同时，信号传输电路10的电路连接简单。
在一种实施方式中，如图4所示，N级工作电路100还包括至少一个第二工作芯片，第二工作芯片包括第三供电电源域113和第四供电电源域114，第二工作芯片的第三供电电源域113输入的传输信号电压和第四供电电源域114输入的传输信号电压由不同的信号传输供电电路400提供，即第三供电电源域113和第四供电电源域114采用不同的IO供电。例如，可以是第三供电电源域113和第四供电电源域114中的其中一个由本级工作电路100对应的信号传输供电电路400提供，第三供电电源域113和第四供电电源域114中的另一个由其他级工作电路100对应的信号传输供电电路400提供；或者，第三供电电源域113和第四供电电源域114均由其他级工作电路100对应的信号传输供电电路400提供，第三供电电源域113和第四供电电源域114采用不同的电源芯片410输出电源。
进一步地，参照图4，第二工作芯片的第三供电电源域113输入的信号传输电压由前一级信号传输供电电路400提供，第二工作芯片的第四供电电源域114输入的信号传输电压由对应级的信号传输供电电路400提供。例如，在第二工作芯片位于第二级工作电路100中的情况下，第二工作芯片的第三供电电源域113输入的信号传输电压由第一级信号传输供电电路400提供，第二工作芯片的第四供电电源域114输入的信号传输电压由第二级信号传输供电电路400提供。
可选地，信号传输电路10还可以包括隔离电路/隔离芯片。其中，信号可经过隔离电路/隔离芯片，也可以不经过隔离电路/隔离芯片。在信号不经过隔离电路/隔离芯片的情况下，信号可以通过AN外部或内部传输至A1，从A1传输至控制板。
如图2A、图2B、图4中，AN至A1以及至控制板的信号传输路径参照如中的信号虚线，此外，相邻工作芯片之间的信号传输可以是信号线来传输，也可以是其他适合的方式，此处不做限定。
在一种实施方式中，结合图4和图5，第一级工作电路100中的工作芯片110均配置为第一工作芯片，第二级至第N级工作电路100分别包括至少一个第一工作芯片和至少一个第二工作芯片。例如，在图4和图5的示例中，各级工作电路100中均包括两个工作芯片110。其中，第一级工作电路100中的两个工作芯片110均为第一工作芯片，第二级至第N级中的两个工作芯片110分别为第一工作芯片和第二工作芯片。其中，第一级工作电路100输出与第二级工作电路100的输入高电平一个电压一个电源，第二级工作电路100输出与第三级工作电路100的输入高电平一个电压一个电源……第N-1级工作电路100输出和第N级工作电路100的输入高电平一个电压一个电源，这样，同样可以满足第二级至第N级工作电路100的芯片的供电电平满量程输出。
图4中显示各级工作电路100中均包括两个工作芯片110用于示例说明的目的，但是普通技术人员在阅读了本申请的技术方案之后，显然可以理解将该方案应用到其它数量的工作芯片110的技术方案中，这也落入本申请的保护范围之内。
在一种实施方式中，同一级工作电路100中的工作芯片110的参考电压相同，相邻两级工作电路100中的工作芯片110的参考电压不同。
示例性地，C1～CX的参考电压相同，D1～DY的参考电压相同，E1～EZ的参考电压相同，且C1～CX、D1～DY、E1～EZ的参考电压不同。其中，第i+1级工作电路100中的各工作芯片110的参考电压均来自于第i级工作电路100，i为大于等于1的整数，例如，第二级工作电路100中的各工作芯片110的参考电压均来自于第一级工作电路100，第三级工作电路100中的各工作芯片110的参考电压均来自于第二级工作电路100……第N级工作电路100中的各工作芯片110的参考电压均来自于第N-1级工作电路100。第一级工作电路100中的各工作芯片110的参考电压可以来自于第一系统电压200。
在一种实施方式中，参照图3，第i级工作电路100输出的低电平电压等于第i+1级工作电路100输入的低电平电压，所述第i+1级工作电路100输出的低电平电压大于所述第i+1级工作电路100输入的低电平电压。第i级工作电路100输出的高电平电压等于第i+1级工作电路100输入的高电平电压，所述第i+1级工作电路100输出的高电平电压大于所述第i+1级工作电路100输入的高电平电压。
示例性地，第i级工作电路100输出的信号波形与第i+1级工作电路100输入的信号波形可以相同。例如，结合图3，在前三级工作电路100中，第一级工作电路100输出的信号波形与第二级工作电路100输入的信号波形相同。其中，第一级工作电路100输出的低电平电压等于第二级工作电路100输入的低电平电压，第一级工作电路100输出的高电平电压等于第二级工作电路100输入的高电平电压。第二级工作电路 100输出的信号波形与第三级工作电路100输入的信号波形相同。其中，第二级工作电路100输出的低电平电压等于第三级工作电路100输入的低电平电压，第二级工作电路100输出的高电平电压等于第三级工作电路100输入的高电平电压。
在一种实施方式中，信号传输电路10还包括信号电压转换电路，信号电压转换电路用于将控制板20发送的控制板信号发送给N级工作电路100。具体地，控制板20将自身的控制板信号发送给信号电压转换电路，信号电压转换电路可以对该控制板信号进行电压转换，然后发送给N级工作电路100；N级工作电路100根据电压转换后的控制板信号进行工作，以及根据最终的工作结果(如计算结果)生成工作电路信号，并向控制板20发送该工作电路信号。
示例性地，控制板20向信号电压转换电路发送控制板信号，信号电压转换电路用于向第N级工作电路100AN发送电压转换后的控制板信号，第一级工作电路100A1用于向控制板20发送工作电路信号。也就是说，N级工作电路100的信号传输方向为：从AN到A1的方向传输。
本实施例中，信号电压转换电路可以在N级工作电路100与控制板20之间，实现控制板信号和工作电路信号并行传输，从而提供工作效率。
需要说明的是，信号电压转换电路传输的信号可以是一个，也可以是多个。也就是说，信号电压转换电路可以实现多路不同波形的控制板信号和工作电路信号的并行传输。
当然，本申请不限于此，在另一种实施方式中，信号电压转换电路用于将N级工作电路100发送的工作电路信号发送给控制板20。具体地，控制板20将自身的控制板信号发送给N级工作电路100；N级工作电路100根据控制板信号工作，并根据最终的工作结果生成工作电路信号，进而向信号电压转换电路发送该工作电路信号；信号电压转换电路对工作电路信号进行电压转换后发送给控制板20。
其中，工作电路信号可以是计算结果等数据信号，控制板信号可以是数据源等数据信号。例如，N级工作电路100对控制板信号中的数据源进行计算或运算，得到计算结果。
示例性地，第一级工作电路100A1用于接收控制板20的控制板信号，信号电压转换电路用于向控制板20发送第N级工作电路100AN的工作电路信号。也就是说，N级工作电路100的信号传输方向为：从A1到AN的方向传输。
在一种实施方式中，如图2A-图4所示，各工作芯片110分别包括多个供电电源域，信号传输供电电路400包括多个子供电传输电路，分别连接于电源芯片410与工作芯 片110之间以及同一工作芯片110的多个供电电源域之间，其中，连接于同一工作芯片110的多个供电电源域之间的子供电传输电路位于对应的工作芯片110的内部或外部。也就是说，多个供电电源域可以通过工作芯片110内部连接，也可以通过工作芯片110外部连接，从而在实现信号传输的同时，可以根据实际需求选择供电电源域的连接方式。
图6示出根据本申请第二方面实施例的信号传输电路10的电路图。如图6所示，该信号传输电路10包括串联的N级工作电路100、N级信号传输供电电路400以及上拉电阻500。为了便于说明，如图6所示，N级工作电路100分别编号为A1、A2、A3……AN-1、AN。其中，N为大于1的整数。
其中，各工作电路100中包括至少一个工作芯片110，工作芯片110可以是各种计算芯片或控制芯片等，以实现相应的计算功能或控制功能等核心功能。在同一级工作电路100中包括多个工作芯片110的情况下，多个工作芯片110可以并联连接。
可选地，各级工作电路100中的工作芯片110的数量可以相等，也可以不相等。可以理解的是，各级工作电路100中的工作芯片110的数量可以根据实际需求具体配置，以更好地满足实际应用。
上拉电阻500串联连接于相邻两级工作电路100之间，用于将第i级工作电路100输出的第一高电平电压转换为第i+1级工作电路100输入的第二高电平电压，其中，第二高电平电压高于第一高电平电压，i为大于等于1且小于等于N-1的正整数。
示例性地，如图7所示，在第一级工作电路100输出的电平电压为0的情况下，对应第二级工作电路100输入的电平电压为0；在第一级工作电路100输出的第一高电平电压为z的情况下，第二高电平电压通过位于第一级工作电路100和第二级工作电路100之间的上拉电阻500将第一高电平电压转换为第二高电平电压，使IO供电2为高电平。其中，z对应高电平输出。类似地，在第二级工作电路100输出的电平电压为0的情况下，对应第三级工作电路100输入的电平电压为0；在第二级工作电路100输出的第一高电平电压为z的情况下，第二高电平电压通过位于第二级工作电路100和第三级工作电路100之间的上拉电阻500将第一高电平电压转换为第二高电平电压，使IO供电3为高电平。其中，上拉电阻500可以根据驱动电流选择不同的值。
在一种实施方式中，第i级工作电路100输出的第三高电平电压等于第i级工作电路100输入的第二高电平电压。例如，在图7的示例中，同一级工作电路100输入的信号高电平与输出的信号高电平一致。具体地，第一级工作电路100输出的高电平电压等于第一级工作电路100输入的高电平电压。第二级工作电路100输出的高电平 电压等于第二级工作电路100输入的高电平电压，且第二级工作电路100输入的高电平电压可以大于第一级工作电路100输出的高电平电压。类似地，第三级工作电路100输出的高电平电压等于第三级工作电路100输入的高电平电压，且第三级工作电路100输出的高电平电压可以大于第二级工作电路100输出的高电平电压。
在一种实施方式中，如图7所示，第i级工作电路100输出的第一低电平电压等于第i+1级工作电路100输入的第二低电平电压，第i+1级工作电路输出的第二低电平电压大于第i+1级工作电路100输入的第二低电平电压。例如，在图7的示例中，前一级工作电路100输出的信号低电平与后一级工作电路100输入的信号低电平一致。具体地，同一级工作电路输入的信号高电平与输出的信号高电平一致。第一级工作电路100输出的低电平电压等于第二级工作电路100输入的低电平电压。第二级工作电路100输出的低电平电压等于第三级工作电路100输入的低电平电压。而且，第二级工作电路100输出的低电平电压可以大于第二级工作电路100输入的低电平电压。
在一种实施方式中，第二高电平电压与对应的阈值电压的最小差值大于0V。例如，在图7的示例中，第二级工作电路100对应的阈值高电压为VIOH2，阈值低电压为VIOL2，核心工作电压为芯片供电2，参考电压为GND2。第二高电平电压为IO供电2，IO供电2与对应的阈值电压的最小差值为IO供电2与阈值高电压为VIOH2的差值。也就是说，IO供电2与阈值高电压为VIOH2的差值大于0V。
在一种实施方式中，同一级工作电路100中的工作芯片110的参考电压相同，相邻两级工作电路100中的工作芯片110的参考电压不同。
其中，第i+1级工作电路100中的各工作芯片110的参考电压均来自于第i级工作电路100，i为大于等于1的整数，例如，第二级工作电路100中的各工作芯片110的参考电压均来自于第一级工作电路100，第三级工作电路100中的各工作芯片110的参考电压均来自于第二级工作电路100……第N级工作电路100中的各工作芯片110的参考电压均来自于第N-1级工作电路100。第一级工作电路100中的各工作芯片110的参考电压可以来自于第一系统电压200。其中，第i级工作电路输出的第一参考电压可以小于第i+1级工作电路输入的第二参考电压。或者，第一高电平电压与对应的第一参考电压的差值可以等于第二高电平电压与对应的第二参考电压的差值。此处的“等于”应当作广义理解，指的是第一高电平电压与对应的第一参考电压的差值和第二高电平电压与对应的第二参考电压的差值在一定的误差范围内相等，而不限于完全相等。
在一种实施方式中，信号传输电路10还包括信号电压转换电路，信号电压转换电路的第一输入输出端连接于第N级工作电路，信号电压转换电路的第二输入输出端连 接于控制板，信号电压转换电路用于将控制板发送的控制板信号进行电压转换后发送给N级工作电路100；或者，信号电压转换电路用于将N级工作电路发送的工作电路信号进行电压转换后发送给控制板。由此，本实施例中，信号电压转换电路可以在N级工作电路100与控制板20之间，实现控制板信号和工作电路信号并行传输，从而提供工作效率。
在一种实施方式中，第一级工作电路100用于接收控制板信号，信号电压转换电路用于向控制板发送第N级工作电路100的工作电路信号。
根据本申请第三方面实施例的电路板，包括根据本申请上述第一方面或第二方面任一实施方式的信号传输电路10。
示例性地，电路板可以包括基板、第一系统电压200接口和第二系统电压300接口，第一系统电压200接口和第二系统电压300接口分别用于与系统电源和系统接地端连接，以分别提供第一系统电压200和第二系统电压300。其中，基板上设置有上述信号传输电路10。其中，该电路板可以为计算电路板，也可以叫做算力板，满足人工智能以及大数据等领域的算力要求。
根据本申请第四方面实施例的电子设备，包括根据本申请上述第三方面实施例的电路板。示例性地，该电子设备可以为计算设备，应用于人工智能以及大数据等领域的高运算量场景下。
上述实施例的电路板或电子设备的其他构成可以采用于本领域普通技术人员现在和未来知悉的各种技术方案，这里不再详细描述。
在本说明书的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体； 可以是机械连接，也可以是电连接，还可以是通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度小于第二特征。
上文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，上文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种信号传输电路，其特征在于，包括：
    串联的N级工作电路，各所述工作电路中包括至少一个工作芯片，第一级工作电路连接于第一系统电压，第N级工作电路连接于第二系统电压，所述第二系统电压高于所述第一系统电压，所述第二系统电压与所述第一系统电压之间的压差为各级工作电路提供核心工作电压；
    N级信号传输供电电路，与N级工作电路一一对应，各所述信号传输供电电路中分别包括至少一个电源芯片，所述信号传输供电电路用于为至少一个所述工作电路中的工作芯片提供传输信号电压，其中，N为大于1的整数。
  2. 根据权利要求1所述的信号传输电路，其特征在于，所述工作芯片输入的传输信号高电压大于阈值高电压，所述工作芯片输入的传输信号低电压小于阈值低电压，所述工作芯片的核心工作电压小于所述传输信号电压与所述阈值高电压之差。
  3. 根据权利要求1所述的信号传输电路，其特征在于，所述工作芯片包括至少一个供电电源域，用于给所述工作芯片提供信号传输供电。
  4. 根据权利要求1所述的信号传输电路，其特征在于，所述N级工作电路中包括至少一个第一工作芯片，所述第一工作芯片包括第一供电电源域和第二供电电源域，所述第一工作芯片的第一供电电源域输入的传输信号电压和所述第二供电电源域输入的传输信号电压均由相同的信号传输供电电路提供。
  5. 根据权利要求4所述的信号传输电路，其特征在于，所述第一工作芯片的第一供电电源域和第二供电电源域通过传输线在所述第一工作芯片内部或外部连接。
  6. 根据权利要求4所述的信号传输电路，其特征在于，所述N级工作电路中的所有工作芯片均配置为第一工作芯片。
  7. 根据权利要求4所述的信号传输电路，其特征在于，所述N级工作电路还包括至少一个第二工作芯片，所述第二工作芯片包括第三供电电源域和第四供电电源域，所述第二工作芯片的第三供电电源域输入的传输信号电压和第四供电电源域输入的传输信号电压由不同的信号传输供电电路提供。
  8. 根据权利要求7所述的信号传输电路，其特征在于，所述第二工作芯片的第三供电电源域输入的信号传输电压由前一级信号传输供电电路提供，所述第二工作芯片的第四供电电源域输入的信号传输电压由对应级的信号传输供电电路提供。
  9. 根据权利要求7所述的信号传输电路，其特征在于，第一级工作电路中的工作芯片均配置为第一工作芯片，第二级至第N级工作电路分别包括至少一个第一工作芯 片和至少一个第二工作芯片。
  10. 根据权利要求1所述的信号传输电路，其特征在于，同一级工作电路中的工作芯片的参考电压相同，相邻两级工作电路中的工作芯片的参考电压不同。
  11. 根据权利要求10所述的信号传输电路，其特征在于，第i+1级工作电路中的各工作芯片的参考电压均来自于第i级工作电路，其中，i为大于等于1的整数。
  12. 根据权利要求10所述的信号传输电路，其特征在于，第i级工作电路输出的低电平电压等于第i+1级工作电路输入的低电平电压，所述第i+1级工作电路输出的低电平电压大于所述第i+1级工作电路输入的低电平电压；
    第i级工作电路输出的高电平电压等于第i+1级工作电路输入的高电平电压，所述第i+1级工作电路输出的高电平电压大于所述第i+1级工作电路输入的高电平电压。
  13. 根据权利要求1-12中任一项所述的信号传输电路，其特征在于，还包括：
    信号电压转换电路，用于将控制板发送的控制板信号发送给所述N级工作电路或将所述N级工作电路发送的工作电路信号发送给所述控制板。
  14. 根据权利要求13所述的信号传输电路，其特征在于，第一级工作电路用于接收所述控制板信号，所述信号电压转换电路用于向所述控制板发送第N级工作电路的工作电路信号。
  15. 根据权利要求1所述的信号传输电路，其特征在于，还包括：
    上拉电阻，串联连接于相邻两级工作电路之间，用于将第i级工作电路输出的第一高电平电压转换为第i+1级工作电路输入的第二高电平电压，其中，所述第二高电平电压高于所述第一高电平电压，i为大于等于1且小于等于N-1的正整数。
  16. 根据权利要求15所述的信号传输电路，其特征在于，所述第i+1级工作电路输出的第三高电平电压等于所述第i+1级工作电路输入的第二高电平电压。
  17. 根据权利要求15所述的信号传输电路，其特征在于，第i级工作电路输出的第一低电平电压等于第i+1级工作电路输入的第二低电平电压，所述第i+1级工作电路输出的第二低电平电压大于所述第i+1级工作电路输入的第二低电平电压。
  18. 根据权利要求15所述的信号传输电路，其特征在于，同一级工作电路中的工作芯片的参考电压相同，相邻两级工作电路中的工作芯片的参考电压不同。
  19. 根据权利要求18所述的信号传输电路，其特征在于，第i级工作电路输出的第一参考电压小于第i+1级工作电路输入的第二参考电压。
  20. 根据权利要求18所述的信号传输电路，其特征在于，所述第一高电平电压与对应的第一参考电压的差值等于所述第二高电平电压与对应的第二参考电压的差值。
  21. 根据权利要求15所述的信号传输电路，其特征在于，第i+1级工作电路中的各工作芯片的参考电压均来自于第i级工作电路，第一级工作电路中的各工作芯片的参考电压来自于第一系统电压。
  22. 根据权利要求15-21中任一项所述的信号传输电路，其特征在于，还包括：
    信号电压转换电路，所述信号电压转换电路的第一输入输出端连接于第N级工作电路，所述信号电压转换电路的第二输入输出端连接于控制板，所述信号电压转换电路用于将所述控制板发送的控制板信号进行电压转换后发送给所述N级工作电路；或者，所述信号电压转换电路用于将所述N级工作电路发送的工作电路信号进行电压转换后发送给所述控制板。
  23. 根据权利要求22所述的信号传输电路，其特征在于，第一级工作电路用于接收所述控制板信号，所述信号电压转换电路用于向所述控制板发送第N级工作电路的工作电路信号。
  24. 一种电路板，其特征在于，包括根据权利要求1-23中任一项所述的信号传输电路。
  25. 一种电子设备，其特征在于，包括根据权利要求24所述的电路板。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090058510A1 (en) * 2007-08-29 2009-03-05 Hynix Semiconductor, Inc. Semiconductor memory device
CN106774767A (zh) * 2016-12-16 2017-05-31 算丰科技（北京）有限公司 串联供电芯片和系统、虚拟数字币挖矿机、及服务器
CN206557766U (zh) * 2017-02-27 2017-10-13 浙江亿邦通信科技股份有限公司 算力板每组芯片级联通信控制装置
CN109104179A (zh) * 2018-06-22 2018-12-28 比飞力（深圳）科技有限公司 一种集成电路和电子设备
CN114201024A (zh) * 2020-09-17 2022-03-18 深圳比特微电子科技有限公司 串联供电电路和虚拟货币挖矿机设备
CN115426838A (zh) * 2022-08-24 2022-12-02 北京嘉楠捷思信息技术有限公司 一种电子设备
CN218499486U (zh) * 2022-08-24 2023-02-17 北京嘉楠捷思信息技术有限公司 一种工作组件和电子设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090058510A1 (en) * 2007-08-29 2009-03-05 Hynix Semiconductor, Inc. Semiconductor memory device
CN106774767A (zh) * 2016-12-16 2017-05-31 算丰科技（北京）有限公司 串联供电芯片和系统、虚拟数字币挖矿机、及服务器
CN206557766U (zh) * 2017-02-27 2017-10-13 浙江亿邦通信科技股份有限公司 算力板每组芯片级联通信控制装置
CN109104179A (zh) * 2018-06-22 2018-12-28 比飞力（深圳）科技有限公司 一种集成电路和电子设备
CN114201024A (zh) * 2020-09-17 2022-03-18 深圳比特微电子科技有限公司 串联供电电路和虚拟货币挖矿机设备
CN115426838A (zh) * 2022-08-24 2022-12-02 北京嘉楠捷思信息技术有限公司 一种电子设备
CN218499486U (zh) * 2022-08-24 2023-02-17 北京嘉楠捷思信息技术有限公司 一种工作组件和电子设备

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