WO2024082578A1 - 一种芯片封装电源网络电磁建模方法及系统 - Google Patents

一种芯片封装电源网络电磁建模方法及系统 Download PDF

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WO2024082578A1
WO2024082578A1 PCT/CN2023/087432 CN2023087432W WO2024082578A1 WO 2024082578 A1 WO2024082578 A1 WO 2024082578A1 CN 2023087432 W CN2023087432 W CN 2023087432W WO 2024082578 A1 WO2024082578 A1 WO 2024082578A1
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decomposition
circuit connection
electromagnetic field
magnetic field
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PCT/CN2023/087432
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English (en)
French (fr)
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代文亮
凌峰
钟章民
蒋历国
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芯和半导体科技（上海）股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation

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  • the present invention belongs to the technical field of chip packaging, and more specifically, relates to a chip packaging power supply network electromagnetic modeling method and system.
  • heterogeneous integration is an advanced technology in the post-Moore era, which makes it possible to achieve higher computing power.
  • heterogeneous integration technology is widely used. Typical examples include AMD's FijiGPU and Nvidia's PascalGPU, where a GPU is connected to four surrounding HBMs through a silicon adapter.
  • Intel and Samsung are also continuously investing in the field of advanced packaging.
  • 2.5D and 3DIC advanced packaging is to use silicon-based boards or chip stacks to interconnect functions that originally required packaging substrates for chip-to-chip interconnection through TSV (through silicon via).
  • TSV through silicon via
  • One of the biggest advantages of 2.5D and 3DIC is the heterogeneity in heterogeneous integration, which actually corresponds to the previous monolithic single-chip integration.
  • the biggest advantage of making monolithic integration heterogeneous is that it is very flexible and can be mixed and matched with different process nodes.
  • Another benefit is that the two dies are directly connected so close together.
  • the wiring density on the silicon substrate can be much higher than on the package, and the chip size can be made smaller, so as to obtain higher signal performance and better thermal performance. This poses new challenges to the electromagnetic field modeling scheme. Especially for the electromagnetic field modeling of the power supply network.
  • the area containing only the signal network can be cut out from the original large-scale data according to the range of the signal routing, and the electromagnetic field modeling can be performed after the range is appropriately expanded to a certain extent. This can meet the accuracy of the electromagnetic field model of the signal within a certain frequency range.
  • the power supply network in advanced packaging, the power supply network is usually completed by grid-shaped power routing, including hole connections between multi-layer routing. Since the power supply network routing basically covers a large range, it is difficult to cut out a small piece according to the routing area for analysis like the signal network, making the electromagnetic field modeling of the power supply network a difficulty in the field of advanced packaging.
  • the existing electromagnetic field modeling scheme for this advanced packaging power supply network is to calculate it equivalently as an algorithm for the RLCK (resistance, inductance, capacitance, mutual inductance) circuit.
  • the advantage of this method is that it can process large-scale data, but the accuracy of high frequency is difficult to guarantee. If the electromagnetic field algorithm is used to model the entire power network, the advantage is that the accuracy can be guaranteed, but the disadvantage is that the time and machine resources required to solve the electromagnetic field for such a large-scale data (holes and micro-bump connections may reach hundreds of thousands) are difficult to meet engineering needs. New technology is needed to quickly and accurately solve the electromagnetic field for the current advanced packaging power network and obtain the electromagnetic field model of the entire power network.
  • Chinese patent application number CN202210036350.8 published on May 27, 2022, discloses a chip packaging electromagnetic modeling system, method and device.
  • the model system includes a design module and a simulation module: the design module completes the chip layout, constructs the chip package and optimizes and improves the chip package according to the simulation result of the chip package to obtain a qualified chip package; the simulation module simulates the chip package in the design environment of the design module and transmits the simulation result to the design module.
  • the disadvantage of this patent is that it cannot balance efficiency and accuracy.
  • Another example is Chinese patent application number CN201710000639.3, published on July 10, 2018.
  • the patent discloses a method for creating a three-dimensional electromagnetic field parametric simulation model, which extracts physical and geometric parameters from the physical layout and automatically creates parametric variables and a three-dimensional electromagnetic field parametric simulation model, and automatically improves the physical layout design after simulation optimization.
  • This method greatly simplifies the modeling and simulation process, improves the speed of modeling and simulation, and thus shortens the time of the entire layout design and simulation analysis process.
  • the shortcoming of this patent is that its accuracy cannot be guaranteed.
  • the present invention provides a chip packaging power supply network electromagnetic modeling method and system.
  • the method of the present invention can greatly reduce the time of subsequent electromagnetic field modeling by decomposing and solving the power supply network, and obtain the required large-scale electromagnetic field model by connecting the decomposed and solved sub-magnetic field models through circuits to ensure accuracy.
  • the system of the present invention has a simple structure, and the modules operate stably, achieving a balance between accuracy and speed in electromagnetic field modeling of large-scale power supply networks.
  • the present invention adopts the following technical solutions.
  • a chip packaging power supply network electromagnetic modeling method comprises the following steps:
  • step S1 includes the following steps:
  • the step S11 also includes judging the decomposition surface. If the decomposition surface is at a via, ubump, bump or plane in the initial power network, the decomposition surface is adjusted outside the above structures so that the decomposition surface is not on these structures.
  • step 2 includes the following steps:
  • step S3 includes the following steps:
  • a system using any one of the above chip packaging power supply network electromagnetic modeling methods comprising:
  • Decomposition module used to decompose the initial power network into several decomposition areas
  • Electromagnetic field solution module used to solve the electromagnetic field in each decomposition area to obtain a sub-magnetic field model
  • Circuit connection module used to connect the sub-magnetic field model to obtain a complete circuit connection
  • Electromagnetic field model generation module used to solve the complete circuit connection and obtain a complete electromagnetic field model.
  • the present invention has the following beneficial effects:
  • the present invention decomposes a large-scale initial power supply network to obtain a number of decomposition regions, which greatly saves computing resources and reduces the time for subsequent electromagnetic field modeling; and solves the several decomposition regions to obtain sub-magnetic field models, and the sub-magnetic field models are connected by circuits to obtain the electromagnetic field model of the final large-scale power supply network required, thereby ensuring the accuracy of the final electromagnetic field model to meet engineering needs; the entire method has higher efficiency and accuracy than the traditional method of directly solving the electromagnetic field of the large-scale initial power supply network;
  • the present invention divides the initial power supply network into several decomposition areas, which is convenient for the smooth progress of subsequent calculation and statistical work.
  • the decomposition surface is geometrically judged so that the decomposition surface avoids some specific structures, ensuring that the decomposition surface is at the location of the wiring connection as much as possible, avoiding problems caused by the connection at the subsequent decomposition surface, and further ensuring the accuracy of the electromagnetic field model generated subsequently;
  • the present invention uses the MOM electromagnetic field simulation engine to solve the electromagnetic field in each decomposition area. This method does not require the setting of a solution space, thereby improving the solution efficiency; and the power network port and the ground network port are set at the decomposition surface, so that they serve as nodes for subsequent circuit connection, further improving the solution accuracy;
  • the system of the present invention decomposes a large-scale power supply network into small areas for solution through decomposition modules, which greatly speeds up the solution speed and reduces computing resources.
  • each area can be solved in parallel to further speed up the solution speed, thereby improving the overall efficiency.
  • the work efficiency of the process is improved; the decomposed area is converted into a sub-magnetic field model through the electromagnetic field solving module, and the final electromagnetic field model is obtained by interconnecting the sub-magnetic field model through circuits.
  • the whole system has a simple structure and the modules run stably, achieving a balance between the accuracy and speed of electromagnetic field modeling for large-scale power supply networks.
  • Fig. 1 is a schematic diagram of the process of the present invention
  • FIG2 is a circuit cascade diagram of a neutron magnetic field model of the present invention.
  • Figure 3 is a comparison of the self-impedance of the electromagnetic field model of the power supply network of 20 ubump ports;
  • FIG4 is an impedance diagram of the electromagnetic field model of the power supply network after merging 20 ubump ports
  • Figure 5 is a comparison diagram of the impedance of the electromagnetic field model of the power supply network after merging 20 ubump ports.
  • a chip package power network electromagnetic modeling method includes the following steps:
  • step S1 Decompose the initial power supply network according to the set grid to obtain a number of decomposition areas; it is worth noting that when decomposing the initial power supply network, the specific number of decomposition areas may depend on the amount of data and resource configuration and other conditions, and the basis for decomposition may be to divide the initial power supply network into rectangular blocks; specifically, step S1 includes the following steps:
  • decomposition surfaces are set on the initial power supply network, and the several decomposition surfaces divide the initial power supply network into several decomposition areas; in this embodiment, the initial power supply network is evenly divided into 6 decomposition areas, and the equal division setting is convenient for calculation and statistics; and in order to further ensure the progress of subsequent work, this step also includes judging the decomposition surface. If the decomposition surface is in a special structure such as a via (a via is a hole on the decomposition surface), ubump (micro-bump), bump (bump) or plane in the initial power supply network, the decomposition surface is adjusted outside the above structures so that the decomposition surface is not on these structures.
  • a via is a hole on the decomposition surface
  • ubump micro-bump
  • bump bump
  • the principle of setting the decomposition surface should try to ensure that it is in the place where the wiring is connected, avoiding the occurrence of vias or plane structures that affect the subsequent connection process, thereby affecting the overall accuracy; and the decomposition surface is judged by geometric judgment, and the split surface is avoided to meet the decomposition action of the design structure, avoiding the decomposition surface from being on a geometric structure that affects the block solution, and the entire judgment is more accurate, reducing the phenomenon of missed judgment or misjudgment;
  • Step S1 decomposes the large-scale initial power supply network into several decomposition areas, which greatly speeds up the solution speed and reduces computing resources; at the same time, each decomposition area can also be solved in parallel to further speed up the solution speed.
  • Table 1 The comparison of computing resources consumed and speed after this step is decomposed into 6 decomposition areas is shown in Table 1:
  • Table 1 Comparison of electromagnetic field modeling resources and efficiency between the original large-scale network direct solution and the regional solution into 6 decomposition regions:
  • the solution resources of each decomposition region are reduced by 6 to 9 times compared with the original large-scale network direct solution, and the time consumption is reduced by about 10 times.
  • the total time consumed by the 6 decomposition regions is 1580s. Even if all 6 decomposition regions are calculated serially, the total time is reduced by 42% compared with the original 2720s. If each decomposition region can be calculated in parallel, the solution time can be reduced exponentially.
  • step 2 Solve the electromagnetic field for each decomposed area to obtain several sub-magnetic field models; it should be noted that traditional electromagnetic field simulation requires huge computing resources for large-scale design and has the disadvantage of long solution time.
  • the FEM solution method is usually used. This solution method requires setting boundaries. The overall design and the design divided into small blocks have different boundary sizes, which will affect the results. If the boundary size of the small block design is set the same as the overall design, the simulation efficiency will not be improved.
  • the FEM method port needs to set a reference. When setting the power network port at the decomposition surface, only the ground network port can be set as a reference. The ground at the decomposition surface needs to be set as a port to connect the circuit of the divided electromagnetic field model. If it is set as a reference, the final result will cause a large accuracy error.
  • step 2 includes the following steps:
  • Each sub-magnetic field model after solution includes the original ubump and the solution port on the bump, as well as the power network port and the ground network port set at the decomposition surface.
  • the MOM electromagnetic field simulation engine does not need to set the solution space.
  • the ground network at the decomposition surface which is usually used as a reference ground, is also set as a normal port to ensure accuracy.
  • step S2 effectively avoids the limitations of the traditional FEM method in solving in different regions, and there is no need to set boundaries. And more importantly, a power network port and a ground network port are set on the decomposition surface of each decomposition area, and the ground network is not set as a reference. Because if the ground network is set as a reference on the decomposition surface, then when the cascade circuit, that is, the subsequent circuit is connected, only the power network is connected, and the ground network is directly used as a reference.
  • the green line in Figure 5 represents the entire initial power network direct electromagnetic field solution; the red line represents the regional decomposition circuit cascade method for the initial power network, but there is only a power network port at the decomposition surface.
  • the impedance of the entire network solution model is 0.11032, and the impedance solved by the regional decomposition circuit cascade is 0.115512, with an error of 4.71%.
  • the error meets the requirements, as shown in Figure 4 below.
  • the green line in Figure 4 represents the direct electromagnetic field solution of the entire initial power network; the red line represents the regional decomposition circuit cascade method for the initial power network, but there are power network ports and ground network interfaces at the decomposition surface.
  • step S3 Conduct circuit connection for each sub-magnetic field model itself, and then conduct circuit connection between two adjacent sub-magnetic field models to form a complete circuit connection; in this step, for each sub-magnetic field model, conduct circuit connection according to its actual physical connection, and the power network port and ground network port set in step S2 are used as nodes for circuit connection to realize the circuit connection between two adjacent sub-magnetic field models, wherein the original ubump and the solution port on the bump remain unchanged as ports.
  • step S3 includes the following steps:
  • S32 The power network port and the ground network interface set at the decomposition surface of each decomposition area are used as nodes for circuit connection to realize the circuit connection between two adjacent sub-magnetic field models, as shown in FIG2 ;
  • the present invention decomposes the large-scale initial power supply network and solves the electromagnetic field for each decomposed area, thereby avoiding the high-frequency accuracy problem of the equivalent RLCK circuit and the efficiency and resource problems of directly solving the electromagnetic field for the entire large-scale network; and by setting the power network port and the ground network port on the decomposition surface to make them nodes for subsequent circuit connection, the accuracy of synthesizing the sub-electromagnetic field model of each decomposed area into the entire large-scale final electromagnetic field model is guaranteed to meet the needs of engineering companies.
  • the present invention also conducted the following result test: the present invention used the electromagnetic field model obtained by the method of this application It is compared with the electromagnetic field model obtained by directly solving the initial power supply network.
  • the electromagnetic field model of the power supply network mainly focuses on the impedance parameters, the C4bump port is short-circuited during the comparison, and the self-impedance at the 20 ubump ports is checked.
  • the accuracy results are shown in Figure 3.
  • the green line in Figure 3 represents the direct solution of the initial power supply network; the red line represents the solution of the present invention, that is, the circuit cascade solution after regional decomposition of the initial power supply network.
  • the impedance comparison of the three curves with the largest errors in Figure 3 at 5GHz is shown in Table 2 below. The case 5Ghz with the smallest error is basically close to 0 error.
  • the electromagnetic field model of the power network obtained by the present application has an error within 10% even at a high frequency of 5 GHz (usually the power network model focuses on a frequency range of 1 to 2 GHz), which can meet engineering needs while greatly saving computing resources. Therefore, compared with the traditional method of directly solving the electromagnetic field of a large-scale initial power network, the present invention has higher efficiency and accuracy.
  • a system using the chip packaging power supply network electromagnetic modeling method as described in the above embodiment 1 comprises:
  • Decomposition module used to decompose the initial power network into several decomposition areas; the basis of the decomposition module can be determined according to the data volume and resource configuration conditions, and the algorithm for decomposing the initial power network is relatively mature, so in this embodiment, the principle of how the decomposition module performs the decomposition operation is no longer described in detail.
  • the basis of decomposition should ensure that the decomposition surface is set at the place where the wiring is connected, to avoid the occurrence of vias or plane structures on the decomposition surface affecting the subsequent connection process, thereby affecting the overall accuracy.
  • Electromagnetic field solution module used to solve the electromagnetic field in each decomposition area to obtain a sub-magnetic field model; the electromagnetic field solution module uses the MOM electromagnetic field simulation engine for solution, which effectively avoids the limitations of the traditional FEM method in sub-regional solution; and in the electromagnetic field solution module, the power network port and the ground network port are automatically set at the decomposition surface of each decomposition area.
  • the power network port and the ground network port serve as nodes for subsequent circuit connections to ensure accuracy and reduce errors.
  • Circuit connection module used to perform circuit connection on the sub-magnetic field model to obtain a complete circuit connection; in the circuit connection module, first the sub-magnetic field itself is circuit connected according to the actual physical connection, and then the two adjacent sub-magnetic field models are connected through the power network port and the ground network port to obtain a complete circuit connection.
  • Electromagnetic field model generation module used to solve the complete circuit connection in the form of circuit simulation to obtain a complete electromagnetic field model.
  • the system of the present invention decomposes a large-scale power supply network into small areas for solution through a decomposition module, which greatly speeds up the solution speed and reduces computing resources.
  • each area can be solved in parallel to further speed up the solution speed, thereby improving the work efficiency of the entire working process.
  • the decomposed area is converted into a sub-magnetic field model through an electromagnetic field solution module, and the final electromagnetic field model is obtained from the sub-magnetic field model through circuit interconnection.
  • high-frequency accuracy can be met.
  • the entire system has a simple structure and the modules operate stably, achieving a balance between accuracy and speed of electromagnetic field modeling for large-scale power supply networks.

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Abstract

本发明公开了一种芯片封装电源网络电磁建模方法及系统，属于芯片封装领域。针对现有对大规模的电源网络进行电磁场建模无法兼顾精度与速度的问题，本发明提供了一种芯片封装电源网络电磁建模方法，它包括对初始电源网络进行分解处理，得到若干个分解区域；对每个分解区域进行电磁场求解，得到若干个子磁场模型；对每个子磁场模型本身进行电路连接，随后再进行相邻两个子磁场模型之间的电路连接，形成完整的电路连接；对完整的电路连接进行电路求解，生成完整的电磁场模型。本发明通过对电源网络进行分解后求解，可以降低时间，对分解求解的子磁场模型通过电路连接的方式得到需要的大规模电磁场模型，保证精度。本发明的系统结构简单，工作稳定。

Description

一种芯片封装电源网络电磁建模方法及系统 技术领域
本发明属于芯片封装技术领域，更具体地说，涉及一种芯片封装电源网络电磁建模方法及系统。
背景技术
随着人工智能、5G、数据中心的不断发展，海量数据的源源不断的产生，传统架构的CPU已经不能满足高性能计算HPC的要求。以异构集成Heterogeneous Integration为代表的先进封装技术是后摩尔时代的一项先进技术，给实现更高的算力提供了可能，在FPGA、GPU、CPU领域，异构集成技术被广泛采用，典型的例子包括AMD的FijiGPU和Nvidia的PascalGPU，一个GPU通过硅转接板和周围的四个HBM连起来。除了TSMC，Intel和三星在先进封装领域也在持续投入。2.5D与3DIC先进封装就是把原来需要封装基板进行芯片间互连的功能采用硅基版或者芯片堆叠通过TSV(through silicon via)来进行互连。2.5D与3DIC其中最大的一个优势是异构集成中的异构，它实际上对应的是以前的monolithic单片集成，单片集成做成异构的最大的一个好处就是非常灵活，可以用不同的工艺节点实现混搭。另外一个好处就是把两个Die靠的这么近直接连起来，布线密度做在硅载板上比在封装上可以大很多，芯片的尺寸可以做的更小，获得更高的信号性能及更好的热性能等。这对电磁场建模方案提出了新的挑战。尤其是对于电源网络的电磁场建模。不同于信号的电磁场建模，可以根据信号走线的范围从原始的大规模数据中截取出只包含信号网络的区域，适当扩大一定范围，再进行电磁场建模，就可以满足在一定频率范围内信号电磁场模型的准确性。对于电源网络，在先进封装中，电源网络通常由网格状电源走线完成，包括多层走线之间的孔连接。由于电源网络走线基本覆盖很大的范围，难以像信号网络一样根据走线区域截取出一小块进行分析，使得电源网络的电磁场建模成为先进封装领域里的一个难点。现有的针对这种先进封装电源网络的电磁场建模方案是将其等效计算为RLCK(电阻，电感，电容，互感)的电路的算法，这种方式的优点是可以处理大规模的数据，但是高频的精度方面难以保证。如果利用电磁场的算法对整个电源网络进行建模，优点是可以保证精度，缺点是对于如此大规模的数据(孔和微凸点连接可能达到几十万个)进行电磁场的求解时间和机器资源很难保证工程上的需要。需要新的技术能够针对现在的先进封装电源网络进行快速准确的电磁场求解，得到整个电源网络的电磁场模型。
如中国专利申请号CN202210036350.8，公开日为2022年5月27日，该专利公开了一种芯片封装电磁建模系统、方法和装置。一种芯片封装电磁建模系统，所述的芯片封装电磁建 模系统包括设计模块和仿真模块：所述设计模块完成芯片布局，建构芯片封装并根据所述芯片封装的仿真结果优化改进所述芯片封装，得到合格芯片封装；所述仿真模块在所述设计模块的设计环境中对所述芯片封装进行仿真模拟，将所述仿真结果传递给所述设计模块。该专利的不足之处在于：效率与精度无法进行很好的兼顾。
又如中国专利申请号CN201710000639.3，公开日为2018年7月10日，该专利公开了一种三维电磁场参数化仿真模型的创建方法，它采用从物理版图中提取物理和几何参数并自动创建参数化变量和三维电磁场参数化仿真模型，并经过仿真优化后自动完善物理版图设计的完整方法，极大的简化了建模和仿真流程，提高了建模和仿真的速度，由此缩短了整个版图设计和仿真分析流程的时间。该专利的不足之处在于：其精度无法得到保障。
发明内容
1、要解决的问题
针对现有对大规模的电源网络进行电磁场建模无法兼顾精度与速度的问题，本发明提供一种芯片封装电源网络电磁建模方法及系统。本发明的方法通过对电源网络进行分解后求解，可以极大的降低后续电磁场建模的时间，对分解求解的子磁场模型通过电路连接的方式得到需要的大规模电磁场模型，保证精度。本发明的系统构成简单，各模块之间运行稳定，实现了对于大规模电源网络的电磁场建模精度与速度的同时兼顾。
2、技术方案
为解决上述问题，本发明采用如下的技术方案。
一种芯片封装电源网络电磁建模方法，包括以下步骤：
S1：对初始电源网络进行分解处理，得到若干个分解区域；
S2：对每个分解区域进行电磁场求解，得到若干个子磁场模型；
S3：对每个子磁场模型本身进行电路连接，随后再进行相邻两个子磁场模型之间的电路连接，形成完整的电路连接；
S4：对完整的电路连接进行电路求解，生成完整的电磁场模型。
更进一步的，所述步骤S1包括如下步骤：
S11：在初始电源网络上设置有若干个分解面，若干个分解面将初始电源网络均分为若干个分解区域；
S12：每个分解区域对应的电源网络中的ubump和bump上设置求解端口。
更进一步的，所述步骤S11中还包括对分解面进行判断，若分解面处于初始电源网络中的过孔、ubump、bump或平面处时，则将分解面调节至上述这些结构之外以使得分解面不处于这些结构上。
更进一步的，步骤2包括如下步骤：
S21：对每个分解区域进行增加电源网络端口和地网络端口，电源网络端口和地网络端口设置在该分解区域的分解面处；
S22：利用MOM电磁场仿真引擎对每个分解区域进行电磁场求解，得到若干个子磁场模型。
更进一步的，所述步骤S3包括如下步骤：
S31：对每个子磁场模型本身，按照实际的物理连接进行电路连接；
S32：每个分解区域的分解面处设置的电源网络端口和地网络接口作为电路连接的节点，实现相邻两个子磁场模型之间的电路连接；
S33：依次进行相邻两个子磁场模型之间的电路连接，形成最终完整的电路连接。
更进一步的，对完整的电路连接采用电路仿真的求解方式得到最终的完整的电磁场模型
一种应用如上述任一项所述的芯片封装电源网络电磁建模方法的系统，包括：
分解模块：用于对初始电源网络进行分解成若干个分解区域；
电磁场求解模块：用于对每个分解区域进行电磁场求解，得到子磁场模型；
电路连接模块：用于对子磁场模型进行电路连接，得到完整的电路连接；
电磁场模型生成模块：用于对完整的电路连接进行求解，得到完整的电磁场模型。
3、有益效果
相比于现有技术，本发明的有益效果为：
(1)本发明通过对大规模的初始电源网络进行分解处理得到若干个分解区域，大大节省了计算资源，降低了后续电磁场建模的时间；并且对若干个分解区域进行求解得到子磁场模型，子磁场模型通过电路连接的方式得到最终需要的大规模电源网络的电磁场模型，保证最终电磁场模型的准确性，以满足工程上的需求；整个方法相比于传统直接对大规模的初始电源网络进行电磁场求解而言，具有更高的效率和精度；
(2)本发明对初始电源网络进行均分成若干个分解区域，便于计算和统计后续工作的顺利进行，同时对分解面进行几何判断的方式使得分解面避免一些特定结构，保证分解面尽可能处于走线连接的位置，避免后续分解面处的连接造成问题，进一步保障后续生成的电磁场模型的精度；本发明利用MOM电磁场仿真引擎对每个分解区域进行电磁场求解，此种方式不需要设置求解空间，提高求解效率；并且在分解面处设置电源网络端口和地网络端口，使其作为后续电路连接的节点，进一步提高求解精度；
(3)本发明的系统通过分解模块将大规模的电源网络分解成小区域求解，大大加快求解速度，降低计算资源，并且各区域可以采用并行求解，进一步加快求解速度，继而提高整个 过程的工作效率；通过电磁场求解模块将分解区域转换成子磁场模型，由子磁场模型通过电路互连的方式得到最终的电磁场模型，相对于传统RLCK等效电路方案，可以满足高频的准确性；整个系统构成简单，各模块之间运行稳定，实现了对于大规模电源网络的电磁场建模精度与速度的同时兼顾。
附图说明
图1为本发明的流程示意图；
图2为本发明中子磁场模型电路级联图；
图3为20个ubump端口电源网络电磁场模型自阻抗对比图；
图4为20个ubump端口合并后电源网络电磁场模型阻抗图；
图5为20个ubump端口合并后电源网络电磁场模型阻抗对比图。
具体实施方式
下面结合具体实施例和附图对本发明进一步进行描述。
实施例1
如图1所示，一种芯片封装电源网络电磁建模方法，包括以下步骤：
S1：对初始电源网络根据设定的网格进行分解处理，得到若干个分解区域；在这值得说明的是，对初始电源网络进行分解处理时，分解成具体多少区域可视数据量大小以及资源配置等条件而定，分解的基准可以为对初始电源网络进行矩形分块；具体的，步骤S1包括如下步骤：
S11：在初始电源网络上设置有若干个分解面，若干个分解面将初始电源网络均分为若干个分解区域；在本实施例中将初始电源网络平均分为6个分解区域，均分的设置便于计算和统计；并且为了进一步保障后续工作的进行，该步骤还包括对分解面进行判断，若分解面处于初始电源网络中的过孔(过孔即孔处于分解面上)、ubump(微凸块)、bump(凸点)或平面处等特殊结构时，则将分解面调节至上述这些结构之外以使得分解面不处于这些结构上，分解面设置的原则应尽量保证其处于走线连接的地方，避免出现过孔或平面结构影响后续连接过程，从而影响整体精度；并且采用几何判断的方式对分解面进行判断，将分割面进行避开以满足设计结构的分解动作，避免了分解面处于影响分块求解的几何结构上，整个判断较为准确，减少出现漏判或误判的现象；
S12：每个分解区域对应的电源网络中的ubump和bump上设置求解端口；
步骤S1对大规模的初始电源网络进行分解为若干个分解区域，大大加快了求解速度，降低计算资源；同时每个分解区域还可以采用并行求解的方式进一步达到加快求解速度的目的。该步骤分解为6个分解区域后消耗的计算资源和速度的对比如表1所示：
表1：原始大规模网络直接求解和分区域求解为6个分解区域的电磁场建模资源和效率对比：
从表1可以看出，区域分解后，各个分解区域的求解资源相对于原始大规模网络直接求解，消耗内存资源降低6～9倍，消耗时间降低10倍左右。6个分解区域消耗的总时间为1580s，即使考虑所有6个分解区域串行计算，总时间也比原始的2720s降低42％。如果考虑各个分解区域可以进行并行计算，求解时间可以指数级减少。
S2：对每个分解区域进行电磁场求解，得到若干个子磁场模型；在这进行说明的是，传统的电磁场仿真对大规模设计需要计算资源巨大，且求解时间长的缺点，且传统采用分块再进行级联时，通常采用FEM的求解方式，此种求解方式需要设置边界，整体设计和分成小块的设计设置边界大小不同结果会产生影响，如果小块设计边界大小设置和整体设计一样，并不能改善仿真效率。并且FEM方式端口需要设置参考，在分解面处设置电源网络端口时，只能将地网络端口设置为参考，分解面处需要对地也设置为端口来对分块的电磁场模型进行电路连接，如果设置为参考，最终结果会造成精度误差较大；。具体的，步骤2包括如下步骤：
S21：对每个分解区域进行增加电源网络端口和地网络端口，该分解区域内的求解端口保持不变(譬如芯片的微凸点端口，C4凸点端口)，电源网络端口和地网络端口设置在该分解区域的分解面处，一改往日将地网络端口作为参考的方式，直接在每个分解区域的分解面对电源网络的截面设置端口，地网络截面也设置端口用来与其他分解区域的分解面的地网络进行连接，不作为参考，有效提高整个精度；
S22：利用MOM电磁场仿真引擎对每个分解区域进行电磁场求解，得到若干个子磁场模型，求解后的每个子磁场模型包括原始的ubump和bump上的求解端口，以及在分解面处设置的电源网络端口和地网络端口；采用MOM电磁场仿真引擎的方式则不需要设置求解空间， 并且分解面处的通常作为参考地的地网络也设置成正常端口，能够保证精度。
步骤S2中采用MOM的求解方式有效的避免了传统FEM方式在分区域求解方面的局限性，无需设置边界。并且更重要的是，在每个分解区域的分解面上设置有电源网络端口和地网络端口，不将地网络设置为参考。因为如果在分解面将地网络设置参考，然后级联电路即后续电路连接时，只有电源网络进行连接，地网络直接作为参考，这种情况下将20个ubump端口合并在一起看整体的这个芯片封装电源网路设计的阻抗效果时，可以看到，在5GHz处，整个网络求解模型阻抗是0.03007，区域分解电路级联求解出的阻抗是0.068721，误差不能满足要求，如图5所示，图5中绿色线条代表整个初始的电源网络直接电磁场求解；红色线条代表对初始的电源网络进行区域分解电路级联方式，但分解面处只有电源网络端口。而采用本申请的方式，将20个ubump端口合并在一起看整体的这个芯片封装电源网路设计的阻抗效果，可以看到，在5GHz处，整个网络求解模型阻抗是0.11032，区域分解电路级联求解出的阻抗是0.115512，误差4.71％，误差满足要求，如下图4所示，图4中绿色线条代表整个初始的电源网络直接电磁场求解；红色线条代表对初始的电源网络进行区域分解电路级联方式，但分解面处有电源网络端口和地网络接口。
S3：对每个子磁场模型本身进行电路连接，随后再进行相邻两个子磁场模型之间的电路连接，形成完整的电路连接；在该步骤中，对于每个子磁场模型而言，依据其实际的物理连接进行电路连接，步骤S2中设置的电源网络端口和地网络端口作为电路连接的节点，实现相邻两个子磁场模型之间电路的连接，其中，原有的ubump和bump上的求解端口仍然作为端口保持不变。具体的，步骤S3包括如下步骤：
S31：对每个子磁场模型本身，按照实际的物理连接进行电路连接；
S32：每个分解区域的分解面处设置的电源网络端口和地网络接口作为电路连接的节点，实现相邻两个子磁场模型之间的电路连接，如图2所示；
S33：依次进行相邻两个子磁场模型之间的电路连接，形成最终完整的电路连接。
S4：对完整的电路连接进行电路求解，生成完整的电磁场模型。在该步骤中对完整的电路连接采用电路仿真的求解方式得到最终的完整的电磁场模型，电路仿真求解速度快且精度高。
本发明通过对大规模的初始的电源网络进行分解操作，对每个分解区域进行电磁场求解，避免了等效RLCK电路的高频精度问题和直接对整个大规模网络进行电磁场求解的效率和资源问题；并且通过在分解面上设置电源网络端口和地网络端口使其作为后续电路连接的节点，保证每个分解区域的子电磁场模型合成整个大规模的最终的电磁场模型的准确性，满足工程商的需求。同时本发明还做了如下结果试验：本发明将通过本申请的方式得到的电磁场模型 和对初始的电源网络直接求解得到的电磁场模型进行对比。因为电源网络的电磁场模型主要关注阻抗参数，因此在进行对比的时候将C4bump端口短路，查看20个ubump端口处的自阻抗，其精度结果如图3所示，图3中绿色线条代表对初始的电源网络直接求解；红色线条代表本发明的方案，即对初始的电源网络进行区域分解后电路级联求解。将图3中误差最大的三条曲线在5GHz处的阻抗比较如下表2所示，误差最小的case 5Ghz基本是接近0误差。
表2初始电源网络直接求解和进行区域分解后电路级联求解在5GHz处的阻抗比较
由表2可知，利用本申请得到的电源网络的电磁场模型即使到5GHz的高频处(通常电源网络模型关注频率范围在1～2GHz以内)，误差也在10％范围以内，可以满足工程需要的同时大大节省计算资源。因此本发明相比于传统直接对大规模的初始电源网络进行电磁场求解而言，具有更高的效率和精度。
实施例2
一种应用如上述实施例1所述的芯片封装电源网络电磁建模方法的系统，包括：
分解模块：用于对初始电源网络进行分解成若干个分解区域；分解模块的基准可以视数据量大小以及资源配置等条件情况而定，并且对初始电源网络进行分解的算法已经相对比较成熟，因此，在本实施例中不再对分解模块如何进行分解操作的原理进行详细说明。分解的基准则应保证分解面设置在处于走线连接的地方，避免分解面出现过孔或平面结构影响后续连接过程，从而影响整体精度。
电磁场求解模块：用于对每个分解区域进行电磁场求解，得到子磁场模型；该电磁场求解模块中采用MOM电磁场仿真引擎进行求解，有效的避免了传统FEM方式在分区域求解方面的局限性；并且在该电磁场求解模块中还对每个分解区域的分解面处自动设置电源网络端口和地网络端口，电源网络端口和地网络端口作为后续电路连接的节点，保证精度，减小误差。
电路连接模块：用于对子磁场模型进行电路连接，得到完整的电路连接；在电路连接模块，首先子磁场自身按照实际的物理连接进行电路连接，随后相邻两个子磁场模型之间通过电源网络端口和地网络端口进行连接，得到完整的电路连接。
电磁场模型生成模块：用于对完整的电路连接以电路仿真的形式进行求解，得到完整的电磁场模型。
本发明的系统通过分解模块将大规模的电源网络分解成小区域求解，大大加快求解速度，降低计算资源，并且各区域可以采用并行求解，进一步加快求解速度，继而提高整个工作过程的工作效率；通过电磁场求解模块将分解区域转换成子磁场模型，由子磁场模型通过电路互连的方式得到最终的电磁场模型，相对于传统RLCK等效电路方案，可以满足高频的准确性；整个系统构成简单，各模块之间运行稳定，实现了对于大规模电源网络的电磁场建模精度与速度的同时兼顾。
本发明所述实例仅仅是对本发明的优选实施方式进行描述，并非对本发明构思和范围进行限定，在不脱离本发明设计思想的前提下，本领域工程技术人员对本发明的技术方案作出的各种变形和改进，均应落入本发明的保护范围。

Claims (5)

  1. 一种芯片封装电源网络电磁建模方法，其特征在于：包括以下步骤：
    S1：对初始电源网络进行分解处理，得到若干个分解区域；所述步骤S1包括如下步骤：
    S11：在初始电源网络上设置有若干个分解面，若干个分解面将初始电源网络均分为若干个分解区域；
    S12：每个分解区域对应的电源网络中的ubump和bump上设置求解端口；
    S2：对每个分解区域进行电磁场求解，得到若干个子磁场模型；步骤2包括如下步骤：
    S21：对每个分解区域进行增加电源网络端口和地网络端口，电源网络端口和地网络端口设置在该分解区域的分解面处；
    S22：利用MOM电磁场仿真引擎对每个分解区域进行电磁场求解，得到若干个子磁场模型；
    S3：对每个子磁场模型本身进行电路连接，随后再进行相邻两个子磁场模型之间的电路连接，形成完整的电路连接；
    S4：对完整的电路连接进行电路求解，生成完整的电磁场模型。
  2. 根据权利要求1所述的一种芯片封装电源网络电磁建模方法，其特征在于：所述步骤S11中还包括对分解面进行判断，若分解面处于初始电源网络中的过孔、ubump、bump或平面处时，则将分解面调节至上述这些结构之外以使得分解面不处于这些结构上。
  3. 根据权利要求1所述的一种芯片封装电源网络电磁建模方法，其特征在于：所述步骤S3包括如下步骤：
    S31：对每个子磁场模型本身，按照实际的物理连接进行电路连接；
    S32：每个分解区域的分解面处设置的电源网络端口和地网络接口作为电路连接的节点，实现相邻两个子磁场模型之间的电路连接；
    S33：依次进行相邻两个子磁场模型之间的电路连接，形成最终完整的电路连接。
  4. 根据权利要求1或3所述的一种芯片封装电源网络电磁建模方法，其特征在于：对完整的电路连接采用电路仿真的求解方式得到最终的完整的电磁场模型。
  5. 一种应用如权利要求1-4任一项权利要求所述的芯片封装电源网络电磁建模方法的系统，其特征在于：包括：
    分解模块：用于对初始电源网络进行分解成若干个分解区域；
    电磁场求解模块：用于对每个分解区域进行电磁场求解，得到子磁场模型；
    电路连接模块：用于对子磁场模型进行电路连接，得到完整的电路连接；
    电磁场模型生成模块：用于对完整的电路连接进行求解，得到完整的电磁场模型。
PCT/CN2023/087432 2022-10-21 2023-04-11 一种芯片封装电源网络电磁建模方法及系统 WO2024082578A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007249642A (ja) * 2006-03-16 2007-09-27 Nec Corp 電磁界解析装置
CN112329303A (zh) * 2020-11-03 2021-02-05 西安电子科技大学 基于有限元区域分解的阵列天线电磁特性求解方法
CN114021517A (zh) * 2021-12-09 2022-02-08 芯和半导体科技(上海)有限公司 一种集成电路版图仿真方法、计算机设备和存储介质
CN114547854A (zh) * 2022-01-13 2022-05-27 芯和半导体科技(上海)有限公司 一种芯片封装电磁建模系统、方法和装置
CN115358173A (zh) * 2022-10-21 2022-11-18 芯和半导体科技(上海)有限公司 一种芯片封装电源网络电磁建模方法及系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5125768B2 (ja) * 2008-05-29 2013-01-23 富士通株式会社 電源網解析装置、電源網解析方法及び電源網解析プログラム
CN101739473B (zh) * 2008-10-22 2011-11-09 盛群半导体股份有限公司 电路模拟仿真系统
CN107526887B (zh) * 2017-08-22 2020-02-18 电子科技大学 一种基于GPU并行的LeapfrogADI-FDTD方法
JP7218666B2 (ja) * 2019-04-26 2023-02-07 富士通株式会社 設計方法、および設計プログラム
US10831938B1 (en) * 2019-08-14 2020-11-10 International Business Machines Corporation Parallel power down processing of integrated circuit design
JP7228840B2 (ja) * 2019-09-24 2023-02-27 日本電信電話株式会社 解析装置、解析方法及び解析プログラム
CN114117989A (zh) * 2020-08-31 2022-03-01 长鑫存储技术有限公司 一种芯片的设计方法、设计装置、计算机设备及存储介质
CN114117872B (zh) * 2022-01-24 2022-06-14 广州中望龙腾软件股份有限公司 一种多gpu并行的时域有限差分电磁仿真方法、设备及介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007249642A (ja) * 2006-03-16 2007-09-27 Nec Corp 電磁界解析装置
CN112329303A (zh) * 2020-11-03 2021-02-05 西安电子科技大学 基于有限元区域分解的阵列天线电磁特性求解方法
CN114021517A (zh) * 2021-12-09 2022-02-08 芯和半导体科技(上海)有限公司 一种集成电路版图仿真方法、计算机设备和存储介质
CN114547854A (zh) * 2022-01-13 2022-05-27 芯和半导体科技(上海)有限公司 一种芯片封装电磁建模系统、方法和装置
CN115358173A (zh) * 2022-10-21 2022-11-18 芯和半导体科技(上海)有限公司 一种芯片封装电源网络电磁建模方法及系统

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