WO2024078091A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

Info

Publication number
WO2024078091A1
WO2024078091A1 PCT/CN2023/109156 CN2023109156W WO2024078091A1 WO 2024078091 A1 WO2024078091 A1 WO 2024078091A1 CN 2023109156 W CN2023109156 W CN 2023109156W WO 2024078091 A1 WO2024078091 A1 WO 2024078091A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
level
switch
driving circuit
pixel driving
Prior art date
Application number
PCT/CN2023/109156
Other languages
English (en)
French (fr)
Inventor
樊涛
袁海江
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2024078091A1 publication Critical patent/WO2024078091A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Definitions

  • the present application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel.
  • OLED Organic Light Emitting Diode
  • the driving circuit of the OLED display panel is driven by a DC power supply, and a separate power line provides a DC voltage to each pixel.
  • the power line itself has a certain degree of internal resistance, and due to the instability of the OLED display panel manufacturing process and technical limitations, the thickness of the power line in different areas may vary, resulting in different voltage drops of the pixel driving voltage in each area, thereby causing uneven brightness of the OLED display panel.
  • the threshold voltage of the driving transistor of each pixel unit in the OLED display panel may be different, which may cause the current of the light emitting diode in each pixel unit to be inconsistent, resulting in uneven brightness of the OLED display panel.
  • the present application provides a pixel driving circuit and a display panel to improve the uneven display phenomenon of the display panel.
  • the present application provides a pixel driving circuit, wherein the working phases of the pixel driving circuit include a sampling phase and a data writing phase, and the pixel driving circuit includes:
  • a scan line is used to provide a scan voltage, the scan voltage is a first level in a sampling phase and a second level in a data writing phase;
  • a data line is used to provide a data voltage, the data voltage is a high level in a sampling phase, and is a low level in a data writing phase;
  • a capacitor comprising a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being electrically connected to the data line in both a sampling phase and a data writing phase;
  • a driving transistor wherein the driving transistor includes a gate terminal, a source terminal and a drain terminal, the source terminal is electrically connected to the scan line, the gate terminal is electrically connected to the second capacitor terminal, and the drain terminal is used to be electrically connected to the gate terminal in a sampling phase and disconnected from the gate terminal in a data writing phase.
  • the source terminal of the driving transistor is electrically connected to the scanning line, and the gate terminal of the driving transistor is electrically connected to the data line through a capacitor.
  • the drain terminal of the driving transistor is controlled to be electrically connected to the gate terminal in the sampling stage, so that the driving transistor forms a diode-like structure and reaches a balanced state.
  • the driving current is independent of the threshold voltage VTH, thereby reducing or even eliminating the influence of the threshold voltage VTH on the driving current, thereby improving the uneven display of the display panel.
  • the driving current is independent of the threshold voltage VTH, thereby reducing or even eliminating the influence of the threshold voltage VTH on the driving current, thereby improving the uneven display of the display panel.
  • the pixel driving circuit provided in the present application may not be provided with a power line, but a scanning line is used instead of a power line to provide voltage to the pixel driving circuit, which has a good improvement effect on reducing the voltage drop of the pixel driving voltage in each area of the display panel, and is conducive to further improving the display uniformity of the display panel.
  • the working phase of the pixel driving circuit further includes a light-emitting phase, the scanning voltage is at the first level in the light-emitting phase, and the data voltage is at the low level in the light-emitting phase;
  • the pixel driving circuit also includes a light-emitting diode, which has a positive terminal and a negative terminal.
  • the negative terminal is grounded, and the positive terminal is used to be disconnected from the drain terminal in both the sampling stage and the data writing stage; the positive terminal is used to be electrically connected to the drain terminal in the light-emitting stage.
  • the pixel driving circuit further includes a switch module, one end of which is electrically connected to the data line, and the other end of which is electrically connected to the first capacitor end.
  • the switch module is used to be turned on during the sampling stage and the data writing stage, and to be turned off during the light emitting stage.
  • the switch module includes a first switch, the first switch includes a first control end, a first end and a second end, the first end is electrically connected to the data line, and the second end is electrically connected to the first capacitor end;
  • the pixel driving circuit also includes a first control signal line, which is electrically connected to the first control end.
  • the first control signal line is used to provide a first control voltage.
  • the first control voltage is a third level in the sampling stage and the data writing stage, and the first control voltage is a fourth level in the light emitting stage.
  • One of the third level and the fourth level is a high level, and the other is a low level.
  • the switch module includes a second switch and a third switch
  • the second switch includes a second control end, a third end and a fourth end
  • the third switch includes a third control end, a fifth end and a sixth end
  • the third end and the fifth end are both electrically connected to the data line, and the fourth end and the sixth end are both electrically connected to the first capacitor end;
  • the second control terminal is electrically connected to the scan line
  • the pixel driving circuit also includes a second control signal line
  • the third control terminal is electrically connected to the second control signal line
  • the second control signal line is used to provide a second control voltage
  • the second control voltage is a fifth level in the sampling stage
  • the second control voltage is a sixth level in the data writing stage and the light emitting stage
  • one of the fifth level and the sixth level is a high level
  • the other is a low level.
  • the pixel driving circuit also includes a fourth switch, the fourth switch includes a fourth control terminal, a seventh terminal and an eighth terminal, the seventh terminal is electrically connected to the gate terminal, the eighth terminal is electrically connected to the drain terminal, and the fourth control terminal is electrically connected to the second control signal line.
  • the pixel driving circuit further includes a fifth switch, the fifth switch includes a fifth control terminal, a ninth terminal and a tenth terminal, the ninth terminal is electrically connected to the drain terminal, and the tenth terminal is electrically connected to the positive terminal;
  • the pixel driving circuit also includes a third control signal line, the fifth control end is electrically connected to the third control signal line, the third control signal line is used to provide a third control voltage, the third control voltage is a seventh level in the sampling stage and the data writing stage, the third control voltage is an eighth level in the light emitting stage, one of the seventh level and the eighth level is a high level, and the other is a low level.
  • the driving transistor and the second switch are P-type thin film transistors
  • the third switch, the fourth switch and the fifth switch are N-type thin film transistors
  • the fifth level is a high level
  • the sixth level is a low level
  • the seventh level is a low level
  • the eighth level is a high level.
  • the driving transistor, the second switch, the third switch, the fourth switch and the fifth switch are P-type thin film transistors, the fifth level is a low level, the sixth level is a high level, the seventh level is a high level, and the eighth level is a low level.
  • the present application provides a display panel including the pixel driving circuit.
  • FIG1 is a circuit diagram of a pixel driving circuit provided in Embodiment 1 of the present application.
  • FIG2 is a timing diagram of a pixel driving circuit provided in Embodiment 1 of the present application.
  • FIG. 3 is a circuit diagram of a pixel driving circuit provided in Embodiment 2 of the present application.
  • FIG4 is a circuit diagram of a pixel driving circuit provided in Embodiment 3 of the present application.
  • FIG5 is a timing diagram of a pixel driving circuit provided in Embodiment 3 of the present application.
  • FIG. 6 is a circuit structure diagram of a display panel provided in Embodiment 4 of the present application.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate component, or the internal communication of two components.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate component, or the internal communication of two components.
  • AMOLED Active-matrix organic light emitting diode
  • ⁇ -si TFT technology is not suitable for AMOLED driving due to its poor stability and low carrier mobility
  • LTPS is considered to be the most suitable TFT technology for AMOLED driving because of its best stability and highest carrier mobility among the three.
  • LTPS low temperature polycrystalline silicon
  • the internal resistance of the power line may cause the thickness of the power line in different areas to vary, resulting in different voltage drops of the pixel driving voltage in each area; the threshold voltage of the driving transistor of each pixel unit in the OLED display panel will be different; as the driving time of the driving transistor goes by, the driving transistor material will age and mutate, causing the threshold voltage of the driving transistor to drift, etc., which will cause uneven display of the OLED display panel, and this display unevenness will become more serious with the passage of driving time and the aging of the driving transistor material.
  • the present application provides a pixel driving circuit 100 that can improve the uneven display of an OLED display panel.
  • the working phases of the pixel driving circuit 100 include a sampling phase T1 and a data writing phase T2.
  • the pixel driving circuit 100 includes a scan line 101 , a data line 102 , a capacitor 20 and a driving transistor 30 .
  • the scan line 101 is used to provide a scan voltage.
  • the scan voltage is at a first level in the sampling phase T1 and at a second level in the data writing phase T2.
  • One of the first level and the second level is a high level, and the other is a low level.
  • the data line 102 is used to provide a data voltage.
  • the data voltage is at a high level in the sampling phase T1 and at a low level in the data writing phase T2.
  • the capacitor 20 includes a first capacitor terminal 21 and a second capacitor terminal 22 .
  • the first capacitor terminal 21 is electrically connected to the data line 102 in both the sampling phase T1 and the data writing phase T2 .
  • the driving transistor 30 includes a gate terminal 31, a source terminal 32 and a drain terminal 33.
  • the source terminal 32 is electrically connected to the scan line 101
  • the gate terminal 31 is electrically connected to the second capacitor terminal 22
  • the drain terminal 33 is used to be electrically connected to the gate terminal 31 in the sampling phase T1 and disconnected from the gate terminal 31 in the data writing phase T2.
  • the scanning voltage provided by the scanning line 101 is a first level.
  • the first level is a high level. In other embodiments, the first level can also be a low level.
  • the data voltage provided by the data line 102 is a high level.
  • the first capacitor terminal 21 is electrically connected to the data line 102 in the sampling phase T1, so the voltage VA at the first capacitor terminal 21 is VDATA.
  • the driving transistor 30 is a P-type thin film transistor.
  • the drain terminal 33 in the driving transistor 30 is electrically connected to the gate terminal 31 during the sampling phase T1, so that the driving transistor 30 forms a diode-like structure, and the voltage in the driving transistor 30 is in a balanced state.
  • the present application does not limit how the first capacitor terminal 21 is electrically connected to the data line 102 and how the drain terminal 33 is electrically connected to the gate terminal 31 in the sampling phase T1 of the pixel driving circuit 100 , which will be described in detail below.
  • the scanning voltage is at the second level.
  • the second level is a low level.
  • the second level can also be a high level.
  • the driving current generated by the driving transistor is expressed as:
  • ⁇ carrier mobility
  • W channel width
  • L channel length
  • CGI gate capacitance
  • VTH threshold voltage
  • W and L are fixed in design
  • the driving current expression generated by the driving transistor 30 can be simplified as follows:
  • the driving current generated by the driving transistor 30 of the present application is ultimately determined only by ⁇ , W, L, CGI, and the data voltage VDATA.
  • the source terminal 32 of the driving transistor 30 is electrically connected to the scanning line 101, and the gate terminal 31 of the driving transistor 30 is electrically connected to the data line 102 through the capacitor 20.
  • the drain terminal 33 of the driving transistor 30 is controlled to be electrically connected to the gate terminal in the sampling stage T1, so that the driving transistor 30 forms a diode-like structure and reaches a balanced state.
  • the voltage VG of the gate terminal 31 is VSC-VTH.
  • the drain terminal 33 of the driving transistor 30 is controlled to be disconnected from the gate terminal 31, and the data line 102 jumps from a high level to a low level.
  • the driving current formula of the subsequent light-emitting stage T3 it can be seen that the driving current is independent of the threshold voltage VTH, thereby reducing or even eliminating the influence of the threshold voltage VTH on the driving current, thereby improving the uneven display phenomenon of the display panel.
  • the voltage drop transmitted to the light-emitting device is larger.
  • the pixel driving circuit 100 provided in the present application may not be provided with a power line, but a scanning line 101 is used to replace the power line to provide a voltage to the pixel driving circuit 100, which has a good improvement effect on reducing the voltage drop of the pixel driving voltage in each area of the display panel, and is conducive to further improving the display uniformity of the display panel.
  • the working phase of the pixel driving circuit 100 further includes a light emitting phase T3 , in which the scan voltage is at a first level and the data voltage is at a low level.
  • the pixel driving circuit 100 further includes a light emitting diode 40, which has a positive terminal 41 and a negative terminal 42.
  • the negative terminal 42 is grounded, and the positive terminal 41 is used to be disconnected from the drain terminal 33 in both the sampling phase T1 and the data writing phase T2.
  • the positive terminal 41 is used to be electrically connected to the drain terminal 33 in the light emitting phase T3.
  • the driving current generated by the driving transistor 30 is independent of the threshold voltage VTH of the driving transistor 30, reducing or even eliminating the influence of the threshold voltage VTH on the driving current, thereby stabilizing the current flowing through the light-emitting diode 40, ensuring uniform brightness of the light-emitting diode 40, and improving the display effect of the picture.
  • the pixel driving circuit 100 further includes a switch module, one end of the switch module is electrically connected to the data line 102, and the other end is electrically connected to the first capacitor terminal 21, and the switch module is used to be turned on in the sampling phase T1 and the data writing phase T2.
  • the electrical connection between the data line 102 and the first capacitor terminal 21 includes but is not limited to the following implementations.
  • the switch module includes a first switch 50
  • the first switch 50 includes a first control terminal 51 , a first terminal 52 and a second terminal 53
  • the first terminal 52 is electrically connected to the data line 102
  • the second terminal 53 is electrically connected to the first capacitor terminal 21 .
  • the pixel driving circuit 100 also includes a first control signal line 103, the first control terminal 51 is electrically connected to the first control signal line 103, the first control signal line 103 is used to provide a first control voltage, the first control voltage is a third level in the sampling stage T1 and the data writing stage T2, the first control voltage is a fourth level in the light emitting stage T3, one of the third level and the fourth level is a high level, and the other is a low level.
  • the first control voltage is at a third level in the sampling phase T1 and the data writing phase T2, and the first switch 50 is in an on state, so that the data line 102 is electrically connected to the first capacitor terminal 21.
  • the first control voltage is at a fourth level in the light emitting phase T3, and the first switch 50 is in an off state, so that the data line 102 is electrically disconnected from the first capacitor terminal 21.
  • the switch module includes a second switch 60 and a third switch 70
  • the second switch 60 includes a second control terminal 61, a third terminal 62 and a fourth terminal 63
  • the third switch 70 includes a third control terminal 71, a fifth terminal 72 and a sixth terminal 73.
  • the third terminal 62 and the fifth terminal 72 are both electrically connected to the data line 102
  • the fourth terminal 63 and the sixth terminal 73 are both electrically connected to the first capacitor terminal 21.
  • the second control terminal 61 is electrically connected to the scan line 101.
  • the pixel driving circuit 100 also includes a second control signal line 104.
  • the third control terminal 71 is electrically connected to the second control signal line 104.
  • the second control signal line 104 is used to provide a second control voltage.
  • the second control voltage is at a fifth level in the sampling stage T1.
  • the second control voltage is at a sixth level in the data writing stage T2 and the light emitting stage T3.
  • One of the fifth level and the sixth level is a high level, and the other is a low level.
  • the second control terminal 61 is electrically connected to the scan line 101.
  • the scan voltage is at the first level in the sampling phase T1, and the second switch 60 is disconnected.
  • the second control voltage is at the fifth level in the sampling phase T1, and the third switch 70 is turned on.
  • the scan voltage is at the second level in the data writing phase T2, and the second switch 60 is turned on. That is, it is ensured that the data line 102 is electrically connected to the first capacitor terminal 21 in the sampling phase T1 and the data writing phase T2.
  • the scan voltage is at the first level in the light-emitting stage T3, the second switch 60 is turned off, the second control voltage is at the sixth level in the light-emitting stage T3, the third switch 70 is turned off, that is, the data line 102 is electrically disconnected from the first capacitor terminal 21 in the light-emitting stage T3.
  • the pixel driving circuit 100 further includes a fourth switch 80 , the fourth switch 80 includes a fourth control terminal 81 , a seventh terminal 82 , and an eighth terminal 83 , the seventh terminal 82 is electrically connected to the gate terminal 31 , the eighth terminal 83 is electrically connected to the drain terminal 33 , and the fourth control terminal 81 is electrically connected to the second control signal line 104 .
  • the second control voltage is at the fifth level in the sampling phase T1, the fourth switch 80 is turned on, and the gate terminal 31 is electrically connected to the drain terminal 33, so that the voltage VG of the gate terminal 31 in the sampling phase T1 is equal to VSCAN-VTH.
  • the second control voltage is at the sixth level in the data writing phase T2 and the light emitting phase T3, and the fourth switch 80 is turned off.
  • the pixel driving circuit 100 further includes a fifth switch 90 , which includes a fifth control terminal 91 , a ninth terminal 92 and a tenth terminal 93 , wherein the ninth terminal 92 is electrically connected to the drain terminal 33 , and the tenth terminal 93 is electrically connected to the positive terminal 41 .
  • a fifth switch 90 which includes a fifth control terminal 91 , a ninth terminal 92 and a tenth terminal 93 , wherein the ninth terminal 92 is electrically connected to the drain terminal 33 , and the tenth terminal 93 is electrically connected to the positive terminal 41 .
  • the pixel driving circuit 100 also includes a third control signal line 105, the fifth control terminal 91 is electrically connected to the third control signal line 105, and the third control signal line 105 is used to provide a third control voltage.
  • the third control voltage is a seventh level in the sampling stage T1 and the data writing stage T2, and the third control voltage is an eighth level in the light emitting stage.
  • One of the seventh level and the eighth level is a high level, and the other is a low level.
  • the third control voltage is at the seventh level in the sampling stage T1 and the data writing stage T2, the fifth switch 90 is disconnected, and no voltage and current pass through the light emitting diode 40; the third control voltage is at the eighth level in the light emitting stage T3, the fifth switch 90 is turned on, and the light emitting diode 40 is turned on.
  • the drain terminal 33 can be electrically connected to the positive terminal 41 and provide a driving current to the positive terminal 41 to drive the light emitting diode 40 to emit light.
  • the fifth control terminal 91 is electrically connected to the first control signal line 103, and the first control signal line 103 is used to provide a first control voltage.
  • the first control voltage is at a third level in the sampling phase T1 and the data writing phase T2, and the first control voltage is at a fourth level in the light emitting phase T3, and one of the third level and the fourth level is a high level, and the other is a low level.
  • the first control voltage is at the third level in the sampling stage T1 and the data writing stage T2, the fifth switch 90 is disconnected, and no voltage and current pass through the light-emitting diode 40; the first control voltage is at the fourth level in the light-emitting stage T3, the fifth switch 90 is turned on, so that the drain terminal 33 can be electrically connected to the positive terminal 41, and a driving current is provided to the positive terminal 41 to drive the light-emitting diode 40 to emit light.
  • the first control signal line 103 and the third control signal line 105 are merely signal lines with the same function in different implementations. For the convenience of description, they are named separately, which should not be construed as a limitation to the present application.
  • the fifth level includes but is not limited to a high level or a low level
  • the sixth level includes but is not limited to a high level or a low level
  • the seventh level includes but is not limited to a high level or a low level
  • the eighth level includes but is not limited to a high level or a low level.
  • the level conditions of the fifth level, the sixth level, the seventh level and the eighth level need to be determined according to the thin film transistor types of the third switch 70, the fourth switch 80 and the fifth switch 90.
  • the driving transistor 30 and the second switch 60 are P-type thin film transistors
  • the third switch 70, the fourth switch 80 and the fifth switch 90 are N-type thin film transistors (such as triodes, field effect transistors)
  • the fifth level is a high level
  • the sixth level is a low level
  • the seventh level is a low level
  • the eighth level is a high level.
  • the second control voltage is at the fifth level in the sampling stage T1, the fifth level is a high level, and the third switch 70 is an N-type thin film transistor, so the third switch 70 is turned on. It is ensured that in the sampling stage T1, the data line 102 is electrically connected to the first capacitor terminal 21.
  • the third control voltage is at the seventh level in the sampling stage T1 and the data writing stage T2, and the seventh level is a low level.
  • the fifth switch 90 is an N-type thin film transistor, so the fifth switch 90 is disconnected, and no voltage and current pass through the light-emitting diode 40; the third control voltage is at the eighth level in the light-emitting stage T3, and the eighth level is a high level, so the fifth switch 90 is turned on, so that the drain terminal 33 can be electrically connected to the positive terminal 41, and provide a driving current to the positive terminal 41 to drive the light-emitting diode 40 to emit light.
  • the driving transistor 30, the second switch 60, the third switch 70, the fourth switch 80 and the fifth switch 90 are P-type thin film transistors (such as triodes, field effect transistors), the seventh level is a high level, the eighth level is a low level, the fifth level is a low level, and the sixth level is a high level.
  • the second control voltage is at the fifth level in the sampling stage T1, the fifth level is a low level, and the third switch 70 is a P-type thin film transistor, so the third switch 70 is turned on. It is ensured that in the sampling stage T1, the data line 102 is electrically connected to the first capacitor terminal 21.
  • the fourth switch 80 is a P-type thin film transistor, so the fourth switch 80 is turned on, and the gate terminal 31 is electrically connected to the drain terminal 33, so that the voltage VG of the gate terminal 31 in the sampling stage T1 is VSCAN-VTH.
  • the third control voltage is at the seventh level in the sampling stage T1 and the data writing stage T2, and the seventh level is a high level.
  • the fifth switch 90 is a P-type thin film transistor, so the fifth switch 90 is disconnected, and no voltage and current pass through the light-emitting diode 40; the third control voltage is at the eighth level in the light-emitting stage T3, and the eighth level is a low level, so the fifth switch 90 is turned on, so that the drain terminal 33 can be electrically connected to the positive terminal 41, and provide a driving current to the positive terminal 41 to drive the light-emitting diode 40 to emit light.
  • the present application further provides a display panel 1000 .
  • the display panel 1000 includes a control chip 200 and a pixel driving circuit 100 provided in any one of the above embodiments.
  • the control chip 200 can be used to control the level of the pixel driving circuit 100 .
  • the pixel driving circuit 100 eliminates the influence of the threshold voltage VTH on the driving current, so that the light emitting diode 40 displays stably and improves the uniformity of the display brightness of the display panel 1000, thus greatly improving the display quality of the display panel 1000. Furthermore, the pixel driving circuit 100 may not be provided with a power line, but instead utilizes the scanning line 101 instead of the power line to provide voltage to the pixel driving circuit 100, which has a good improvement effect on reducing the voltage drop of the pixel driving voltage in each area of the display panel 1000, and is beneficial to further improve the display uniformity of the display panel 1000.
  • the display panel 1000 includes but is not limited to being an OLED display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路(100)及显示面板(1000)，像素驱动电路(100)包括扫描线(101)，用于提供扫描电压，扫描电压在采样阶段(T1)为第一电平，在数据写入阶段(T2)为第二电平；数据线(102)，用于提供数据电压，数据电压在采样阶段(T1)为高电平，在数据写入阶段(T2)为低电平；电容(20)，第一电容端(21)在采样阶段(T1)和数据写入阶段(T2)皆电连接数据线(102)；驱动晶体管(30)，源极端(32)电连接扫描线(101)，栅极端(31)电连接第二电容端(22)，漏极端(33)用于在采样阶段(T1)与栅极端(31)电连接，在数据写入阶段(T2)与栅极端(31)断开。像素驱动电路(100)能够提高显示面板(1000)的显示均匀性。

Description

像素驱动电路及显示面板
本申请要求于2022年10月11日提交中国专利局、申请号为2022112419843、申请名称为“像素驱动电路及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及显示面板。
背景技术
随着光电显示技术和半导体制造技术的发展，搭配薄膜晶体管的显示面板(Thin Film Transistor，TFT)已经越发成熟。在厚度、色彩饱和度、对比度、柔性显示等方面，OLED(Organic Light Emitting Diode，OLED)显示面板均具有明显的优势，OLED显示面板的发展具有广阔的前景。
相关技术中，OLED显示面板的驱动电路采用直流电源进行驱动，有一条单独的电源线对每个像素提供直流电压。电源线本身存在一定程度的内阻，并且由于OLED显示面板制备过程不稳定性和技术受限等原因，不同区域的电源线厚度可能发生变化导致各个区域内像素驱动电压的压降不同，从而引起OLED显示面板的亮度不均匀。
另外，OLED显示面板内每个像素单元的驱动晶体管的阈值电压会有差别，这样会造成每个像素单元中发光二极管的电流不一致，使得OLED显示面板的亮度不均匀。
发明内容
本申请提供一种像素驱动电路及显示面板，以改善显示面板显示的不均匀现象。
第一方面，本申请提供了一种像素驱动电路，所述像素驱动电路的工作阶段包括采样阶段及数据写入阶段，所述像素驱动电路包括：
扫描线，所述扫描线用于提供扫描电压，所述扫描电压在采样阶段为第一电平，在数据写入阶段为第二电平；
数据线，所述数据线用于提供数据电压，所述数据电压在采样阶段为高电平，在数据写入阶段为所述低电平；
电容，所述电容包括第一电容端和第二电容端，所述第一电容端在采样阶段和数据写入阶段皆电连接所述数据线；以及
驱动晶体管，所述驱动晶体管包括栅极端、源极端和漏极端，源极端电连接所述扫描线，所述栅极端电连接所述第二电容端，所述漏极端用于在采样阶段与所述栅极端电连接，在数据写入阶段与所述栅极端断开。
本申请提供的像素驱动电路中，通过将驱动晶体管的源极端电连接所述扫描线，驱动晶体管的栅极端通过电容电连接至数据线，在采样阶段，并控制驱动晶体管的漏极端在采样阶段与所述栅极端电连接，使驱动晶体管形成类二极管结构，达到平衡状态，栅极端的电压VG＝VSCAN－VTH；在数据写入阶段时，控制所述驱动晶体管的漏极端与所述栅极端断开，数据线从高电平跳变至低电平，由于电容耦合作用，栅极端的电压跳变为VG＝VSCAN－VTH－VDATA，根据后续发光阶段的驱动电流公式可知，驱动电流与阈值电压VTH无关，从而降低甚至消除阈值电压VTH对于驱动电流的影响，进而改善显示面板显示不均匀的现象。并且相较于相关技术中的像素驱动电路中有一条具有内阻的电源线对每个像素提供直流电压，使 得传递至发光器件的电压压降较大。本申请提供的像素驱动电路可以不设有电源线，而是利用扫描线代替电源线对像素驱动电路提供电压，对降低显示面板各个区域内像素驱动电压的压降有很好的改善效果，有利于进一步地提高显示面板的显示均匀性。
其中，所述像素驱动电路的工作阶段还包括发光阶段，所述扫描电压在所述发光阶段为所述第一电平，所述数据电压在所述发光阶段为所述低电平；
所述像素驱动电路还包括发光二极管，所述发光二极管具有正极端和负极端，所述负极端接地，所述正极端用于在所述采样阶段和所述数据写入阶段皆与所述漏极端断开；所述正极端用于在所述发光阶段电连接所述漏极端。
其中，所述像素驱动电路还包括开关模块，所述开关模块的一端电连接所述数据线，另一端电连接所述第一电容端，所述开关模块用于在所述采样阶段和所述数据写入阶段时导通，及在所述发光阶段断开。
其中，所述开关模块包括第一开关，所述第一开关包括第一控制端、第一端以及第二端，所述第一端电连接所述数据线，所述第二端电连接所述第一电容端；
所述像素驱动电路还包括第一控制信号线，所述第一控制信号线电连接所述第一控制端，所述第一控制信号线用于提供第一控制电压，所述第一控制电压在所述采样阶段及所述数据写入阶段为第三电平，所述第一控制电压在所述发光阶段为第四电平，所述第三电平和所述第四电平中的一者为高电平，另一者为低电平。
其中，所述开关模块包括第二开关以及第三开关，所述第二开关包括第二控制端、第三端以及第四端，所述第三开关包括第三控制端、第五端以及第六端；
所述第三端与所述第五端皆电连接所述数据线，所述第四端与所述第六端皆电连接所述第一电容端；
所述第二控制端电连接于所述扫描线，所述像素驱动电路还包括第二控制信号线，所述第三控制端电连接于所述第二控制信号线，所述第二控制信号线用于提供第二控制电压，所述第二控制电压在所述采样阶段为第五电平，所述第二控制电压在所述数据写入阶段及所述发光阶段为第六电平，所述第五电平和所述第六电平中的一者为高电平，另一者为低电平。
其中，所述像素驱动电路还包括第四开关，所述第四开关包括第四控制端、第七端以及第八端，所述第七端电连接于所述栅极端，所述第八端电连接于所述漏极端，所述第四控制端电连接于所述第二控制信号线。
其中，所述像素驱动电路还包括第五开关，所述第五开关包括第五控制端、第九端以及第十端，所述第九端电连接于所述漏极端，所述第十端电连接于所述正极端；
所述像素驱动电路还包括第三控制信号线，所述第五控制端电连接于所述第三控制信号线，所述第三控制信号线用于提供第三控制电压，所述第三控制电压在所述采样阶段及所述数据写入阶段为第七电平，所述第三控制电压在发光阶段为第八电平，所述第七电平和所述第八电平中的一者为高电平，另一者为低电平。
其中，所述驱动晶体管、所述第二开关为P型薄膜晶体管，所述第三开关、所述第四开关及所述第五开关为N型薄膜晶体管，所述第五电平为高电平，所述第六电平为低电平，所述第七电平为低电平，所述第八电平为高电平。
其中，所述驱动晶体管、所述第二开关、所述第三开关、所述第四开关及所述第五开关为P型薄膜晶体管，所述第五电平为低电平，所述第六电平为高电平，所述第七电平为高电平，所述第八电平为低电平。
第二方面，本申请提供了显示面板，包括所述像素驱动电路。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施方式一提供的一种像素驱动电路的电路示意图；
图2是本申请实施方式一提供的一种像素驱动电路的时序图；
图3是本申请实施方式二提供的一种像素驱动电路的电路示意图；
图4是本申请实施方式三提供的一种像素驱动电路的电路示意图；
图5是本申请实施方式三提供的一种像素驱动电路的时序图；
图6是本申请实施方式四提供的一种显示面板的电路结构图。
标号说明：
显示面板-1000、像素驱动电路-100、控制芯片-200、扫描线-101、数据线-102、第一控
制信号线-103、第二控制信号线-104、第三控制信号线-105、电容-20、第一电容端-21、第二电容端-22、驱动晶体管-30、栅极端-31、源极端-32、漏极端-33、发光二极管-40、正极端-41、负极端-42、第一开关-50、第一控制端-51、第一端-52、第二端-53、第二开关-60、第二控制端-61、第三端-62、第四端-63、第三开关-70、第三控制端-71、第五端-72、第六端-73、第四开关-80、第四控制端-81、第七端-82、第八端-83、第五开关-90、第五控制端-91、第九端-92、第十端-93。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本文中提及“实施例”或“实施方式”意味着，结合实施例或实施方式描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术 人员而言，可以根据情况理解上述术语在本公开中的含义。
有源矩阵有机发光二极管(Active-matrix organic light emitting diode，AMOLED)由于其自发光、低功耗、宽视角、高色域、高对比度、快速响应等优点，被业界评为最有潜力的显示技术之一。要实现精准的AMOLED控制需要使用TFT技术进行像素驱动，目前主流的TFT技术主要有α-si TFT技术、LTPS TFT技术、Oxide TFT技术，α-si TFT技术由于其稳定性差及载流子迁移率低等缺陷不适用于AMOLED驱动，而LTPS因其在三者之中最好的稳定性及最高的载流子迁移率被认为是最适用于AMOLED驱动的TFT技术。但是LTPS(低温多晶硅)技术因为工序相对复杂且在大尺寸应用时均匀性差等缺点限制了其大规模量产应用。
电源线内阻，使不同区域的电源线厚度可能发生变化导致各个区域内像素驱动电压的压降不同；OLED显示面板内每个像素单元的驱动晶体管的阈值电压会有差别；随着驱动晶体管驱动时间的推移，会造成驱动晶体管材料老化、变异，从而导致驱动晶体管的阈值电压发生漂移等问题，会造成OLED显示面板显示的不均匀现象，并且这种显示不均匀现象会随着驱动时间的推移和驱动晶体管材料的老化变得更严重。
如何使得OLED显示面板的显示亮度更加均匀成为需要解决的技术问题。
请参照图1及图2，本申请提供了一种像素驱动电路100，能够改善OLED显示面板显示的不均匀现象。
像素驱动电路100的工作阶段包括采样阶段T1及数据写入阶段T2。
像素驱动电路100包括扫描线101、数据线102、电容20以及驱动晶体管30。
扫描线101用于提供扫描电压，扫描电压在采样阶段T1为第一电平，在数据写入阶段T2为第二电平，第一电平和第二电平中的一者为高电平，另一者为低电平。
数据线102用于提供数据电压，数据电压在采样阶段T1为高电平，在数据写入阶段T2为低电平。
电容20包括第一电容端21和第二电容端22，第一电容端21在采样阶段T1和数据写入阶段T2皆电连接数据线102。
驱动晶体管30包括栅极端31、源极端32和漏极端33，源极端32电连接扫描线101，栅极端31电连接第二电容端22，漏极端33用于在采样阶段T1与栅极端31电连接，在数据写入阶段T2与栅极端31断开。
在本实施方式中，当像素驱动电路100的工作阶段为采样阶段T1时，扫描线101提供的扫描电压为第一电平，本实施方式中，第一电平为高电平，在其他实施方式中，第一电平还可以为低电平。源极端32的电压VS等于扫描线101的扫描电压VSCAN，即VS＝VSCAN。数据线102提供的数据电压为高电平，第一电容端21在采样阶段T1电连接数据线102，因此第一电容端21处的电压VA＝VDATA。
在本实施方式中，驱动晶体管30为P型薄膜晶体管。驱动晶体管30内的漏极端33在采样阶段T1时与栅极端31电连接，使驱动晶体管30形成类二极管结构，驱动晶体管30内的电压处于平衡状态，换言之，即驱动晶体管30内栅极端31的电压VG与源极端32的电压VS之间的差值等于驱动晶体管30的阈值电压VTH，即VSG＝VTH，根据公式VSG＝VS－VG，由此可以推出VG＝VSCAN－VTH。
本申请对于像素驱动电路100在采样阶段T1，第一电容端21如何电连接数据线102以及漏极端33电连接栅极端31的方式不作限定，在下文进行详细描述。
当像素驱动电路100的工作阶段为数据写入阶段T2时，扫描电压为第二电平，本实施方式中，第二电平为低电平，在其他实施方式中，第二电平还可以为高电平。数据线102提供的数 据电压为低电平，第一电容端21在数据写入阶段T2时电连接数据线102，因此第一电容端21处的电压VA＝0，由于电容20耦合作用，第二电容端22即栅极端31的电压进行跳变，跳变为VG＝VSCAN－VTH－VDATA。
在相关技术中，驱动晶体管产生的驱动电流表达式为：
其中μ为载流子迁移率，W为沟道宽度，L为沟道长度，CGI为栅极电容，VTH为阈值电压，W、L在设计时已经固定，CGI取决于栅极绝缘层厚度和材料。由此可知，影响OLED器件驱动电流和发光亮度的因素有载流子迁移率μ，阈值电压VTH，以及VSG。其中VSG＝VS－VG，即VSG与数据电压以及电源电压有关。但在本实施方式中，经像素驱动电路100在采样阶段T1以及数据写入阶段T2的工作，驱动晶体管30产生的驱动电流表达式可进行简化为：
经公式推导可得，本申请的驱动晶体管30产生的驱动电流最终只由μ、W、L、CGI、以及数据电压VDATA所决定。
本申请提供的像素驱动电路100中，通过将驱动晶体管30的源极端32电连接扫描线101，驱动晶体管30的栅极端31通过电容20电连接至数据线102，在采样阶段T1，并控制驱动晶体管30的漏极端33在采样阶段T1与栅极端电连接，使驱动晶体管30形成类二极管结构，达到平衡状态，栅极端31的电压VG＝VSCAN－VTH；在数据写入阶段T2时，控制驱动晶体管30的漏极端33与栅极端31断开，数据线102从高电平跳变至低电平，由于电容耦合作用，栅极端31的电压跳变为VG＝VSCAN－VTH－VDATA，根据后续发光阶段T3的驱动电流公式可知，驱动电流与阈值电压VTH无关，从而降低甚至消除阈值电压VTH对于驱动电流的影响，进而改善显示面板显示不均匀的现象。并且相较于相关技术中的像素驱动电路中有一条具有内阻的电源线对每个像素提供直流电压，使得传递至发光器件的电压压降较大。本申请提供的像素驱动电路100可以不设有电源线，而是利用扫描线101代替电源线对像素驱动电路100提供电压，对降低显示面板各个区域内像素驱动电压的压降有很好的改善效果，有利于进一步地提高显示面板的显示均匀性。
像素驱动电路100的工作阶段还包括发光阶段T3，扫描电压在发光阶段T3为第一电平，数据电压在发光阶段T3为低电平。
像素驱动电路100还包括发光二极管40，发光二极管40具有正极端41和负极端42，负极端42接地，正极端41用于在采样阶段T1和数据写入阶段T2皆与漏极端33断开。正极端41用于在发光阶段T3电连接漏极端33。
本实施方式中驱动晶体管30产生的驱动电流与驱动晶体管30的阈值电压VTH无关，降低甚至消除阈值电压VTH对于驱动电流的影响，从而使流过发光二极管40的电流稳定，保证发光二极管40的发光亮度均匀，改善画面的显示效果。
请参照图1、图3及图4，像素驱动电路100还包括开关模块，开关模块的一端电连接数据线102，另一端电连接第一电容端21，开关模块用于在采样阶段T1和数据写入阶段T2时导通， 及发光阶段T3断开。数据线102与第一电容端21之间的电连接方式包括但不限于以下实施方式。
在一种实施方式中，请参照图3，开关模块包括第一开关50，第一开关50包括第一控制端51、第一端52以及第二端53，第一端52电连接数据线102，第二端53电连接第一电容端21。
像素驱动电路100还包括第一控制信号线103，第一控制端51电连接于第一控制信号线103，第一控制信号线103用于提供第一控制电压，第一控制电压在采样阶段T1及数据写入阶段T2为第三电平，第一控制电压在发光阶段T3为第四电平，所述第三电平和所述第四电平中的一者为高电平，另一者为低电平。
第一控制电压在采样阶段T1及数据写入阶段T2为第三电平，第一开关50处于导通状态，使得数据线102与第一电容端21之间实现电连接。第一控制电压在发光阶段T3为第四电平，第一开关50处于断开状态，使得数据线102与第一电容端21之间断开电连接。
在另一种实施方式中，请参照图4，开关模块包括第二开关60以及第三开关70，第二开关60包括第二控制端61、第三端62以及第四端63，第三开关70包括第三控制端71、第五端72以及第六端73。第三端62与第五端72皆电连接数据线102，第四端63与第六端73皆电连接第一电容端21。
第二控制端61电连接于扫描线101，像素驱动电路100还包括第二控制信号线104，第三控制端71电连接于第二控制信号线104，第二控制信号线104用于提供第二控制电压，第二控制电压在采样阶段T1为第五电平，第二控制电压在数据写入阶段T2及发光阶段T3为第六电平，所述第五电平和所述第六电平中的一者为高电平，另一者为低电平。
第二控制端61电连接于扫描线101，扫描电压在采样阶段T1时为第一电平，第二开关60断开，第二控制电压在采样阶段T1为第五电平，第三开关70导通；扫描电压在数据写入阶段T2时为第二电平，第二开关60导通。即保证在采样阶段T1及数据写入阶段T2时，数据线102与第一电容端21实现电连接。
扫描电压在发光阶段T3时为第一电平，第二开关60断开，第二控制电压在发光阶段T3为第六电平，第三开关70断开。即保证在发光阶段T3时数据线102与第一电容端21之间断开电连接。
在一种实施方式中，请参阅图1及图3，像素驱动电路100还包括第四开关80，第四开关80包括第四控制端81、第七端82以及第八端83，第七端82电连接于栅极端31，第八端83电连接于漏极端33，第四控制端81电连接于第二控制信号线104。
第二控制电压在采样阶段T1为第五电平，第四开关80导通，栅极端31与漏极端33进行电连接，以使得采样阶段T1栅极端31的电压VG＝VSCAN－VTH。第二控制电压在数据写入阶段T2以及发光阶段T3为第六电平，第四开关80断开。
在一种实施方式中，请参阅图1，像素驱动电路100还包括第五开关90，第五开关90包括第五控制端91、第九端92以及第十端93，第九端92电连接于漏极端33，第十端93电连接于正极端41。
所述像素驱动电路100还包括第三控制信号线105，所述第五控制端91电连接于所述第三控制信号线105，所述第三控制信号线105用于提供第三控制电压，所述第三控制电压在采样阶段T1及数据写入阶段T2为第七电平，所述第三控制电压在发光阶段为第八电平，所述第七电平和所述第八电平中的一者为高电平，另一者为低电平。
第三控制电压在采样阶段T1及数据写入阶段T2为第七电平，第五开关90断开，发光二极管40无电压和电流通过；第三控制电压在发光阶段T3为第八电平，第五开关90导通，进而使 得漏极端33能够电连接于正极端41，并向正极端41提供驱动电流，以驱动发光二极管40发光。
需要说明的是，在一种实施方式中，请参阅图3，所述第五控制端91电连接于所述第一控制信号线103，所述第一控制信号线103用于提供第一控制电压。第一控制电压在采样阶段T1及数据写入阶段T2为第三电平，第一控制电压在发光阶段T3为第四电平，所述第三电平和所述第四电平中的一者为高电平，另一者为低电平。
第一控制电压在采样阶段T1及数据写入阶段T2为第三电平，第五开关90断开，发光二极管40无电压和电流通过；第一控制电压在发光阶段T3为第四电平，第五开关90导通，进而使得漏极端33能够电连接于正极端41，并向正极端41提供驱动电流，以驱动发光二极管40发光。
换言之，所述第一控制信号线103和所述第三控制信号线105仅为不同实施方式中同一作用的信号线，为了便于描述，对其进行分开命名，不应理解为对本申请的限制。
需要说明的是，第五电平包括但不限于为高电平或低电平，第六电平包括但不限于为高电平或低电平，第七电平包括但不限于为高电平或低电平，第八电平包括但不限于为高电平或低电平。第五电平、第六电平、第七电平以及第八电平的电平情况需要根据第三开关70、第四开关80以及第五开关90的薄膜晶体管类型决定。
举例而言，在一种实施方式中，请参照图1及图2，驱动晶体管30、第二开关60为P型薄膜晶体管，第三开关70、第四开关80及第五开关90为N型薄膜晶体管(例如三极管、场效应管)，第五电平为高电平，第六电平为低电平，所述第七电平为低电平，所述第八电平为高电平。
第二控制电压在采样阶段T1为第五电平，第五电平为高电平，第三开关70为N型薄膜晶体管，因此第三开关70导通。保证在采样阶段T1，数据线102与第一电容端21实现电连接。第四开关80为N型薄膜晶体管，因此第四开关80导通，栅极端31与漏极端33进行电连接，以使得采样阶段T1栅极端31的电压VG＝VSCAN－VTH。
第三控制电压在采样阶段T1及数据写入阶段T2为第七电平，第七电平为低电平，第五开关90为N型薄膜晶体管，因此第五开关90断开，发光二极管40无电压和电流通过；第三控制电压在发光阶段T3为第八电平，第八电平为高电平，因此第五开关90导通，进而使得漏极端33能够电连接于正极端41，并向正极端41提供驱动电流，以驱动发光二极管40发光。
在另一种实施方式中，请参照图4及图5，驱动晶体管30、第二开关60、第三开关70、第四开关80及第五开关90为P型薄膜晶体管(例如三极管、场效应管)，第七电平为高电平，第八电平为低电平，第五电平为低电平，第六电平为高电平。
第二控制电压在采样阶段T1为第五电平，第五电平为低电平，第三开关70为P型薄膜晶体管，因此第三开关70导通。保证在采样阶段T1，数据线102与第一电容端21实现电连接。第四开关80为P型薄膜晶体管，因此第四开关80导通，栅极端31与漏极端33进行电连接，以使得采样阶段T1栅极端31的电压VG＝VSCAN－VTH。
第三控制电压在采样阶段T1及数据写入阶段T2为第七电平，第七电平为高电平，第五开关90为P型薄膜晶体管，因此第五开关90断开，发光二极管40无电压和电流通过；第三控制电压在发光阶段T3为第八电平，第八电平为低电平，因此第五开关90导通，进而使得漏极端33能够电连接于正极端41，并向正极端41提供驱动电流，以驱动发光二极管40发光。
请参照图6，本申请还提供了一种显示面板1000。显示面板1000包括控制芯片200及上述任意一种实施方式提供的像素驱动电路100。控制芯片200可用于控制像素驱动电路100中的电平情况。
像素驱动电路100消除了阈值电压VTH对驱动电流的影响，使得发光二极管40显示稳定，改善了显示面板1000显示亮度的均匀性，因此可以极大的提升显示面板1000的显示品质。并 且像素驱动电路100可以不设有电源线，而是利用扫描线101代替电源线对像素驱动电路100提供电压，对降低显示面板1000各个区域内像素驱动电压的压降有很好的改善效果，有利于进一步地提高显示面板1000的显示均匀性。
可选地，显示面板1000包括但不限于为OLED显示面板。
以上是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (20)

  1. 一种像素驱动电路，其中，所述像素驱动电路的工作阶段包括采样阶段及数据写入阶段，所述像素驱动电路包括：
    扫描线，所述扫描线用于提供扫描电压，所述扫描电压在所述采样阶段为第一电平，在所述数据写入阶段为第二电平，所述第一电平和所述第二电平中的一者为高电平，另一者为低电平；
    数据线，所述数据线用于提供数据电压，所述数据电压在所述采样阶段为高电平，在所述数据写入阶段为低电平；
    电容，所述电容包括第一电容端和第二电容端，所述第一电容端在所述采样阶段和所述数据写入阶段皆电连接所述数据线；以及
    驱动晶体管，所述驱动晶体管包括栅极端、源极端和漏极端，所述源极端电连接所述扫描线，所述栅极端电连接所述第二电容端，所述漏极端用于在所述采样阶段与所述栅极端电连接，及在所述数据写入阶段与所述栅极端断开。
  2. 根据权利要求1所述的像素驱动电路，其中，在所述采样阶段，所述驱动晶体管的栅极端的电压与所述源极端的电压之间的差值等于所述驱动晶体管的阈值电压。
  3. 根据权利要求1所述的像素驱动电路，其中，在所述数据写入阶段，所述第一电容端的电压为0，所述栅极端的电压为VSCAN－VTH－VDATA，所述VSCAN为所述扫描电压，所述VTH为所述驱动晶体管的阈值电压，所述VDATA为所述数据电压。
  4. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路的工作阶段还包括发光阶段，所述扫描电压在所述发光阶段为所述第一电平，所述数据电压在所述发光阶段为低电平。
  5. 根据权利要求4所述的像素驱动电路，其中，所述像素驱动电路还包括发光二极管，所述发光二极管具有正极端和负极端，所述负极端接地，所述正极端用于在所述采样阶段和所述数据写入阶段皆与所述漏极端断开；所述正极端用于在所述发光阶段电连接所述漏极端。
  6. 根据权利要求5所述的像素驱动电路，其中，所述像素驱动电路还包括开关模块，所述开关模块的一端电连接所述数据线，另一端电连接所述第一电容端，所述开关模块用于在所述采样阶段和所述数据写入阶段时导通，及在所述发光阶段断开。
  7. 根据权利要求6所述的像素驱动电路，其中，所述开关模块包括第一开关，所述第一开关包括第一控制端、第一端以及第二端，所述第一端电连接所述数据线，所述第二端电连接所述第一电容端。
  8. 根据权利要求7所述的像素驱动电路，其中，所述像素驱动电路还包括第一控制信号线，所述第一控制信号线电连接所述第一控制端，所述第一控制信号线用于提供第一控制电压，所述第一控制电压在所述采样阶段及所述数据写入阶段为第三电平，所述第一控制电压 在所述发光阶段为第四电平，所述第三电平和所述第四电平中的一者为高电平，另一者为低电平。
  9. 根据权利要求6所述的像素驱动电路，其中，所述开关模块包括第二开关以及第三开关，所述第二开关包括第二控制端、第三端以及第四端，所述第三开关包括第三控制端、第五端以及第六端；
    所述第三端与所述第五端皆电连接所述数据线，所述第四端与所述第六端皆电连接所述第一电容端；
    所述第二控制端电连接于所述扫描线，所述像素驱动电路还包括第二控制信号线，所述第三控制端电连接于所述第二控制信号线，所述第二控制信号线用于提供第二控制电压，所述第二控制电压在所述采样阶段为第五电平。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第二控制电压在所述数据写入阶段及所述发光阶段为第六电平，所述第五电平和所述第六电平中的一者为高电平，另一者为低电平。
  11. 根据权利要求9所述的像素驱动电路，其中，在所述采样阶段时所述第二开关断开，及所述第三开关导通；在所述数据写入阶段所述第二开关导通；在所述发光阶段时所述第二开关断开，及所述第三开关断开。
  12. 根据权利要求10所述的像素驱动电路，其中，所述像素驱动电路还包括第四开关，所述第四开关包括第四控制端、第七端以及第八端，所述第七端电连接于所述栅极端，所述第八端电连接于所述漏极端，所述第四控制端电连接于所述第二控制信号线。
  13. 根据权利要求12所述的像素驱动电路，其中，在所述采样阶段时所述第四开关导通，在数据写入阶段时所述第四开关断开。
  14. 根据权利要求12所述的像素驱动电路，其中，所述像素驱动电路还包括第五开关，所述第五开关包括第五控制端、第九端以及第十端，所述第九端电连接于所述漏极端，所述第十端电连接于所述正极端；
    所述像素驱动电路还包括第三控制信号线，所述第五控制端电连接于所述第三控制信号线，所述第三控制信号线用于提供第三控制电压，所述第三控制电压在所述采样阶段及所述数据写入阶段为第七电平。
  15. 根据权利要求14所述的像素驱动电路，其中，所述第三控制电压在发光阶段为第八电平，所述第七电平和所述第八电平中的一者为高电平，另一者为低电平。
  16. 根据权利要求15所述的像素驱动电路，其中，所述驱动晶体管、所述第二开关为P型薄膜晶体管，所述第三开关、所述第四开关及所述第五开关为N型薄膜晶体管。
  17. 根据权利要求16所述的像素驱动电路，其中，所述第五电平为高电平，所述第六电 平为低电平，所述第七电平为低电平，所述第八电平为高电平。
  18. 根据权利要求14所述的像素驱动电路，其中，所述驱动晶体管、所述第二开关、所述第三开关、所述第四开关及所述第五开关为P型薄膜晶体管。
  19. 根据权利要求15所述的像素驱动电路，其中，所述第五电平为低电平，所述第六电平为高电平，所述第七电平为高电平，所述第八电平为低电平。
  20. 一种显示面板，其中，包括如权利要求1～19任一项所述的像素驱动电路。
PCT/CN2023/109156 2022-10-11 2023-07-25 像素驱动电路及显示面板 WO2024078091A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211241984.3 2022-10-11
CN202211241984.3A CN115311998B (zh) 2022-10-11 2022-10-11 像素驱动电路及显示面板

Publications (1)

Publication Number Publication Date
WO2024078091A1 true WO2024078091A1 (zh) 2024-04-18

Family

ID=83868457

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/109156 WO2024078091A1 (zh) 2022-10-11 2023-07-25 像素驱动电路及显示面板

Country Status (3)

Country Link
US (1) US11908412B1 (zh)
CN (1) CN115311998B (zh)
WO (1) WO2024078091A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115311998B (zh) * 2022-10-11 2023-01-10 惠科股份有限公司 像素驱动电路及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1848223A (zh) * 2005-03-18 2006-10-18 株式会社半导体能源研究所 半导体器件，显示器件，驱动方法及其电子装置
JP2010091608A (ja) * 2008-10-03 2010-04-22 Toshiba Mobile Display Co Ltd アクティブマトリクス型表示装置及びアクティブマトリクス型表示装置の駆動方法
CN111048044A (zh) * 2019-12-31 2020-04-21 南华大学 电压编程型amoled像素驱动电路及其驱动方法
CN111613180A (zh) * 2020-05-18 2020-09-01 武汉华星光电半导体显示技术有限公司 Amoled像素补偿驱动电路、方法及显示面板
WO2021070368A1 (ja) * 2019-10-11 2021-04-15 シャープ株式会社 表示装置
CN115311998A (zh) * 2022-10-11 2022-11-08 惠科股份有限公司 像素驱动电路及显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005099715A (ja) * 2003-08-29 2005-04-14 Seiko Epson Corp 電子回路の駆動方法、電子回路、電子装置、電気光学装置、電子機器および電子装置の駆動方法
CN103413521B (zh) * 2013-07-31 2015-06-10 京东方科技集团股份有限公司 有机发光二极管像素电路及其驱动方法、显示装置
CN106847182A (zh) * 2016-12-28 2017-06-13 深圳市华星光电技术有限公司 像素驱动电路及有机发光显示装置
CN108711400B (zh) * 2018-05-31 2020-08-07 京东方科技集团股份有限公司 像素电路及显示装置
CN109584786B (zh) * 2019-01-21 2020-12-04 惠科股份有限公司 一种显示面板的驱动电路、驱动方法及显示装置
CN114730542A (zh) * 2020-09-29 2022-07-08 京东方科技集团股份有限公司 像素驱动电路、显示设备以及像素驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1848223A (zh) * 2005-03-18 2006-10-18 株式会社半导体能源研究所 半导体器件，显示器件，驱动方法及其电子装置
JP2010091608A (ja) * 2008-10-03 2010-04-22 Toshiba Mobile Display Co Ltd アクティブマトリクス型表示装置及びアクティブマトリクス型表示装置の駆動方法
WO2021070368A1 (ja) * 2019-10-11 2021-04-15 シャープ株式会社 表示装置
CN111048044A (zh) * 2019-12-31 2020-04-21 南华大学 电压编程型amoled像素驱动电路及其驱动方法
CN111613180A (zh) * 2020-05-18 2020-09-01 武汉华星光电半导体显示技术有限公司 Amoled像素补偿驱动电路、方法及显示面板
CN115311998A (zh) * 2022-10-11 2022-11-08 惠科股份有限公司 像素驱动电路及显示面板

Also Published As

Publication number Publication date
CN115311998B (zh) 2023-01-10
US11908412B1 (en) 2024-02-20
CN115311998A (zh) 2022-11-08

Similar Documents

Publication Publication Date Title
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
US11915651B2 (en) Electroluminescent display
US10769998B2 (en) Pixel circuit and driving method thereof, array substrate, and display panel
WO2016202037A1 (zh) Oled像素电路及其显示装置
WO2017080379A1 (zh) 像素补偿电路及其驱动方法、阵列基板以及显示装置
WO2019218713A1 (zh) 显示面板及显示装置
WO2015085699A1 (zh) Oled像素电路及驱动方法、显示装置
WO2018205574A1 (zh) 显示面板、显示设备及补偿方法
CN106531067B (zh) 一种像素电路及其显示装置
CN105225636B (zh) 像素驱动电路、驱动方法、阵列基板及显示装置
WO2023005648A1 (zh) 像素电路及其驱动方法、阵列基板和显示装置
CN104933993A (zh) 像素驱动电路及其驱动方法、显示装置
WO2016155471A1 (zh) 像素电路及其驱动方法、显示装置
WO2016188012A1 (zh) 像素电路、其驱动方法及显示装置
US20190096337A1 (en) Pixel circuit and display device
WO2015180344A1 (zh) 像素电路及其驱动方法、有机发光显示面板及显示装置
WO2019010873A1 (zh) 一种像素驱动电路及驱动方法
WO2014176834A1 (zh) 像素电路及其驱动方法、显示装置
WO2014153815A1 (zh) Amoled像素单元及其驱动方法、显示装置
WO2018233599A1 (zh) 像素电路及其驱动方法、阵列基板和显示装置
WO2013034075A1 (zh) 电压驱动像素电路及其驱动方法、显示面板
CN110036435A (zh) 像素电路、主动矩阵有机发光二极管显示面板、显示设备和补偿驱动晶体管阈值电压的方法
CN106935201B (zh) 像素电路及其驱动方法和有源矩阵有机发光显示器
WO2016078282A1 (zh) 像素单元驱动电路和方法、像素单元和显示装置
CN109785797A (zh) 一种新型的amoled像素电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23876297

Country of ref document: EP

Kind code of ref document: A1