WO2024075463A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024075463A1
WO2024075463A1 PCT/JP2023/032467 JP2023032467W WO2024075463A1 WO 2024075463 A1 WO2024075463 A1 WO 2024075463A1 JP 2023032467 W JP2023032467 W JP 2023032467W WO 2024075463 A1 WO2024075463 A1 WO 2024075463A1
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WO
WIPO (PCT)
Prior art keywords
circuit pattern
region
wall portion
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/032467
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English (en)
French (fr)
Japanese (ja)
Inventor
智紀 池田
吉純 川端
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to US19/115,523 priority Critical patent/US20260114318A1/en
Priority to JP2024555675A priority patent/JPWO2024075463A1/ja
Publication of WO2024075463A1 publication Critical patent/WO2024075463A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/13—Containers comprising a conductive base serving as an interconnection
    • H10W76/136—Containers comprising a conductive base serving as an interconnection having other interconnections perpendicular to the conductive base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00—Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/20—Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D1/00 - H10D48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes
    • H10D80/251—FETs covered by H10D30/00, e.g. power FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • a semiconductor device includes a substrate having a metal pattern, a case, resin filled in the case, and a semiconductor element electrically connected to the metal pattern (see, for example, Patent Document 1).
  • the case has a wall portion extending upward, and a protrusion connected to the wall portion and protruding toward the center of the substrate.
  • the protrusion has a first surface that is connected to the tip of the protrusion and is a slope that approaches the substrate the further away from the tip of the protrusion, and a second surface that is connected below the first surface and is closer to perpendicular to the top surface of the substrate than the first surface.
  • the metal pattern is located directly below the first surface.
  • the semiconductor device comprises a substrate having a circuit pattern, a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern, a frame including a wall portion, and a plate-shaped terminal electrically connected to the circuit pattern.
  • the wall portion surrounds the substrate.
  • the terminal includes a first region attached to the wall portion and a second region connected to the first region and disposed inside the frame portion. The distance between the inner wall surface of the wall portion and the circuit pattern is 500 ⁇ m or less. The second region is directly connected to the circuit pattern.
  • FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment as viewed in the thickness direction of a substrate.
  • FIG. 2 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG.
  • FIG. 3 is a schematic cross-sectional view showing a semiconductor device at an intermediate stage in the manufacturing process.
  • FIG. 4 is a schematic cross-sectional view showing a semiconductor device at an intermediate stage in the manufacturing process.
  • FIG. 5 is a schematic cross-sectional view showing a semiconductor device at an intermediate stage in the manufacturing process.
  • FIG. 6 is a schematic perspective view showing a part of a semiconductor device according to the second embodiment.
  • one of the objectives is to provide a semiconductor device that can be easily miniaturized and has reduced inductance.
  • a semiconductor device includes a substrate having a circuit pattern, a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern, a frame including a wall portion, and a plate-shaped terminal electrically connected to the circuit pattern.
  • the wall portion surrounds the substrate.
  • the terminal includes a first region attached to the wall portion and a second region connected to the first region and disposed inside the frame body. The distance between the inner wall surface of the wall portion and the circuit pattern is 500 ⁇ m or less. The second region is directly connected to the circuit pattern.
  • the distance between the inner wall surface of the wall portion and the circuit pattern is 500 ⁇ m or less, and the second region of the terminal is directly connected to the circuit pattern, making it easy to simplify the device configuration and reduce its size.
  • components such as wires that connect the terminal and the circuit pattern are no longer necessary, making it possible to reduce inductance while omitting wiring work. Therefore, with such a semiconductor device, it is easy to reduce its size and inductance can be reduced.
  • the semiconductor device includes: (2) A substrate having a circuit pattern, a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern, a frame including a wall, and a plate-shaped terminal electrically connected to the circuit pattern.
  • the wall surrounds the substrate.
  • the terminal includes a third region attached to the wall, a fourth region disposed inside the frame and directly connected to the circuit pattern, and a fifth region disposed between the third and fourth regions.
  • the distance between the inner wall surface of the wall and the circuit pattern is 500 ⁇ m or less.
  • a through hole penetrating the substrate in the thickness direction is formed in the fifth region.
  • the distance between the inner wall surface of the wall and the circuit pattern is 500 ⁇ m or less, and the fourth region of the terminal is directly connected to the circuit pattern, so that it is easy to simplify the device configuration and reduce the size.
  • a member such as a wire connecting the terminal and the circuit pattern is not necessary, and the inductance can be reduced while omitting the wiring work. Therefore, with this semiconductor device, it is easy to reduce the size and the inductance can be reduced.
  • a through hole is formed in the fifth region having a gap between the circuit pattern and the fifth region.
  • the distance between the inner wall surface of the wall portion and the circuit pattern may be 100 ⁇ m or less from the viewpoint of further suppressing the generation of air bubbles.
  • the inner wall surface of the wall portion may be in contact with the circuit pattern.
  • the inner wall surface of the wall portion and the circuit pattern can be brought into close contact with each other, reducing the risk of resin containing air bubbles being disposed between the inner wall surface of the wall portion and the circuit pattern. This can further suppress the decrease in resistance and further improve reliability.
  • At least one of the second region and the circuit pattern and the fourth region and the circuit pattern may be connected by welding, ultrasonic bonding, a conductive adhesive, or solder. Such a connection makes it possible to more reliably connect the second region and the circuit pattern while ensuring electrical conductivity.
  • a base plate may be provided so as to come into contact with the substrate and to which the frame is attached. Such a base plate is effectively used to fasten the frame and is also effectively used to dissipate heat from the semiconductor chip.
  • a sealant may be further provided to fill the space surrounded by the wall portion.
  • the terminal may include a control terminal that controls the operation of the semiconductor chip. In this way, the inductance of the control terminal can be reduced.
  • the terminal may include a main terminal that electrically connects the semiconductor device to the outside. In this way, the inductance of the main terminal can be reduced.
  • the outer wall surface of the substrate and the inner wall surface of the wall portion may be in contact with each other.
  • the outer wall surface of the substrate can be fitted into the inner wall surface of the wall portion, making it easy to attach the frame to the substrate.
  • the substrate can be more reliably positioned relative to the frame.
  • At least one of the first region and the third region may include a portion that is inserted into the wall portion.
  • the terminal can be pre-fixed to the wall portion of the frame body, so that the terminal can be more reliably attached to the frame body.
  • the semiconductor chip may include a SiC transistor chip.
  • a semiconductor chip includes SiC (silicon carbide) as a semiconductor layer, and therefore is capable of high-speed switching. Therefore, it is suitable for the semiconductor device of the present disclosure, which is premised on switching of a current path.
  • the inner wall surface of the wall portion may extend in the thickness direction of the substrate. This reduces the risk of preventing trapped air bubbles from escaping when degassing when the sealant is filled inside the frame.
  • Such a semiconductor device is highly reliable as it suppresses the deterioration of resistance.
  • FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate.
  • FIG. 2 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 1.
  • FIG. 2 is a schematic cross-sectional view taken along the YZ plane. In order to facilitate understanding, FIG. 2 omits some of the components shown in FIG. 1.
  • the thickness direction of the substrate is defined as the Z direction.
  • the semiconductor device 11a in the first embodiment includes a base plate 12, a frame body 13, a substrate 15 having a circuit pattern 16, four terminals 19a (main terminal 19a), 19b (main terminal 19b), 19c (main terminal 19c), and 19d (main terminal 19d), four terminals 29a (control terminal 29a), 29b (control terminal 29b), 29c (control terminal 29c), and 29d (control terminal 29d), and six semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f.
  • the base plate 12 is made of metal.
  • the base plate 12 is made of copper, for example.
  • the base plate 12 is a so-called heat sink, and is used to dissipate heat from the semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f.
  • the external shape of the base plate 12 is a rectangle whose long sides extend in the X direction and whose short sides extend in the Y direction, and the four corners are rounded.
  • the substrate 15 having the circuit pattern 16 is disposed on the base plate 12. Specifically, the substrate 15 is disposed on the first surface 12a located in the thickness direction of the base plate 12.
  • the substrate 15 is insulating. Examples of materials for the substrate 15 include Al2O3 , AlN , and Si3N4 .
  • the thickness direction of the base plate 12 and the thickness direction of the substrate 15 are both Z directions.
  • the outer shape of the substrate 15 is a rectangle with the long side extending in the X direction and the short side extending in the Y direction when viewed in the thickness direction of the substrate 15. The configuration of the circuit pattern 16 will be described in detail later.
  • the frame body 13 rises from the first surface 12a of the base plate 12 and is arranged to surround the substrate 15.
  • the frame body 13 includes a wall portion 13a (first wall portion 13a), a wall portion 13b (second wall portion 13b), a wall portion 13c (third wall portion 13c), and a wall portion 13d (fourth wall portion 13d).
  • the first wall portion 13a, the second wall portion 13b, the third wall portion 13c, and the fourth wall portion 13d surround the substrate 15.
  • the inner wall surfaces 27 of the first wall portion 13a, the second wall portion 13b, the third wall portion 13c, and the fourth wall portion 13d extend in the thickness direction of the substrate 15, i.e., in the Z direction.
  • the first wall portion 13a and the second wall portion 13b are arranged opposite each other in the Y direction.
  • the third wall portion 13c and the fourth wall portion 13d are arranged opposite each other in the X direction.
  • the frame 13 is made of, for example, an insulating resin.
  • the frame 13 is fixed to the base plate 12 by, for example, an adhesive.
  • the base plate 12 and the frame 13 form the case 20 included in the semiconductor device 11a.
  • the space 30 inside the case 20 is filled with a resin sealant 14.
  • Circuit pattern 16 is disposed on substrate 15.
  • Circuit pattern 16 is made of, for example, copper.
  • Circuit pattern 16 includes seven circuit boards 17a, 17b, 17c, 17d, 17e, 17f, and 17g. That is, circuit pattern 16 is composed of seven circuit boards 17a, 17b, 17c, 17d, 17e, 17f, and 17g provided on substrate 15.
  • Circuit board 17a is a strip extending in the X direction and is disposed in contact with first wall 13a.
  • Circuit board 17b is disposed closer to second wall 13b than circuit board 17a and includes a strip portion that is long in the X direction.
  • Circuit board 17b also has a portion that contacts first wall 13a.
  • Circuit board 17c is a strip that is long in the X direction and is disposed in contact with third wall 13c.
  • Circuit board 17e has a strip-shaped portion that is long in the X direction and has a portion that contacts third wall portion 13c.
  • Circuit board 17f includes a strip-shaped portion that is long in the X direction.
  • Circuit board 17f also has a portion that contacts second wall portion 13b.
  • Circuit board 17g is strip-shaped extending in the X direction and is disposed in contact with second wall portion 13b.
  • Circuit boards 17a, 17b, 17c, 17d, 17e, 17f, and 17g are disposed with a gap between each other.
  • the circuit board 17d includes a first portion 18a in a strip shape extending in the X direction, a second portion 18b in a strip shape also extending in the X direction, and a third portion 18c in a strip shape extending in the Y direction connecting the first portion 18a and the second portion 18b.
  • the first portion 18a and the second portion 18b are disposed at a distance in the Y direction.
  • the circuit board 17c is disposed between the first portion 18a and the circuit board 17b.
  • the circuit board 17e is disposed between the first portion 18a and the second portion 18b.
  • the third portion 18c is in contact with the fourth wall portion 13d.
  • Main terminal 19a, main terminal 19b, main terminal 19c, and main terminal 19d are each plate-shaped and made of metal.
  • main terminal 19a is a P terminal
  • main terminal 19b and main terminal 19c are O terminals
  • main terminal 19d is an N terminal.
  • Main terminal 19a, main terminal 19b, main terminal 19c, and main terminal 19d each have a curved belt-like shape.
  • main terminal 19a, main terminal 19b, main terminal 19c, and main terminal 19d are each formed, for example, by bending a belt-shaped copper plate.
  • Main terminal 19a and main terminal 19d are attached to third wall portion 13c with a gap in the Y direction, and main terminal 19b and main terminal 19c are attached to fourth wall portion 13d with a gap in the Y direction.
  • Semiconductor device 11a ensures electrical connection with the outside by main terminal 19a, main terminal 19b, main terminal 19c, and main terminal 19d.
  • Each of main terminals 19a, 19b, 19c, and 19d has a portion that is exposed from the inner wall surface 27 of the frame body 13 toward the space 30 inside the case 20. These portions are used to electrically connect the wires that serve as connection members.
  • the main terminal 19a includes a first region 31a attached to the third wall portion 13c and a second region 32a arranged inside the frame body 13. In this embodiment, the first region 31a is embedded in the third wall portion 13c.
  • the main terminal 19b includes a first region 31b attached to the fourth wall portion 13d and a second region 32b arranged inside the frame body 13. In this embodiment, the first region 31b is embedded in the fourth wall portion 13d.
  • the main terminal 19c includes a first region 31c attached to the fourth wall portion 13d and a second region 32c arranged inside the frame body 13. In this embodiment, the first region 31c is embedded in the fourth wall portion 13d.
  • the main terminal 19d includes a first region 31d attached to the third wall portion 13c and a second region 32d arranged inside the frame body 13. In this embodiment, the first region 31d is embedded in the third wall portion 13c.
  • the main terminals 19a, 19b, 19c, and 19d are each inserted into the frame body 13. That is, the main terminals 19a, 19b, 19c, and 19d are attached to the frame body 13 by insert molding.
  • Semiconductor chip 21a, semiconductor chip 21b, semiconductor chip 21c, semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f each contain SiC as a semiconductor layer.
  • Semiconductor chip 21a, semiconductor chip 21b, semiconductor chip 21c, semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f are each SiC transistor chips.
  • semiconductor chip 21a, semiconductor chip 21b, semiconductor chip 21c, semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f are each, for example, metal-oxide-semiconductor field effect transistors (MOSFETs).
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • Semiconductor chip 21a, semiconductor chip 21b, and semiconductor chip 21c are each electrically connected to circuit board 17c by, for example, solder or the like.
  • Semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f are arranged on second portion 18b of circuit board 17d at intervals in the X direction.
  • Semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f are each electrically connected to circuit board 17d by, for example, solder or the like.
  • the control terminals 29a, 29b, 29c, and 29d are also plate-shaped and made of metal.
  • the control terminal 29a is a gate terminal
  • the control terminal 29b is a source sense terminal
  • the control terminal 29c is a gate terminal
  • the control terminal 29d is a source sense terminal.
  • the control terminals 29a, 29b, 29c, and 29d each have a curved belt-like shape.
  • the control terminals 29a, 29b, 29c, and 29d are each formed, for example, by bending a belt-shaped copper plate.
  • control terminals 29a and 29b are attached to the first wall portion 13a with a gap in the X direction
  • the control terminals 29c and 29d are attached to the second wall portion 13b with a gap in the X direction.
  • Semiconductor device 11a controls the operation of six semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f by control terminals 29a, 29b, 29c, and 29d.
  • Control terminals 29a, 29b, 29c, and 29d each have a portion exposed from inner wall surface 27 of frame 13 toward space 30 inside case 20. These portions are used to electrically connect the wires that serve as connection members.
  • Each of the control terminals 29a includes a first region 33a attached to the first wall portion 13a and a second region 34a disposed inside the frame body 13.
  • the control terminal 29b includes a first region attached to the first wall portion 13a and a second region disposed inside the frame body 13.
  • Each of the control terminals 29c and 29d also includes a first region attached to the second wall portion 13b and a second region disposed inside the frame body 13.
  • Each of the control terminals 29a, 29b, 29c, and 29d is inserted into the frame body 13. That is, the control terminals 29a, 29b, 29c, and 29d are attached to the frame body 13 by insert molding.
  • the gate pad of the semiconductor chip 21a and the circuit board 17b are electrically connected by a wire 22a.
  • the source pad of the semiconductor chip 21a and the circuit board 17a are electrically connected by a wire 23a.
  • the source pad of the semiconductor chip 21a and the first portion 18a of the circuit board 17d are electrically connected by a plurality of wires 24a.
  • the gate pad of the semiconductor chip 21b and the circuit board 17b are electrically connected by a wire 22b.
  • the source pad of the semiconductor chip 21b and the circuit board 17a are electrically connected by a wire 23b.
  • the source pad of the semiconductor chip 21b and the first portion 18a of the circuit board 17d are electrically connected by a plurality of wires 24b.
  • the gate pad of the semiconductor chip 21c and the circuit board 17b are electrically connected by a wire 22c.
  • the source pad of the semiconductor chip 21c and the circuit board 17a are electrically connected by a wire 23c.
  • the source pad of the semiconductor chip 21c and the first portion 18a of the circuit board 17d are electrically connected by a plurality of wires 24c.
  • the gate pad of the semiconductor chip 21d and the circuit board 17f are electrically connected by a wire 22d.
  • the source pad of the semiconductor chip 21d and the circuit board 17g are electrically connected by a wire 23d.
  • the source pad of the semiconductor chip 21d and the circuit board 17e are electrically connected by a plurality of wires 24d.
  • the gate pad of the semiconductor chip 21e and the circuit board 17f are electrically connected by a wire 22e.
  • the source pad of the semiconductor chip 21e and the circuit board 17g are electrically connected by a wire 23e.
  • the source pad of the semiconductor chip 21d and the circuit board 17e are electrically connected by a plurality of wires 24e.
  • the gate pad of the semiconductor chip 21f and the circuit board 17f are electrically connected by a wire 22f.
  • the source pad of the semiconductor chip 21f and the circuit board 17g are electrically connected by a wire 23f.
  • the source pad of the semiconductor chip 21f and the circuit board 17e are electrically connected by a plurality of wires 24f.
  • the distance D between the inner wall surface 27 of the wall portion 13a (first wall portion 13a) and the circuit pattern 16 is 500 ⁇ m or less.
  • the distance D is the distance in the Y direction.
  • the distance between the inner wall surface 27 of the first wall portion 13a and the circuit pattern 16 is 0 ⁇ m. In other words, the inner wall surface 27 of the first wall portion 13a and the circuit pattern 16 are in contact.
  • the second region 34a of the control terminal 29a is directly connected to the circuit pattern 16. Specifically, the second region 34a and the circuit board 17b of the circuit pattern 16 are directly connected by ultrasonic bonding. Similarly, the control terminals 29b, 29c, 29d, main terminals 19a, 19b, 19c, and 19d are each directly connected to the circuit pattern 16 by ultrasonic bonding.
  • the flow of current can be briefly explained as follows: When semiconductor chip 21a, semiconductor chip 21b, and semiconductor chip 21c are turned on by control via control terminals 29a, 29b, 29c, and 29d, the electrical connection between main terminal 19a and main terminal 19b is on, and the electrical connection between main terminal 19c and main terminal 19d is off, current flows from main terminal 19a to circuit board 17c of circuit pattern 16, flows to semiconductor chip 21a, semiconductor chip 21b, and semiconductor chip 21c which are in the on state, flows to wires 24a, 24b, and 24c, flows to first portion 18a of circuit board 17d of circuit pattern 16, third portion 18c of circuit board 17d of circuit pattern 16, and flows to main terminal 19b. At this time, no current flows through the second portion 18b of the circuit board 17d of the circuit pattern 16 on which the semiconductor chips 21d, 21e, and 21f are mounted, which are in the off state.
  • Figures 3, 4, and 5 are schematic cross-sectional views showing intermediate stages in the manufacturing process of the semiconductor device 11a.
  • the substrate 15 having the circuit pattern 16 and the base plate 12 are bonded with an adhesive (not shown).
  • the semiconductor chip 21a is bonded on the circuit pattern 16 with solder.
  • the drain pad of the semiconductor chip 21a and the circuit pattern 16 are electrically connected.
  • wire bonding is performed using a bond tool to electrically connect each member with a wire.
  • the frame body 13 to which the control terminal 29a and the like are attached by insert molding is bonded to the base plate 12 with an adhesive.
  • the second region 34a of the control terminal 29a is ultrasonically bonded to the circuit pattern 16. In this way, the control terminal 29a is directly connected to the circuit pattern 16. Then, as shown in Figure 2, the space 30 formed by the base plate 12 and the frame body 13 is filled with the sealant 14 and sealed. In this way, the semiconductor device 11a is manufactured.
  • the distance D between the inner wall surface 27 of the wall 13a, the wall 13b, the wall 13c, and the wall 13d and the circuit pattern 16 is 500 ⁇ m or less, and the second region 32a, the second region 32b, the second region 32c, the second region 32d, and the second region 34a of the control terminal 29a, the control terminal 29b, the control terminal 29c, and the control terminal 29d are directly connected to the circuit pattern 16, so that it is easy to simplify the device configuration and achieve miniaturization.
  • members such as wires connecting the control terminal 29a, the control terminal 29b, the control terminal 29c, and the control terminal 29d to the circuit pattern 16 are not required, and the inductance can be reduced while omitting wiring work. Therefore, with this semiconductor device 11a, it is easy to achieve miniaturization and reduce inductance.
  • the inner wall surface 27 of the wall portion 13a is in contact with the circuit pattern 16. Therefore, the inner wall surface 27 of the wall portion 13a and the circuit pattern 16 can be brought into close contact with each other, reducing the risk of resin containing air bubbles being disposed between the inner wall surface 27 of the wall portion 13a and the circuit pattern 16. This further reduces the decrease in resistance and further improves reliability.
  • the second region 34a and the circuit pattern 16 are connected by ultrasonic bonding. This type of connection makes it possible to more reliably connect the second region 34a and the circuit pattern 16 while ensuring electrical conductivity.
  • a base plate 12 is provided that is in contact with the substrate 15 and to which the frame body 13 is attached.
  • Such a base plate 12 is effectively used to fix the frame body 13 and is also effectively used to dissipate heat from the semiconductor chip 21a, etc.
  • a sealant 14 is provided that fills the space surrounded by walls 13a, 13b, 13c, and 13d. By providing such a sealant 14, it is possible to suppress a decrease in the resistance of semiconductor device 11a, and to improve reliability.
  • the terminals include control terminals 29a, 29b, 29c, and 29d that control the operation of semiconductor chip 21a, semiconductor chip 21b, semiconductor chip 21c, semiconductor chip 21d, semiconductor chip 21e, and semiconductor chip 21f. Therefore, it is possible to reduce the inductance at control terminals 29a, 29b, 29c, and 29d.
  • the terminals include main terminal 19a, main terminal 19b, main terminal 19c, and main terminal 19d that electrically connect semiconductor device 11a to the outside. Therefore, it is possible to reduce the inductance in main terminal 19a, main terminal 19b, main terminal 19c, and main terminal 19d.
  • the outer wall surface of the substrate 15 is in contact with the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d. Therefore, the outer wall surface of the substrate 15 can be fitted into the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d, making it easy to attach the frame 13 to the substrate 15. In addition, the positioning of the substrate 15 relative to the frame 13 can be more reliably performed.
  • the first region 31a, the first region 31b, the first region 31c, and the first region 31d include portions inserted into the walls 13a, 13b, 13c, and 13d. Therefore, the main terminals 19a, 19b, 19c, 19d, the control terminals 29a, 29b, 29c, and 29d can be pre-fixed to the walls 13a, 13b, 13c, and 13d of the frame body 13, so that the main terminals 19a, 19b, 19c, 19d, the control terminals 29a, 29b, 29c, and 29d can be more reliably attached to the frame body 13.
  • the inner wall surfaces 27 of the walls 13a, 13b, 13c, and 13d extend in the thickness direction of the substrate 15. This reduces the risk that the trapped air bubbles will be prevented from escaping when degassing when the sealant 14 is filled inside the frame 13.
  • This semiconductor device 11a has high reliability by suppressing the decrease in resistance.
  • FIG. 6 is a schematic perspective view showing a part of a semiconductor device according to embodiment 2.
  • the semiconductor device in embodiment 2 basically has the same configuration as embodiment 1, and achieves the same effects. However, the semiconductor device in embodiment 2 has a different terminal configuration from embodiment 1.
  • the semiconductor device 11b of the second embodiment includes a plate-shaped terminal 41 electrically connected to the circuit pattern.
  • the terminal 41 includes a third region 43a attached to the wall 13a, a fourth region 44a disposed inside the frame body and directly connected to the circuit pattern, specifically, a circuit board 17b included in the circuit pattern, and a fifth region 45a disposed between the third region 43a and the fourth region 44a.
  • the inner wall surface of the wall 13a extends in the thickness direction of the substrate.
  • the distance between the inner wall surface of the wall 13a and the circuit pattern is 500 ⁇ m or less.
  • a through hole 42 penetrating the fifth region 45a in the thickness direction of the substrate is formed.
  • the distance between the inner wall surface 27 of the wall portion 13a and the circuit board 17b of the circuit pattern 16 is 500 ⁇ m or less, and the fourth region 44a of the terminal 41 is directly connected to the circuit board 17b of the circuit pattern 16, making it easy to simplify the device configuration and reduce its size.
  • a through hole 42 is formed in the fifth region 45a having a gap 46 between the circuit pattern 16 and the fifth region 45a, penetrating the substrate 15 in the thickness direction.
  • a gap 46 may be formed during ultrasonic bonding or the like during manufacturing based on a design that takes tolerances into account.
  • the air bubbles can escape through the through hole 42 formed in the fifth region 45a during degassing, and the air bubbles can be removed from the sealant 14. This prevents air bubbles from accumulating on the lower side of the terminal 41, and prevents a decrease in the resistance of the semiconductor device 11b. As a result, the reliability of this semiconductor device 11b can be improved.
  • At least one of the second region and the circuit pattern and the fourth region and the circuit pattern may be connected by welding, ultrasonic bonding, a conductive adhesive, or soldering. Such a connection can more reliably connect the second region and the circuit pattern while ensuring electrical conductivity.
  • At least one of the first region and the third region may include a portion that is inserted into the wall portion.
  • the terminal can be pre-fixed to the wall portion of the frame body, so that the terminal can be more securely attached to the frame body.
  • 11a, 11b semiconductor device 12 base plate, 12a first surface, 13 frame, 13a wall portion (first wall portion), 13b wall portion (second wall portion), 13c wall portion (third wall portion), 13d wall portion (fourth wall portion), 14 sealing material, 15 substrate, 16 circuit pattern, 17a, 17b, 17c, 17d, 17e, 17f, 17g circuit board, 18a first portion, 18b second portion, 18c third portion, 19a, 19b, 19c, 19d main terminal, 20 case, 21a, 21b, 21c, 21d, 21e, 21f Semiconductor chips, 22a, 22b, 22c, 22d, 22e, 22f, 23a, 23b, 23c, 23d, 23e, 23f, 24a, 24b, 24c, 24d, 24e, 24 Wires, 27 Inner wall surface, 29a, 29b, 29c, 29d Control terminals, 31a, 31b, 31c, 31d, 33a First region, 32a, 32b, 32c, 32d, 34a Second region

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2023/032467 2022-10-07 2023-09-06 半導体装置 Ceased WO2024075463A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009081723A1 (ja) * 2007-12-20 2009-07-02 Fuji Electric Device Technology Co., Ltd. 半導体装置およびその製造方法
WO2018135465A1 (ja) * 2017-01-17 2018-07-26 三菱電機株式会社 半導体装置および電力変換装置
JP2018182131A (ja) * 2017-04-17 2018-11-15 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2022006924A (ja) * 2020-06-25 2022-01-13 株式会社 日立パワーデバイス パワーモジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009081723A1 (ja) * 2007-12-20 2009-07-02 Fuji Electric Device Technology Co., Ltd. 半導体装置およびその製造方法
WO2018135465A1 (ja) * 2017-01-17 2018-07-26 三菱電機株式会社 半導体装置および電力変換装置
JP2018182131A (ja) * 2017-04-17 2018-11-15 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2022006924A (ja) * 2020-06-25 2022-01-13 株式会社 日立パワーデバイス パワーモジュール

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